Add Smstateen/Ssstateen extension regs

riscv · Jan 23, 2025 · 0b935cb · 0b935cb
1 parent 39f702c
commit 0b935cb
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Showing 9 changed files with 344 additions and 0 deletions.
diff --git a/Makefile b/Makefile
@@ -101,6 +101,7 @@ PRELUDE = prelude.sail riscv_errors.sail $(SAIL_XLEN) $(SAIL_FLEN) $(SAIL_VLEN)
 
 SAIL_REGS_SRCS =  riscv_csr_begin.sail       # Start of CSR scattered definitions.
 SAIL_REGS_SRCS += riscv_reg_type.sail riscv_freg_type.sail riscv_regs.sail riscv_pc_access.sail riscv_sys_regs.sail
+SAIL_REGS_SRCS += riscv_stateen_regs.sail
 SAIL_REGS_SRCS += riscv_pmp_regs.sail riscv_pmp_control.sail
 SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
 SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail

diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
@@ -67,11 +67,21 @@ bool sys_enable_zicboz(unit u)
   return rv_enable_zicboz;
 }
 
+bool sys_enable_ssstateen(unit u)
+{
+  return rv_enable_ssstateen;
+}
+
 bool sys_enable_sstc(unit u)
 {
   return rv_enable_sstc;
 }
 
+bool sys_enable_smstateen(unit u)
+{
+  return rv_enable_smstateen;
+}
+
 uint64_t sys_pmp_count(unit u)
 {
   return rv_pmp_count;

diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
@@ -12,7 +12,9 @@ bool sys_enable_vext(unit);
 bool sys_enable_bext(unit);
 bool sys_enable_zicbom(unit);
 bool sys_enable_zicboz(unit);
+bool sys_enable_ssstateen(unit u);
 bool sys_enable_sstc(unit);
+bool sys_enable_smstateen(unit u);
 
 uint64_t sys_pmp_count(unit);
 uint64_t sys_pmp_grain(unit);

diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
@@ -19,7 +19,9 @@ bool rv_enable_vext = true;
 bool rv_enable_bext = false;
 bool rv_enable_zicbom = false;
 bool rv_enable_zicboz = false;
+bool rv_enable_ssstateen = false;
 bool rv_enable_sstc = false;
+bool rv_enable_smstateen = false;
 
 bool rv_enable_dirty_update = false;
 bool rv_enable_misaligned = false;

diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
@@ -23,7 +23,9 @@ extern bool rv_enable_vext;
 extern bool rv_enable_bext;
 extern bool rv_enable_zicbom;
 extern bool rv_enable_zicboz;
+extern bool rv_enable_ssstateen;
 extern bool rv_enable_sstc;
+extern bool rv_enable_smstateen;
 extern bool rv_enable_writable_misa;
 extern bool rv_enable_dirty_update;
 extern bool rv_enable_misaligned;

diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
@@ -58,7 +58,9 @@ enum {
   OPT_ENABLE_ZCB,
   OPT_ENABLE_ZICBOM,
   OPT_ENABLE_ZICBOZ,
+  OPT_ENABLE_SSSTATEEN,
   OPT_ENABLE_SSTC,
+  OPT_ENABLE_SMSTATEEN,
   OPT_CACHE_BLOCK_SIZE,
 };
 
@@ -429,10 +431,18 @@ static int process_args(int argc, char **argv)
       fprintf(stderr, "enabling Zicboz extension.\n");
       rv_enable_zicboz = true;
       break;
+    case OPT_ENABLE_SSSTATEEN:
+      fprintf(stderr, "enabling Ssstateen extension.\n");
+      rv_enable_ssstateen = true;
+      break;
     case OPT_ENABLE_SSTC:
       fprintf(stderr, "enabling Sstc extension.\n");
       rv_enable_sstc = true;
       break;
+    case OPT_ENABLE_SMSTATEEN:
+      fprintf(stderr, "enabling Smstateen extension.\n");
+      rv_enable_smstateen = true;
+      break;
     case OPT_CACHE_BLOCK_SIZE:
       block_size_exp = ilog2(atol(optarg));
 

diff --git a/model/riscv_extensions.sail b/model/riscv_extensions.sail
@@ -103,7 +103,12 @@ enum clause extension = Ext_Zksh
 // Floating-Point in Integer Registers (half precision)
 enum clause extension = Ext_Zhinx
 
+// Supervisor-mode view of the state-enable extension
+enum clause extension = Ext_Ssstateen
 // Supervisor-mode Timer Interrupts
 enum clause extension = Ext_Sstc
 // Fine-Grained Address-Translation Cache Invalidation
 enum clause extension = Ext_Svinval
+
+// Machine-mode view of the state-enable extension
+enum clause extension = Ext_Smstateen