From eba666f95c0bc51b6a964578fdc47bb3928cd0c3 Mon Sep 17 00:00:00 2001 From: Brendan Sweeney Date: Fri, 27 Oct 2023 10:36:50 -0500 Subject: [PATCH] Add support for the unratified Zalasr extension --- Makefile.old | 1 + model/CMakeLists.txt | 1 + model/riscv_extensions.sail | 2 + model/riscv_insts_zalasr.sail | 53 +++++++++++++++++++++++++++ test/riscv-tests/rv32ua-p-zalasr.elf | Bin 0 -> 13688 bytes test/riscv-tests/rv64ua-p-zalasr.elf | Bin 0 -> 14320 bytes 6 files changed, 57 insertions(+) create mode 100644 model/riscv_insts_zalasr.sail create mode 100755 test/riscv-tests/rv32ua-p-zalasr.elf create mode 100755 test/riscv-tests/rv64ua-p-zalasr.elf diff --git a/Makefile.old b/Makefile.old index 7502af667..35a9f156b 100644 --- a/Makefile.old +++ b/Makefile.old @@ -53,6 +53,7 @@ SAIL_DEFAULT_INST += riscv_insts_zbkb.sail SAIL_DEFAULT_INST += riscv_insts_zbkx.sail SAIL_DEFAULT_INST += riscv_insts_zicond.sail +SAIL_DEFAULT_INST += riscv_insts_zalasr.sail SAIL_DEFAULT_INST += riscv_insts_vext_utils.sail SAIL_DEFAULT_INST += riscv_insts_vext_fp_utils.sail diff --git a/model/CMakeLists.txt b/model/CMakeLists.txt index 2719eb8c6..4934f3d6a 100644 --- a/model/CMakeLists.txt +++ b/model/CMakeLists.txt @@ -78,6 +78,7 @@ foreach (xlen IN ITEMS 32 64) ${vext_srcs} "riscv_insts_zicbom.sail" "riscv_insts_zicboz.sail" + "riscv_insts_zalasr.sail" ) if (variant STREQUAL "rmem") diff --git a/model/riscv_extensions.sail b/model/riscv_extensions.sail index 82ef9416d..f1d68b3a2 100644 --- a/model/riscv_extensions.sail +++ b/model/riscv_extensions.sail @@ -50,6 +50,8 @@ enum clause extension = Ext_Zaamo enum clause extension = Ext_Zabha // Load-Reserved/Store-Conditional Instructions enum clause extension = Ext_Zalrsc +// Load-Acquire/Store-Release Instructions +enum clause extension = Ext_Zalasr // Additional Floating-Point Instructions enum clause extension = Ext_Zfa diff --git a/model/riscv_insts_zalasr.sail b/model/riscv_insts_zalasr.sail new file mode 100644 index 000000000..5e9828b47 --- /dev/null +++ b/model/riscv_insts_zalasr.sail @@ -0,0 +1,53 @@ +/*=======================================================================================*/ +/* This Sail RISC-V architecture model, comprising all files and */ +/* directories except where otherwise noted is subject the BSD */ +/* two-clause license in the LICENSE file. */ +/* */ +/* SPDX-License-Identifier: BSD-2-Clause */ +/*=======================================================================================*/ + +/* *********************************************************************** */ +/* This file specifies the atomic instructions in the 'Zalasr' extension. */ + +/* *********************************************************************** */ + +function clause extensionEnabled(Ext_Zalasr) = true + +union clause ast = LOADAQ : (bool, bool, regidx, word_width, regidx) + +mapping clause encdec = LOADAQ(aq, rl, rs1, size, rd) if extensionEnabled(Ext_Zalasr) + <-> 0b00110 @ bool_bits(aq) @ bool_bits(rl) @ 0b00000 @ rs1 @ 0b0 @ size_enc(size) @ rd @ 0b0101111 if extensionEnabled(Ext_Zalasr) + +function clause execute(LOADAQ(aq, rl, rs1, width, rd)) = { + // load-acquire is required to have the acquire bit set + if not(aq) + then { handle_illegal(); RETIRE_FAIL } + else { + execute(LOAD(zeros(), rs1, rd, false, width, aq, rl)) + } +} + +mapping clause assembly = LOADAQ(aq, rl, rs1, size, rd) + <-> "l" ^ size_mnemonic(size) + ^ maybe_aq(aq) ^ maybe_rl(rl) + ^ spc() ^ reg_name(rd) + ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" + +union clause ast = STORERL : (bool, bool, regidx, regidx, word_width) +mapping clause encdec = STORERL(aq, rl, rs2, rs1, size) if extensionEnabled(Ext_Zalasr) + <-> 0b00111 @ bool_bits(aq) @ bool_bits(rl) @ rs2 @ rs1 @ 0b0 @ size_enc(size) @ 0b00000 @ 0b0101111 if extensionEnabled(Ext_Zalasr) + +function clause execute (STORERL(aq, rl, rs2, rs1, width)) = { + // store-release is required to have the release bit set + if not(rl) + then { handle_illegal(); RETIRE_FAIL } + else { + execute(STORE(zeros(), rs2, rs1, width, aq, rl)) + } +} + +mapping clause assembly = STORERL(aq, rl, rs2, rs1, size) + <-> "s" ^ size_mnemonic(size) + ^ maybe_aq(aq) ^ maybe_rl(rl) + ^ spc() ^ reg_name(rs2) + ^ sep() ^ "(" ^ reg_name(rs1) ^ ")" diff --git a/test/riscv-tests/rv32ua-p-zalasr.elf b/test/riscv-tests/rv32ua-p-zalasr.elf new file mode 100755 index 0000000000000000000000000000000000000000..4157060fd3aed006d6a48dedc7cfc875952a1cef GIT binary patch literal 13688 zcmeHO-)kII6h3!$H;pm6(@wM@1UqPjKFDTwv!;-0Tx--mtWdQ+_@L`#GD!xryTi;h zTT8)div)d293cok=u;7Vs3PXUm%J-l1wk;N^%tceq!wR9jNh3bn`zPq|A2ep%y+(f z&bjx_H+LU)ckb&?Hl7kfP}&r_NeK&T=)5)_M{1-~fsW7s^~Z5F>JM-YKFtxa6}Sui zQN14d0eEl%E?Xb07caxtDPZHF*wXm3zxlJEds-AnFQ#%-u20%CK(;(Anmg&2AQg}b zNCl(* zpvG(WNXHx)V_!gPI&y>h?_c+1NzRL@#Hw zdmt2-lQq*1n!x(`nJzyq#sYmZw@lbG0iLtKKES;Ub=6R8r1{_P%AeYkKiVA(#g#Pw zJLEgP@mDbZ+AZTd7=IuXKc)HK?#iFqlRw(+3&mEN|MgMPSJ1@yojKme9G72D%6O8xH8zR~}x7$yiN*mZ#vPlJ`0#X5~ zfK)&#AQg}bNCl(=kP1izqykcbJqq;Wf8Tsg z>Ag1pcmpY}?U_p?j>9duOXF3$>QtJos#9(n?9El3YIBw^XKmASx&N#^XSGcWiSUg@ z!*k0{g&KDIRm+{!Pjp(=jB9oEMq^s994(bg6MGhdj${!*923!bfKxbMka7(UULELh zym~el@55NaA>-!LVI>SE(e=oy71INLNfPqM% z&toUK-q_yAa2@_vyZC0z0|piM^Goamcs&DLq3ggp#!vZ8jwgDml&73PUWV`A#i`_5 zXZ(`gwtcvrg^tIFE-K9$zCopEAC?T?ckP+ezU5KL?6g`|8wuWPE#H^{E_l8hdoj}C zGo>=QmS_3RCCl_XF8QwEq<+`6eXE&FwqUep7pLQL0tw_39077(G#>96obTZ?L1{~U z9UaJVdi}`b&vn{(3~p5z`v^zvB{-vr&%iOZV=x7lwsTy74!n9q!!TZ-3VQ+;tqsWS Z942@ncB5-LFRvw=_YLyyO@oM~?tfu&%LxDg literal 0 HcmV?d00001 diff --git a/test/riscv-tests/rv64ua-p-zalasr.elf b/test/riscv-tests/rv64ua-p-zalasr.elf new file mode 100755 index 0000000000000000000000000000000000000000..309a89afb783ce80d8a8ad518951c7bac0a5bceb GIT binary patch literal 14320 zcmeHOUuYaf9RAH+E{!qvF5TFKHrTaR2~sY1=`|^>#*+m8@TN3yDyHv6l08JiP7&QMlR>_yg{k$4Uo5a+D8eroz&smCODbmjbGd_ z-fas;5~Ur_(axuI-k_w&4da+UAd>~( zd&xO6+Bq(e5nGA(Cdt*3$-j)YB%Ponaa-ePlHf<)o%65t?jU+Xf9_8o)5-hQguS_TfWL>zMk)IL7C_*z$^Z<1*QEu>BxZ?n_QaLaSd+%=fMW$yg2U9);i|&(46}t z=7#;bzIxhY89rAF{FZ(gocH}|#*7{D5x&II&{|#acZy2Me{+P!Wgm&%?4e{pr-fFze23>uByg}Hz zF7_M4euSp|^=%$olJ?gk_M>a;d+L22yDsgo!oJpwKZp49E%CX&Js!I)?Z1xLkFK%r zsc-Svvb6tlgtaHOv$Lx?K0%I4t2sjYZ^qta!M&$1*6|x%*RQ|ciTx)0+$$qz^R%6H zcWK?-Ok>%B07Ll~kbg0hf1`Vus<&gW%JqEy0C7hjC~i-kj8rDZpEbk9Jv`ryzeA|} znR}1<&)j;?p`D^7JdUa;1(X6x0i}RaKq;UUPzopolmbctrGQdEDWDWk3Md7X0!jg; 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