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Simplify mstatus[SD] bit handling #717

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Feb 10, 2025
Merged

Simplify mstatus[SD] bit handling #717

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2 changes: 1 addition & 1 deletion model/riscv_fdext_regs.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -88,7 +88,7 @@ register f31 : fregtype
function dirty_fd_context() -> unit = {
assert(sys_enable_fdext());
mstatus[FS] = extStatus_to_bits(Dirty);
mstatus = set_mstatus_SD(mstatus, 0b1);
mstatus[SD] = 0b1;
}

function dirty_fd_context_if_present() -> unit = {
Expand Down
29 changes: 5 additions & 24 deletions model/riscv_sys_regs.sail
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Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,7 @@ function have_privLevel(priv : priv_level) -> bool =
}

bitfield Mstatus : bits(64) = {
SD_64: 63,
SD : xlen - 1,

//MDT : 42,
//MPELP: 41,
Expand All @@ -190,8 +190,6 @@ bitfield Mstatus : bits(64) = {
SXL : 35 .. 34,
UXL : 33 .. 32,

SD_32: 31,

//SDT : 24,
//SPELP: 23,
TSR : 22,
Expand Down Expand Up @@ -232,17 +230,6 @@ function get_mstatus_UXL(m : Mstatus) -> arch_xlen = {
else m[UXL]
}

function get_mstatus_SD(m : Mstatus) -> bits(1) = {
if xlen == 32 then m[SD_32]
else m[SD_64]
}

function set_mstatus_SD(m : Mstatus, v : bits(1)) -> Mstatus = {
if xlen == 32
then [m with SD_32 = v]
else [m with SD_64 = v]
}

function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
/*
* Populate all defined fields using the bits of v, stripping anything
Expand Down Expand Up @@ -292,10 +279,7 @@ function legalize_mstatus(o : Mstatus, v : bits(64)) -> Mstatus = {
extStatus_of_bits(o[XS]) == Dirty |
extStatus_of_bits(o[VS]) == Dirty;

[o with
SD_64 = if xlen == 64 then bool_to_bits(dirty) else o[SD_64],
SD_32 = if xlen == 32 then bool_to_bits(dirty) else o[SD_32],
]
[o with SD = bool_to_bits(dirty)]
}

register mstatus : Mstatus = {
Expand Down Expand Up @@ -708,10 +692,9 @@ function clause read_CSR(0xF15) = mconfigptr

/* sstatus reveals a subset of mstatus */
bitfield Sstatus : bits(64) = {
SD_64 : 63,
SD : xlen - 1,

UXL : 33 .. 32,
SD_32 : 31,
// SDT : 24,
// SPELP : 23,
MXR : 19,
Expand All @@ -729,9 +712,8 @@ function lower_mstatus(m : Mstatus) -> Sstatus = {
let s = Mk_Sstatus(zeros());

[s with
SD_64 = m[SD_64],
SD = m[SD],
UXL = m[UXL],
SD_32 = m[SD_32],
//SDT = m[SDT],
//SPELP = m[SPELP],
MXR = m[MXR],
Expand All @@ -750,8 +732,7 @@ function lift_sstatus(m : Mstatus, s : Sstatus) -> Mstatus = {
extStatus_of_bits(s[VS]) == Dirty;

[m with
SD_64 = if xlen == 64 then bool_to_bits(dirty) else m[SD_64],
SD_32 = if xlen == 32 then bool_to_bits(dirty) else m[SD_32],
SD = bool_to_bits(dirty),
UXL = s[UXL],
//SDT = s[SDT],
//SPELP = s[SPELP],
Expand Down
2 changes: 1 addition & 1 deletion model/riscv_vext_regs.sail
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Expand Up @@ -79,7 +79,7 @@ mapping vreg_name = {
function dirty_v_context() -> unit = {
assert(sys_enable_vext());
mstatus[VS] = extStatus_to_bits(Dirty);
mstatus = set_mstatus_SD(mstatus, 0b1);
mstatus[SD] = 0b1;
}

function rV (r : regno) -> vregtype = {
Expand Down
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