Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Refactor instruction retire and stepper #755

Open
wants to merge 3 commits into
base: master
Choose a base branch
from
+962 −498
Open

Refactor instruction retire and stepper #755

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
3 commits
Select commit Hold shift + click to select a range
79fc5ad
Refactor instruction retirement.
pmundkur Feb 24, 2025
43bdc64
Implement a Wait state in the Sail stepper.
pmundkur Feb 24, 2025
a0d2393
Use the exposed Wait state in the C emulator to implement a wait loop.
pmundkur Feb 17, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
3 changes: 2 additions & 1 deletion Makefile.old
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -107,8 +107,9 @@ SAIL_ARCH_SRCS += riscv_extensions.sail riscv_types_common.sail riscv_types_ext.
SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
SAIL_ARCH_SRCS += riscv_sstc.sail
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail riscv_inst_retire.sail
SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension.
SAIL_ARCH_SRCS += riscv_inst_retire.sail

SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail
RVFI_STEP_SRCS = riscv_step_common.sail riscv_step_rvfi.sail riscv_decode_ext.sail riscv_fetch_rvfi.sail riscv_step.sail
Expand Down
8 changes: 7 additions & 1 deletion c_emulator/riscv_sail.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,14 @@ extern struct zMisa zmisa;
void model_init(void);
void model_fini(void);

enum zStepState { zSTEP_ACTIVE, zSTEP_WAIT };
struct zstep_result {
enum zStepState zstate;
bool zstepped;
};

unit zinit_model(unit);
bool zstep(sail_int);
struct zstep_result zstep(sail_int, bool);
unit ztick_clock(unit);
unit ztick_platform(unit);

Expand Down
44 changes: 35 additions & 9 deletions c_emulator/riscv_sim.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -54,6 +54,7 @@ enum {
OPT_ENABLE_ZICBOZ,
OPT_ENABLE_SSTC,
OPT_CACHE_BLOCK_SIZE,
OPT_MAX_WAIT_STEPS,
};

static bool do_show_times = false;
Expand All @@ -72,6 +73,8 @@ static int rvfi_dii_port;
static int rvfi_dii_sock;
#endif

int max_wait_steps = 0;

char *sig_file = NULL;
uint64_t mem_sig_start = 0;
uint64_t mem_sig_end = 0;
Expand Down Expand Up @@ -151,6 +154,7 @@ static struct option options[] = {
{"enable-zicbom", no_argument, 0, OPT_ENABLE_ZICBOM },
{"enable-zicboz", no_argument, 0, OPT_ENABLE_ZICBOZ },
{"cache-block-size", required_argument, 0, OPT_CACHE_BLOCK_SIZE },
{"max-wait-steps", required_argument, 0, OPT_MAX_WAIT_STEPS },
#ifdef SAILCOV
{"sailcov-file", required_argument, 0, 'c' },
#endif
Expand Down Expand Up @@ -240,6 +244,7 @@ static int process_args(int argc, char **argv)
uint64_t pmp_count = 0;
uint64_t pmp_grain = 0;
uint64_t block_size_exp = 0;
int wait_steps = 0;
while (true) {
c = getopt_long(argc, argv,
"a"
Expand Down Expand Up @@ -412,6 +417,15 @@ static int process_args(int argc, char **argv)
block_size_exp, 1 << block_size_exp);
rv_cache_block_size_exp = block_size_exp;
break;
case OPT_MAX_WAIT_STEPS:
wait_steps = atoi(optarg);
if (wait_steps < 0) {
fprintf(stderr, "invalid max-wait-steps '%s' provided.\n", optarg);
exit(1);
}
fprintf(stderr, "setting max-wait-states to %d steps.\n", wait_steps);
max_wait_steps = wait_steps;
break;
case 'x':
fprintf(stderr, "enabling Zfinx support.\n");
rv_enable_zfinx = true;
Expand Down Expand Up @@ -692,12 +706,14 @@ void rvfi_send_trace(unsigned version)

void run_sail(void)
{
bool stepped;
struct zstep_result step_result;
bool exit_wait = (max_wait_steps > 0) ? false : true;
bool diverged = false;

/* initialize the step number */
mach_int step_no = 0;
int insn_cnt = 0;
int wait_steps = 0;
#ifdef RVFI_DII
bool need_instr = true;
#endif
Expand Down Expand Up @@ -800,7 +816,7 @@ void run_sail(void)
sail_int sail_step;
CREATE(sail_int)(&sail_step);
CONVERT_OF(sail_int, mach_int)(&sail_step, step_no);
stepped = zstep(sail_step);
step_result = zstep(sail_step, exit_wait);
if (have_exception)
goto step_exception;
flush_logs();
Expand All @@ -812,19 +828,29 @@ void run_sail(void)
sail_int sail_step;
CREATE(sail_int)(&sail_step);
CONVERT_OF(sail_int, mach_int)(&sail_step, step_no);
stepped = zstep(sail_step);
step_result = zstep(sail_step, exit_wait);
if (have_exception)
goto step_exception;
flush_logs();
KILL(sail_int)(&sail_step);
}
if (stepped) {
if (config_print_step) {
fprintf(trace_log, "\n");
switch (step_result.zstate) {
case zSTEP_WAIT:
if (++wait_steps >= max_wait_steps)
exit_wait = true;
break;
case zSTEP_ACTIVE:
wait_steps = 0;
exit_wait = (max_wait_steps > 0) ? false : true;
if (step_result.zstepped) {
if (config_print_step) {
fprintf(trace_log, "\n");
}
step_no++;
insn_cnt++;
total_insns++;
}
step_no++;
insn_cnt++;
total_insns++;
break;
}

if (do_show_times && (total_insns & 0xfffff) == 0) {
Expand Down
1 change: 1 addition & 0 deletions model/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -166,6 +166,7 @@ foreach (xlen IN ITEMS 32 64)
${sail_vm_srcs}
# Shared/common code for the cryptography extension.
"riscv_types_kext.sail"
"riscv_inst_retire.sail"
)

if (variant STREQUAL "rvfi")
Expand Down
28 changes: 28 additions & 0 deletions model/riscv_inst_retire.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

/* Reasons an instruction retire might fail or be incomplete. */

union Retire_Failure = {
// standard reasons
Illegal_Instruction : unit,
Wait_For_Interrupt : unit,
Trap : (Privilege, ctl_result, xlenbits),
Memory_Exception : (virtaddr, ExceptionType),

// reasons from external extensions
Ext_CSR_Check_Failure : unit,
Ext_ControlAddr_Check_Failure : ext_control_addr_error,
Ext_DataAddr_Check_Failure : ext_data_addr_error,
Ext_XRET_Priv_Failure : unit,
}

// For backwards compatibility, this global definition is used
// instead of the previous RETIRE_SUCCESS enum value.

let RETIRE_SUCCESS : Retired(Retire_Failure) = RETIRE_OK()
30 changes: 15 additions & 15 deletions model/riscv_insts_aext.sail
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -80,19 +80,19 @@ function clause execute(LOADRES(aq, rl, rs1, width, rd)) = {
* Extensions might perform additional checks on address validity.
*/
match ext_data_get_addr(rs1, zeros(), Read(Data), width_bytes) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_Error(e) => RETIRE_FAIL(Ext_DataAddr_Check_Failure(e)),
Ext_DataAddr_OK(vaddr) => {
/* "LR faults like a normal load, even though it's in the AMO major opcode space."
* - Andrew Waterman, isa-dev, 10 Jul 2018.
*/
if not(is_aligned(virtaddr_bits(vaddr), width))
then { handle_mem_exception(vaddr, E_Load_Addr_Align()); RETIRE_FAIL }
then RETIRE_FAIL(Memory_Exception(vaddr, E_Load_Addr_Align()))
else match translateAddr(vaddr, Read(Data)) {
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
TR_Failure(e, _) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
TR_Address(addr, _) =>
match mem_read(Read(Data), addr, width_bytes, aq, aq & rl, true) {
Ok(result) => { load_reservation(physaddr_bits(addr)); X(rd) = sign_extend(result); RETIRE_SUCCESS },
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
},
}
}
Expand Down Expand Up @@ -128,14 +128,14 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
* Extensions might perform additional checks on address validity.
*/
match ext_data_get_addr(rs1, zeros(), Write(Data), width_bytes) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_Error(e) => RETIRE_FAIL(Ext_DataAddr_Check_Failure(e)),
Ext_DataAddr_OK(vaddr) => {
if not(is_aligned(virtaddr_bits(vaddr), width))
then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
then RETIRE_FAIL(Memory_Exception(vaddr, E_SAMO_Addr_Align()))
else {
match translateAddr(vaddr, Write(Data)) { /* Write and ReadWrite are equivalent here:
* both result in a SAMO exception */
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
TR_Failure(e, _) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
TR_Address(addr, _) => {
// Check reservation with physical address.
if not(match_reservation(physaddr_bits(addr))) then {
Expand All @@ -144,13 +144,13 @@ function clause execute (STORECON(aq, rl, rs2, rs1, width, rd)) = {
} else {
let eares = mem_write_ea(addr, width_bytes, aq & rl, rl, true);
match eares {
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
Ok(_) => {
let rs2_val = X(rs2);
match mem_write_value(addr, width_bytes, rs2_val[width_bytes * 8 - 1 .. 0], aq & rl, rl, true) {
Ok(true) => { X(rd) = zero_extend(0b0); cancel_reservation(); RETIRE_SUCCESS },
Ok(false) => { X(rd) = zero_extend(0b1); cancel_reservation(); RETIRE_SUCCESS },
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
}
}
}
Expand Down Expand Up @@ -198,20 +198,20 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
* Some extensions perform additional checks on address validity.
*/
match ext_data_get_addr(rs1, zeros(), ReadWrite(Data, Data), width_bytes) {
Ext_DataAddr_Error(e) => { ext_handle_data_check_error(e); RETIRE_FAIL },
Ext_DataAddr_Error(e) => RETIRE_FAIL(Ext_DataAddr_Check_Failure(e)),
Ext_DataAddr_OK(vaddr) => {
if not(is_aligned(virtaddr_bits(vaddr), width))
then { handle_mem_exception(vaddr, E_SAMO_Addr_Align()); RETIRE_FAIL }
then RETIRE_FAIL(Memory_Exception(vaddr, E_SAMO_Addr_Align()))
else match translateAddr(vaddr, ReadWrite(Data, Data)) {
TR_Failure(e, _) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
TR_Failure(e, _) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
TR_Address(addr, _) => {
let eares = mem_write_ea(addr, width_bytes, aq & rl, rl, true);
let rs2_val = X(rs2)[width_bytes * 8 - 1 .. 0];
match eares {
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
Ok(_) => {
match mem_read(ReadWrite(Data, Data), addr, width_bytes, aq, aq & rl, true) {
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL },
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
Ok(loaded) => {
let result : bits('width_bytes * 8) =
match op {
Expand All @@ -228,7 +228,7 @@ function clause execute (AMO(op, aq, rl, rs2, rs1, width, rd)) = {
match mem_write_value(addr, width_bytes, sign_extend(result), aq & rl, rl, true) {
Ok(true) => { X(rd) = sign_extend(loaded); RETIRE_SUCCESS },
Ok(false) => { internal_error(__FILE__, __LINE__, "AMO got false from mem_write_value") },
Err(e) => { handle_mem_exception(vaddr, e); RETIRE_FAIL }
Err(e) => RETIRE_FAIL(Memory_Exception(vaddr, e)),
}
}
}
Expand Down
Loading
Loading