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Replace ad-hoc model configuration with Sail-native configuration #758

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Replace ad-hoc model configuration with Sail-native configuration #758

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c665e72
Config: Update CMake build system for Sail configuration
Alasdair Feb 26, 2025
d67cbc9
Config: Replace existing C simulator configuration options
Alasdair Feb 26, 2025
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142 changes: 0 additions & 142 deletions c_emulator/riscv_platform.c
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Original file line number Diff line number Diff line change
Expand Up @@ -17,152 +17,12 @@
static mach_bits reservation = 0;
static bool reservation_valid = false;

bool sys_enable_rvc(unit u)
{
return rv_enable_rvc;
}

bool sys_enable_fdext(unit u)
{
return rv_enable_fdext;
}

bool sys_enable_svinval(unit u)
{
return rv_enable_svinval;
}

bool sys_enable_zcb(unit u)
{
return rv_enable_zcb;
}

bool sys_enable_zfinx(unit u)
{
return rv_enable_zfinx;
}

bool sys_enable_writable_fiom(unit u)
{
return rv_enable_writable_fiom;
}

bool sys_enable_vext(unit u)
{
return rv_enable_vext;
}

bool sys_enable_bext(unit u)
{
return rv_enable_bext;
}

bool sys_enable_zicbom(unit u)
{
return rv_enable_zicbom;
}

bool sys_enable_zicboz(unit u)
{
return rv_enable_zicboz;
}

bool sys_enable_sstc(unit u)
{
return rv_enable_sstc;
}

uint64_t sys_pmp_count(unit u)
{
return rv_pmp_count;
}

uint64_t sys_pmp_grain(unit u)
{
return rv_pmp_grain;
}

uint64_t sys_vector_vlen_exp(unit u)
{
return rv_vector_vlen_exp;
}

uint64_t sys_vector_elen_exp(unit u)
{
return rv_vector_elen_exp;
}

bool sys_enable_writable_misa(unit u)
{
return rv_enable_writable_misa;
}

mach_bits sys_writable_hpm_counters(unit u)
{
return rv_writable_hpm_counters;
}

bool sys_vext_vl_use_ceil(unit u)
{
return rv_vext_vl_use_ceil;
}

bool plat_enable_dirty_update(unit u)
{
return rv_enable_dirty_update;
}

bool plat_enable_misaligned_access(unit u)
{
return rv_enable_misaligned;
}

bool plat_mtval_has_illegal_inst_bits(unit u)
{
return rv_mtval_has_illegal_inst_bits;
}

mach_bits plat_ram_base(unit u)
{
return rv_ram_base;
}

mach_bits plat_ram_size(unit u)
{
return rv_ram_size;
}

mach_bits plat_rom_base(unit u)
{
return rv_rom_base;
}

mach_bits plat_rom_size(unit u)
{
return rv_rom_size;
}

mach_bits plat_cache_block_size_exp()
{
return rv_cache_block_size_exp;
}

// Provides entropy for the scalar cryptography extension.
mach_bits plat_get_16_random_bits(unit u)
{
return rv_16_random_bits();
}

mach_bits plat_clint_base(unit u)
{
return rv_clint_base;
}

mach_bits plat_clint_size(unit u)
{
return rv_clint_size;
}

unit load_reservation(mach_bits addr)
{
reservation = addr;
Expand Down Expand Up @@ -205,8 +65,6 @@ unit plat_term_write(mach_bits s)
return UNIT;
}

void plat_insns_per_tick(sail_int *rop, unit u) { }

mach_bits plat_htif_tohost(unit u)
{
return rv_htif_tohost;
Expand Down
40 changes: 1 addition & 39 deletions c_emulator/riscv_platform.h
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Original file line number Diff line number Diff line change
@@ -1,54 +1,16 @@
#pragma once
#include "sail.h"

bool sys_enable_rvc(unit);
bool sys_enable_fdext(unit);
bool sys_enable_svinval(unit);
bool sys_enable_zcb(unit);
bool sys_enable_zfinx(unit);
bool sys_enable_writable_misa(unit);
bool sys_enable_writable_fiom(unit);
bool sys_enable_vext(unit);
bool sys_enable_bext(unit);
bool sys_enable_zicbom(unit);
bool sys_enable_zicboz(unit);
bool sys_enable_sstc(unit);

uint64_t sys_pmp_count(unit);
uint64_t sys_pmp_grain(unit);

bool sys_vext_vl_use_ceil(unit);
uint64_t sys_vector_vlen_exp(unit);
uint64_t sys_vector_elen_exp(unit);

bool plat_enable_dirty_update(unit);
bool plat_enable_misaligned_access(unit);
bool plat_mtval_has_illegal_inst_bits(unit);
mach_bits sys_writable_hpm_counters(unit u);

mach_bits plat_ram_base(unit);
mach_bits plat_ram_size(unit);
bool within_phys_mem(mach_bits, sail_int);

mach_bits plat_rom_base(unit);
mach_bits plat_rom_size(unit);

mach_bits plat_cache_block_size_exp(unit);

// Provides entropy for the scalar cryptography extension.
mach_bits plat_get_16_random_bits(unit);

mach_bits plat_clint_base(unit);
mach_bits plat_clint_size(unit);

bool speculate_conditional(unit);
unit load_reservation(mach_bits);
bool match_reservation(mach_bits);
unit cancel_reservation(unit);

void plat_insns_per_tick(sail_int *rop, unit);

unit plat_term_write(mach_bits);

mach_bits plat_htif_tohost(unit);

unit memea(mach_bits, sail_int);
40 changes: 0 additions & 40 deletions c_emulator/riscv_platform_impl.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2,42 +2,6 @@
#include <unistd.h>
#include <stdio.h>

/* Settings of the platform implementation, with common defaults. */
uint64_t rv_pmp_count = 0;
uint64_t rv_pmp_grain = 0;

uint64_t rv_vector_vlen_exp = 0x9;
uint64_t rv_vector_elen_exp = 0x6;

bool rv_enable_svinval = false;
bool rv_enable_zcb = false;
bool rv_enable_zfinx = false;
bool rv_enable_rvc = true;
bool rv_enable_writable_misa = true;
bool rv_enable_fdext = true;
bool rv_enable_vext = true;
bool rv_enable_bext = false;
bool rv_enable_zicbom = false;
bool rv_enable_zicboz = false;
bool rv_enable_sstc = false;

bool rv_enable_dirty_update = false;
bool rv_enable_misaligned = false;
bool rv_mtval_has_illegal_inst_bits = false;
bool rv_enable_writable_fiom = true;
uint64_t rv_writable_hpm_counters = 0xFFFFFFFF;

uint64_t rv_ram_base = UINT64_C(0x80000000);
uint64_t rv_ram_size = UINT64_C(0x80000000);

uint64_t rv_rom_base = UINT64_C(0x1000);
uint64_t rv_rom_size = UINT64_C(0x100);

bool rv_vext_vl_use_ceil = false;

// Default 64, which is mandated by RVA22.
uint64_t rv_cache_block_size_exp = UINT64_C(6);

// Provides entropy for the scalar cryptography extension.
uint64_t rv_16_random_bits(void)
{
Expand All @@ -53,11 +17,7 @@ uint64_t rv_16_random_bits(void)
return (uint64_t)val;
}

uint64_t rv_clint_base = UINT64_C(0x2000000);
uint64_t rv_clint_size = UINT64_C(0xc0000);

uint64_t rv_htif_tohost = UINT64_C(0x80001000);
uint64_t rv_insns_per_tick = UINT64_C(100);

int term_fd = 1; // set during startup
void plat_term_write_impl(char c)
Expand Down
41 changes: 0 additions & 41 deletions c_emulator/riscv_platform_impl.h
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Original file line number Diff line number Diff line change
Expand Up @@ -4,51 +4,10 @@
#include <stdint.h>
#include <stdio.h>

/* Settings of the platform implementation. */

#define DEFAULT_RSTVEC 0x00001000

extern uint64_t rv_pmp_count;
extern uint64_t rv_pmp_grain;

extern uint64_t rv_vector_vlen_exp;
extern uint64_t rv_vector_elen_exp;

extern bool rv_enable_svinval;
extern bool rv_enable_zcb;
extern bool rv_enable_zfinx;
extern bool rv_enable_rvc;
extern bool rv_enable_fdext;
extern bool rv_enable_vext;
extern bool rv_enable_bext;
extern bool rv_enable_zicbom;
extern bool rv_enable_zicboz;
extern bool rv_enable_sstc;
extern bool rv_enable_writable_misa;
extern bool rv_enable_dirty_update;
extern bool rv_enable_misaligned;
extern bool rv_mtval_has_illegal_inst_bits;
extern bool rv_enable_writable_fiom;
extern uint64_t rv_writable_hpm_counters;

extern uint64_t rv_ram_base;
extern uint64_t rv_ram_size;

extern uint64_t rv_rom_base;
extern uint64_t rv_rom_size;

extern uint64_t rv_cache_block_size_exp;

extern bool rv_vext_vl_use_ceil;

// Provides entropy for the scalar cryptography extension.
extern uint64_t rv_16_random_bits(void);

extern uint64_t rv_clint_base;
extern uint64_t rv_clint_size;

extern uint64_t rv_htif_tohost;
extern uint64_t rv_insns_per_tick;

extern FILE *trace_log;
extern int term_fd;
Expand Down
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