From 2217f9b6c9ff23f68250d5a00393539b63574733 Mon Sep 17 00:00:00 2001 From: Lin Sinan Date: Wed, 18 Aug 2021 22:29:24 +0300 Subject: [PATCH] fix wrong format of swap16 & add testcases --- gas/config/tc-riscv.c | 5 +++++ gas/testsuite/gas/riscv/insn-dsp.d | 2 ++ gas/testsuite/gas/riscv/insn-dsp.s | 2 ++ opcodes/riscv-dis.c | 1 + opcodes/riscv-opc.c | 2 +- 5 files changed, 11 insertions(+), 1 deletion(-) diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index 764ab7d460d8..6ca301d5bae3 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1106,6 +1106,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'Z': /* RS1, CSR number. */ case 'S': /* RS1, floating point. */ case 's': USE_BITS (OP_MASK_RS1, OP_SH_RS1); break; + case 'g': /* RS1 and RS2 are the same. */ case 'U': /* RS1 and RS2 are the same, floating point. */ USE_BITS (OP_MASK_RS1, OP_SH_RS1); /* Fall through. */ @@ -2586,6 +2587,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'd': /* Destination register. */ case 's': /* Source register. */ + case 'g': /* RS1 and RS2. */ case 't': /* Target register. */ case 'r': /* RS3 */ if (reg_lookup (&s, RCLASS_GPR, ®no)) @@ -2604,6 +2606,9 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case 'd': INSERT_OPERAND (RD, *ip, regno); break; + case 'g': + INSERT_OPERAND (RS1, *ip, regno); + /* Fall through. */ case 't': INSERT_OPERAND (RS2, *ip, regno); break; diff --git a/gas/testsuite/gas/riscv/insn-dsp.d b/gas/testsuite/gas/riscv/insn-dsp.d index ef0033b2a701..6c6d68cbf98f 100644 --- a/gas/testsuite/gas/riscv/insn-dsp.d +++ b/gas/testsuite/gas/riscv/insn-dsp.d @@ -98,6 +98,7 @@ Disassembly of section .text: [ ]+.*:[ ]+.*[ ]+clrs16[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+clz16[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+clo16[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+pkbt16[ ]+a1,a2,a2 [ ]+.*:[ ]+.*[ ]+smin8[ ]+a1,a2,a3 [ ]+.*:[ ]+.*[ ]+umin8[ ]+a1,a2,a3 [ ]+.*:[ ]+.*[ ]+smax8[ ]+a1,a2,a3 @@ -110,6 +111,7 @@ Disassembly of section .text: [ ]+.*:[ ]+.*[ ]+clrs8[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+clz8[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+clo8[ ]+a1,a2 +[ ]+.*:[ ]+.*[ ]+swap8[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+sunpkd810[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+sunpkd820[ ]+a1,a2 [ ]+.*:[ ]+.*[ ]+sunpkd830[ ]+a1,a2 diff --git a/gas/testsuite/gas/riscv/insn-dsp.s b/gas/testsuite/gas/riscv/insn-dsp.s index 95e4a0b5bd7a..08d75fa7340d 100644 --- a/gas/testsuite/gas/riscv/insn-dsp.s +++ b/gas/testsuite/gas/riscv/insn-dsp.s @@ -102,6 +102,7 @@ dsp: clrs16 a1, a2 clz16 a1, a2 clo16 a1, a2 + swap16 a1, a2 # Table 8. SIMD 8-bit Miscellaneous Instructions (12) smin8 a1, a2, a3 @@ -116,6 +117,7 @@ dsp: clrs8 a1, a2 clz8 a1, a2 clo8 a1, a2 + swap8 a1, a2 # Table 9. 8-bit Unpacking Instructions (10) sunpkd810 a1, a2 diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 66d9e3ce897f..e6b5cba205d0 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -298,6 +298,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info) print (info->stream, "0"); break; + case 'g': case 'b': case 's': if ((l & MASK_JALR) == MATCH_JALR) diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 68ea703c5d06..703f1372779d 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1023,7 +1023,7 @@ const struct riscv_opcode riscv_opcodes[] = {"sunpkd831", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD831, MASK_SUNPKD831, match_opcode, 0 }, {"sunpkd832", 0, INSN_CLASS_ZPN, "d,s", MATCH_SUNPKD832, MASK_SUNPKD832, match_opcode, 0 }, {"swap8", 0, INSN_CLASS_ZPN, "d,s", MATCH_SWAP8, MASK_SWAP8, match_opcode, 0 }, -{"swap16", 0, INSN_CLASS_ZPN, "d,s,t", MATCH_PKBT16, MASK_PKBT16, match_rs1_eq_rs2, INSN_ALIAS }, +{"swap16", 0, INSN_CLASS_ZPN, "d,g", MATCH_PKBT16, MASK_PKBT16, match_opcode, INSN_ALIAS }, {"uclip8", 0, INSN_CLASS_ZPN, "d,s,nds_i3u", MATCH_UCLIP8, MASK_UCLIP8, match_opcode, 0 }, {"uclip16", 0, INSN_CLASS_ZPN, "d,s,nds_i4u", MATCH_UCLIP16, MASK_UCLIP16, match_opcode, 0 }, {"uclip32", 0, INSN_CLASS_ZPN, "d,s,nds_i5u", MATCH_UCLIP32, MASK_UCLIP32, match_opcode, 0 },