remove minw, maxw and bpick

riscvarchive · Nov 9, 2021 · ebd2150 · ebd2150
1 parent e78ce2b
commit ebd2150
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Showing 11 changed files with 3 additions and 50 deletions.
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
@@ -1160,9 +1160,7 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length)
         char field_name[RVP_MAX_KEYWORD_LEN];
         if (parse_rvp_field (&p, field_name))
           {
-            if (strcmp (field_name, "nds_rc") == 0)
-        USE_BITS (OP_MASK_RC, OP_SH_RC);
-            else if (strcmp (field_name, "nds_rdp") == 0)
+            if (strcmp (field_name, "nds_rdp") == 0)
         USE_BITS (OP_MASK_RD, OP_SH_RD);
             else if (strcmp (field_name, "nds_rsp") == 0)
         USE_BITS (OP_MASK_RD, OP_SH_RS1);
@@ -2496,14 +2494,7 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr,
 		args++;
 		if (parse_rvp_field (&args, field_name))
 		  {
-		    if (strcmp (field_name, "nds_rc") == 0
-			&& reg_lookup (&s, RCLASS_GPR, &regno))
-		      {
-			INSERT_OPERAND (RC, *ip, regno);
-			args--;
-			continue;
-		      }
-		    else if (strcmp (field_name, "nds_rdp") == 0
+		    if (strcmp (field_name, "nds_rdp") == 0
 			     && reg_lookup (&s, RCLASS_GPR, &regno))
 		      {
 			if (xlen == 32 && (regno % 2) != 0)

diff --git a/gas/testsuite/gas/riscv/insn-dsp-zbpbo.d b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.d
@@ -11,13 +11,10 @@ Disassembly of section .text:
 [ 	]+.*:[ 	]+.*[ 	]+clz[ 	]+a1,a2
 [ 	]+.*:[ 	]+.*[ 	]+clz[ 	]+a1,a2
 [ 	]+.*:[ 	]+.*[ 	]+cmix[ 	]+a1,a2,a3,a4
-[ 	]+.*:[ 	]+.*[ 	]+cmix[ 	]+a0,a2,a1,a3
 [ 	]+.*:[ 	]+.*[ 	]+fsr[ 	]+a1,a2,a3,a4
 [ 	]+.*:[ 	]+.*[ 	]+fsri[ 	]+a1,a2,a3,0x5
 [ 	]+.*:[ 	]+.*[ 	]+max[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+min[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+max[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+min[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+packu[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a1,a2,a3

diff --git a/gas/testsuite/gas/riscv/insn-dsp-zbpbo.s b/gas/testsuite/gas/riscv/insn-dsp-zbpbo.s
@@ -2,13 +2,10 @@ dsp:
 	clz a1,a2
 	clz32 a1,a2
 	cmix a1,a2,a3,a4
-	bpick a0,a1,a3,a2
 	fsr a1,a2,a3,a4
 	fsri a1,a2,a3,5
 	max a1,a2,a3
 	min a1,a2,a3
-	maxw a1,a2,a3
-	minw a1,a2,a3
 	pack a1,a2,a3
 	packu a1,a2,a3
 	pktt16 a1,a2,a3

diff --git a/gas/testsuite/gas/riscv/insn-dsp.d b/gas/testsuite/gas/riscv/insn-dsp.d
@@ -239,11 +239,8 @@ Disassembly of section .text:
 [ 	]+.*:[ 	]+.*[ 	]+bitrevi[ 	]+a1,a2,5
 [ 	]+.*:[ 	]+.*[ 	]+wext[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+wexti[ 	]+a1,a2,5
-[ 	]+.*:[ 	]+.*[ 	]+bpick[ 	]+a1,a2,a3,a4
 [ 	]+.*:[ 	]+.*[ 	]+insb[ 	]+a1,a2,2
 [ 	]+.*:[ 	]+.*[ 	]+maddr32[ 	]+a2,a4,a6
-[ 	]+.*:[ 	]+.*[ 	]+maxw[ 	]+a2,a4,a6
-[ 	]+.*:[ 	]+.*[ 	]+minw[ 	]+a2,a4,a6
 [ 	]+.*:[ 	]+.*[ 	]+msubr32[ 	]+a2,a4,a6
 [ 	]+.*:[ 	]+.*[ 	]+mulr64[ 	]+a2,a4,a6
 [ 	]+.*:[ 	]+.*[ 	]+mulsr64[ 	]+a2,a4,a6

diff --git a/gas/testsuite/gas/riscv/insn-dsp.s b/gas/testsuite/gas/riscv/insn-dsp.s
@@ -277,13 +277,10 @@ dsp:
 	bitrevi   a1, a2, 5
 	wext      a1, a2, a3
 	wexti     a1, a2, 5
-	bpick     a1, a2, a3, a4
 	insb      a1, a2, 2
 
 	# New Instructions in ZPSF
 	maddr32   a2, a4, a6
-	maxw      a2, a4, a6
-	minw      a2, a4, a6
 	msubr32   a2, a4, a6
 	mulr64    a2, a4, a6
 	mulsr64   a2, a4, a6

diff --git a/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.d
@@ -9,12 +9,9 @@ Disassembly of section .text:
 
 0+000 <dsp64>:
 [ 	]+.*:[ 	]+.*[ 	]+cmix[ 	]+a1,a2,a3,a4
-[ 	]+.*:[ 	]+.*[ 	]+cmix[ 	]+a0,a2,a1,a3
 [ 	]+.*:[ 	]+.*[ 	]+fsrw[ 	]+a1,a2,a3,a4
 [ 	]+.*:[ 	]+.*[ 	]+max[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+min[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+max[ 	]+a1,a2,a3
-[ 	]+.*:[ 	]+.*[ 	]+min[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+packu[ 	]+a1,a2,a3
 [ 	]+.*:[ 	]+.*[ 	]+pack[ 	]+a1,a2,a3

diff --git a/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s b/gas/testsuite/gas/riscv/insn-dsp64-zbpbo.s
@@ -1,11 +1,8 @@
 dsp64:
 	cmix a1,a2,a3,a4
-	bpick a0,a1,a3,a2
 	fsrw a1,a2,a3,a4
 	max a1,a2,a3
 	min a1,a2,a3
-	maxw a1,a2,a3
-	minw a1,a2,a3
 	pack a1,a2,a3
 	packu a1,a2,a3
 	pkbb32 a1,a2,a3

diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
@@ -634,8 +634,6 @@
 #define MASK_BITREV 0xfe00707f
 #define MATCH_BITREVI 0xe8000077
 #define MASK_BITREVI 0xfc00707f
-#define MATCH_BPICK 0x3077
-#define MASK_BPICK 0x600707f
 #define MATCH_CLRS8 0xae000077
 #define MASK_CLRS8 0xfff0707f
 #define MATCH_CLRS16 0xae800077
@@ -810,10 +808,6 @@
 #define MASK_MTLEI 0xfe00707f
 #define MATCH_MADDR32 0xc4001077
 #define MASK_MADDR32 0xfe00707f
-#define MATCH_MAXW 0xf2000077
-#define MASK_MAXW 0xfe00707f
-#define MATCH_MINW 0xf0000077
-#define MASK_MINW 0xfe00707f
 #define MATCH_MSUBR32 0xc6001077
 #define MASK_MSUBR32 0xfe00707f
 #define MATCH_MULR64 0xf0001077
@@ -1831,7 +1825,6 @@ DECLARE_INSN(add64, MATCH_ADD64, MASK_ADD64)
 DECLARE_INSN(ave, MATCH_AVE, MASK_AVE)
 DECLARE_INSN(bitrev, MATCH_BITREV, MASK_BITREV)
 DECLARE_INSN(bitrevi, MATCH_BITREVI, MASK_BITREVI)
-DECLARE_INSN(bpick, MATCH_BPICK, MASK_BPICK)
 DECLARE_INSN(clrs8, MATCH_CLRS8, MASK_CLRS8)
 DECLARE_INSN(clrs16, MATCH_CLRS16, MASK_CLRS16)
 DECLARE_INSN(clrs32, MATCH_CLRS32, MASK_CLRS32)
@@ -1918,8 +1911,6 @@ DECLARE_INSN(ksubw, MATCH_KSUBW, MASK_KSUBW)
 DECLARE_INSN(kwmmul, MATCH_KWMMUL, MASK_KWMMUL)
 DECLARE_INSN(kwmmul_u, MATCH_KWMMUL_U, MASK_KWMMUL_U)
 DECLARE_INSN(maddr32, MATCH_MADDR32, MASK_MADDR32)
-DECLARE_INSN(maxw, MATCH_MAXW, MASK_MAXW)
-DECLARE_INSN(minw, MATCH_MINW, MASK_MINW)
 DECLARE_INSN(msubr32, MATCH_MSUBR32, MASK_MSUBR32)
 DECLARE_INSN(mulr64, MATCH_MULR64, MASK_MULR64)
 DECLARE_INSN(mulsr64, MATCH_MULSR64, MASK_MULSR64)

diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
@@ -253,8 +253,6 @@ static const char * const riscv_pred_succ[16] =
 #define OP_SH_AQ		26
 #define OP_MASK_RL		0x1
 #define OP_SH_RL		25
-#define OP_MASK_RC		0x1f
-#define OP_SH_RC		27
 
 #define OP_MASK_CSR		0xfffU
 #define OP_SH_CSR		20

diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
@@ -346,10 +346,7 @@ print_insn_args (const char *d, insn_t l, bfd_vma pc, disassemble_info *info)
 	    char field_name[RVP_MAX_KEYWORD_LEN];
 	    if (parse_rvp_field (&d, field_name))
 	      {
-		if (strcmp (field_name, "nds_rc") == 0)
-		  print (info->stream, "%s",
-			 riscv_gpr_names[EXTRACT_OPERAND (RC, l)]);
-		else if (strcmp (field_name, "nds_rdp") == 0)
+		if (strcmp (field_name, "nds_rdp") == 0)
 		  print (info->stream, "%s", riscv_gpr_names[rd]);
 		else if (strcmp (field_name, "nds_rsp") == 0)
 		  print (info->stream, "%s", riscv_gpr_names[rs1]);

diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
@@ -850,8 +850,6 @@ const struct riscv_opcode riscv_opcodes[] =
 {"ave",         0, INSN_CLASS_ZPN, "d,s,t",     MATCH_AVE, MASK_AVE, match_opcode, 0 },
 {"bitrev",      0, INSN_CLASS_ZPN, "d,s,t",     MATCH_BITREV, MASK_BITREV, match_opcode, 0 },
 {"bitrevi",     0, INSN_CLASS_ZPN, "d,s,l",     MATCH_BITREVI, MASK_BITREVI, match_opcode, 0 },
-{"bpick",       0, INSN_CLASS_ZBPBO, "d,s,r,t", MATCH_CMIX, MASK_CMIX, match_opcode, INSN_ALIAS },
-{"bpick",       0, INSN_CLASS_ZPN, "d,s,t,nds_rc", MATCH_BPICK, MASK_BPICK, match_opcode, 0 },
 {"clrs8",       0, INSN_CLASS_ZPN, "d,s",       MATCH_CLRS8, MASK_CLRS8, match_opcode, 0 },
 {"clrs16",      0, INSN_CLASS_ZPN, "d,s",       MATCH_CLRS16, MASK_CLRS16, match_opcode, 0 },
 {"clrs32",      0, INSN_CLASS_ZPN, "d,s",       MATCH_CLRS32, MASK_CLRS32, match_opcode, 0 },
@@ -939,10 +937,6 @@ const struct riscv_opcode riscv_opcodes[] =
 {"kwmmul",      0, INSN_CLASS_ZPN, "d,s,t",     MATCH_KWMMUL, MASK_KWMMUL, match_opcode, 0 },
 {"kwmmul.u",    0, INSN_CLASS_ZPN, "d,s,t",     MATCH_KWMMUL_U, MASK_KWMMUL_U, match_opcode, 0 },
 {"maddr32",     0, INSN_CLASS_ZPN, "d,s,t",     MATCH_MADDR32, MASK_MADDR32, match_opcode, 0 },
-{"maxw",        0, INSN_CLASS_ZBPBO, "d,s,t",   MATCH_MAX, MASK_MAX, match_opcode, INSN_ALIAS },
-{"maxw",        0, INSN_CLASS_ZPN, "d,s,t",     MATCH_MAXW, MASK_MAXW, match_opcode, 0 },
-{"minw",        0, INSN_CLASS_ZBPBO, "d,s,t",   MATCH_MIN, MASK_MIN, match_opcode, INSN_ALIAS },
-{"minw",        0, INSN_CLASS_ZPN, "d,s,t",     MATCH_MINW, MASK_MINW, match_opcode, 0 },
 {"msubr32",     0, INSN_CLASS_ZPN, "d,s,t",     MATCH_MSUBR32, MASK_MSUBR32, match_opcode, 0 },
 {"mulr64",      0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULR64, MASK_MULR64, match_opcode, 0 },
 {"mulsr64",     0, INSN_CLASS_ZPSF, "nds_rdp,s,t", MATCH_MULSR64, MASK_MULSR64, match_opcode, 0 },