From 24e00b68c9737fd4db754c826a160eb30a2faa40 Mon Sep 17 00:00:00 2001 From: beeman Date: Tue, 27 Feb 2024 16:13:28 -0800 Subject: [PATCH] add backticks to register names --- body.adoc | 176 +++++++++++++++++++++++++++--------------------------- 1 file changed, 88 insertions(+), 88 deletions(-) diff --git a/body.adoc b/body.adoc index f40f61d..9683360 100644 --- a/body.adoc +++ b/body.adoc @@ -4,52 +4,52 @@ [width="100%",cols="15%,12%,12%,15%,46%",options="header",] |=== |*Number* |*Privilege* |*Width* |*Name* |*Description* -|0x350 |MRW |XLEN |miselect |Machine indirect register select -|0x351 |MRW |XLEN |mireg |Machine indirect register alias -|0x352 |MRW |XLEN |mireg2 |Machine indirect register alias 2 -|0x353 |MRW |XLEN |mireg3 |Machine indirect register alias 3 -|0x355 |MRW |XLEN |mireg4 |Machine indirect register alias 4 -|0x356 |MRW |XLEN |mireg5 |Machine indirect register alias 5 -|0x357 |MRW |XLEN |mireg6 |Machine indirect register alias 6 +|0x350 |MRW |XLEN |`miselect` |Machine indirect register select +|0x351 |MRW |XLEN |`mireg` |Machine indirect register alias +|0x352 |MRW |XLEN |`mireg2` |Machine indirect register alias 2 +|0x353 |MRW |XLEN |`mireg3` |Machine indirect register alias 3 +|0x355 |MRW |XLEN |`mireg4` |Machine indirect register alias 4 +|0x356 |MRW |XLEN |`mireg5` |Machine indirect register alias 5 +|0x357 |MRW |XLEN |`mireg6` |Machine indirect register alias 6 |=== [NOTE] [%unbreakable] ==== -_The mireg* CSR numbers are not consecutive because miph is CSR number +_The `mireg*` CSR numbers are not consecutive because miph is CSR number 0x354._ ==== The CSRs listed in the table above provide a window for accessing -register state indirectly. The value of miselect determines which +register state indirectly. The value of `miselect` determines which register is accessed upon read or write of each of the machine indirect alias -CSRs (mireg*). miselect value ranges are allocated to dependent +CSRs (`mireg*`). `miselect` value ranges are allocated to dependent extensions, which specify the register state accessible via each -mireg__i__ register, for each miselect value. miselect is a WARL +`mireg__i__` register, for each `miselect` value. `miselect` is a WARL register. -The miselect register implements at least enough bits to support all -implemented miselect values (corresponding to the implemented extensions -that utilize miselect/mireg* to indirectly access register state). The -miselect register may be read-only zero if there are no extensions +The `miselect` register implements at least enough bits to support all +implemented `miselect` values (corresponding to the implemented extensions +that utilize `miselect`/`mireg*` to indirectly access register state). The +`miselect` register may be read-only zero if there are no extensions implemented that utilize it. -Values of miselect with the most-significant bit set (bit XLEN - 1 = 1) +Values of `miselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom -registers through the alias CSRs. Values of miselect with the +registers through the alias CSRs. Values of `miselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN -is changed, the most-significant bit of miselect moves to the new +is changed, the most-significant bit of `miselect` moves to the new position, retaining its value from before. [NOTE] [%unbreakable] ==== _An implementation is not required to support any custom values for -miselect._ +`miselect`._ ==== -The behavior upon accessing mireg* from M-mode, while miselect holds a +The behavior upon accessing `mireg*` from M-mode, while `miselect` holds a value that is not implemented, is UNSPECIFIED. [NOTE] @@ -62,23 +62,23 @@ the Privileged ISA spec may place more restrictions on behavior for such accesses._ ==== -Attempts to access mireg* while miselect holds a number in an allocated +Attempts to access `mireg*` while `miselect` holds a number in an allocated and implemented range results in a specific behavior that, for each -combination of miselect and mireg__i__, is defined by the extension to -which the miselect value is allocated. +combination of `miselect` and `mireg__i__`, is defined by the extension to +which the `miselect` value is allocated. [NOTE] [%unbreakable] ==== -__Ordinarily, each mireg__i _will access register state, access +_Ordinarily, each_ `__mireg__i` _will access register state, access read-only 0 state, or raise an illegal instruction exception._ -_For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is recommended that the lower 32 bits of the register are accessed through one of mireg, mireg2, or mireg3, while the upper 32 bits are accessed through mireg4, mireg5, or mireg6, respectively._ +_For RV32, if an extension defines an indirectly accessed register as 64 bits wide, it is recommended that the lower 32 bits of the register are accessed through one of `mireg`, `mireg2`, or `mireg3`, while the upper 32 bits are accessed through `mireg4`, `mireg5`, or `mireg6`, respectively._ ==== [NOTE] [%unbreakable] ==== -_Six \*ireg* registers are defined in order to ensure that the needs of extensions in development are covered, with some room for growth. For example, for an siselect value associated with counter X, sireg/sireg2 could be used to access mhpmcounterX/mhpmeventX, while sireg4/sireg5 could access mhpmcounterXh/mhpmeventXh. Six \*ireg* registers allows for accessing up to 3 CSR arrays per index (*iselect) with RV32-only CSRs, or up to 6 CSR arrays per index value without RV32-only CSRs._ +_Six `\*ireg*` registers are defined in order to ensure that the needs of extensions in development are covered, with some room for growth. For example, for an `siselect` value associated with counter X, `sireg`/`sireg2` could be used to access `mhpmcounterX`/`mhpmeventX`, while `sireg4`/`sireg5` could access `mhpmcounterXh`/`mhpmeventXh`. Six `\*ireg*` registers allows for accessing up to 3 CSR arrays per index (`*iselect`) with RV32-only CSRs, or up to 6 CSR arrays per index value without RV32-only CSRs._ ==== @@ -87,40 +87,40 @@ _Six \*ireg* registers are defined in order to ensure that the needs of extensio [width="100%",cols="15%,12%,12%,15%,46%",options="header",] |=== |*Number* |*Privilege* |*Width* |*Name* |*Description* -|0x150 |SRW |XLEN |siselect |Supervisor indirect register select -|0x151 |SRW |XLEN |sireg |Supervisor indirect register alias -|0x152 |SRW |XLEN |sireg2 |Supervisor indirect register alias 2 -|0x153 |SRW |XLEN |sireg3 |Supervisor indirect register alias 3 -|0x155 |SRW |XLEN |sireg4 |Supervisor indirect register alias 4 -|0x156 |SRW |XLEN |sireg5 |Supervisor indirect register alias 5 -|0x157 |SRW |XLEN |sireg6 |Supervisor indirect register alias 6 +|0x150 |SRW |XLEN |`siselect` |Supervisor indirect register select +|0x151 |SRW |XLEN |`sireg` |Supervisor indirect register alias +|0x152 |SRW |XLEN |`sireg2` |Supervisor indirect register alias 2 +|0x153 |SRW |XLEN |`sireg3` |Supervisor indirect register alias 3 +|0x155 |SRW |XLEN |`sireg4` |Supervisor indirect register alias 4 +|0x156 |SRW |XLEN |`sireg5` |Supervisor indirect register alias 5 +|0x157 |SRW |XLEN |`sireg6` |Supervisor indirect register alias 6 |=== The CSRs in the table above are required if S-mode is implemented. -The siselect register will support the value range 0..0xFFF at a +The `siselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this -minimum range. Only if such an extension is implemented will siselect be +minimum range. Only if such an extension is implemented will `siselect` be required to support larger values. [NOTE] [%unbreakable] ==== -_Requiring a range of 0–0xFFF for siselect, even though most or +_Requiring a range of 0–0xFFF for `siselect`, even though most or all of the space may be reserved or inaccessible, permits M-mode to emulate indirectly accessed registers in this implemented range, including registers that may be standardized in the future._ ==== -Values of siselect with the most-significant bit set (bit XLEN - 1 = 1) +Values of `siselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias -CSRs. Values of siselect with the most-significant bit clear are +CSRs. Values of `siselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the -most-significant bit of siselect moves to the new position, retaining +most-significant bit of `siselect` moves to the new position, retaining its value from before. -The behavior upon accessing sireg* from M-mode or S-mode, while siselect +The behavior upon accessing `sireg*` from M-mode or S-mode, while `siselect` holds a value that is not implemented at supervisor level, is UNSPECIFIED. [NOTE] @@ -135,24 +135,24 @@ M-mode) of these accesses._ ==== _An extension is considered not to be implemented at supervisor level if machine level has disabled the extension for S-mode, such as by the -settings of certain fields in CSR menvcfg, for example._ +settings of certain fields in CSR `menvcfg`, for example._ ==== -Otherwise, attempts to access sireg* from M-mode or S-mode while -siselect holds a number in a standard-defined and implemented range -result in specific behavior that, for each combination of siselect and -sireg__i__, is defined by the extension to which the siselect value is +Otherwise, attempts to access `sireg*` from M-mode or S-mode while +`siselect` holds a number in a standard-defined and implemented range +result in specific behavior that, for each combination of `siselect` and +`sireg__i__`, is defined by the extension to which the `siselect` value is allocated. [NOTE] [%unbreakable] ==== -__Ordinarily, each sireg__i _will access register state, access +_Ordinarily, each_ `__sireg__i` _will access register state, access read-only 0 state, or, unless executing in a virtual machine (covered in the next section), raise an illegal instruction exception._ ==== -Note that the widths of siselect and sireg* are always the +Note that the widths of `siselect` and `sireg*` are always the current XLEN rather than SXLEN. Hence, for example, if MXLEN = 64 and SXLEN = 32, then these registers are 64 bits when the current privilege mode is M (running RV64 code) but 32 bits when the privilege mode is S @@ -163,20 +163,20 @@ mode is M (running RV64 code) but 32 bits when the privilege mode is S [width="100%",cols="15%,12%,12%,15%,46%",options="header",] |=== |*Number* |*Privilege* |*Width* |*Name* |*Description* -|0x250 |HRW |XLEN |vsiselect |Virtual supervisor indirect register +|0x250 |HRW |XLEN |`vsiselect` |Virtual supervisor indirect register select -|0x251 |HRW |XLEN |vsireg |Virtual supervisor indirect register alias +|0x251 |HRW |XLEN |`vsireg` |Virtual supervisor indirect register alias -|0x252 |HRW |XLEN |vsireg2 |Virtual supervisor indirect register alias 2 +|0x252 |HRW |XLEN |`vsireg2` |Virtual supervisor indirect register alias 2 -|0x253 |HRW |XLEN |vsireg3 |Virtual supervisor indirect register alias 3 +|0x253 |HRW |XLEN |`vsireg3` |Virtual supervisor indirect register alias 3 -|0x255 |HRW |XLEN |vsireg4 |Virtual supervisor indirect register alias 4 +|0x255 |HRW |XLEN |`vsireg4` |Virtual supervisor indirect register alias 4 -|0x256 |HRW |XLEN |vsireg5 |Virtual supervisor indirect register alias 5 +|0x256 |HRW |XLEN |`vsireg5` |Virtual supervisor indirect register alias 5 -|0x257 |HRW |XLEN |vsireg6 |Virtual supervisor indirect register alias 6 +|0x257 |HRW |XLEN |`vsireg6` |Virtual supervisor indirect register alias 6 |=== The CSRs in the table above are required if the hypervisor extension is @@ -184,44 +184,44 @@ implemented. These VS CSRs all match supervisor CSRs, and substitute for those supervisor CSRs when executing in a virtual machine (in VS-mode or VU-mode). -The vsiselect register will support the value range 0..0xFFF at a +The `vsiselect` register will support the value range 0..0xFFF at a minimum. A future extension may define a value range outside of this -minimum range. Only if such an extension is implemented will vsiselect +minimum range. Only if such an extension is implemented will `vsiselect` be required to support larger values. [NOTE] [%unbreakable] ==== -_Requiring a range of 0–0xFFF for vsiselect, even though most or all of +_Requiring a range of 0–0xFFF for `vsiselect`, even though most or all of the space may be reserved or inaccessible, permits a hypervisor to emulate indirectly accessed registers in this implemented range, including registers that may be standardized in the future._ -_More generally it is recommended that vsiselect and siselect be +_More generally it is recommended that `vsiselect` and `siselect` be implemented with the same number of bits. This also avoids creation of a -virtualization hole due to observable differences between vsiselect and -siselect widths._ +virtualization hole due to observable differences between `vsiselect` and +`siselect` widths._ ==== -Values of vsiselect with the most-significant bit set (bit XLEN - 1 = 1) +Values of `vsiselect` with the most-significant bit set (bit XLEN - 1 = 1) are designated only for custom use, presumably for accessing custom registers through the alias -CSRs. Values of vsiselect with the most-significant bit clear are +CSRs. Values of `vsiselect` with the most-significant bit clear are designated only for standard use and are reserved until allocated to a standard architecture extension. If XLEN is changed, the -most-significant bit of vsiselect moves to the new position, retaining +most-significant bit of `vsiselect` moves to the new position, retaining its value from before. -For alias CSRs sireg* and vsireg*, the hypervisor extension’s usual +For alias CSRs `sireg*` and `vsireg*`, the hypervisor extension’s usual rules for when to raise a virtual instruction exception (based on whether an instruction is HS-qualified) are not applicable. The -rules given in this section for sireg and vsireg apply instead, unless +rules given in this section for `sireg` and `vsireg` apply instead, unless overridden by the requirements specified in the section below, which take precedence over this section when extension Smstateen is also implemented. -A virtual instruction exception is raised for attempts from VS-mode or VU-mode to directly access vsiselect or vsireg*, or attempts from VU-mode to access siselect or sireg*. +A virtual instruction exception is raised for attempts from VS-mode or VU-mode to directly access `vsiselect` or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`. -The behavior upon accessing vsireg* from M-mode or HS-mode, or accessing sireg* (really vsireg*) from VS-mode, while vsiselect holds a value that is not implemented at HS level, is UNSPECIFIED. +The behavior upon accessing `vsireg*` from M-mode or HS-mode, or accessing `sireg*` (really `vsireg*`) from VS-mode, while `vsiselect` holds a value that is not implemented at HS level, is UNSPECIFIED. [NOTE] [%unbreakable] @@ -229,20 +229,20 @@ The behavior upon accessing vsireg* from M-mode or HS-mode, or accessing sireg* _It is recommended that implementations raise an illegal instruction exception for such accesses, to facilitate possible emulation (by M-mode) of these accesses._ ==== -Otherwise, while vsiselect holds a number in a standard-defined and -implemented range, attempts to access vsireg* from a sufficiently -privileged mode, or to access sireg* (really vsireg*) from VS-mode, -result in specific behavior that, for each combination of vsiselect and -vsireg__i__, is defined by the extension to which the vsiselect value is +Otherwise, while `vsiselect` holds a number in a standard-defined and +implemented range, attempts to access `vsireg*` from a sufficiently +privileged mode, or to access `sireg*` (really `vsireg*`) from VS-mode, +result in specific behavior that, for each combination of `vsiselect` and +`vsireg__i__`, is defined by the extension to which the `vsiselect` value is allocated. [NOTE] [%unbreakable] ==== -__Ordinarily, each vsireg__i _will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When vsiselect holds a value that is implemented at HS level but not at VS level, attempts to access sireg* (really vsireg*) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate._ +_Ordinarily, each_ `__vsireg__i` _will access register state, access read-only 0 state, or raise an exception (either an illegal instruction exception or, for select accesses from VS-mode, a virtual instruction exception). When `vsiselect` holds a value that is implemented at HS level but not at VS level, attempts to access `sireg*` (really `vsireg*`) from VS-mode will typically raise a virtual instruction exception. But there may be cases specific to an extension where different behavior is more appropriate._ ==== -Like siselect and sireg*, the widths of vsiselect and vsireg* are always +Like `siselect` and `sireg*`, the widths of `vsiselect` and `vsireg*` are always the current XLEN rather than VSXLEN. Hence, for example, if HSXLEN = 64 and VSXLEN = 32, then these registers are 64 bits when accessed by a hypervisor in HS-mode (running RV64 code) but 32 bits for a guest OS in @@ -251,8 +251,8 @@ VS-mode (RV32 code). == Access control by the state-enable CSRs If extension Smstateen is implemented together with Smcsrind, bit 60 of -state-enable register mstateen0 controls access to siselect, sireg*, -vsiselect, and vsireg*. When mstateen0[60]=0, an attempt to access one +state-enable register `mstateen0` controls access to `siselect`, `sireg*`, +`vsiselect`, and `vsireg*`. When `mstateen0`[60]=0, an attempt to access one of these CSRs from a privilege mode less privileged than M-mode results in an illegal instruction exception. As always, the state-enable CSRs do not affect the accessibility of any state when in M-mode, only in less @@ -261,26 +261,26 @@ extension https://github.com/riscv/riscv-state-enable/releases/download/v1.0.0/Smstateen.pdf[[.underline]#Smstateen#]. Other extensions may specify that certain mstateen bits control access -to registers accessed indirectly through siselect + sireg*, and/or -vsiselect + vsireg*. However, regardless of any other mstateen bits, if -mstateen0[60] = 1, a virtual instruction exception is raised as +to registers accessed indirectly through `siselect` + `sireg*`, and/or +`vsiselect` + `vsireg*`. However, regardless of any other mstateen bits, if +`mstateen0`[60] = 1, a virtual instruction exception is raised as described in the previous section for all attempts from VS-mode or -VU-mode to directly access vsiselect or vsireg*, and for all attempts -from VU-mode to access siselect or sireg*. +VU-mode to directly access `vsiselect` or `vsireg*`, and for all attempts +from VU-mode to access `siselect` or `sireg*`. If the hypervisor extension is implemented, the same bit is defined also -in hypervisor CSR hstateen0, but controls access to only siselect and sireg* -(really vsiselect and vsireg*), which is the state potentially +in hypervisor CSR `hstateen0`, but controls access to only `siselect` and `sireg*` +(really `vsiselect` and `vsireg*`), which is the state potentially accessible to a virtual machine executing in VS or VU-mode. When -hstateen0[60]=0 and mstateen0[60]=1, all attempts from VS or VU-mode to -access siselect or sireg* raise a virtual instruction exception, not an -illegal instruction exception, regardless of the value of vsiselect or +`hstateen0`[60]=0 and `mstateen0`[60]=1, all attempts from VS or VU-mode to +access `siselect` or `sireg*` raise a virtual instruction exception, not an +illegal instruction exception, regardless of the value of `vsiselect` or any other mstateen bit. Extension Ssstateen is defined as the supervisor-level view of Smstateen. Therefore, the combination of Sscsrind and Ssstateen -incorporates the bit defined above for hstateen0 but not that for -mstateen0, since machine-level CSRs are not visible to supervisor level. +incorporates the bit defined above for `hstateen0` but not that for +`mstateen0`, since machine-level CSRs are not visible to supervisor level. [NOTE] ====