Skip to content

Commit d004022

Browse files
committed
Sync from rust cdd545be1b4f024d38360aa9f000dcb782fbc81b
2 parents 4e3bf2d + 83be7a8 commit d004022

File tree

5 files changed

+12
-13
lines changed

5 files changed

+12
-13
lines changed

example/neon.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -233,7 +233,7 @@ unsafe fn test_vaddvq_f32() {
233233

234234
#[cfg(target_arch = "aarch64")]
235235
unsafe fn test_vrndnq_f32() {
236-
// AArch64 llvm intrinsic: llvm.aarch64.neon.frintn.v4f32
236+
// llvm intrinsic: llvm.roundeven.v4f32
237237
let a = f32x4::from([0.1, -1.9, 4.5, 5.5]);
238238
let e = f32x4::from([0., -2., 4., 6.]);
239239
let r: f32x4 = transmute(vrndnq_f32(transmute(a)));

src/inline_asm.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -850,7 +850,7 @@ fn asm_clif_type<'tcx>(fx: &FunctionCx<'_, '_, 'tcx>, ty: Ty<'tcx>) -> Option<ty
850850
// Adapted from https://github.com/rust-lang/rust/blob/f3c66088610c1b80110297c2d9a8b5f9265b013f/compiler/rustc_hir_analysis/src/check/intrinsicck.rs#L136-L151
851851
ty::Adt(adt, args) if fx.tcx.is_lang_item(adt.did(), LangItem::MaybeUninit) => {
852852
let fields = &adt.non_enum_variant().fields;
853-
let ty = fields[FieldIdx::from_u32(1)].ty(fx.tcx, args);
853+
let ty = fields[FieldIdx::ONE].ty(fx.tcx, args);
854854
let ty::Adt(ty, args) = ty.kind() else {
855855
unreachable!("expected first field of `MaybeUninit` to be an ADT")
856856
};

src/intrinsics/llvm.rs

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -62,6 +62,14 @@ pub(crate) fn codegen_llvm_intrinsic_call<'tcx>(
6262
});
6363
}
6464

65+
_ if intrinsic.starts_with("llvm.roundeven.v") => {
66+
intrinsic_args!(fx, args => (v); intrinsic);
67+
68+
simd_for_each_lane(fx, v, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
69+
fx.bcx.ins().nearest(lane)
70+
});
71+
}
72+
6573
_ => {
6674
fx.tcx
6775
.dcx()

src/intrinsics/llvm_aarch64.rs

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -264,14 +264,6 @@ pub(super) fn codegen_aarch64_llvm_intrinsic_call<'tcx>(
264264
simd_reduce(fx, v, None, ret, &|fx, _ty, a, b| fx.bcx.ins().fadd(a, b));
265265
}
266266

267-
_ if intrinsic.starts_with("llvm.aarch64.neon.frintn.v") => {
268-
intrinsic_args!(fx, args => (v); intrinsic);
269-
270-
simd_for_each_lane(fx, v, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
271-
fx.bcx.ins().nearest(lane)
272-
});
273-
}
274-
275267
_ if intrinsic.starts_with("llvm.aarch64.neon.smaxv.i") => {
276268
intrinsic_args!(fx, args => (v); intrinsic);
277269

src/vtable.rs

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -53,7 +53,7 @@ pub(crate) fn get_ptr_and_method_ref<'tcx>(
5353
.layout()
5454
.non_1zst_field(fx)
5555
.expect("not exactly one non-1-ZST field in a `DispatchFromDyn` type");
56-
arg = arg.value_field(fx, FieldIdx::new(idx));
56+
arg = arg.value_field(fx, idx);
5757
}
5858
}
5959

@@ -62,8 +62,7 @@ pub(crate) fn get_ptr_and_method_ref<'tcx>(
6262
let inner_layout = fx.layout_of(arg.layout().ty.builtin_deref(true).unwrap());
6363
let dyn_star = CPlace::for_ptr(Pointer::new(arg.load_scalar(fx)), inner_layout);
6464
let ptr = dyn_star.place_field(fx, FieldIdx::ZERO).to_ptr();
65-
let vtable =
66-
dyn_star.place_field(fx, FieldIdx::new(1)).to_cvalue(fx).load_scalar(fx);
65+
let vtable = dyn_star.place_field(fx, FieldIdx::ONE).to_cvalue(fx).load_scalar(fx);
6766
break 'block (ptr, vtable);
6867
}
6968
}

0 commit comments

Comments
 (0)