From 27ddb52ff6ff719b14f3b61d5b02493127ddafa3 Mon Sep 17 00:00:00 2001 From: Adam Gemmell Date: Wed, 25 Oct 2023 14:04:37 +0100 Subject: [PATCH 1/8] Add SVE support to stdarch-verify Co-authored-by: Jamie Cunliffe Co-authored-by: Jacob Bramley Co-authored-by: Luca Vizzarro --- crates/stdarch-verify/src/lib.rs | 88 +- crates/stdarch-verify/tests/arm.rs | 182 +- intrinsics_data/arm_intrinsics.json | 190680 ++++++++++++++++++++++++- vendor.yml | 3 +- 4 files changed, 190889 insertions(+), 64 deletions(-) diff --git a/crates/stdarch-verify/src/lib.rs b/crates/stdarch-verify/src/lib.rs index 5e4db96a70..c53f1e6297 100644 --- a/crates/stdarch-verify/src/lib.rs +++ b/crates/stdarch-verify/src/lib.rs @@ -45,7 +45,9 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { for &mut (ref mut file, ref path) in &mut files { for mut item in file.items.drain(..) { match item { - syn::Item::Fn(f) => functions.push((f, path)), + syn::Item::Fn(f) => { + functions.push((f, path)); + } syn::Item::Mod(ref mut m) => { if let Some(ref mut m) = m.content { for i in m.1.drain(..) { @@ -71,12 +73,9 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { assert!(!tests.is_empty()); functions.retain(|(f, _)| { - if let syn::Visibility::Public(_) = f.vis { - if f.sig.unsafety.is_some() { - return true; - } - } - false + matches!(f.vis, syn::Visibility::Public(_)) + // Many SVE intrinsics are safe + && (f.sig.unsafety.is_some() || f.sig.ident.to_string().starts_with("sv")) }); assert!(!functions.is_empty()); @@ -99,7 +98,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { for generic in f.sig.generics.params.iter() { match *generic { syn::GenericParam::Const(ref c) => const_arguments.push(to_type(&c.ty)), - syn::GenericParam::Type(ref _t) => (), + syn::GenericParam::Type(_) => (), _ => panic!("invalid generic argument on {name}"), }; } @@ -118,25 +117,31 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { }; let required_const = find_required_const("rustc_args_required_const", &f.attrs); - let mut legacy_const_generics = + let mut const_generics_indices = find_required_const("rustc_legacy_const_generics", &f.attrs); - if !required_const.is_empty() && !legacy_const_generics.is_empty() { + if !required_const.is_empty() && !const_generics_indices.is_empty() { panic!( "Can't have both #[rustc_args_required_const] and \ #[rustc_legacy_const_generics]" ); } + // Newer intrinsics don't have legacy support - assume they belong at the end of the argument list + if required_const.is_empty() && const_generics_indices.is_empty() { + const_generics_indices = + (arguments.len()..(arguments.len() + const_arguments.len())).collect(); + } + // The list of required consts, used to verify the arguments, comes from either the // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. let required_const = if required_const.is_empty() { - legacy_const_generics.clone() + const_generics_indices.clone() } else { required_const }; - legacy_const_generics.sort(); - for (idx, ty) in legacy_const_generics + const_generics_indices.sort(); + for (idx, ty) in const_generics_indices .into_iter() .zip(const_arguments.into_iter()) { @@ -145,12 +150,12 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { // strip leading underscore from fn name when building a test // _mm_foo -> mm_foo such that the test name is test_mm_foo. - let test_name_string = format!("{name}"); - let mut test_name_id = test_name_string.as_str(); - while test_name_id.starts_with('_') { - test_name_id = &test_name_id[1..]; - } - let has_test = tests.contains(&format!("test_{test_name_id}")); + let test_name = name.to_string(); + let test_name_id = test_name.trim_start_matches('_'); + let has_test = tests.contains(&format!("test_{test_name_id}")) + // SVE load/store tests + || tests.iter().any(|t| t.starts_with(&format!("test_{test_name_id}")) + || t.ends_with(&format!("_with_{test_name_id}"))); let doc = find_doc(&f.attrs); @@ -221,8 +226,53 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "p16" => quote! { &P16 }, "Ordering" => quote! { &ORDERING }, "CpuidResult" => quote! { &CPUID }, + "T" => quote! { &GENERICT }, // arm ... + "svbool_t" => quote! { &SVBOOL }, + "svint8_t" => quote! { &SVI8 }, + "svint8x2_t" => quote! { &SVI8X2 }, + "svint8x3_t" => quote! { &SVI8X3 }, + "svint8x4_t" => quote! { &SVI8X4 }, + "svint16_t" => quote! { &SVI16 }, + "svint16x2_t" => quote! { &SVI16X2 }, + "svint16x3_t" => quote! { &SVI16X3 }, + "svint16x4_t" => quote! { &SVI16X4 }, + "svint32_t" => quote! { &SVI32 }, + "svint32x2_t" => quote! { &SVI32X2 }, + "svint32x3_t" => quote! { &SVI32X3 }, + "svint32x4_t" => quote! { &SVI32X4 }, + "svint64_t" => quote! { &SVI64 }, + "svint64x2_t" => quote! { &SVI64X2 }, + "svint64x3_t" => quote! { &SVI64X3 }, + "svint64x4_t" => quote! { &SVI64X4 }, + "svuint8_t" => quote! { &SVU8 }, + "svuint8x2_t" => quote! { &SVU8X2 }, + "svuint8x3_t" => quote! { &SVU8X3 }, + "svuint8x4_t" => quote! { &SVU8X4 }, + "svuint16_t" => quote! { &SVU16 }, + "svuint16x2_t" => quote! { &SVU16X2 }, + "svuint16x3_t" => quote! { &SVU16X3 }, + "svuint16x4_t" => quote! { &SVU16X4 }, + "svuint32_t" => quote! { &SVU32 }, + "svuint32x2_t" => quote! { &SVU32X2 }, + "svuint32x3_t" => quote! { &SVU32X3 }, + "svuint32x4_t" => quote! { &SVU32X4 }, + "svuint64_t" => quote! { &SVU64 }, + "svuint64x2_t" => quote! { &SVU64X2 }, + "svuint64x3_t" => quote! { &SVU64X3 }, + "svuint64x4_t" => quote! { &SVU64X4 }, + "svfloat32_t" => quote! { &SVF32 }, + "svfloat32x2_t" => quote! { &SVF32X2 }, + "svfloat32x3_t" => quote! { &SVF32X3 }, + "svfloat32x4_t" => quote! { &SVF32X4 }, + "svfloat64_t" => quote! { &SVF64 }, + "svfloat64x2_t" => quote! { &SVF64X2 }, + "svfloat64x3_t" => quote! { &SVF64X3 }, + "svfloat64x4_t" => quote! { &SVF64X4 }, + "svprfop" => quote! { &SVPRFOP }, + "svpattern" => quote! { &SVPATTERN }, + "int8x4_t" => quote! { &I8X4 }, "int8x8_t" => quote! { &I8X8 }, "int8x8x2_t" => quote! { &I8X8X2 }, diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs index ac1d5793d0..fe51a6730c 100644 --- a/crates/stdarch-verify/tests/arm.rs +++ b/crates/stdarch-verify/tests/arm.rs @@ -27,6 +27,8 @@ static U16: Type = Type::PrimUnsigned(16); static U32: Type = Type::PrimUnsigned(32); static U64: Type = Type::PrimUnsigned(64); static U8: Type = Type::PrimUnsigned(8); +static BOOL: Type = Type::PrimBool; +static VOID: Type = Type::Void; static NEVER: Type = Type::Never; static GENERICT: Type = Type::GenericParam("T"); static GENERICU: Type = Type::GenericParam("U"); @@ -151,19 +153,70 @@ static U8X8X2: Type = Type::U(8, 8, 2); static U8X8X3: Type = Type::U(8, 8, 3); static U8X8X4: Type = Type::U(8, 8, 4); +static SVBOOL: Type = Type::Pred; +static SVF32: Type = Type::SVF(32, 1); +static SVF32X2: Type = Type::SVF(32, 2); +static SVF32X3: Type = Type::SVF(32, 3); +static SVF32X4: Type = Type::SVF(32, 4); +static SVF64: Type = Type::SVF(64, 1); +static SVF64X2: Type = Type::SVF(64, 2); +static SVF64X3: Type = Type::SVF(64, 3); +static SVF64X4: Type = Type::SVF(64, 4); +static SVI8: Type = Type::SVI(8, 1); +static SVI8X2: Type = Type::SVI(8, 2); +static SVI8X3: Type = Type::SVI(8, 3); +static SVI8X4: Type = Type::SVI(8, 4); +static SVI16: Type = Type::SVI(16, 1); +static SVI16X2: Type = Type::SVI(16, 2); +static SVI16X3: Type = Type::SVI(16, 3); +static SVI16X4: Type = Type::SVI(16, 4); +static SVI32: Type = Type::SVI(32, 1); +static SVI32X2: Type = Type::SVI(32, 2); +static SVI32X3: Type = Type::SVI(32, 3); +static SVI32X4: Type = Type::SVI(32, 4); +static SVI64: Type = Type::SVI(64, 1); +static SVI64X2: Type = Type::SVI(64, 2); +static SVI64X3: Type = Type::SVI(64, 3); +static SVI64X4: Type = Type::SVI(64, 4); +static SVU8: Type = Type::SVU(8, 1); +static SVU8X2: Type = Type::SVU(8, 2); +static SVU8X3: Type = Type::SVU(8, 3); +static SVU8X4: Type = Type::SVU(8, 4); +static SVU16: Type = Type::SVU(16, 1); +static SVU16X2: Type = Type::SVU(16, 2); +static SVU16X3: Type = Type::SVU(16, 3); +static SVU16X4: Type = Type::SVU(16, 4); +static SVU32: Type = Type::SVU(32, 1); +static SVU32X2: Type = Type::SVU(32, 2); +static SVU32X3: Type = Type::SVU(32, 3); +static SVU32X4: Type = Type::SVU(32, 4); +static SVU64: Type = Type::SVU(64, 1); +static SVU64X2: Type = Type::SVU(64, 2); +static SVU64X3: Type = Type::SVU(64, 3); +static SVU64X4: Type = Type::SVU(64, 4); +static SVPRFOP: Type = Type::Enum("svprfop"); +static SVPATTERN: Type = Type::Enum("svpattern"); + #[derive(Debug, Copy, Clone, PartialEq)] enum Type { + Void, + PrimBool, PrimFloat(u8), PrimSigned(u8), PrimUnsigned(u8), PrimPoly(u8), MutPtr(&'static Type), ConstPtr(&'static Type), + Enum(&'static str), GenericParam(&'static str), I(u8, u8, u8), U(u8, u8, u8), P(u8, u8, u8), F(u8, u8, u8), + Pred, + SVI(u8, u8), + SVU(u8, u8), + SVF(u8, u8), Never, } @@ -182,6 +235,7 @@ fn verify_all_signatures() { let mut all_valid = true; for rust in FUNCTIONS { + // Most SVE intrinsics just rely on the intrinsics test tool for validation if !rust.has_test { let skip = [ "vaddq_s64", @@ -407,18 +461,16 @@ fn verify_all_signatures() { "__clrex", "__dbg", ]; - if !skip.contains(&rust.name) { - println!( - "missing run-time test named `test_{}` for `{}`", - { - let mut id = rust.name; - while id.starts_with('_') { - id = &id[1..]; - } - id - }, - rust.name - ); + if !skip.contains(&rust.name) + // Most run-time tests are handled by the intrinsic-test tool, except for + // load/stores (which have generated tests) + && (!rust.name.starts_with("sv") || rust.name.starts_with("svld") + || rust.name.starts_with("svst")) + // The load/store test generator can't handle these cases yet + && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset")) + && !(rust.name.starts_with("svldff1") && rust.name.contains("gather")) + { + println!("missing run-time test for `{}`", rust.name); all_valid = false; } } @@ -493,12 +545,21 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { let mut nconst = 0; let iter = rust.arguments.iter().zip(&arm.arguments).enumerate(); for (i, (rust_ty, (arm, arm_const))) in iter { - if *rust_ty != arm { - bail!("mismatched arguments: {rust_ty:?} != {arm:?}") + match (*rust_ty, arm) { + // SVE uses generic type parameters to handle void pointers + (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), + // SVE const generics use i32 over u64 for usability reasons + (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { + () + } + // svset doesn't have its const argument last as we assumed when building the Function + _ if rust.name.starts_with("svset") => (), + (x, y) if x == y => (), + _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"), } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) { + if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { bail!("argument const mismatch"); } } @@ -507,7 +568,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { bail!("wrong number of const arguments"); } - if rust.instrs.is_empty() { + if rust.instrs.is_empty() && arm.instruction != "" { bail!( "instruction not listed for `{}`, but arm lists {:?}", rust.name, @@ -546,7 +607,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { Ok(()) } -#[derive(PartialEq)] +#[derive(Debug, PartialEq)] struct Intrinsic { name: String, ret: Option, @@ -561,7 +622,7 @@ struct JsonIntrinsic { arguments: Vec, return_type: ReturnType, #[serde(default)] - instructions: Vec>, + instructions: Option>>, } #[derive(Deserialize, Debug)] @@ -578,8 +639,8 @@ fn parse_intrinsics(intrinsics: Vec) -> HashMap Intrinsic { - let name = intr.name; +fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic { + let name = intr.name.replace('[', "").replace(']', ""); let ret = if intr.return_type.value == "void" { None } else { @@ -588,18 +649,24 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { // This ignores multiple instructions and different optional sequences for now to mimic // the old HTML scraping behaviour - let instruction = intr.instructions.swap_remove(0).swap_remove(0); + let instruction = intr + .instructions + .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0)); let arguments = intr .arguments .iter() .map(|s| { - let (ty, konst) = match s.strip_prefix("const") { - Some(stripped) => (stripped.trim_start(), true), - None => (s.as_str(), false), + let ty = if let Some(i) = s.find('*') { + &s[..i + 1] + } else { + s.rsplit_once(' ').unwrap().0.trim_start_matches("const ") }; - let ty = ty.rsplit_once(' ').unwrap().0; - (parse_ty(ty), konst) + let ty = parse_ty(ty); + let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_)) + || s.starts_with("enum") + || s.rsplit_once(" ").unwrap().1.starts_with("imm"); + (ty, konst) }) .collect::>(); @@ -612,18 +679,26 @@ fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { } fn parse_ty(s: &str) -> Type { - let suffix = " const *"; - if let Some(base) = s.strip_suffix(suffix) { - Type::ConstPtr(parse_ty_base(base)) - } else if let Some(base) = s.strip_suffix(" *") { - Type::MutPtr(parse_ty_base(base)) + if let Some(ty) = s.strip_suffix("*") { + let ty = ty.trim(); + if let Some(ty) = ty.strip_prefix("const") { + // SVE intrinsics are west-const (const int8_t *) + Type::ConstPtr(parse_ty_base(ty)) + } else if let Some(ty) = ty.strip_suffix("const") { + // Neon intrinsics are east-const (int8_t const *) + Type::ConstPtr(parse_ty_base(ty)) + } else { + Type::MutPtr(parse_ty_base(ty)) + } } else { *parse_ty_base(s) } } fn parse_ty_base(s: &str) -> &'static Type { - match s { + match s.trim() { + "bool" => &BOOL, + "void" => &VOID, "float16_t" => &F16, "float16x4_t" => &F16X4, "float16x4x2_t" => &F16X4X2, @@ -753,6 +828,49 @@ fn parse_ty_base(s: &str) -> &'static Type { "uint8x8x2_t" => &U8X8X2, "uint8x8x3_t" => &U8X8X3, "uint8x8x4_t" => &U8X8X4, + "svbool_t" => &SVBOOL, + "svfloat32_t" => &SVF32, + "svfloat32x2_t" => &SVF32X2, + "svfloat32x3_t" => &SVF32X3, + "svfloat32x4_t" => &SVF32X4, + "svfloat64_t" => &SVF64, + "svfloat64x2_t" => &SVF64X2, + "svfloat64x3_t" => &SVF64X3, + "svfloat64x4_t" => &SVF64X4, + "svint8_t" => &SVI8, + "svint8x2_t" => &SVI8X2, + "svint8x3_t" => &SVI8X3, + "svint8x4_t" => &SVI8X4, + "svint16_t" => &SVI16, + "svint16x2_t" => &SVI16X2, + "svint16x3_t" => &SVI16X3, + "svint16x4_t" => &SVI16X4, + "svint32_t" => &SVI32, + "svint32x2_t" => &SVI32X2, + "svint32x3_t" => &SVI32X3, + "svint32x4_t" => &SVI32X4, + "svint64_t" => &SVI64, + "svint64x2_t" => &SVI64X2, + "svint64x3_t" => &SVI64X3, + "svint64x4_t" => &SVI64X4, + "svuint8_t" => &SVU8, + "svuint8x2_t" => &SVU8X2, + "svuint8x3_t" => &SVU8X3, + "svuint8x4_t" => &SVU8X4, + "svuint16_t" => &SVU16, + "svuint16x2_t" => &SVU16X2, + "svuint16x3_t" => &SVU16X3, + "svuint16x4_t" => &SVU16X4, + "svuint32_t" => &SVU32, + "svuint32x2_t" => &SVU32X2, + "svuint32x3_t" => &SVU32X3, + "svuint32x4_t" => &SVU32X4, + "svuint64_t" => &SVU64, + "svuint64x2_t" => &SVU64X2, + "svuint64x3_t" => &SVU64X3, + "svuint64x4_t" => &SVU64X4, + "enum svprfop" => &SVPRFOP, + "enum svpattern" => &SVPATTERN, _ => panic!("failed to parse json type {s:?}"), } diff --git a/intrinsics_data/arm_intrinsics.json b/intrinsics_data/arm_intrinsics.json index a463564932..dedb98092d 100644 --- a/intrinsics_data/arm_intrinsics.json +++ b/intrinsics_data/arm_intrinsics.json @@ -7,6 +7,7 @@ "uint8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -35,6 +36,7 @@ "uint8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -63,6 +65,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -91,6 +94,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -119,6 +123,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -147,6 +152,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -175,6 +181,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -203,6 +210,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -223,6 +231,186920 @@ ] ] }, + { + "SIMD_ISA": "sve2", + "name": "svaba[_n_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2", + "int16_t op3" + ], + "return_type": { + "element_bit_size": "16", + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "sve2", + "name": "svaba[_n_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2", + "int32_t op3" + ], + "return_type": { + "element_bit_size": "32", + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S|Ztied1.S" + }, + "op2": { + "register": "Zop2.S" + }, + "op3": { + "register": "Zop3.S[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "sve2", + "name": "svaba[_n_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2", + "int64_t op3" + ], + "return_type": { + "element_bit_size": "64", + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D|Ztied1.D" + }, + "op2": { + "register": "Zop2.D" + }, + "op3": { + "register": "Zop3.D[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "sve2", + "name": "svaba[_n_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2", + "int8_t op3" + ], + "return_type": { + "element_bit_size": "8", + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B|Ztied1.B" + }, + "op2": { + "register": "Zop2.B" + }, + "op3": { + "register": "Zop3.B[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "SABA" + ], + [ + "MOVPRFX", + "SABA" + ] + ] + }, + { + "SIMD_ISA": "sve2", + "name": "svaba[_n_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2", + "uint16_t op3" + ], + "return_type": { + "element_bit_size": "16", + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H|Ztied1.H" + }, + "op2": { + "register": "Zop2.H" + }, + "op3": { + "register": "Zop3.H[*]" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "UABA" + ], + [ + "MOVPRFX", + "UABA" + ] + ] + }, + { + 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{ + "element_bit_size": "16", + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "element_bit_size": "8", + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "element_bit_size": "16", + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.H" + }, + "op2": { + "register": "Zop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.S" + }, + "op2": { + "register": "Zop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.D" + }, + "op2": { + "register": "Zop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "element_bit_size": "8", + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.B" + }, + "op2": { + "register": "Zop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2_b16", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "element_bit_size": "16", + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.H" + }, + "op2": { + "register": "Pop2.H" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2_b32", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.S" + }, + "op2": { + "register": "Pop2.S" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2_b64", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.D" + }, + "op2": { + "register": "Pop2.D" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2_b8", + "arguments": [ + "svbool_t op1", + "svbool_t op2" + ], + "return_type": { + "element_bit_size": "8", + "value": "svbool_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Pop1.B" + }, + "op2": { + "register": "Pop2.B" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_f32]", + "arguments": [ + "svfloat32_t op1", + "svfloat32_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svfloat32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_f64]", + "arguments": [ + "svfloat64_t op1", + "svfloat64_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svfloat64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_s16]", + "arguments": [ + "svint16_t op1", + "svint16_t op2" + ], + "return_type": { + "element_bit_size": "16", + "value": "svint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_s32]", + "arguments": [ + "svint32_t op1", + "svint32_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_s64]", + "arguments": [ + "svint64_t op1", + "svint64_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_s8]", + "arguments": [ + "svint8_t op1", + "svint8_t op2" + ], + "return_type": { + "element_bit_size": "8", + "value": "svint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_u16]", + "arguments": [ + "svuint16_t op1", + "svuint16_t op2" + ], + "return_type": { + "element_bit_size": "16", + "value": "svuint16_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_u32]", + "arguments": [ + "svuint32_t op1", + "svuint32_t op2" + ], + "return_type": { + "element_bit_size": "32", + "value": "svuint32_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_u64]", + "arguments": [ + "svuint64_t op1", + "svuint64_t op2" + ], + "return_type": { + "element_bit_size": "64", + "value": "svuint64_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, + { + "SIMD_ISA": "sve", + "name": "svzip2q[_u8]", + "arguments": [ + "svuint8_t op1", + "svuint8_t op2" + ], + "return_type": { + "element_bit_size": "8", + "value": "svuint8_t" + }, + "Arguments_Preparation": { + "op1": { + "register": "Zop1.Q" + }, + "op2": { + "register": "Zop2.Q" + } + }, + "Architectures": [ + "A64" + ], + "instructions": [ + [ + "ZIP2" + ] + ] + }, { "SIMD_ISA": "Neon", "name": "vaba_s16", @@ -232,6 +187154,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -265,6 +187188,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -298,6 +187222,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -331,6 +187256,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -364,6 +187290,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -397,6 +187324,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -430,6 +187358,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -461,6 +187390,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -492,6 +187422,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -523,6 +187454,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -554,6 +187486,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -585,6 +187518,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -616,6 +187550,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -649,6 +187584,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -682,6 +187618,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -715,6 +187652,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -748,6 +187686,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -781,6 +187720,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -814,6 +187754,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -847,6 +187788,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -880,6 +187822,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -913,6 +187856,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -946,6 +187890,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -979,6 +187924,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -1011,6 +187957,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -1040,6 +187987,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -1067,6 +188015,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -1096,6 +188045,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -1125,6 +188075,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -1154,6 +188105,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -1183,6 +188135,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -1212,6 +188165,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -1241,6 +188195,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -1268,6 +188223,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -1295,6 +188251,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -1322,6 +188279,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -1349,6 +188307,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -1376,6 +188335,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -1403,6 +188363,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -1430,6 +188391,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -1459,6 +188421,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -1488,6 +188451,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -1517,6 +188481,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -1546,6 +188511,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -1575,6 +188541,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -1604,6 +188571,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -1633,6 +188601,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -1660,6 +188629,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -1689,6 +188659,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -1718,6 +188689,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -1747,6 +188719,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -1776,6 +188749,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -1805,6 +188779,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -1834,6 +188809,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -1860,6 +188836,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -1885,6 +188862,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -1908,6 +188886,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -1933,6 +188912,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -1958,6 +188938,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -1981,6 +188962,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -2006,6 +188988,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -2029,6 +189012,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -2054,6 +189038,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -2077,6 +189062,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -2102,6 +189088,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -2127,6 +189114,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -2150,6 +189138,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -2176,6 +189165,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -2205,6 +189195,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -2232,6 +189223,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -2261,6 +189253,7 @@ "poly64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -2290,6 +189283,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -2319,6 +189313,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -2348,6 +189343,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -2377,6 +189373,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -2406,6 +189403,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -2435,6 +189433,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -2464,6 +189463,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -2493,6 +189493,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -2522,6 +189523,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -2551,6 +189553,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -2578,6 +189581,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -2606,6 +189610,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -2637,6 +189642,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -2668,6 +189674,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -2699,6 +189706,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -2730,6 +189738,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -2761,6 +189770,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -2791,6 +189801,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -2820,6 +189831,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -2849,6 +189861,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -2878,6 +189891,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -2907,6 +189921,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -2936,6 +189951,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -2965,6 +189981,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -2992,6 +190009,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -3019,6 +190037,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -3046,6 +190065,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -3073,6 +190093,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -3100,6 +190121,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -3127,6 +190149,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -3156,6 +190179,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -3185,6 +190209,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -3214,6 +190239,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -3243,6 +190269,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -3272,6 +190299,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -3300,6 +190328,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -3323,6 +190352,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -3346,6 +190376,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -3369,6 +190400,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -3392,6 +190424,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -3415,6 +190448,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -3438,6 +190472,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -3461,6 +190496,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -3484,6 +190520,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -3507,6 +190544,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -3530,6 +190568,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -3553,6 +190592,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -3577,6 +190617,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -3606,6 +190647,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -3633,6 +190675,7 @@ "poly128_t b" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -3662,6 +190705,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -3691,6 +190735,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -3720,6 +190765,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -3749,6 +190795,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -3778,6 +190825,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -3807,6 +190855,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -3836,6 +190885,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -3865,6 +190915,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -3894,6 +190945,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -3923,6 +190975,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -3952,6 +191005,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -3980,6 +191034,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -4003,6 +191058,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -4026,6 +191082,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -4049,6 +191106,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -4072,6 +191130,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -4095,6 +191154,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -4118,6 +191178,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -4141,6 +191202,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -4165,6 +191227,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -4188,6 +191251,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -4211,6 +191275,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -4234,6 +191299,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -4257,6 +191323,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -4280,6 +191347,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -4303,6 +191371,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -4326,6 +191395,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -4349,6 +191419,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -4373,6 +191444,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -4400,6 +191472,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -4427,6 +191500,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -4454,6 +191528,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -4481,6 +191556,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -4508,6 +191584,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -4535,6 +191612,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -4564,6 +191642,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -4593,6 +191672,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -4622,6 +191702,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -4651,6 +191732,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -4680,6 +191762,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -4709,6 +191792,7 @@ "uint8x16_t key" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -4737,6 +191821,7 @@ "uint8x16_t key" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -4764,6 +191849,7 @@ "uint8x16_t data" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -4788,6 +191874,7 @@ "uint8x16_t data" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -4813,6 +191900,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -4842,6 +191930,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -4871,6 +191960,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -4900,6 +191990,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -4929,6 +192020,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -4958,6 +192050,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -4987,6 +192080,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -5016,6 +192110,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -5045,6 +192140,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -5074,6 +192170,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -5103,6 +192200,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -5132,6 +192230,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -5161,6 +192260,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -5190,6 +192290,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -5219,6 +192320,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -5248,6 +192350,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -5278,6 +192381,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -5305,6 +192409,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -5332,6 +192437,7 @@ "int64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -5359,6 +192465,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -5386,6 +192493,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -5413,6 +192521,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -5440,6 +192549,7 @@ "uint64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -5467,6 +192577,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -5493,6 +192604,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -5522,6 +192634,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -5551,6 +192664,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -5580,6 +192694,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -5609,6 +192724,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -5638,6 +192754,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -5667,6 +192784,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -5696,6 +192814,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -5725,6 +192844,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -5754,6 +192874,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -5783,6 +192904,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -5812,6 +192934,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -5841,6 +192964,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -5870,6 +192994,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -5899,6 +193024,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -5928,6 +193054,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -5958,6 +193085,7 @@ "float32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -5991,6 +193119,7 @@ "float64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -6022,6 +193151,7 @@ "poly16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -6055,6 +193185,7 @@ "poly64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -6087,6 +193218,7 @@ "poly8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -6120,6 +193252,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -6153,6 +193286,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -6186,6 +193320,7 @@ "int64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -6219,6 +193354,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -6252,6 +193388,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -6285,6 +193422,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -6318,6 +193456,7 @@ "uint64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -6351,6 +193490,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -6384,6 +193524,7 @@ "float32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -6417,6 +193558,7 @@ "float64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -6448,6 +193590,7 @@ "poly16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -6481,6 +193624,7 @@ "poly64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -6513,6 +193657,7 @@ "poly8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -6546,6 +193691,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -6579,6 +193725,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -6612,6 +193759,7 @@ "int64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -6645,6 +193793,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -6678,6 +193827,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -6711,6 +193861,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -6744,6 +193895,7 @@ "uint64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -6777,6 +193929,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -6809,6 +193962,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -6837,6 +193991,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -6865,6 +194020,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -6893,6 +194049,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -6920,6 +194077,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -6948,6 +194106,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -6975,6 +194134,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7004,6 +194164,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7031,6 +194192,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -7058,6 +194220,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -7087,6 +194250,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -7114,6 +194278,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -7141,6 +194306,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7170,6 +194336,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7197,6 +194364,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -7224,6 +194392,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -7253,6 +194422,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -7280,6 +194450,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -7307,6 +194478,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7336,6 +194508,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7363,6 +194536,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -7390,6 +194564,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -7419,6 +194594,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -7446,6 +194622,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -7473,6 +194650,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7502,6 +194680,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7529,6 +194708,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -7556,6 +194736,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -7585,6 +194766,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -7612,6 +194794,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -7639,6 +194822,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7668,6 +194852,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7695,6 +194880,7 @@ "poly64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7723,6 +194909,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -7752,6 +194939,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -7781,6 +194969,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7810,6 +194999,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7837,6 +195027,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -7866,6 +195057,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -7895,6 +195087,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -7924,6 +195117,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -7951,6 +195145,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -7980,6 +195175,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8007,6 +195203,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8034,6 +195231,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8061,6 +195259,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -8090,6 +195289,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8117,6 +195317,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8145,6 +195346,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -8174,6 +195376,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -8203,6 +195406,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -8232,6 +195436,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8259,6 +195464,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -8288,6 +195494,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -8317,6 +195524,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -8346,6 +195554,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8373,6 +195582,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -8402,6 +195612,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -8428,6 +195639,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -8451,6 +195663,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -8474,6 +195687,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -8498,6 +195712,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -8521,6 +195736,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -8544,6 +195760,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -8567,6 +195784,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -8590,6 +195808,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -8613,6 +195832,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -8636,6 +195856,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -8659,6 +195880,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -8682,6 +195904,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -8705,6 +195928,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8728,6 +195952,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8751,6 +195976,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -8774,6 +196000,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -8797,6 +196024,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8820,6 +196048,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8844,6 +196073,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -8867,6 +196097,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -8890,6 +196121,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -8913,6 +196145,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -8936,6 +196169,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -8959,6 +196193,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -8982,6 +196217,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -9005,6 +196241,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -9028,6 +196265,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -9051,6 +196289,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -9075,6 +196314,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -9104,6 +196344,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -9131,6 +196372,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -9160,6 +196402,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -9189,6 +196432,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -9216,6 +196460,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -9245,6 +196490,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -9274,6 +196520,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -9303,6 +196550,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -9330,6 +196578,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -9359,6 +196608,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -9386,6 +196636,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -9413,6 +196664,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -9440,6 +196692,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -9469,6 +196722,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -9496,6 +196750,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -9525,6 +196780,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -9554,6 +196810,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -9581,6 +196838,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -9610,6 +196868,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -9639,6 +196898,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -9668,6 +196928,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -9695,6 +196956,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -9724,6 +196986,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -9750,6 +197013,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -9773,6 +197037,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -9796,6 +197061,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -9819,6 +197085,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -9842,6 +197109,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -9865,6 +197133,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -9888,6 +197157,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -9911,6 +197181,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -9934,6 +197205,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -9957,6 +197229,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -9980,6 +197253,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -10003,6 +197277,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -10026,6 +197301,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -10049,6 +197325,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -10072,6 +197349,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -10096,6 +197374,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -10125,6 +197404,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -10152,6 +197432,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -10181,6 +197462,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -10210,6 +197492,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -10237,6 +197520,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -10266,6 +197550,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -10295,6 +197580,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -10324,6 +197610,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -10351,6 +197638,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -10380,6 +197668,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -10407,6 +197696,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -10434,6 +197724,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -10461,6 +197752,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -10490,6 +197782,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -10517,6 +197810,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -10546,6 +197840,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -10575,6 +197870,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -10602,6 +197898,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -10631,6 +197928,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -10660,6 +197958,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -10689,6 +197988,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -10716,6 +198016,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -10745,6 +198046,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -10771,6 +198073,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -10794,6 +198097,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -10817,6 +198121,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -10840,6 +198145,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -10863,6 +198169,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -10886,6 +198193,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -10909,6 +198217,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -10932,6 +198241,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -10955,6 +198265,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -10978,6 +198289,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -11001,6 +198313,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -11024,6 +198337,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -11047,6 +198361,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -11070,6 +198385,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -11093,6 +198409,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -11117,6 +198434,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -11146,6 +198464,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -11173,6 +198492,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -11202,6 +198522,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -11231,6 +198552,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -11258,6 +198580,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -11287,6 +198610,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -11316,6 +198640,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -11345,6 +198670,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -11372,6 +198698,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -11401,6 +198728,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -11428,6 +198756,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -11455,6 +198784,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -11482,6 +198812,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -11511,6 +198842,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -11538,6 +198870,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -11567,6 +198900,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -11596,6 +198930,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -11623,6 +198958,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -11652,6 +198988,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -11681,6 +199018,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -11710,6 +199048,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -11737,6 +199076,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -11766,6 +199106,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -11792,6 +199133,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -11815,6 +199157,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -11838,6 +199181,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -11861,6 +199205,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -11884,6 +199229,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -11907,6 +199253,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -11930,6 +199277,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -11953,6 +199301,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -11976,6 +199325,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -11999,6 +199349,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -12022,6 +199373,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -12045,6 +199397,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -12068,6 +199421,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -12091,6 +199445,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -12114,6 +199469,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -12137,6 +199493,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -12162,6 +199519,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -12187,6 +199545,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -12212,6 +199571,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -12237,6 +199597,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -12262,6 +199623,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -12287,6 +199649,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -12312,6 +199675,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -12337,6 +199701,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -12362,6 +199727,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -12387,6 +199753,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -12412,6 +199779,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -12438,6 +199806,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -12467,6 +199836,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -12494,6 +199864,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -12523,6 +199894,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -12552,6 +199924,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -12579,6 +199952,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -12608,6 +199982,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -12637,6 +200012,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -12666,6 +200042,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -12693,6 +200070,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -12722,6 +200100,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -12749,6 +200128,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -12776,6 +200156,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -12803,6 +200184,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -12832,6 +200214,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -12859,6 +200242,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -12888,6 +200272,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -12917,6 +200302,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -12944,6 +200330,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -12973,6 +200360,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -13002,6 +200390,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -13031,6 +200420,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -13058,6 +200448,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -13087,6 +200478,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -13113,6 +200505,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -13136,6 +200529,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -13159,6 +200553,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -13182,6 +200577,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -13205,6 +200601,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -13228,6 +200625,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -13251,6 +200649,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -13274,6 +200673,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -13297,6 +200697,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -13320,6 +200721,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -13343,6 +200745,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -13366,6 +200769,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -13389,6 +200793,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -13412,6 +200817,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -13435,6 +200841,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -13458,6 +200865,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -13483,6 +200891,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -13508,6 +200917,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -13533,6 +200943,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -13558,6 +200969,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -13583,6 +200995,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -13608,6 +201021,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -13633,6 +201047,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -13658,6 +201073,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -13683,6 +201099,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -13708,6 +201125,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -13733,6 +201151,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -13760,6 +201179,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13789,6 +201209,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13822,6 +201243,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13855,6 +201277,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13884,6 +201307,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13917,6 +201341,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13950,6 +201375,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -13979,6 +201405,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -14012,6 +201439,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -14045,6 +201473,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -14074,6 +201503,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -14107,6 +201537,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -14140,6 +201571,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14168,6 +201600,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -14196,6 +201629,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14229,6 +201663,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14261,6 +201696,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14289,6 +201725,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -14317,6 +201754,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14350,6 +201788,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14382,6 +201821,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14410,6 +201850,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -14438,6 +201879,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14471,6 +201913,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14503,6 +201946,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14531,6 +201975,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -14559,6 +202004,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14592,6 +202038,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14622,6 +202069,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -14647,6 +202095,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -14672,6 +202121,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -14697,6 +202147,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -14722,6 +202173,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -14747,6 +202199,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -14773,6 +202226,7 @@ "float32x2_t high" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -14803,6 +202257,7 @@ "float64x1_t high" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -14831,6 +202286,7 @@ "poly16x4_t high" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -14861,6 +202317,7 @@ "poly64x1_t high" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -14890,6 +202347,7 @@ "poly8x8_t high" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -14920,6 +202378,7 @@ "int16x4_t high" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -14950,6 +202409,7 @@ "int32x2_t high" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -14980,6 +202440,7 @@ "int64x1_t high" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -15010,6 +202471,7 @@ "int8x8_t high" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -15040,6 +202502,7 @@ "uint16x4_t high" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -15070,6 +202533,7 @@ "uint32x2_t high" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -15100,6 +202564,7 @@ "uint64x1_t high" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -15130,6 +202595,7 @@ "uint8x8_t high" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -15162,6 +202628,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -15199,6 +202666,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -15236,6 +202704,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -15273,6 +202742,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -15311,6 +202781,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -15348,6 +202819,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -15385,6 +202857,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -15422,6 +202895,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -15459,6 +202933,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -15496,6 +202971,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -15533,6 +203009,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -15570,6 +203047,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -15607,6 +203085,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -15644,6 +203123,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -15681,6 +203161,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -15718,6 +203199,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -15755,6 +203237,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -15793,6 +203276,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -15830,6 +203314,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -15867,6 +203352,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -15904,6 +203390,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -15941,6 +203428,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -15978,6 +203466,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -16015,6 +203504,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -16052,6 +203542,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -16089,6 +203580,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -16126,6 +203618,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -16163,6 +203656,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -16200,6 +203694,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -16237,6 +203732,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -16275,6 +203771,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -16312,6 +203809,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -16349,6 +203847,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -16386,6 +203885,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -16423,6 +203923,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -16460,6 +203961,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -16497,6 +203999,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -16534,6 +204037,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -16571,6 +204075,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -16608,6 +204113,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -16645,6 +204151,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -16682,6 +204189,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -16719,6 +204227,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -16757,6 +204266,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -16794,6 +204304,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -16831,6 +204342,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -16868,6 +204380,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -16905,6 +204418,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -16942,6 +204456,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -16979,6 +204494,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -17016,6 +204532,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -17053,6 +204570,7 @@ "const int lane2" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -17087,6 +204605,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17112,6 +204631,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -17135,6 +204655,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -17160,6 +204681,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -17184,6 +204706,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -17209,6 +204732,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -17234,6 +204758,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -17259,6 +204784,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -17284,6 +204810,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -17309,6 +204836,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -17334,6 +204862,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -17359,6 +204888,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -17384,6 +204914,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -17409,6 +204940,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17432,6 +204964,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17457,6 +204990,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17482,6 +205016,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -17505,6 +205040,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -17528,6 +205064,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -17552,6 +205089,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -17578,6 +205116,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -17602,6 +205141,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17632,6 +205172,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -17662,6 +205203,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -17690,6 +205232,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -17718,6 +205261,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -17748,6 +205292,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -17776,6 +205321,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -17806,6 +205352,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -17833,6 +205380,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -17858,6 +205406,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -17881,6 +205430,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -17906,6 +205456,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -17929,6 +205480,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -17953,6 +205505,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -17976,6 +205529,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -18000,6 +205554,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -18023,6 +205578,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -18046,6 +205602,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -18069,6 +205626,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -18093,6 +205651,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -18116,6 +205675,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -18140,6 +205700,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -18163,6 +205724,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -18186,6 +205748,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -18209,6 +205772,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -18232,6 +205796,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -18256,6 +205821,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -18284,6 +205850,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -18312,6 +205879,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -18340,6 +205908,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -18367,6 +205936,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -18390,6 +205960,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -18413,6 +205984,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -18437,6 +206009,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -18460,6 +206033,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -18484,6 +206058,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -18507,6 +206082,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -18530,6 +206106,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -18553,6 +206130,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -18577,6 +206155,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -18600,6 +206179,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -18624,6 +206204,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -18647,6 +206228,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -18670,6 +206252,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -18693,6 +206276,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -18717,6 +206301,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -18740,6 +206325,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -18764,6 +206350,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -18787,6 +206374,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -18810,6 +206398,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -18833,6 +206422,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -18857,6 +206447,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -18880,6 +206471,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -18904,6 +206496,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -18927,6 +206520,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -18950,6 +206544,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -18973,6 +206568,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -18997,6 +206593,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -19020,6 +206617,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -19044,6 +206642,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -19067,6 +206666,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -19090,6 +206690,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -19113,6 +206714,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -19137,6 +206739,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -19160,6 +206763,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -19184,6 +206788,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -19207,6 +206812,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -19230,6 +206836,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -19253,6 +206860,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -19278,6 +206886,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -19303,6 +206912,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -19326,6 +206936,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -19350,6 +206961,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -19380,6 +206992,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -19410,6 +207023,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -19438,6 +207052,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -19466,6 +207081,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -19496,6 +207112,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -19524,6 +207141,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -19554,6 +207172,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -19581,6 +207200,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -19606,6 +207226,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -19629,6 +207250,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -19654,6 +207276,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -19677,6 +207300,7 @@ "int32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -19700,6 +207324,7 @@ "uint32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -19724,6 +207349,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -19752,6 +207378,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -19780,6 +207407,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -19808,6 +207436,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -19835,6 +207464,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -19858,6 +207488,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -19881,6 +207512,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -19905,6 +207537,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -19931,6 +207564,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -19955,6 +207589,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -19982,6 +207617,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -20009,6 +207645,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -20036,6 +207673,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -20065,6 +207703,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -20102,6 +207741,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -20139,6 +207779,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -20175,6 +207816,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -20210,6 +207852,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -20242,6 +207885,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -20275,6 +207919,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -20312,6 +207957,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -20349,6 +207995,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -20385,6 +208032,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -20420,6 +208068,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -20452,6 +208101,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -20483,6 +208133,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -20513,6 +208164,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -20541,6 +208193,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -20571,6 +208224,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -20600,6 +208254,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -20630,6 +208285,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -20660,6 +208316,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -20690,6 +208347,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -20720,6 +208378,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -20750,6 +208409,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -20780,6 +208440,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -20810,6 +208471,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -20840,6 +208502,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -20870,6 +208533,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -20898,6 +208562,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -20926,6 +208591,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -20954,6 +208620,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -20982,6 +208649,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -21010,6 +208678,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -21038,6 +208707,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -21066,6 +208736,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -21094,6 +208765,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -21122,6 +208794,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -21150,6 +208823,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -21178,6 +208852,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -21206,6 +208881,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -21233,6 +208909,7 @@ "float32_t value" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -21258,6 +208935,7 @@ "float64_t value" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -21281,6 +208959,7 @@ "poly16_t value" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -21306,6 +208985,7 @@ "poly64_t value" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -21330,6 +209010,7 @@ "poly8_t value" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -21355,6 +209036,7 @@ "int16_t value" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -21380,6 +209062,7 @@ "int32_t value" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -21405,6 +209088,7 @@ "int64_t value" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -21430,6 +209114,7 @@ "int8_t value" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -21455,6 +209140,7 @@ "uint16_t value" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -21480,6 +209166,7 @@ "uint32_t value" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -21505,6 +209192,7 @@ "uint64_t value" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -21530,6 +209218,7 @@ "uint8_t value" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -21556,6 +209245,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -21584,6 +209274,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -21612,6 +209303,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -21640,6 +209332,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -21668,6 +209361,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -21696,6 +209390,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -21724,6 +209419,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -21752,6 +209448,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -21780,6 +209477,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -21808,6 +209506,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -21836,6 +209535,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -21864,6 +209564,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -21892,6 +209593,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -21920,6 +209622,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -21948,6 +209651,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -21976,6 +209680,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -22004,6 +209709,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -22032,6 +209738,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -22060,6 +209767,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -22090,6 +209798,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -22118,6 +209827,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -22148,6 +209858,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -22177,6 +209888,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -22207,6 +209919,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -22237,6 +209950,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -22267,6 +209981,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -22297,6 +210012,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -22327,6 +210043,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -22357,6 +210074,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -22387,6 +210105,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -22417,6 +210136,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -22447,6 +210167,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -22475,6 +210196,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -22503,6 +210225,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -22531,6 +210254,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -22559,6 +210283,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -22587,6 +210312,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -22615,6 +210341,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -22643,6 +210370,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -22671,6 +210399,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -22699,6 +210428,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -22727,6 +210457,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -22755,6 +210486,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -22783,6 +210515,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -22810,6 +210543,7 @@ "float32_t value" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -22835,6 +210569,7 @@ "float64_t value" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -22858,6 +210593,7 @@ "poly16_t value" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -22883,6 +210619,7 @@ "poly64_t value" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -22907,6 +210644,7 @@ "poly8_t value" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -22932,6 +210670,7 @@ "int16_t value" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -22957,6 +210696,7 @@ "int32_t value" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -22982,6 +210722,7 @@ "int64_t value" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -23007,6 +210748,7 @@ "int8_t value" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -23032,6 +210774,7 @@ "uint16_t value" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -23057,6 +210800,7 @@ "uint32_t value" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -23082,6 +210826,7 @@ "uint64_t value" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -23107,6 +210852,7 @@ "uint8_t value" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -23133,6 +210879,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -23161,6 +210908,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -23189,6 +210937,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -23217,6 +210966,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -23245,6 +210995,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -23273,6 +211024,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -23302,6 +211054,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -23329,6 +211082,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -23356,6 +211110,7 @@ "int64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -23383,6 +211138,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -23410,6 +211166,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -23437,6 +211194,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -23464,6 +211222,7 @@ "uint64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -23491,6 +211250,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -23517,6 +211277,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -23546,6 +211307,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -23575,6 +211337,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -23604,6 +211367,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -23633,6 +211397,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -23662,6 +211427,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -23691,6 +211457,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -23720,6 +211487,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -23749,6 +211517,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -23778,6 +211547,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -23807,6 +211577,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -23836,6 +211607,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -23865,6 +211637,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -23894,6 +211667,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -23923,6 +211697,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -23952,6 +211727,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -23982,6 +211758,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -24016,6 +211793,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -24048,6 +211826,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -24082,6 +211861,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -24115,6 +211895,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -24149,6 +211930,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -24183,6 +211965,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -24217,6 +212000,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -24251,6 +212035,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -24285,6 +212070,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -24319,6 +212105,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -24353,6 +212140,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -24387,6 +212175,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -24421,6 +212210,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -24455,6 +212245,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -24487,6 +212278,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -24521,6 +212313,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -24554,6 +212347,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -24588,6 +212382,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -24622,6 +212417,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -24656,6 +212452,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -24690,6 +212487,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -24724,6 +212522,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -24758,6 +212557,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -24792,6 +212592,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -24826,6 +212627,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -24860,6 +212662,7 @@ "float32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -24893,6 +212696,7 @@ "float64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -24925,6 +212729,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -24961,6 +212766,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -24997,6 +212803,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25033,6 +212840,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25068,6 +212876,7 @@ "float32_t n" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25101,6 +212910,7 @@ "float64_t n" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25133,6 +212943,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -25169,6 +212980,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -25204,6 +213016,7 @@ "float32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25237,6 +213050,7 @@ "float64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -25269,6 +213083,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25305,6 +213120,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -25341,6 +213157,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25377,6 +213194,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -25412,6 +213230,7 @@ "float32_t n" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25445,6 +213264,7 @@ "float64_t n" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -25477,6 +213297,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -25513,6 +213334,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -25548,6 +213370,7 @@ "float32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25581,6 +213404,7 @@ "float64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25613,6 +213437,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25649,6 +213474,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25685,6 +213511,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25721,6 +213548,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25756,6 +213584,7 @@ "float32_t n" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -25787,6 +213616,7 @@ "float64_t n" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -25819,6 +213649,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -25855,6 +213686,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -25890,6 +213722,7 @@ "float32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25923,6 +213756,7 @@ "float64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -25955,6 +213789,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -25991,6 +213826,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -26027,6 +213863,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -26063,6 +213900,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -26098,6 +213936,7 @@ "float32_t n" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -26129,6 +213968,7 @@ "float64_t n" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -26161,6 +214001,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -26197,6 +214038,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -26230,6 +214072,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -26255,6 +214098,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -26278,6 +214122,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -26303,6 +214148,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -26327,6 +214173,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -26352,6 +214199,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -26377,6 +214225,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -26402,6 +214251,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -26427,6 +214277,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -26452,6 +214303,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -26477,6 +214329,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -26502,6 +214355,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -26527,6 +214381,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -26553,6 +214408,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -26583,6 +214439,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -26611,6 +214468,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -26641,6 +214499,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64_t" }, "Arguments_Preparation": { @@ -26670,6 +214529,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -26700,6 +214560,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -26730,6 +214591,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -26760,6 +214622,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -26790,6 +214653,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -26820,6 +214684,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -26850,6 +214715,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -26880,6 +214746,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -26910,6 +214777,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -26939,6 +214807,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -26964,6 +214833,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -26987,6 +214857,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -27012,6 +214883,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -27036,6 +214908,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -27061,6 +214934,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -27086,6 +214960,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -27111,6 +214986,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -27136,6 +215012,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -27161,6 +215038,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -27186,6 +215064,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -27211,6 +215090,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -27236,6 +215116,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -27262,6 +215143,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -27292,6 +215174,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -27320,6 +215203,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -27350,6 +215234,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64_t" }, "Arguments_Preparation": { @@ -27379,6 +215264,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -27409,6 +215295,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -27439,6 +215326,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -27469,6 +215357,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -27499,6 +215388,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -27529,6 +215419,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -27559,6 +215450,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -27589,6 +215481,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -27619,6 +215512,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -27649,6 +215543,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -27678,6 +215573,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -27707,6 +215603,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -27736,6 +215633,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -27765,6 +215663,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -27794,6 +215693,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -27823,6 +215723,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -27852,6 +215753,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -27881,6 +215783,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -27910,6 +215813,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -27939,6 +215843,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -27968,6 +215873,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -27997,6 +215903,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -28026,6 +215933,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -28055,6 +215963,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -28084,6 +215993,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -28113,6 +216023,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -28142,6 +216053,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -28171,6 +216083,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -28200,6 +216113,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -28229,6 +216143,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -28258,6 +216173,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -28287,6 +216203,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -28316,6 +216233,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -28344,6 +216262,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -28369,6 +216288,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -28392,6 +216312,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -28417,6 +216338,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -28441,6 +216363,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -28466,6 +216389,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -28491,6 +216415,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -28516,6 +216441,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -28541,6 +216467,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -28566,6 +216493,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -28591,6 +216519,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -28616,6 +216545,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -28641,6 +216571,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -28666,6 +216597,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -28691,6 +216623,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -28716,6 +216649,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -28741,6 +216675,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -28766,6 +216701,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -28789,6 +216725,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -28812,6 +216749,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -28835,6 +216773,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -28860,6 +216799,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -28894,6 +216834,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -28926,6 +216867,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -28960,6 +216902,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -28993,6 +216936,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -29027,6 +216971,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -29061,6 +217006,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -29095,6 +217041,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -29129,6 +217076,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -29163,6 +217111,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -29197,6 +217146,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -29231,6 +217181,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -29265,6 +217216,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -29297,6 +217249,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -29322,6 +217275,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -29347,6 +217301,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -29372,6 +217327,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -29397,6 +217353,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -29421,6 +217378,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -29445,6 +217403,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -29469,6 +217428,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -29493,6 +217453,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -29518,6 +217479,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -29543,6 +217505,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -29568,6 +217531,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -29593,6 +217557,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -29618,6 +217583,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -29643,6 +217609,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -29668,6 +217635,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -29693,6 +217661,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -29718,6 +217687,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -29743,6 +217713,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -29768,6 +217739,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -29793,6 +217765,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -29818,6 +217791,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -29843,6 +217817,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -29868,6 +217843,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -29893,6 +217869,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -29918,6 +217895,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -29943,6 +217921,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -29968,6 +217947,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -29993,6 +217973,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -30018,6 +217999,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -30043,6 +218025,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -30068,6 +218051,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -30093,6 +218077,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -30118,6 +218103,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -30143,6 +218129,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -30168,6 +218155,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -30193,6 +218181,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -30218,6 +218207,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -30243,6 +218233,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -30268,6 +218259,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -30293,6 +218285,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -30318,6 +218311,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -30343,6 +218337,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -30368,6 +218363,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -30393,6 +218389,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -30418,6 +218415,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -30441,6 +218439,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -30466,6 +218465,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -30490,6 +218490,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -30515,6 +218516,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -30540,6 +218542,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -30565,6 +218568,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -30590,6 +218594,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -30615,6 +218620,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -30640,6 +218646,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -30665,6 +218672,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -30690,6 +218698,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -30715,6 +218724,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -30740,6 +218750,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -30765,6 +218776,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -30790,6 +218802,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -30815,6 +218828,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -30838,6 +218852,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -30861,6 +218876,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -30884,6 +218900,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -30909,6 +218926,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -30943,6 +218961,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -30975,6 +218994,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -31009,6 +219029,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -31042,6 +219063,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -31076,6 +219098,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -31110,6 +219133,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -31144,6 +219168,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -31178,6 +219203,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -31212,6 +219238,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -31246,6 +219273,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -31280,6 +219308,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -31314,6 +219343,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -31346,6 +219376,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -31371,6 +219402,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -31396,6 +219428,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -31421,6 +219454,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -31446,6 +219480,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -31470,6 +219505,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -31494,6 +219530,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -31518,6 +219555,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -31542,6 +219580,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -31567,6 +219606,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -31592,6 +219632,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -31617,6 +219658,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -31642,6 +219684,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -31667,6 +219710,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -31692,6 +219736,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -31717,6 +219762,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -31742,6 +219788,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -31767,6 +219814,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -31792,6 +219840,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -31817,6 +219866,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -31842,6 +219892,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -31867,6 +219918,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -31892,6 +219944,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -31917,6 +219970,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -31942,6 +219996,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -31967,6 +220022,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -31992,6 +220048,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -32017,6 +220074,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -32042,6 +220100,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -32067,6 +220126,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -32092,6 +220152,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -32117,6 +220178,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -32142,6 +220204,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -32167,6 +220230,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -32192,6 +220256,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -32217,6 +220282,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -32242,6 +220308,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -32267,6 +220334,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -32292,6 +220360,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -32317,6 +220386,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -32342,6 +220412,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -32367,6 +220438,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -32392,6 +220464,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -32417,6 +220490,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -32442,6 +220516,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -32467,6 +220542,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -32490,6 +220566,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -32515,6 +220592,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -32539,6 +220617,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -32564,6 +220643,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -32589,6 +220669,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -32614,6 +220695,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -32639,6 +220721,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -32664,6 +220747,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -32689,6 +220773,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -32714,6 +220799,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -32739,6 +220825,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -32764,6 +220851,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -32789,6 +220877,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -32814,6 +220903,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -32848,6 +220938,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -32880,6 +220971,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -32914,6 +221006,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -32946,6 +221039,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -32980,6 +221074,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -33014,6 +221109,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -33048,6 +221144,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -33080,6 +221177,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -33114,6 +221212,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -33148,6 +221247,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -33182,6 +221282,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -33214,6 +221315,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -33246,6 +221348,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -33271,6 +221374,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -33295,6 +221399,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -33320,6 +221425,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -33345,6 +221451,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -33370,6 +221477,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -33395,6 +221503,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -33420,6 +221529,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -33445,6 +221555,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -33470,6 +221581,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -33495,6 +221607,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -33520,6 +221633,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -33545,6 +221659,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -33568,6 +221683,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -33593,6 +221709,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -33616,6 +221733,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -33641,6 +221759,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -33666,6 +221785,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -33691,6 +221811,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -33714,6 +221835,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -33739,6 +221861,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -33764,6 +221887,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -33789,6 +221913,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -33812,6 +221937,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -33837,6 +221963,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -33862,6 +221989,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -33887,6 +222015,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -33921,6 +222050,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -33953,6 +222083,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -33987,6 +222118,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -34019,6 +222151,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -34051,6 +222184,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -34085,6 +222219,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -34119,6 +222254,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -34151,6 +222287,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -34183,6 +222320,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -34217,6 +222355,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -34251,6 +222390,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -34283,6 +222423,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -34313,6 +222454,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -34338,6 +222480,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -34361,6 +222504,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -34386,6 +222530,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -34411,6 +222556,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -34436,6 +222582,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -34459,6 +222606,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -34484,6 +222632,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -34509,6 +222658,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -34534,6 +222684,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -34557,6 +222708,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -34582,6 +222734,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -34607,6 +222760,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -34630,6 +222784,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -34655,6 +222810,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -34679,6 +222835,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -34704,6 +222861,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -34729,6 +222887,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -34754,6 +222913,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -34779,6 +222939,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -34804,6 +222965,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -34829,6 +222991,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -34854,6 +223017,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -34879,6 +223043,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -34904,6 +223069,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -34929,6 +223095,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -34954,6 +223121,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -34988,6 +223156,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -35020,6 +223189,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -35054,6 +223224,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -35086,6 +223257,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -35120,6 +223292,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -35154,6 +223327,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -35188,6 +223362,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -35220,6 +223395,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -35254,6 +223430,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -35288,6 +223465,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -35322,6 +223500,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -35354,6 +223533,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -35386,6 +223566,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -35411,6 +223592,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -35435,6 +223617,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -35460,6 +223643,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -35485,6 +223669,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -35510,6 +223695,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -35535,6 +223721,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -35560,6 +223747,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -35585,6 +223773,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -35610,6 +223799,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -35635,6 +223825,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -35660,6 +223851,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -35685,6 +223877,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -35708,6 +223901,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -35733,6 +223927,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -35756,6 +223951,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -35781,6 +223977,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -35806,6 +224003,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -35831,6 +224029,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -35854,6 +224053,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -35879,6 +224079,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -35904,6 +224105,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -35929,6 +224131,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -35952,6 +224155,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -35977,6 +224181,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -36002,6 +224207,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -36027,6 +224233,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -36061,6 +224268,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -36093,6 +224301,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -36127,6 +224336,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -36159,6 +224369,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -36191,6 +224402,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -36225,6 +224437,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -36259,6 +224472,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -36291,6 +224505,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -36323,6 +224538,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -36357,6 +224573,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -36391,6 +224608,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -36423,6 +224641,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -36453,6 +224672,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -36478,6 +224698,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -36501,6 +224722,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -36526,6 +224748,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -36551,6 +224774,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -36576,6 +224800,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -36599,6 +224824,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -36624,6 +224850,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -36649,6 +224876,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -36674,6 +224902,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -36697,6 +224926,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -36722,6 +224952,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -36747,6 +224978,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -36770,6 +225002,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -36795,6 +225028,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -36819,6 +225053,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -36844,6 +225079,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -36869,6 +225105,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -36894,6 +225131,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -36919,6 +225157,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -36944,6 +225183,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -36969,6 +225209,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -36994,6 +225235,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -37019,6 +225261,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -37044,6 +225287,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -37069,6 +225313,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -37094,6 +225339,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -37128,6 +225374,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -37160,6 +225407,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -37194,6 +225442,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -37226,6 +225475,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -37260,6 +225510,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -37294,6 +225545,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -37328,6 +225580,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -37360,6 +225613,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -37394,6 +225648,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -37428,6 +225683,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -37462,6 +225718,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -37494,6 +225751,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -37526,6 +225784,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -37551,6 +225810,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -37575,6 +225835,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -37600,6 +225861,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -37625,6 +225887,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -37650,6 +225913,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -37675,6 +225939,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -37700,6 +225965,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -37725,6 +225991,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -37750,6 +226017,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -37775,6 +226043,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -37800,6 +226069,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -37825,6 +226095,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -37848,6 +226119,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -37873,6 +226145,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -37896,6 +226169,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -37921,6 +226195,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -37946,6 +226221,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -37971,6 +226247,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -37994,6 +226271,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -38019,6 +226297,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -38044,6 +226323,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -38069,6 +226349,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -38092,6 +226373,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -38117,6 +226399,7 @@ "float32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -38142,6 +226425,7 @@ "float64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -38167,6 +226451,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -38201,6 +226486,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -38233,6 +226519,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -38267,6 +226554,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -38299,6 +226587,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -38331,6 +226620,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -38365,6 +226655,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -38399,6 +226690,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -38431,6 +226723,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -38463,6 +226756,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -38497,6 +226791,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -38531,6 +226826,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -38563,6 +226859,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -38593,6 +226890,7 @@ "poly16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -38618,6 +226916,7 @@ "poly64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -38641,6 +226940,7 @@ "poly8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -38666,6 +226966,7 @@ "int16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -38691,6 +226992,7 @@ "int32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -38716,6 +227018,7 @@ "int64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -38739,6 +227042,7 @@ "int8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -38764,6 +227068,7 @@ "uint16_t const * ptr" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -38789,6 +227094,7 @@ "uint32_t const * ptr" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -38814,6 +227120,7 @@ "uint64_t const * ptr" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -38837,6 +227144,7 @@ "uint8_t const * ptr" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -38862,6 +227170,7 @@ "poly128_t const * ptr" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -38887,6 +227196,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -38916,6 +227226,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -38943,6 +227254,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -38972,6 +227284,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -39001,6 +227314,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -39030,6 +227344,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -39059,6 +227374,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -39088,6 +227404,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -39117,6 +227434,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -39145,6 +227463,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -39172,6 +227491,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -39200,6 +227520,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -39226,6 +227547,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -39249,6 +227571,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -39272,6 +227595,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -39296,6 +227620,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -39325,6 +227650,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -39352,6 +227678,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -39381,6 +227708,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -39410,6 +227738,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -39439,6 +227768,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -39468,6 +227798,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -39497,6 +227828,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -39525,6 +227857,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -39548,6 +227881,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -39571,6 +227905,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -39594,6 +227929,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -39617,6 +227953,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -39640,6 +227977,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -39663,6 +228001,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -39686,6 +228025,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -39709,6 +228049,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -39732,6 +228073,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -39755,6 +228097,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -39778,6 +228121,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -39801,6 +228145,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -39824,6 +228169,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -39847,6 +228193,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -39871,6 +228218,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -39900,6 +228248,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -39927,6 +228276,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -39956,6 +228306,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -39985,6 +228336,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -40014,6 +228366,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -40043,6 +228396,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -40072,6 +228426,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -40101,6 +228456,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -40129,6 +228485,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -40156,6 +228513,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -40184,6 +228542,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -40210,6 +228569,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -40233,6 +228593,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -40256,6 +228617,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -40280,6 +228642,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -40309,6 +228672,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -40336,6 +228700,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -40365,6 +228730,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -40394,6 +228760,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -40423,6 +228790,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -40452,6 +228820,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -40481,6 +228850,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -40509,6 +228879,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -40532,6 +228903,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -40555,6 +228927,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -40578,6 +228951,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -40601,6 +228975,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -40624,6 +228999,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -40647,6 +229023,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -40670,6 +229047,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -40693,6 +229071,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -40716,6 +229095,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -40739,6 +229119,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -40762,6 +229143,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -40785,6 +229167,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -40808,6 +229191,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -40831,6 +229215,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -40856,6 +229241,7 @@ "float32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -40889,6 +229275,7 @@ "float64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -40921,6 +229308,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -40953,6 +229341,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -40991,6 +229380,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -41029,6 +229419,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -41067,6 +229458,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -41105,6 +229497,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -41135,6 +229528,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -41171,6 +229565,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -41207,6 +229602,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -41243,6 +229639,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -41278,6 +229675,7 @@ "float32_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -41311,6 +229709,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -41344,6 +229743,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -41377,6 +229777,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -41410,6 +229811,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -41443,6 +229845,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -41476,6 +229879,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -41509,6 +229913,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -41542,6 +229947,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -41575,6 +229981,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -41608,6 +230015,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -41642,6 +230050,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -41678,6 +230087,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -41714,6 +230124,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -41750,6 +230161,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -41786,6 +230198,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -41822,6 +230235,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -41858,6 +230272,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -41894,6 +230309,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -41929,6 +230345,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -41960,6 +230377,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -41991,6 +230409,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42022,6 +230441,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42053,6 +230473,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -42084,6 +230505,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -42115,6 +230537,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -42146,6 +230569,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42177,6 +230601,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42208,6 +230633,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -42240,6 +230666,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -42278,6 +230705,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -42316,6 +230744,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42354,6 +230783,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42392,6 +230822,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -42428,6 +230859,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -42464,6 +230896,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42500,6 +230933,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42535,6 +230969,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -42568,6 +231003,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -42601,6 +231037,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42634,6 +231071,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42667,6 +231105,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -42700,6 +231139,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -42733,6 +231173,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -42766,6 +231207,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -42799,6 +231241,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -42832,6 +231275,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -42865,6 +231309,7 @@ "float32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -42898,6 +231343,7 @@ "float64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -42930,6 +231376,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -42962,6 +231409,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -43000,6 +231448,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -43038,6 +231487,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -43076,6 +231526,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -43114,6 +231565,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -43144,6 +231596,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -43180,6 +231633,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -43216,6 +231670,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -43252,6 +231707,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -43287,6 +231743,7 @@ "float32_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -43320,6 +231777,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -43353,6 +231811,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -43386,6 +231845,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -43419,6 +231879,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -43452,6 +231913,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -43485,6 +231947,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -43518,6 +231981,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -43551,6 +232015,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -43584,6 +232049,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -43617,6 +232083,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -43650,6 +232117,7 @@ "float32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -43683,6 +232151,7 @@ "float64x1_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -43715,6 +232184,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -43747,6 +232217,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -43785,6 +232256,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -43823,6 +232295,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -43861,6 +232334,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -43899,6 +232373,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -43929,6 +232404,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -43965,6 +232441,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -44001,6 +232478,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -44037,6 +232515,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -44072,6 +232551,7 @@ "float32_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -44105,6 +232585,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -44138,6 +232619,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -44171,6 +232653,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -44204,6 +232687,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -44237,6 +232721,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -44270,6 +232755,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -44303,6 +232789,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -44336,6 +232823,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -44369,6 +232857,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -44402,6 +232891,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -44436,6 +232926,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -44472,6 +232963,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -44508,6 +233000,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -44544,6 +233037,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -44580,6 +233074,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -44616,6 +233111,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -44652,6 +233148,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -44688,6 +233185,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -44723,6 +233221,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -44754,6 +233253,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -44785,6 +233285,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -44816,6 +233317,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -44847,6 +233349,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -44878,6 +233381,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -44909,6 +233413,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -44940,6 +233445,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -44971,6 +233477,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -45002,6 +233509,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -45034,6 +233542,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -45072,6 +233581,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -45110,6 +233620,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -45148,6 +233659,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -45186,6 +233698,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -45222,6 +233735,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -45258,6 +233772,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -45294,6 +233809,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -45329,6 +233845,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -45362,6 +233879,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -45395,6 +233913,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -45428,6 +233947,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -45461,6 +233981,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -45494,6 +234015,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -45527,6 +234049,7 @@ "int8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -45560,6 +234083,7 @@ "uint16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -45593,6 +234117,7 @@ "uint32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -45626,6 +234151,7 @@ "uint8x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -45659,6 +234185,7 @@ "float32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -45692,6 +234219,7 @@ "float64x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -45724,6 +234252,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -45756,6 +234285,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -45794,6 +234324,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -45832,6 +234363,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -45870,6 +234402,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -45908,6 +234441,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -45938,6 +234472,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -45974,6 +234509,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46010,6 +234546,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -46046,6 +234583,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -46081,6 +234619,7 @@ "float32_t c" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -46114,6 +234653,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -46147,6 +234687,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46180,6 +234721,7 @@ "uint16_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -46213,6 +234755,7 @@ "uint32_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -46246,6 +234789,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -46279,6 +234823,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46312,6 +234857,7 @@ "int8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -46345,6 +234891,7 @@ "uint16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -46378,6 +234925,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -46411,6 +234959,7 @@ "uint8x16_t c" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -46444,6 +234993,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46476,6 +235026,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -46506,6 +235057,7 @@ "float32_t value" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -46531,6 +235083,7 @@ "float64_t value" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -46554,6 +235107,7 @@ "poly16_t value" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -46579,6 +235133,7 @@ "poly8_t value" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -46604,6 +235159,7 @@ "int16_t value" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -46629,6 +235185,7 @@ "int32_t value" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -46654,6 +235211,7 @@ "int64_t value" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -46679,6 +235237,7 @@ "int8_t value" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -46704,6 +235263,7 @@ "uint16_t value" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -46729,6 +235289,7 @@ "uint32_t value" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -46754,6 +235315,7 @@ "uint64_t value" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -46779,6 +235341,7 @@ "uint8_t value" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -46804,6 +235367,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46827,6 +235391,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -46850,6 +235415,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -46873,6 +235439,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -46896,6 +235463,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -46919,6 +235487,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -46942,6 +235511,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -46967,6 +235537,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -46992,6 +235563,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -47017,6 +235589,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -47042,6 +235615,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -47067,6 +235641,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -47093,6 +235668,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -47122,6 +235698,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -47151,6 +235728,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -47180,6 +235758,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -47209,6 +235788,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -47238,6 +235818,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -47266,6 +235847,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -47291,6 +235873,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -47316,6 +235899,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -47341,6 +235925,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -47366,6 +235951,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -47391,6 +235977,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -47416,6 +236003,7 @@ "float32_t value" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -47441,6 +236029,7 @@ "float64_t value" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -47464,6 +236053,7 @@ "poly16_t value" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -47489,6 +236079,7 @@ "poly8_t value" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -47514,6 +236105,7 @@ "int16_t value" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -47539,6 +236131,7 @@ "int32_t value" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -47564,6 +236157,7 @@ "int64_t value" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -47589,6 +236183,7 @@ "int8_t value" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -47614,6 +236209,7 @@ "uint16_t value" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -47639,6 +236235,7 @@ "uint32_t value" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -47664,6 +236261,7 @@ "uint64_t value" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -47689,6 +236287,7 @@ "uint8_t value" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -47715,6 +236314,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -47744,6 +236344,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -47772,6 +236373,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -47806,6 +236408,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -47838,6 +236441,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -47872,6 +236476,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -47906,6 +236511,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -47940,6 +236546,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -47974,6 +236581,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -48006,6 +236614,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -48038,6 +236647,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -48070,6 +236680,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -48102,6 +236713,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -48134,6 +236746,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -48165,6 +236778,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -48194,6 +236808,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -48221,6 +236836,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -48250,6 +236866,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -48279,6 +236896,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -48308,6 +236926,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -48337,6 +236956,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -48366,6 +236986,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -48395,6 +237016,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -48424,6 +237046,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -48453,6 +237076,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -48482,6 +237106,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -48511,6 +237136,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -48541,6 +237167,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -48573,6 +237200,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -48605,6 +237233,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -48637,6 +237266,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -48669,6 +237299,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -48701,6 +237332,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -48733,6 +237365,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -48765,6 +237398,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -48797,6 +237431,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -48829,6 +237464,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -48860,6 +237496,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -48887,6 +237524,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -48914,6 +237552,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -48941,6 +237580,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -48968,6 +237608,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -48996,6 +237637,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -49023,6 +237665,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49050,6 +237693,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -49077,6 +237721,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -49104,6 +237749,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -49131,6 +237777,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -49158,6 +237805,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -49186,6 +237834,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49220,6 +237869,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -49254,6 +237904,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -49288,6 +237939,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -49322,6 +237974,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49354,6 +238007,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -49386,6 +238040,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -49418,6 +238073,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -49449,6 +238105,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49478,6 +238135,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -49507,6 +238165,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -49536,6 +238195,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -49565,6 +238225,7 @@ "poly64_t b" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -49593,6 +238254,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -49622,6 +238284,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49651,6 +238314,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -49680,6 +238344,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -49709,6 +238374,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -49738,6 +238404,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -49767,6 +238434,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -49796,6 +238464,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -49825,6 +238494,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -49853,6 +238523,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -49887,6 +238558,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -49919,6 +238591,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -49953,6 +238626,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -49987,6 +238661,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -50021,6 +238696,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -50055,6 +238731,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -50087,6 +238764,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -50119,6 +238797,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -50151,6 +238830,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -50183,6 +238863,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -50215,6 +238896,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -50246,6 +238928,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -50275,6 +238958,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -50302,6 +238986,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -50331,6 +239016,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -50360,6 +239046,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -50389,6 +239076,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -50418,6 +239106,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -50447,6 +239136,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -50476,6 +239166,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -50505,6 +239196,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -50534,6 +239226,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -50563,6 +239256,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -50592,6 +239286,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -50622,6 +239317,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -50654,6 +239350,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -50685,6 +239382,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -50712,6 +239410,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -50740,6 +239439,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -50772,6 +239472,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -50804,6 +239505,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -50836,6 +239538,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -50867,6 +239570,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -50895,6 +239599,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -50927,6 +239632,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -50958,6 +239664,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -50985,6 +239692,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -51013,6 +239721,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -51045,6 +239754,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -51077,6 +239787,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -51109,6 +239820,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -51140,6 +239852,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -51168,6 +239881,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -51200,6 +239914,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -51230,6 +239945,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -51255,6 +239971,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -51280,6 +239997,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -51305,6 +240023,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -51330,6 +240049,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -51355,6 +240075,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -51380,6 +240101,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -51405,6 +240127,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -51430,6 +240153,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -51455,6 +240179,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -51480,6 +240205,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -51505,6 +240231,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -51530,6 +240257,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -51555,6 +240283,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -51580,6 +240309,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -51605,6 +240335,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -51628,6 +240359,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -51653,6 +240385,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -51678,6 +240411,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -51701,6 +240435,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -51726,6 +240461,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -51749,6 +240485,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -51774,6 +240511,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -51797,6 +240535,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -51822,6 +240561,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -51847,6 +240587,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -51870,6 +240611,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -51896,6 +240638,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -51925,6 +240668,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -51954,6 +240698,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -51983,6 +240728,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -52012,6 +240758,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -52041,6 +240788,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -52070,6 +240818,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -52099,6 +240848,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -52128,6 +240878,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -52157,6 +240908,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -52186,6 +240938,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -52215,6 +240968,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -52244,6 +240998,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -52273,6 +241028,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -52302,6 +241058,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -52331,6 +241088,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -52360,6 +241118,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -52389,6 +241148,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -52418,6 +241178,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -52447,6 +241208,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -52476,6 +241238,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -52505,6 +241268,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -52534,6 +241298,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -52563,6 +241328,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -52592,6 +241358,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -52621,6 +241388,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -52650,6 +241418,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -52679,6 +241448,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -52708,6 +241478,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -52737,6 +241508,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -52766,6 +241538,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -52795,6 +241568,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -52824,6 +241598,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -52853,6 +241628,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -52882,6 +241658,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -52911,6 +241688,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -52940,6 +241718,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -52969,6 +241748,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -52998,6 +241778,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -53027,6 +241808,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -53056,6 +241838,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -53085,6 +241868,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -53114,6 +241898,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -53143,6 +241928,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -53172,6 +241958,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -53201,6 +241988,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -53230,6 +242018,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -53259,6 +242048,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -53288,6 +242078,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -53317,6 +242108,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -53346,6 +242138,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -53374,6 +242167,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -53397,6 +242191,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -53420,6 +242215,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -53443,6 +242239,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -53468,6 +242265,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -53493,6 +242291,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -53518,6 +242317,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -53543,6 +242343,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -53568,6 +242369,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -53593,6 +242395,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -53618,6 +242421,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -53643,6 +242447,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -53668,6 +242473,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -53693,6 +242499,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -53718,6 +242525,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -53744,6 +242552,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -53771,6 +242580,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -53798,6 +242608,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -53825,6 +242636,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -53852,6 +242664,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -53879,6 +242692,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -53906,6 +242720,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -53933,6 +242748,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -53960,6 +242776,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -53987,6 +242804,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -54013,6 +242831,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -54037,6 +242856,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -54066,6 +242886,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -54095,6 +242916,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -54124,6 +242946,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -54153,6 +242976,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -54182,6 +243006,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -54211,6 +243036,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -54240,6 +243066,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -54267,6 +243094,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -54294,6 +243122,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -54320,6 +243149,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -54343,6 +243173,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -54367,6 +243198,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -54394,6 +243226,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -54421,6 +243254,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -54448,6 +243282,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -54475,6 +243310,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -54502,6 +243338,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -54529,6 +243366,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -54556,6 +243394,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -54582,6 +243421,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -54605,6 +243445,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -54629,6 +243470,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -54658,6 +243500,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -54687,6 +243530,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -54716,6 +243560,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -54745,6 +243590,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -54774,6 +243620,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -54803,6 +243650,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -54832,6 +243680,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -54859,6 +243708,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -54886,6 +243736,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -54912,6 +243763,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -54935,6 +243787,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -54959,6 +243812,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -54986,6 +243840,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -55013,6 +243868,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -55040,6 +243896,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -55067,6 +243924,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -55094,6 +243952,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -55121,6 +243980,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -55148,6 +244008,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -55174,6 +244035,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -55197,6 +244059,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -55220,6 +244083,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -55245,6 +244109,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -55270,6 +244135,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -55293,6 +244159,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -55318,6 +244185,7 @@ "int8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -55341,6 +244209,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -55364,6 +244233,7 @@ "int16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -55387,6 +244257,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -55412,6 +244283,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -55437,6 +244309,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -55460,6 +244333,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -55485,6 +244359,7 @@ "int32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -55509,6 +244384,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -55538,6 +244414,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -55567,6 +244444,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -55596,6 +244474,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -55625,6 +244504,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -55654,6 +244534,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -55683,6 +244564,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -55712,6 +244594,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -55741,6 +244624,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -55768,6 +244652,7 @@ "uint8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -55795,6 +244680,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -55822,6 +244708,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -55849,6 +244736,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -55876,6 +244764,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -55903,6 +244792,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -55932,6 +244822,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -55961,6 +244852,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -55990,6 +244882,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -56019,6 +244912,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -56048,6 +244942,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -56077,6 +244972,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -56106,6 +245002,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -56135,6 +245032,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -56162,6 +245060,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -56191,6 +245090,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56227,6 +245127,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56263,6 +245164,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56299,6 +245201,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56334,6 +245237,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56365,6 +245269,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56396,6 +245301,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56427,6 +245333,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56459,6 +245366,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56497,6 +245405,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56535,6 +245444,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56571,6 +245481,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56606,6 +245517,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56639,6 +245551,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56672,6 +245585,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56705,6 +245619,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -56739,6 +245654,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -56775,6 +245691,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -56810,6 +245727,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -56842,6 +245760,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -56878,6 +245797,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -56913,6 +245833,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -56945,6 +245866,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -56981,6 +245903,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57017,6 +245940,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57053,6 +245977,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57088,6 +246013,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57119,6 +246045,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57150,6 +246077,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57181,6 +246109,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57213,6 +246142,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57251,6 +246181,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57289,6 +246220,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57325,6 +246257,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57360,6 +246293,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57393,6 +246327,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57426,6 +246361,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -57459,6 +246395,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -57493,6 +246430,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -57529,6 +246467,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -57564,6 +246503,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -57596,6 +246536,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -57632,6 +246573,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -57667,6 +246609,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -57698,6 +246641,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -57732,6 +246676,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -57766,6 +246711,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -57798,6 +246744,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -57829,6 +246776,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -57858,6 +246806,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -57887,6 +246836,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -57916,6 +246866,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -57946,6 +246897,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -57978,6 +246930,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -58009,6 +246962,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -58037,6 +246991,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -58071,6 +247026,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58105,6 +247061,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -58137,6 +247094,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58168,6 +247126,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -58197,6 +247156,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58226,6 +247186,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -58255,6 +247216,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58285,6 +247247,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58317,6 +247280,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58348,6 +247312,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58376,6 +247341,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58408,6 +247374,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58440,6 +247407,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58472,6 +247440,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58503,6 +247472,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58530,6 +247500,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58557,6 +247528,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58584,6 +247556,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58612,6 +247585,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58646,6 +247620,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58680,6 +247655,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58712,6 +247688,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58743,6 +247720,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58772,6 +247750,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58801,6 +247780,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -58830,6 +247810,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -58860,6 +247841,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58892,6 +247874,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58923,6 +247906,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -58951,6 +247935,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -58983,6 +247968,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -59014,6 +248000,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -59041,6 +248028,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -59068,6 +248056,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -59095,6 +248084,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -59122,6 +248112,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -59149,6 +248140,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -59176,6 +248168,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -59202,6 +248195,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -59227,6 +248221,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -59252,6 +248247,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -59277,6 +248273,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -59302,6 +248299,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -59327,6 +248325,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -59352,6 +248351,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -59375,6 +248375,7 @@ "uint64_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -59398,6 +248399,7 @@ "int16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -59421,6 +248423,7 @@ "uint16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -59444,6 +248447,7 @@ "int32_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -59467,6 +248471,7 @@ "uint32_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -59491,6 +248496,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -59518,6 +248524,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -59545,6 +248552,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -59571,6 +248579,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -59596,6 +248605,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -59621,6 +248631,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -59646,6 +248657,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -59669,6 +248681,7 @@ "int16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -59692,6 +248705,7 @@ "int32_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -59715,6 +248729,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -59740,6 +248755,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -59765,6 +248781,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -59788,6 +248805,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -59813,6 +248831,7 @@ "int8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -59836,6 +248855,7 @@ "int64_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -59859,6 +248879,7 @@ "int16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -59882,6 +248903,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -59907,6 +248929,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -59932,6 +248955,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -59955,6 +248979,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -59980,6 +249005,7 @@ "int32_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -60006,6 +249032,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60042,6 +249069,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60078,6 +249106,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60114,6 +249143,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60149,6 +249179,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60180,6 +249211,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60212,6 +249244,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60248,6 +249281,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60283,6 +249317,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60315,6 +249350,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -60351,6 +249387,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -60387,6 +249424,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -60423,6 +249461,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -60458,6 +249497,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -60489,6 +249529,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -60521,6 +249562,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -60557,6 +249599,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -60592,6 +249635,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -60624,6 +249668,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60660,6 +249705,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60696,6 +249742,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60732,6 +249779,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60767,6 +249815,7 @@ "int16x4_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -60798,6 +249847,7 @@ "int32x2_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -60830,6 +249880,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60866,6 +249917,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60901,6 +249953,7 @@ "int16_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -60933,6 +249986,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -60969,6 +250023,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61005,6 +250060,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61041,6 +250097,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61076,6 +250133,7 @@ "int16x8_t c" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61107,6 +250165,7 @@ "int32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61139,6 +250198,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61175,6 +250235,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61210,6 +250271,7 @@ "int32_t c" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61241,6 +250303,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -61275,6 +250338,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -61309,6 +250373,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -61341,6 +250406,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -61372,6 +250438,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -61401,6 +250468,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -61430,6 +250498,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -61459,6 +250528,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -61489,6 +250559,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -61521,6 +250592,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -61552,6 +250624,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -61580,6 +250653,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61614,6 +250688,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61648,6 +250723,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61680,6 +250756,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61711,6 +250788,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61740,6 +250818,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61769,6 +250848,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -61798,6 +250878,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -61828,6 +250909,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61860,6 +250942,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61891,6 +250974,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -61918,6 +251002,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -61947,6 +251032,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -61976,6 +251062,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -62005,6 +251092,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -62034,6 +251122,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -62063,6 +251152,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -62092,6 +251182,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -62121,6 +251212,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -62150,6 +251242,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -62177,6 +251270,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -62204,6 +251298,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -62231,6 +251326,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -62258,6 +251354,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -62285,6 +251382,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -62312,6 +251410,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -62341,6 +251440,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -62370,6 +251470,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -62399,6 +251500,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -62428,6 +251530,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -62457,6 +251560,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -62486,6 +251590,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -62515,6 +251620,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -62544,6 +251650,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -62571,6 +251678,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -62599,6 +251707,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -62631,6 +251740,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -62663,6 +251773,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -62695,6 +251806,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -62727,6 +251839,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -62759,6 +251872,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -62790,6 +251904,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -62820,6 +251935,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -62850,6 +251966,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -62880,6 +251997,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -62910,6 +252028,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -62940,6 +252059,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -62970,6 +252090,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -62998,6 +252119,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -63026,6 +252148,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -63054,6 +252177,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -63082,6 +252206,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -63110,6 +252235,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -63139,6 +252265,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -63171,6 +252298,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -63203,6 +252331,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -63234,6 +252363,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -63264,6 +252394,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -63294,6 +252425,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -63324,6 +252456,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -63352,6 +252485,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -63380,6 +252514,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -63408,6 +252543,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -63438,6 +252574,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -63468,6 +252605,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -63498,6 +252636,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -63528,6 +252667,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -63558,6 +252698,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -63588,6 +252729,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -63618,6 +252760,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -63648,6 +252791,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -63677,6 +252821,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -63706,6 +252851,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -63735,6 +252881,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -63764,6 +252911,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -63793,6 +252941,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -63822,6 +252971,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -63851,6 +253001,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -63880,6 +253031,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -63908,6 +253060,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -63936,6 +253089,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -63963,6 +253117,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -63990,6 +253145,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -64018,6 +253174,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -64046,6 +253203,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -64073,6 +253231,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -64100,6 +253259,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -64128,6 +253288,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -64156,6 +253317,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -64183,6 +253345,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -64210,6 +253373,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -64240,6 +253404,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -64270,6 +253435,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -64300,6 +253466,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -64330,6 +253497,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -64360,6 +253528,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -64390,6 +253559,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -64420,6 +253590,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -64450,6 +253621,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -64479,6 +253651,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -64508,6 +253681,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -64537,6 +253711,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -64566,6 +253741,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -64595,6 +253771,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -64624,6 +253801,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -64653,6 +253831,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -64682,6 +253861,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -64710,6 +253890,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -64738,6 +253919,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -64765,6 +253947,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -64792,6 +253975,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -64822,6 +254006,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -64852,6 +254037,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -64882,6 +254068,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -64912,6 +254099,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -64940,6 +254128,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -64968,6 +254157,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -64996,6 +254186,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -65026,6 +254217,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -65056,6 +254248,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -65086,6 +254279,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -65116,6 +254310,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -65145,6 +254340,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -65177,6 +254373,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -65209,6 +254406,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -65241,6 +254439,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -65273,6 +254472,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -65305,6 +254505,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -65336,6 +254537,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -65366,6 +254568,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -65396,6 +254599,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -65426,6 +254630,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -65456,6 +254661,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -65486,6 +254692,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -65516,6 +254723,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -65544,6 +254752,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -65572,6 +254781,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -65600,6 +254810,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -65628,6 +254839,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -65656,6 +254868,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -65685,6 +254898,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -65717,6 +254931,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -65749,6 +254964,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -65780,6 +254996,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -65810,6 +255027,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -65840,6 +255058,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -65870,6 +255089,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -65898,6 +255118,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -65926,6 +255147,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -65954,6 +255176,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -65983,6 +255206,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -66012,6 +255236,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -66041,6 +255266,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -66070,6 +255296,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -66099,6 +255326,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -66128,6 +255356,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -66157,6 +255386,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -66186,6 +255416,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -66213,6 +255444,7 @@ "uint8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -66240,6 +255472,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -66267,6 +255500,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -66294,6 +255528,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -66321,6 +255556,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -66348,6 +255584,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -66377,6 +255614,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -66406,6 +255644,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -66435,6 +255674,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -66464,6 +255704,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -66493,6 +255734,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -66522,6 +255764,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -66551,6 +255794,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -66580,6 +255824,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -66607,6 +255852,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -66634,6 +255880,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -66661,6 +255908,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -66688,6 +255936,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -66715,6 +255964,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -66742,6 +255992,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -66769,6 +256020,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -66796,6 +256048,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -66823,6 +256076,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -66850,6 +256104,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -66877,6 +256132,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -66904,6 +256160,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -66931,6 +256188,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -66958,6 +256216,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -66985,6 +256244,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67012,6 +256272,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67039,6 +256300,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67066,6 +256328,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67093,6 +256356,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -67120,6 +256384,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -67147,6 +256412,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67174,6 +256440,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67201,6 +256468,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67228,6 +256496,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67255,6 +256524,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -67283,6 +256553,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -67314,6 +256585,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67345,6 +256617,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67376,6 +256649,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67407,6 +256681,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67438,6 +256713,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -67469,6 +256745,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -67500,6 +256777,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67531,6 +256809,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67562,6 +256841,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67593,6 +256873,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67624,6 +256905,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -67655,6 +256937,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -67686,6 +256969,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67717,6 +257001,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67748,6 +257033,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67779,6 +257065,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67810,6 +257097,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -67841,6 +257129,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -67872,6 +257161,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -67903,6 +257193,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -67934,6 +257225,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -67965,6 +257257,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -67996,6 +257289,7 @@ "uint8x16_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -68027,6 +257321,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -68058,6 +257353,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -68089,6 +257385,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -68120,6 +257417,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -68151,6 +257449,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -68182,6 +257481,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -68212,6 +257512,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -68241,6 +257542,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -68270,6 +257572,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -68299,6 +257602,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -68328,6 +257632,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -68357,6 +257662,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -68386,6 +257692,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -68410,6 +257717,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -68433,6 +257741,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -68456,6 +257765,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -68479,6 +257789,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -68502,6 +257813,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -68525,6 +257837,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -68548,6 +257861,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -68573,6 +257887,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -68596,6 +257911,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -68621,6 +257937,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -68644,6 +257961,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -68669,6 +257987,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -68692,6 +258011,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -68717,6 +258037,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -68741,6 +258062,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -68770,6 +258092,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -68797,6 +258120,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -68824,6 +258148,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -68853,6 +258178,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -68880,6 +258206,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -68906,6 +258233,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -68929,6 +258257,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -68952,6 +258281,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -68975,6 +258305,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69000,6 +258331,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69025,6 +258357,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69050,6 +258383,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69075,6 +258409,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69100,6 +258435,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69125,6 +258461,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69150,6 +258487,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69175,6 +258513,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69200,6 +258539,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -69225,6 +258565,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69248,6 +258589,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69271,6 +258613,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69294,6 +258637,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69317,6 +258661,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69340,6 +258685,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69363,6 +258709,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69386,6 +258733,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69409,6 +258757,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69432,6 +258781,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69455,6 +258805,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69478,6 +258829,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -69501,6 +258853,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69526,6 +258879,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69549,6 +258903,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69573,6 +258928,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69598,6 +258954,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69623,6 +258980,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69648,6 +259006,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69673,6 +259032,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69698,6 +259058,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69723,6 +259084,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69748,6 +259110,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69773,6 +259136,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -69798,6 +259162,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69822,6 +259187,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69845,6 +259211,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69869,6 +259236,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69893,6 +259261,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69917,6 +259286,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69941,6 +259311,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69965,6 +259336,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -69989,6 +259361,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -70013,6 +259386,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -70037,6 +259411,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -70061,6 +259436,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70086,6 +259462,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70109,6 +259486,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70134,6 +259512,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70158,6 +259537,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70183,6 +259563,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70208,6 +259589,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70233,6 +259615,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70258,6 +259641,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70283,6 +259667,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70308,6 +259693,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70333,6 +259719,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -70358,6 +259745,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70383,6 +259771,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70406,6 +259795,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70431,6 +259821,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70455,6 +259846,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70480,6 +259872,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70505,6 +259898,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70530,6 +259924,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70555,6 +259950,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70580,6 +259976,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70605,6 +260002,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70630,6 +260028,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -70655,6 +260054,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70680,6 +260080,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70703,6 +260104,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70728,6 +260130,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70752,6 +260155,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70777,6 +260181,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70802,6 +260207,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70827,6 +260233,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70852,6 +260259,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70877,6 +260285,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70902,6 +260311,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70927,6 +260337,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -70952,6 +260363,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -70977,6 +260389,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71000,6 +260413,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71025,6 +260439,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71049,6 +260464,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71074,6 +260490,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71099,6 +260516,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71124,6 +260542,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71149,6 +260568,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71174,6 +260594,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71199,6 +260620,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71224,6 +260646,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -71249,6 +260672,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71274,6 +260698,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71297,6 +260722,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71322,6 +260748,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71346,6 +260773,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71371,6 +260799,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71396,6 +260825,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71421,6 +260851,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71446,6 +260877,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71471,6 +260903,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71496,6 +260929,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71521,6 +260955,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -71546,6 +260981,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71571,6 +261007,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71594,6 +261031,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71619,6 +261057,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71643,6 +261082,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71668,6 +261108,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71693,6 +261134,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71718,6 +261160,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71743,6 +261186,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71768,6 +261212,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71793,6 +261238,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71818,6 +261264,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -71843,6 +261290,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71868,6 +261316,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71891,6 +261340,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71916,6 +261366,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71940,6 +261391,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71965,6 +261417,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -71990,6 +261443,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72015,6 +261469,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72040,6 +261495,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72065,6 +261521,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72090,6 +261547,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72115,6 +261573,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -72140,6 +261599,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72165,6 +261625,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72188,6 +261649,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72213,6 +261675,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72237,6 +261700,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72262,6 +261726,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72287,6 +261752,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72312,6 +261778,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72337,6 +261804,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72362,6 +261830,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72387,6 +261856,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72412,6 +261882,7 @@ "uint8x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -72437,6 +261908,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72462,6 +261934,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72485,6 +261958,7 @@ "poly16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72510,6 +261984,7 @@ "poly64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72534,6 +262009,7 @@ "poly8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72559,6 +262035,7 @@ "int16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72584,6 +262061,7 @@ "int32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72609,6 +262087,7 @@ "int64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72634,6 +262113,7 @@ "int8x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72659,6 +262139,7 @@ "uint16x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72684,6 +262165,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72709,6 +262191,7 @@ "uint64x1_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -72734,6 +262217,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72757,6 +262241,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72782,6 +262267,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72807,6 +262293,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72832,6 +262319,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72857,6 +262345,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72882,6 +262371,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72907,6 +262397,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72932,6 +262423,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72957,6 +262449,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -72982,6 +262475,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -73007,6 +262501,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73030,6 +262525,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73053,6 +262549,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73076,6 +262573,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73099,6 +262597,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73122,6 +262621,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73145,6 +262645,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73168,6 +262669,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73191,6 +262693,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73214,6 +262717,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73237,6 +262741,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73260,6 +262765,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73285,6 +262791,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -73308,6 +262815,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73332,6 +262840,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73355,6 +262864,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73379,6 +262889,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73403,6 +262914,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73427,6 +262939,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73451,6 +262964,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73475,6 +262989,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73499,6 +263014,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73523,6 +263039,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73547,6 +263064,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73571,6 +263089,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -73595,6 +263114,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73620,6 +263140,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73643,6 +263164,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73667,6 +263189,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73691,6 +263214,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73716,6 +263240,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73741,6 +263266,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73766,6 +263292,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73791,6 +263318,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73816,6 +263344,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73841,6 +263370,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73866,6 +263396,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73891,6 +263422,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -73916,6 +263448,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -73940,6 +263473,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -73963,6 +263497,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -73987,6 +263522,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74011,6 +263547,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74035,6 +263572,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74059,6 +263597,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74083,6 +263622,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74107,6 +263647,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74131,6 +263672,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74155,6 +263697,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74179,6 +263722,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -74203,6 +263747,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74228,6 +263773,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74251,6 +263797,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74275,6 +263822,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74300,6 +263848,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74324,6 +263873,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74349,6 +263899,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74374,6 +263925,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74399,6 +263951,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74424,6 +263977,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74449,6 +264003,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74474,6 +264029,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74499,6 +264055,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -74524,6 +264081,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74549,6 +264107,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74572,6 +264131,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74596,6 +264156,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74621,6 +264182,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74645,6 +264207,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74670,6 +264233,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74695,6 +264259,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74720,6 +264285,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74745,6 +264311,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74770,6 +264337,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74795,6 +264363,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74820,6 +264389,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -74845,6 +264415,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74870,6 +264441,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74893,6 +264465,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74917,6 +264490,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74942,6 +264516,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74966,6 +264541,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -74991,6 +264567,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75016,6 +264593,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75041,6 +264619,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75066,6 +264645,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75091,6 +264671,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75116,6 +264697,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75141,6 +264723,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -75166,6 +264749,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75191,6 +264775,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75214,6 +264799,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75238,6 +264824,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75263,6 +264850,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75287,6 +264875,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75312,6 +264901,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75337,6 +264927,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75362,6 +264953,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75387,6 +264979,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75412,6 +265005,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75437,6 +265031,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75462,6 +265057,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -75487,6 +265083,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75512,6 +265109,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75535,6 +265133,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75559,6 +265158,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75584,6 +265184,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75608,6 +265209,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75633,6 +265235,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75658,6 +265261,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75683,6 +265287,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75708,6 +265313,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75733,6 +265339,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75758,6 +265365,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75783,6 +265391,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -75808,6 +265417,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75833,6 +265443,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75856,6 +265467,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75880,6 +265492,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75905,6 +265518,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75929,6 +265543,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75954,6 +265569,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -75979,6 +265595,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76004,6 +265621,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76029,6 +265647,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76054,6 +265673,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76079,6 +265699,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76104,6 +265725,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -76129,6 +265751,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76154,6 +265777,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76177,6 +265801,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76201,6 +265826,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76226,6 +265852,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76250,6 +265877,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76275,6 +265903,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76300,6 +265929,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76325,6 +265955,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76350,6 +265981,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76375,6 +266007,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76400,6 +266033,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76425,6 +266059,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -76450,6 +266085,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76475,6 +266111,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76498,6 +266135,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76522,6 +266160,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76547,6 +266186,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76571,6 +266211,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76596,6 +266237,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76621,6 +266263,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76646,6 +266289,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76671,6 +266315,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76696,6 +266341,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76721,6 +266367,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76746,6 +266393,7 @@ "uint8x16_t a" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -76771,6 +266419,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76796,6 +266445,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76819,6 +266469,7 @@ "poly128_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76843,6 +266494,7 @@ "poly16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76868,6 +266520,7 @@ "poly64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76892,6 +266545,7 @@ "poly8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76917,6 +266571,7 @@ "int16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76942,6 +266597,7 @@ "int32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76967,6 +266623,7 @@ "int64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -76992,6 +266649,7 @@ "int8x16_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77017,6 +266675,7 @@ "uint16x8_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77042,6 +266701,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77067,6 +266727,7 @@ "uint64x2_t a" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77092,6 +266753,7 @@ "poly8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -77117,6 +266779,7 @@ "int8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -77142,6 +266805,7 @@ "uint8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -77167,6 +266831,7 @@ "poly8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -77192,6 +266857,7 @@ "int8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -77217,6 +266883,7 @@ "uint8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77242,6 +266909,7 @@ "poly16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -77267,6 +266935,7 @@ "poly8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -77292,6 +266961,7 @@ "int16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -77317,6 +266987,7 @@ "int8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -77342,6 +267013,7 @@ "uint16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -77367,6 +267039,7 @@ "uint8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -77392,6 +267065,7 @@ "poly16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -77417,6 +267091,7 @@ "poly8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -77442,6 +267117,7 @@ "int16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -77467,6 +267143,7 @@ "int8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -77492,6 +267169,7 @@ "uint16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -77517,6 +267195,7 @@ "uint8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77542,6 +267221,7 @@ "float32x2_t vec" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -77567,6 +267247,7 @@ "poly16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -77592,6 +267273,7 @@ "poly8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -77617,6 +267299,7 @@ "int16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -77642,6 +267325,7 @@ "int32x2_t vec" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -77667,6 +267351,7 @@ "int8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -77692,6 +267377,7 @@ "uint16x4_t vec" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -77717,6 +267403,7 @@ "uint32x2_t vec" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -77742,6 +267429,7 @@ "uint8x8_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -77767,6 +267455,7 @@ "float32x4_t vec" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -77792,6 +267481,7 @@ "poly16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -77817,6 +267507,7 @@ "poly8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -77842,6 +267533,7 @@ "int16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -77867,6 +267559,7 @@ "int32x4_t vec" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -77892,6 +267585,7 @@ "int8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -77917,6 +267611,7 @@ "uint16x8_t vec" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -77942,6 +267637,7 @@ "uint32x4_t vec" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -77967,6 +267663,7 @@ "uint8x16_t vec" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -77993,6 +267690,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -78022,6 +267720,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -78051,6 +267750,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -78080,6 +267780,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -78109,6 +267810,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -78138,6 +267840,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -78167,6 +267870,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -78196,6 +267900,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -78225,6 +267930,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -78254,6 +267960,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -78283,6 +267990,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -78312,6 +268020,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -78340,6 +268049,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78363,6 +268073,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78386,6 +268097,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78409,6 +268121,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78432,6 +268145,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78455,6 +268169,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78478,6 +268193,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78501,6 +268217,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78524,6 +268241,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78547,6 +268265,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78570,6 +268289,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78593,6 +268313,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78616,6 +268337,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78639,6 +268361,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78662,6 +268385,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78685,6 +268409,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78708,6 +268433,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78732,6 +268458,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78755,6 +268482,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78779,6 +268507,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78802,6 +268531,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78826,6 +268556,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78849,6 +268580,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78873,6 +268605,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78896,6 +268629,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -78920,6 +268654,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -78943,6 +268678,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -78967,6 +268703,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -78990,6 +268727,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -79014,6 +268752,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -79037,6 +268776,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -79061,6 +268801,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -79085,6 +268826,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -79109,6 +268851,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -79133,6 +268876,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -79157,6 +268901,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -79181,6 +268926,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -79204,6 +268950,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -79228,6 +268975,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -79251,6 +268999,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -79275,6 +269024,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -79298,6 +269048,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -79322,6 +269073,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -79345,6 +269097,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -79369,6 +269122,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -79393,6 +269147,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -79422,6 +269177,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -79451,6 +269207,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -79480,6 +269237,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -79509,6 +269267,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -79538,6 +269297,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -79567,6 +269327,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -79596,6 +269357,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -79625,6 +269387,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -79652,6 +269415,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -79679,6 +269443,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -79708,6 +269473,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -79737,6 +269503,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -79766,6 +269533,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -79795,6 +269563,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -79824,6 +269593,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -79853,6 +269623,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -79882,6 +269653,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -79911,6 +269683,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -79941,6 +269714,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -79971,6 +269745,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -80001,6 +269776,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -80031,6 +269807,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -80061,6 +269838,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -80091,6 +269869,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -80121,6 +269900,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -80151,6 +269931,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -80179,6 +269960,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -80208,6 +269990,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -80240,6 +270023,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -80272,6 +270056,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -80304,6 +270089,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -80336,6 +270122,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -80368,6 +270155,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -80399,6 +270187,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -80429,6 +270218,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -80459,6 +270249,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -80489,6 +270280,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -80519,6 +270311,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -80549,6 +270342,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -80579,6 +270373,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -80609,6 +270404,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -80639,6 +270435,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -80669,6 +270466,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -80699,6 +270497,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -80729,6 +270528,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -80759,6 +270559,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -80789,6 +270590,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -80818,6 +270620,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -80843,6 +270646,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -80866,6 +270670,7 @@ "uint32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -80891,6 +270696,7 @@ "float64_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -80914,6 +270720,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -80939,6 +270746,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -80962,6 +270770,7 @@ "uint32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -80987,6 +270796,7 @@ "float32_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -81011,6 +270821,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -81040,6 +270851,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -81067,6 +270879,7 @@ "float64_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -81094,6 +270907,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -81123,6 +270937,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -81150,6 +270965,7 @@ "float32_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -81178,6 +270994,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -81212,6 +271029,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -81246,6 +271064,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -81280,6 +271099,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -81314,6 +271134,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -81348,6 +271169,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -81382,6 +271204,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -81416,6 +271239,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -81450,6 +271274,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -81482,6 +271307,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -81514,6 +271340,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -81548,6 +271375,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -81582,6 +271410,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -81616,6 +271445,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -81650,6 +271480,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -81684,6 +271515,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -81718,6 +271550,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -81752,6 +271585,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -81786,6 +271620,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -81817,6 +271652,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -81848,6 +271684,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -81879,6 +271716,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -81910,6 +271748,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -81941,6 +271780,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -81971,6 +271811,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -82000,6 +271841,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -82029,6 +271871,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -82058,6 +271901,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -82087,6 +271931,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -82116,6 +271961,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -82146,6 +271992,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -82180,6 +272027,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -82212,6 +272060,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -82246,6 +272095,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -82279,6 +272129,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -82313,6 +272164,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -82347,6 +272199,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -82381,6 +272234,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -82415,6 +272269,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -82449,6 +272304,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -82483,6 +272339,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -82517,6 +272374,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -82551,6 +272409,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -82585,6 +272444,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -82619,6 +272479,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -82651,6 +272512,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -82685,6 +272547,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -82718,6 +272581,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -82752,6 +272616,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -82786,6 +272651,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -82820,6 +272686,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -82854,6 +272721,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -82888,6 +272756,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -82922,6 +272791,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -82956,6 +272826,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -82990,6 +272861,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -83024,6 +272896,7 @@ "uint32x4_t wk" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83054,6 +272927,7 @@ "uint32_t hash_e" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -83080,6 +272954,7 @@ "uint32x4_t wk" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83112,6 +272987,7 @@ "uint32x4_t wk" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83144,6 +273020,7 @@ "uint32x4_t w8_11" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83175,6 +273052,7 @@ "uint32x4_t w12_15" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83204,6 +273082,7 @@ "uint32x4_t wk" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83236,6 +273115,7 @@ "uint32x4_t wk" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83267,6 +273147,7 @@ "uint32x4_t w4_7" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83296,6 +273177,7 @@ "uint32x4_t w12_15" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -83328,6 +273210,7 @@ "uint64x2_t hash_ab" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -83357,6 +273240,7 @@ "uint64x2_t kwh_kwh2" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -83385,6 +273269,7 @@ "uint64x2_t w2_" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -83413,6 +273298,7 @@ "uint64x2_t w9_10" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -83441,6 +273327,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -83471,6 +273358,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -83501,6 +273389,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -83531,6 +273420,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -83561,6 +273451,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -83591,6 +273482,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -83621,6 +273513,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -83651,6 +273544,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -83681,6 +273575,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -83710,6 +273605,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -83739,6 +273635,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -83768,6 +273665,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -83797,6 +273695,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -83826,6 +273725,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -83855,6 +273755,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -83884,6 +273785,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -83913,6 +273815,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -83941,6 +273844,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -83969,6 +273873,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -83996,6 +273901,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -84023,6 +273929,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -84031,7 +273938,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84051,6 +273958,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -84059,7 +273967,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84079,6 +273987,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -84087,7 +273996,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84107,6 +274016,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -84115,7 +274025,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84135,6 +274045,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -84143,7 +274054,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84163,6 +274074,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -84171,7 +274083,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84191,6 +274103,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -84199,7 +274112,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84221,6 +274134,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -84229,7 +274143,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84251,6 +274165,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -84259,7 +274174,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84281,6 +274196,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -84289,7 +274205,7 @@ }, "n": { "minimum": 0, - "maximum": 15 + "maximum": 16 } }, "Architectures": [ @@ -84311,6 +274227,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -84319,7 +274236,7 @@ }, "n": { "minimum": 0, - "maximum": 31 + "maximum": 32 } }, "Architectures": [ @@ -84341,6 +274258,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -84349,7 +274267,7 @@ }, "n": { "minimum": 0, - "maximum": 7 + "maximum": 8 } }, "Architectures": [ @@ -84371,6 +274289,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -84401,6 +274320,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -84431,6 +274351,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -84461,6 +274382,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -84491,6 +274413,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -84521,6 +274444,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -84551,6 +274475,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -84581,6 +274506,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -84611,6 +274537,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -84640,6 +274567,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -84669,6 +274597,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -84698,6 +274627,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -84727,6 +274657,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -84756,6 +274687,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -84785,6 +274717,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -84814,6 +274747,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -84843,6 +274777,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -84873,6 +274808,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -84903,6 +274839,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -84933,6 +274870,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -84963,6 +274901,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -84993,6 +274932,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -85023,6 +274963,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -85053,6 +274994,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -85083,6 +275025,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -85111,6 +275054,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -85140,6 +275084,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -85172,6 +275117,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -85204,6 +275150,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -85236,6 +275183,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -85268,6 +275216,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -85300,6 +275249,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -85331,6 +275281,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -85361,6 +275312,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -85391,6 +275343,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -85421,6 +275374,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -85451,6 +275405,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -85481,6 +275436,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -85511,6 +275467,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -85541,6 +275498,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -85571,6 +275529,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -85601,6 +275560,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -85631,6 +275591,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -85661,6 +275622,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -85691,6 +275653,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -85721,6 +275684,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -85752,6 +275716,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -85786,6 +275751,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -85819,6 +275785,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -85853,6 +275820,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -85887,6 +275855,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -85921,6 +275890,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -85955,6 +275925,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -85989,6 +275960,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -86023,6 +275995,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -86057,6 +276030,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -86091,6 +276065,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -86125,6 +276100,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -86157,6 +276133,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -86189,6 +276166,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -86223,6 +276201,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -86256,6 +276235,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -86290,6 +276270,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -86324,6 +276305,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -86358,6 +276340,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -86392,6 +276375,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -86426,6 +276410,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -86460,6 +276445,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86494,6 +276480,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -86528,6 +276515,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -86562,6 +276550,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86589,6 +276578,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86616,6 +276606,7 @@ "uint32x4_t c" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86644,6 +276635,7 @@ "const int imm2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86676,6 +276668,7 @@ "const int imm2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86708,6 +276701,7 @@ "const int imm2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86740,6 +276734,7 @@ "const int imm2" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86770,6 +276765,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86795,6 +276791,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -86820,6 +276817,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -86847,6 +276845,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -86874,6 +276873,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -86901,6 +276901,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -86928,6 +276929,7 @@ "int8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -86955,6 +276957,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -86982,6 +276985,7 @@ "int16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -87009,6 +277013,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -87036,6 +277041,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -87063,6 +277069,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -87090,6 +277097,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -87117,6 +277125,7 @@ "int32_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -87143,6 +277152,7 @@ "float32x2_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -87166,6 +277176,7 @@ "float64x1_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -87189,6 +277200,7 @@ "float32x4_t a" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -87212,6 +277224,7 @@ "float64x2_t a" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -87237,6 +277250,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -87271,6 +277285,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -87305,6 +277320,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -87339,6 +277355,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -87373,6 +277390,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -87407,6 +277425,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -87441,6 +277460,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -87475,6 +277495,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -87509,6 +277530,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -87541,6 +277563,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -87573,6 +277596,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -87607,6 +277631,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -87641,6 +277666,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -87675,6 +277701,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -87709,6 +277736,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -87743,6 +277771,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -87777,6 +277806,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -87811,6 +277841,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -87845,6 +277876,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -87879,6 +277911,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -87912,6 +277945,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -87946,6 +277980,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -87980,6 +278015,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -88014,6 +278050,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -88048,6 +278085,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -88082,6 +278120,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -88116,6 +278155,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -88150,6 +278190,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -88184,6 +278225,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -88218,6 +278260,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -88250,6 +278293,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -88282,6 +278326,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -88316,6 +278361,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -88349,6 +278395,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -88383,6 +278430,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -88417,6 +278465,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -88451,6 +278500,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -88485,6 +278535,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -88519,6 +278570,7 @@ "const int n" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -88553,6 +278605,7 @@ "const int n" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -88587,6 +278640,7 @@ "const int n" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -88621,6 +278675,7 @@ "const int n" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -88654,6 +278709,7 @@ "float32x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88683,6 +278739,7 @@ "float32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88712,6 +278769,7 @@ "float32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88741,6 +278799,7 @@ "float32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88770,6 +278829,7 @@ "float64x1_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88797,6 +278857,7 @@ "float64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88824,6 +278885,7 @@ "float64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88851,6 +278913,7 @@ "float64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88879,6 +278942,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88913,6 +278977,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88945,6 +279010,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -88979,6 +279045,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89012,6 +279079,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89046,6 +279114,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89080,6 +279149,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89114,6 +279184,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89148,6 +279219,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89182,6 +279254,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89216,6 +279289,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89250,6 +279324,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89284,6 +279359,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89317,6 +279393,7 @@ "poly16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89346,6 +279423,7 @@ "poly16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89375,6 +279453,7 @@ "poly16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89404,6 +279483,7 @@ "poly16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89433,6 +279513,7 @@ "poly64x1_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89461,6 +279542,7 @@ "poly64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89489,6 +279571,7 @@ "poly64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89517,6 +279600,7 @@ "poly64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89545,6 +279629,7 @@ "poly8x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89574,6 +279659,7 @@ "poly8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89603,6 +279689,7 @@ "poly8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89632,6 +279719,7 @@ "poly8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89661,6 +279749,7 @@ "int16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89690,6 +279779,7 @@ "int16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89719,6 +279809,7 @@ "int16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89748,6 +279839,7 @@ "int16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89777,6 +279869,7 @@ "int32x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89806,6 +279899,7 @@ "int32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89835,6 +279929,7 @@ "int32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89864,6 +279959,7 @@ "int32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89893,6 +279989,7 @@ "int64x1_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89922,6 +280019,7 @@ "int64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89951,6 +280049,7 @@ "int64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -89980,6 +280079,7 @@ "int64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90009,6 +280109,7 @@ "int8x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90038,6 +280139,7 @@ "int8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90067,6 +280169,7 @@ "int8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90096,6 +280199,7 @@ "int8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90125,6 +280229,7 @@ "uint16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90154,6 +280259,7 @@ "uint16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90183,6 +280289,7 @@ "uint16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90212,6 +280319,7 @@ "uint16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90241,6 +280349,7 @@ "uint32x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90270,6 +280379,7 @@ "uint32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90299,6 +280409,7 @@ "uint32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90328,6 +280439,7 @@ "uint32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90357,6 +280469,7 @@ "uint64x1_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90386,6 +280499,7 @@ "uint64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90415,6 +280529,7 @@ "uint64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90444,6 +280559,7 @@ "uint64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90473,6 +280589,7 @@ "uint8x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90502,6 +280619,7 @@ "uint8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90531,6 +280649,7 @@ "uint8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90560,6 +280679,7 @@ "uint8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90589,6 +280709,7 @@ "float32x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90618,6 +280739,7 @@ "float32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90647,6 +280769,7 @@ "float32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90676,6 +280799,7 @@ "float32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90705,6 +280829,7 @@ "float64x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90732,6 +280857,7 @@ "float64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90759,6 +280885,7 @@ "float64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90786,6 +280913,7 @@ "float64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90814,6 +280942,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90848,6 +280977,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90880,6 +281010,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90914,6 +281045,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90947,6 +281079,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -90981,6 +281114,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91015,6 +281149,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91049,6 +281184,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91083,6 +281219,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91117,6 +281254,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91151,6 +281289,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91185,6 +281324,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91219,6 +281359,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91252,6 +281393,7 @@ "poly16x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91281,6 +281423,7 @@ "poly16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91310,6 +281453,7 @@ "poly16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91339,6 +281483,7 @@ "poly16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91368,6 +281513,7 @@ "poly64x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91396,6 +281542,7 @@ "poly64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91424,6 +281571,7 @@ "poly64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91453,6 +281601,7 @@ "poly64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91481,6 +281630,7 @@ "poly8x16_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91510,6 +281660,7 @@ "poly8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91539,6 +281690,7 @@ "poly8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91568,6 +281720,7 @@ "poly8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91597,6 +281750,7 @@ "int16x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91626,6 +281780,7 @@ "int16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91655,6 +281810,7 @@ "int16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91684,6 +281840,7 @@ "int16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91713,6 +281870,7 @@ "int32x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91742,6 +281900,7 @@ "int32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91771,6 +281930,7 @@ "int32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91800,6 +281960,7 @@ "int32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91829,6 +281990,7 @@ "int64x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91858,6 +282020,7 @@ "int64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91887,6 +282050,7 @@ "int64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91916,6 +282080,7 @@ "int64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91945,6 +282110,7 @@ "int8x16_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -91974,6 +282140,7 @@ "int8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92003,6 +282170,7 @@ "int8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92032,6 +282200,7 @@ "int8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92061,6 +282230,7 @@ "uint16x8_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92090,6 +282260,7 @@ "uint16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92119,6 +282290,7 @@ "uint16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92148,6 +282320,7 @@ "uint16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92177,6 +282350,7 @@ "uint32x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92206,6 +282380,7 @@ "uint32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92235,6 +282410,7 @@ "uint32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92264,6 +282440,7 @@ "uint32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92293,6 +282470,7 @@ "uint64x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92322,6 +282500,7 @@ "uint64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92351,6 +282530,7 @@ "uint64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92380,6 +282560,7 @@ "uint64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92409,6 +282590,7 @@ "uint8x16_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92438,6 +282620,7 @@ "uint8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92467,6 +282650,7 @@ "uint8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92496,6 +282680,7 @@ "uint8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92525,6 +282710,7 @@ "float32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92554,6 +282740,7 @@ "float64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92582,6 +282769,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92616,6 +282804,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92648,6 +282837,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92682,6 +282872,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92714,6 +282905,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92748,6 +282940,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92782,6 +282975,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92816,6 +283010,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92848,6 +283043,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92882,6 +283078,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92916,6 +283113,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92950,6 +283148,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -92982,6 +283181,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93015,6 +283215,7 @@ "poly16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93044,6 +283245,7 @@ "poly64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93072,6 +283274,7 @@ "poly8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93101,6 +283304,7 @@ "int16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93130,6 +283334,7 @@ "int32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93159,6 +283364,7 @@ "int64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93188,6 +283394,7 @@ "int8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93217,6 +283424,7 @@ "uint16x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93246,6 +283454,7 @@ "uint32x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93275,6 +283484,7 @@ "uint64x1x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93304,6 +283514,7 @@ "uint8x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93333,6 +283544,7 @@ "float32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93362,6 +283574,7 @@ "float64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93390,6 +283603,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93424,6 +283638,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93456,6 +283671,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93490,6 +283706,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93522,6 +283739,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93554,6 +283772,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93588,6 +283807,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93622,6 +283842,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93654,6 +283875,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93686,6 +283908,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93720,6 +283943,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93754,6 +283978,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93786,6 +284011,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93817,6 +284043,7 @@ "poly16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93846,6 +284073,7 @@ "poly64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93873,6 +284101,7 @@ "poly8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93902,6 +284131,7 @@ "int16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93931,6 +284161,7 @@ "int32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93960,6 +284191,7 @@ "int64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -93987,6 +284219,7 @@ "int8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94016,6 +284249,7 @@ "uint16x8x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94045,6 +284279,7 @@ "uint32x4x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94074,6 +284309,7 @@ "uint64x2x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94101,6 +284337,7 @@ "uint8x16x2_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94130,6 +284367,7 @@ "float32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94159,6 +284397,7 @@ "float64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94187,6 +284426,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94221,6 +284461,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94253,6 +284494,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94287,6 +284529,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94319,6 +284562,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94353,6 +284597,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94387,6 +284632,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94421,6 +284667,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94453,6 +284700,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94487,6 +284735,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94521,6 +284770,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94555,6 +284805,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94587,6 +284838,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94620,6 +284872,7 @@ "poly16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94649,6 +284902,7 @@ "poly64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94677,6 +284931,7 @@ "poly8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94706,6 +284961,7 @@ "int16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94735,6 +284991,7 @@ "int32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94764,6 +285021,7 @@ "int64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94793,6 +285051,7 @@ "int8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94822,6 +285081,7 @@ "uint16x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94851,6 +285111,7 @@ "uint32x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94880,6 +285141,7 @@ "uint64x1x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94909,6 +285171,7 @@ "uint8x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94938,6 +285201,7 @@ "float32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94967,6 +285231,7 @@ "float64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -94995,6 +285260,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95029,6 +285295,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95061,6 +285328,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95095,6 +285363,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95127,6 +285396,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95161,6 +285431,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95195,6 +285466,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95229,6 +285501,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95261,6 +285534,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95295,6 +285569,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95329,6 +285604,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95363,6 +285639,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95395,6 +285672,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95428,6 +285706,7 @@ "poly16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95457,6 +285736,7 @@ "poly64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95484,6 +285764,7 @@ "poly8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95513,6 +285794,7 @@ "int16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95542,6 +285824,7 @@ "int32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95571,6 +285854,7 @@ "int64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95598,6 +285882,7 @@ "int8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95627,6 +285912,7 @@ "uint16x8x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95656,6 +285942,7 @@ "uint32x4x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95685,6 +285972,7 @@ "uint64x2x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95712,6 +286000,7 @@ "uint8x16x3_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95741,6 +286030,7 @@ "float32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95770,6 +286060,7 @@ "float64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95798,6 +286089,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95832,6 +286124,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95864,6 +286157,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95898,6 +286192,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95930,6 +286225,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95964,6 +286260,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -95998,6 +286295,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96032,6 +286330,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96064,6 +286363,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96098,6 +286398,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96132,6 +286433,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96166,6 +286468,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96198,6 +286501,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96231,6 +286535,7 @@ "poly16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96260,6 +286565,7 @@ "poly64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96288,6 +286594,7 @@ "poly8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96317,6 +286624,7 @@ "int16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96346,6 +286654,7 @@ "int32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96375,6 +286684,7 @@ "int64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96404,6 +286714,7 @@ "int8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96433,6 +286744,7 @@ "uint16x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96462,6 +286774,7 @@ "uint32x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96491,6 +286804,7 @@ "uint64x1x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96520,6 +286834,7 @@ "uint8x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96549,6 +286864,7 @@ "float32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96578,6 +286894,7 @@ "float64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96606,6 +286923,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96640,6 +286958,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96672,6 +286991,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96706,6 +287026,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96738,6 +287059,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96770,6 +287092,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96804,6 +287127,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96838,6 +287162,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96870,6 +287195,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96902,6 +287228,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96936,6 +287263,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -96970,6 +287298,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97002,6 +287331,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97033,6 +287363,7 @@ "poly16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97062,6 +287393,7 @@ "poly64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97089,6 +287421,7 @@ "poly8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97118,6 +287451,7 @@ "int16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97147,6 +287481,7 @@ "int32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97176,6 +287511,7 @@ "int64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97203,6 +287539,7 @@ "int8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97232,6 +287569,7 @@ "uint16x8x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97261,6 +287599,7 @@ "uint32x4x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97290,6 +287629,7 @@ "uint64x2x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97317,6 +287657,7 @@ "uint8x16x4_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97346,6 +287687,7 @@ "poly128_t val" ], "return_type": { + "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -97374,6 +287716,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -97403,6 +287746,7 @@ "float64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -97430,6 +287774,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -97459,6 +287804,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -97488,6 +287834,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -97517,6 +287864,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -97546,6 +287894,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -97575,6 +287924,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -97604,6 +287954,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -97633,6 +287984,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -97662,6 +288014,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -97689,6 +288042,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -97717,6 +288071,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -97748,6 +288103,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -97779,6 +288135,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -97810,6 +288167,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -97841,6 +288199,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -97872,6 +288231,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -97902,6 +288262,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -97931,6 +288292,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -97960,6 +288322,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -97989,6 +288352,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -98018,6 +288382,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -98047,6 +288412,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -98076,6 +288442,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -98103,6 +288470,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -98130,6 +288498,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -98157,6 +288526,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -98184,6 +288554,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -98211,6 +288582,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -98238,6 +288610,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -98267,6 +288640,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -98296,6 +288670,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -98325,6 +288700,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -98354,6 +288730,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -98383,6 +288760,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -98412,6 +288790,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -98441,6 +288820,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -98468,6 +288848,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -98497,6 +288878,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -98526,6 +288908,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -98555,6 +288938,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -98584,6 +288968,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -98613,6 +288998,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -98642,6 +289028,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -98671,6 +289058,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -98700,6 +289088,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -98727,6 +289116,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -98754,6 +289144,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -98781,6 +289172,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -98808,6 +289200,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -98835,6 +289228,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -98862,6 +289256,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -98891,6 +289286,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -98920,6 +289316,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -98949,6 +289346,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -98978,6 +289376,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -99007,6 +289406,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -99038,6 +289438,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -99075,6 +289476,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -99111,6 +289513,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -99148,6 +289551,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -99182,6 +289586,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99209,6 +289614,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99236,6 +289642,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99263,6 +289670,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99290,6 +289698,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99317,6 +289726,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99344,6 +289754,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99371,6 +289782,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99398,6 +289810,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99425,6 +289838,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99452,6 +289866,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99479,6 +289894,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99507,6 +289923,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99539,6 +289956,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99571,6 +289989,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99603,6 +290022,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99632,6 +290052,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99661,6 +290082,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99690,6 +290112,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99722,6 +290145,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99754,6 +290178,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99786,6 +290211,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99815,6 +290241,7 @@ "int8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -99844,6 +290271,7 @@ "uint8x8_t idx" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -99872,6 +290300,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -99899,6 +290328,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -99926,6 +290356,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -99953,6 +290384,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -99980,6 +290412,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -100007,6 +290440,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -100034,6 +290468,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -100061,6 +290496,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -100088,6 +290524,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -100115,6 +290552,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -100142,6 +290580,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -100169,6 +290608,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -100196,6 +290636,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -100223,6 +290664,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -100250,6 +290692,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -100277,6 +290720,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -100304,6 +290748,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -100331,6 +290776,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -100358,6 +290804,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -100385,6 +290832,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -100412,6 +290860,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -100439,6 +290888,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -100466,6 +290916,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -100493,6 +290944,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -100520,6 +290972,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -100547,6 +291000,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -100574,6 +291028,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -100601,6 +291056,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -100628,6 +291084,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -100655,6 +291112,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -100682,6 +291140,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -100709,6 +291168,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -100736,6 +291196,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -100763,6 +291224,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -100790,6 +291252,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -100817,6 +291280,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -100844,6 +291308,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -100871,6 +291336,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -100898,6 +291364,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -100925,6 +291392,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -100952,6 +291420,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -100979,6 +291448,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -101006,6 +291476,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -101033,6 +291504,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -101060,6 +291532,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -101090,6 +291563,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -101120,6 +291594,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -101150,6 +291625,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -101180,6 +291656,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -101210,6 +291687,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -101240,6 +291718,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -101270,6 +291749,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -101300,6 +291780,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -101330,6 +291811,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -101360,6 +291842,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -101390,6 +291873,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -101420,6 +291904,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -101450,6 +291935,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -101480,6 +291966,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -101510,6 +291997,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -101540,6 +292028,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -101570,6 +292059,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -101600,6 +292090,7 @@ "poly64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -101628,6 +292119,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -101657,6 +292149,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -101686,6 +292179,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -101715,6 +292209,7 @@ "int64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -101742,6 +292237,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -101771,6 +292267,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -101800,6 +292297,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -101829,6 +292327,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -101856,6 +292355,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -101885,6 +292385,7 @@ "int64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -101912,6 +292413,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -101939,6 +292441,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -101967,6 +292470,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -101996,6 +292500,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -102025,6 +292530,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -102054,6 +292560,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -102081,6 +292588,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -102110,6 +292618,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -102139,6 +292648,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -102168,6 +292678,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -102195,6 +292706,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -102224,6 +292736,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -102251,6 +292764,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -102278,6 +292792,7 @@ "uint64x1_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -102305,6 +292820,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -102332,6 +292848,7 @@ "uint8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -102359,6 +292876,7 @@ "uint64_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -102386,6 +292904,7 @@ "uint16_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -102413,6 +292932,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -102440,6 +292960,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -102467,6 +292988,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -102494,6 +293016,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -102521,6 +293044,7 @@ "uint32_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -102550,6 +293074,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -102587,6 +293112,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -102622,6 +293148,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -102655,6 +293182,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -102692,6 +293220,7 @@ "const int lane" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -102727,6 +293256,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -102758,6 +293288,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -102789,6 +293320,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -102816,6 +293348,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -102843,6 +293376,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -102870,6 +293404,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -102897,6 +293432,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -102924,6 +293460,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -102951,6 +293488,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -102978,6 +293516,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -103005,6 +293544,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -103032,6 +293572,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -103059,6 +293600,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -103086,6 +293628,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -103113,6 +293656,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -103140,6 +293684,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -103167,6 +293712,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -103194,6 +293740,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -103221,6 +293768,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -103248,6 +293796,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -103275,6 +293824,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -103302,6 +293852,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -103329,6 +293880,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -103356,6 +293908,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -103383,6 +293936,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -103410,6 +293964,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -103437,6 +293992,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -103464,6 +294020,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -103491,6 +294048,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -103518,6 +294076,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -103545,6 +294104,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -103572,6 +294132,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -103599,6 +294160,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -103626,6 +294188,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -103653,6 +294216,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -103680,6 +294244,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -103707,6 +294272,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -103734,6 +294300,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -103761,6 +294328,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -103788,6 +294356,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -103815,6 +294384,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -103842,6 +294412,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -103869,6 +294440,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -103896,6 +294468,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -103923,6 +294496,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -103950,6 +294524,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -103977,6 +294552,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -104007,6 +294583,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -104037,6 +294614,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -104067,6 +294645,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -104097,6 +294676,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -104127,6 +294707,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -104157,6 +294738,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -104187,6 +294769,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -104217,6 +294800,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -104247,6 +294831,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -104277,6 +294862,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -104307,6 +294893,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -104337,6 +294924,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -104367,6 +294955,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -104397,6 +294986,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -104427,6 +295017,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -104457,6 +295048,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -104487,6 +295079,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -104518,6 +295111,7 @@ "const int imm6" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -104547,6 +295141,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -104574,6 +295169,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -104601,6 +295197,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -104628,6 +295225,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -104655,6 +295253,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -104682,6 +295281,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -104709,6 +295309,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -104736,6 +295337,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -104763,6 +295365,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -104790,6 +295393,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -104817,6 +295421,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -104844,6 +295449,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -104871,6 +295477,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -104898,6 +295505,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -104925,6 +295533,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -104952,6 +295561,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -104979,6 +295589,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -105006,6 +295617,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -105033,6 +295645,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -105060,6 +295673,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -105087,6 +295701,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -105114,6 +295729,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -105141,6 +295757,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -105168,6 +295785,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -105195,6 +295813,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -105222,6 +295841,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -105249,6 +295869,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -105276,6 +295897,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -105303,6 +295925,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -105330,6 +295953,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -105357,6 +295981,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -105384,6 +296009,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -105411,6 +296037,7 @@ "float64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -105438,6 +296065,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -105465,6 +296093,7 @@ "poly64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -105492,6 +296121,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -105519,6 +296149,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -105546,6 +296177,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -105573,6 +296205,7 @@ "int64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -105600,6 +296233,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -105627,6 +296261,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -105654,6 +296289,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -105681,6 +296317,7 @@ "uint64x2_t b" ], "return_type": { + "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -105708,6 +296345,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -105735,6 +296373,7 @@ "float32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -105765,6 +296404,7 @@ "poly16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -105795,6 +296435,7 @@ "poly8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -105825,6 +296466,7 @@ "int16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -105855,6 +296497,7 @@ "int32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -105885,6 +296528,7 @@ "int8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -105915,6 +296559,7 @@ "uint16x4_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -105945,6 +296590,7 @@ "uint32x2_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -105975,6 +296621,7 @@ "uint8x8_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -106005,6 +296652,7 @@ "float32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -106035,6 +296683,7 @@ "poly16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -106065,6 +296714,7 @@ "poly8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -106095,6 +296745,7 @@ "int16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -106125,6 +296776,7 @@ "int32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -106155,6 +296807,7 @@ "int8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -106185,6 +296838,7 @@ "uint16x8_t b" ], "return_type": { + "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -106215,6 +296869,7 @@ "uint32x4_t b" ], "return_type": { + "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -106245,6 +296900,7 @@ "uint8x16_t b" ], "return_type": { + "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { diff --git a/vendor.yml b/vendor.yml index ac5b408ac4..fd2bfecba7 100644 --- a/vendor.yml +++ b/vendor.yml @@ -1,2 +1,3 @@ -- crates/stdarch-verify/arm-intrinsics.html - crates/stdarch-verify/x86-intel.xml +- crates/stdarch-verify/mips-msa.h +- intrinsics_data/arm_intrinsics.json From 4d86e66ede8cdc8edce21b08fba5109826fd37c1 Mon Sep 17 00:00:00 2001 From: Luca Vizzarro Date: Wed, 25 Oct 2023 14:04:37 +0100 Subject: [PATCH 2/8] Generator for SVE intrinsics. Co-authored-by: Jamie Cunliffe Co-authored-by: Jacob Bramley Co-authored-by: Luca Vizzarro Co-authored-by: Adam Gemmell --- Cargo.toml | 12 + crates/stdarch-gen2/Cargo.toml | 22 + crates/stdarch-gen2/src/assert_instr.rs | 372 +++++ crates/stdarch-gen2/src/context.rs | 249 +++ crates/stdarch-gen2/src/expression.rs | 546 +++++++ crates/stdarch-gen2/src/input.rs | 432 ++++++ crates/stdarch-gen2/src/intrinsic.rs | 1498 +++++++++++++++++++ crates/stdarch-gen2/src/load_store_tests.rs | 818 ++++++++++ crates/stdarch-gen2/src/main.rs | 273 ++++ crates/stdarch-gen2/src/matching.rs | 170 +++ crates/stdarch-gen2/src/predicate_forms.rs | 249 +++ crates/stdarch-gen2/src/typekinds.rs | 1024 +++++++++++++ crates/stdarch-gen2/src/wildcards.rs | 179 +++ crates/stdarch-gen2/src/wildstring.rs | 353 +++++ 14 files changed, 6197 insertions(+) create mode 100644 crates/stdarch-gen2/Cargo.toml create mode 100644 crates/stdarch-gen2/src/assert_instr.rs create mode 100644 crates/stdarch-gen2/src/context.rs create mode 100644 crates/stdarch-gen2/src/expression.rs create mode 100644 crates/stdarch-gen2/src/input.rs create mode 100644 crates/stdarch-gen2/src/intrinsic.rs create mode 100644 crates/stdarch-gen2/src/load_store_tests.rs create mode 100644 crates/stdarch-gen2/src/main.rs create mode 100644 crates/stdarch-gen2/src/matching.rs create mode 100644 crates/stdarch-gen2/src/predicate_forms.rs create mode 100644 crates/stdarch-gen2/src/typekinds.rs create mode 100644 crates/stdarch-gen2/src/wildcards.rs create mode 100644 crates/stdarch-gen2/src/wildstring.rs diff --git a/Cargo.toml b/Cargo.toml index 0122d770d9..36bd4a6a03 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -3,6 +3,18 @@ resolver = "1" members = [ "crates/*", "examples" + "crates/stdarch-verify", + "crates/core_arch", + "crates/std_detect", + "crates/stdarch-gen-arm", + "crates/stdarch-gen-loongarch", + "crates/stdarch-gen", + "crates/stdarch-gen2", + "crates/intrinsic-test", + "examples/" +] +exclude = [ + "crates/wasm-assert-instr-tests" ] [profile.release] diff --git a/crates/stdarch-gen2/Cargo.toml b/crates/stdarch-gen2/Cargo.toml new file mode 100644 index 0000000000..c9a039ea6b --- /dev/null +++ b/crates/stdarch-gen2/Cargo.toml @@ -0,0 +1,22 @@ +[package] +name = "stdarch-gen2" +version = "0.1.0" +authors = ["Luca Vizzarro ", + "Jamie Cunliffe ", + "Adam Gemmell "] +license = "MIT OR Apache-2.0" +edition = "2021" + +# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html + +[dependencies] +itertools = "0.10" +lazy_static = "1.4.0" +proc-macro2 = "1.0" +quote = "1.0" +regex = "1.5" +serde = { version = "1.0", features = ["derive"] } +serde_with = "1.14" +serde_yaml = "0.8" +walkdir = "2.3.2" diff --git a/crates/stdarch-gen2/src/assert_instr.rs b/crates/stdarch-gen2/src/assert_instr.rs new file mode 100644 index 0000000000..ce1bbe8b55 --- /dev/null +++ b/crates/stdarch-gen2/src/assert_instr.rs @@ -0,0 +1,372 @@ +use proc_macro2::TokenStream; +use quote::{format_ident, quote, ToTokens, TokenStreamExt}; +use serde::de::{self, MapAccess, Visitor}; +use serde::{ser::SerializeSeq, Deserialize, Deserializer, Serialize}; +use std::fmt; + +use crate::{ + context::{self, Context}, + typekinds::{BaseType, BaseTypeKind}, + wildstring::WildString, +}; + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged)] +pub enum InstructionAssertion { + Basic(WildString), + WithArgs(WildString, WildString), +} + +impl InstructionAssertion { + fn build(&mut self, ctx: &Context) -> context::Result { + match self { + InstructionAssertion::Basic(ws) => ws.build_acle(ctx.local), + InstructionAssertion::WithArgs(ws, args_ws) => [ws, args_ws] + .into_iter() + .try_for_each(|ws| ws.build_acle(ctx.local)), + } + } +} + +impl ToTokens for InstructionAssertion { + fn to_tokens(&self, tokens: &mut TokenStream) { + let instr = format_ident!( + "{}", + match self { + Self::Basic(instr) => instr, + Self::WithArgs(instr, _) => instr, + } + .to_string() + ); + tokens.append_all(quote! { #instr }); + + if let Self::WithArgs(_, args) = self { + let ex: TokenStream = args + .to_string() + .parse() + .expect("invalid instruction assertion arguments expression given"); + tokens.append_all(quote! {, #ex}) + } + } +} + +// Asserts that the given instruction is present for the intrinsic of the associated type bitsize. +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(remote = "Self")] +pub struct InstructionAssertionMethodForBitsize { + pub default: InstructionAssertion, + pub byte: Option, + pub halfword: Option, + pub word: Option, + pub doubleword: Option, +} + +impl InstructionAssertionMethodForBitsize { + fn build(&mut self, ctx: &Context) -> context::Result { + if let Some(ref mut byte) = self.byte { + byte.build(ctx)? + } + if let Some(ref mut halfword) = self.halfword { + halfword.build(ctx)? + } + if let Some(ref mut word) = self.word { + word.build(ctx)? + } + if let Some(ref mut doubleword) = self.doubleword { + doubleword.build(ctx)? + } + self.default.build(ctx) + } +} + +impl Serialize for InstructionAssertionMethodForBitsize { + fn serialize(&self, serializer: S) -> Result + where + S: serde::Serializer, + { + match self { + InstructionAssertionMethodForBitsize { + default: InstructionAssertion::Basic(instr), + byte: None, + halfword: None, + word: None, + doubleword: None, + } => serializer.serialize_str(&instr.to_string()), + InstructionAssertionMethodForBitsize { + default: InstructionAssertion::WithArgs(instr, args), + byte: None, + halfword: None, + word: None, + doubleword: None, + } => { + let mut seq = serializer.serialize_seq(Some(2))?; + seq.serialize_element(&instr.to_string())?; + seq.serialize_element(&args.to_string())?; + seq.end() + } + _ => InstructionAssertionMethodForBitsize::serialize(self, serializer), + } + } +} + +impl<'de> Deserialize<'de> for InstructionAssertionMethodForBitsize { + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + struct IAMVisitor; + + impl<'de> Visitor<'de> for IAMVisitor { + type Value = InstructionAssertionMethodForBitsize; + + fn expecting(&self, formatter: &mut fmt::Formatter) -> fmt::Result { + formatter.write_str("array, string or map") + } + + fn visit_str(self, value: &str) -> Result + where + E: de::Error, + { + Ok(InstructionAssertionMethodForBitsize { + default: InstructionAssertion::Basic(value.parse().map_err(E::custom)?), + byte: None, + halfword: None, + word: None, + doubleword: None, + }) + } + + fn visit_seq(self, mut seq: A) -> Result + where + A: de::SeqAccess<'de>, + { + use serde::de::Error; + let make_err = + || Error::custom("invalid number of arguments passed to assert_instruction"); + let instruction = seq.next_element()?.ok_or_else(make_err)?; + let args = seq.next_element()?.ok_or_else(make_err)?; + + if let Some(true) = seq.size_hint().map(|len| len > 0) { + Err(make_err()) + } else { + Ok(InstructionAssertionMethodForBitsize { + default: InstructionAssertion::WithArgs(instruction, args), + byte: None, + halfword: None, + word: None, + doubleword: None, + }) + } + } + + fn visit_map(self, map: M) -> Result + where + M: MapAccess<'de>, + { + InstructionAssertionMethodForBitsize::deserialize( + de::value::MapAccessDeserializer::new(map), + ) + } + } + + deserializer.deserialize_any(IAMVisitor) + } +} + +/// Asserts that the given instruction is present for the intrinsic of the associated type. +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(remote = "Self")] +pub struct InstructionAssertionMethod { + /// Instruction for integer intrinsics + pub default: InstructionAssertionMethodForBitsize, + /// Instruction for floating-point intrinsics (optional) + #[serde(default)] + pub float: Option, + /// Instruction for unsigned integer intrinsics (optional) + #[serde(default)] + pub unsigned: Option, +} + +impl InstructionAssertionMethod { + pub(crate) fn build(&mut self, ctx: &Context) -> context::Result { + if let Some(ref mut float) = self.float { + float.build(ctx)? + } + if let Some(ref mut unsigned) = self.unsigned { + unsigned.build(ctx)? + } + self.default.build(ctx) + } +} + +impl Serialize for InstructionAssertionMethod { + fn serialize(&self, serializer: S) -> Result + where + S: serde::Serializer, + { + match self { + InstructionAssertionMethod { + default: + InstructionAssertionMethodForBitsize { + default: InstructionAssertion::Basic(instr), + byte: None, + halfword: None, + word: None, + doubleword: None, + }, + float: None, + unsigned: None, + } => serializer.serialize_str(&instr.to_string()), + InstructionAssertionMethod { + default: + InstructionAssertionMethodForBitsize { + default: InstructionAssertion::WithArgs(instr, args), + byte: None, + halfword: None, + word: None, + doubleword: None, + }, + float: None, + unsigned: None, + } => { + let mut seq = serializer.serialize_seq(Some(2))?; + seq.serialize_element(&instr.to_string())?; + seq.serialize_element(&args.to_string())?; + seq.end() + } + _ => InstructionAssertionMethod::serialize(self, serializer), + } + } +} + +impl<'de> Deserialize<'de> for InstructionAssertionMethod { + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + struct IAMVisitor; + + impl<'de> Visitor<'de> for IAMVisitor { + type Value = InstructionAssertionMethod; + + fn expecting(&self, formatter: &mut fmt::Formatter) -> fmt::Result { + formatter.write_str("array, string or map") + } + + fn visit_str(self, value: &str) -> Result + where + E: de::Error, + { + Ok(InstructionAssertionMethod { + default: InstructionAssertionMethodForBitsize { + default: InstructionAssertion::Basic(value.parse().map_err(E::custom)?), + byte: None, + halfword: None, + word: None, + doubleword: None, + }, + float: None, + unsigned: None, + }) + } + + fn visit_seq(self, mut seq: A) -> Result + where + A: de::SeqAccess<'de>, + { + use serde::de::Error; + let make_err = + || Error::custom("invalid number of arguments passed to assert_instruction"); + let instruction = seq.next_element()?.ok_or_else(make_err)?; + let args = seq.next_element()?.ok_or_else(make_err)?; + + if let Some(true) = seq.size_hint().map(|len| len > 0) { + Err(make_err()) + } else { + Ok(InstructionAssertionMethod { + default: InstructionAssertionMethodForBitsize { + default: InstructionAssertion::WithArgs(instruction, args), + byte: None, + halfword: None, + word: None, + doubleword: None, + }, + float: None, + unsigned: None, + }) + } + } + + fn visit_map(self, map: M) -> Result + where + M: MapAccess<'de>, + { + InstructionAssertionMethod::deserialize(de::value::MapAccessDeserializer::new(map)) + } + } + + deserializer.deserialize_any(IAMVisitor) + } +} + +#[derive(Debug)] +pub struct InstructionAssertionsForBaseType<'a>( + pub &'a Vec, + pub &'a Option<&'a BaseType>, +); + +impl<'a> ToTokens for InstructionAssertionsForBaseType<'a> { + fn to_tokens(&self, tokens: &mut TokenStream) { + self.0.iter().for_each( + |InstructionAssertionMethod { + default, + float, + unsigned, + }| { + let kind = self.1.map(|ty| ty.kind()); + let instruction = match (kind, float, unsigned) { + (None, float, unsigned) if float.is_some() || unsigned.is_some() => { + unreachable!( + "cannot determine the base type kind for instruction assertion: {self:#?}") + } + (Some(BaseTypeKind::Float), Some(float), _) => float, + (Some(BaseTypeKind::UInt), _, Some(unsigned)) => unsigned, + _ => default, + }; + + let bitsize = self.1.and_then(|ty| ty.get_size().ok()); + let instruction = match (bitsize, instruction) { + ( + Some(8), + InstructionAssertionMethodForBitsize { + byte: Some(byte), .. + }, + ) => byte, + ( + Some(16), + InstructionAssertionMethodForBitsize { + halfword: Some(halfword), + .. + }, + ) => halfword, + ( + Some(32), + InstructionAssertionMethodForBitsize { + word: Some(word), .. + }, + ) => word, + ( + Some(64), + InstructionAssertionMethodForBitsize { + doubleword: Some(doubleword), + .. + }, + ) => doubleword, + (_, InstructionAssertionMethodForBitsize { default, .. }) => default, + }; + + tokens.append_all(quote! { #[cfg_attr(test, assert_instr(#instruction))]}) + }, + ); + } +} diff --git a/crates/stdarch-gen2/src/context.rs b/crates/stdarch-gen2/src/context.rs new file mode 100644 index 0000000000..108f7ab706 --- /dev/null +++ b/crates/stdarch-gen2/src/context.rs @@ -0,0 +1,249 @@ +use itertools::Itertools; +use serde::{Deserialize, Serialize}; +use std::collections::HashMap; + +use crate::{ + expression::Expression, + input::{InputSet, InputType}, + intrinsic::{Constraint, Intrinsic, Signature}, + matching::SizeMatchable, + predicate_forms::PredicateForm, + typekinds::{ToRepr, TypeKind}, + wildcards::Wildcard, + wildstring::WildString, +}; + +/// Maximum SVE vector size +const SVE_VECTOR_MAX_SIZE: u32 = 2048; +/// Vector register size +const VECTOR_REG_SIZE: u32 = 128; + +/// Generator result +pub type Result = std::result::Result; + +#[derive(Debug, Clone, Serialize, Deserialize)] +pub struct ArchitectureSettings { + #[serde(alias = "arch")] + pub arch_name: String, + pub target_feature: Vec, + #[serde(alias = "llvm_prefix")] + pub llvm_link_prefix: String, +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +pub struct GlobalContext { + pub arch_cfgs: Vec, + #[serde(default)] + pub uses_neon_types: bool, +} + +/// Context of an intrinsic group +#[derive(Debug, Clone, Default)] +pub struct GroupContext { + /// LLVM links to target input sets + pub links: HashMap, +} + +#[derive(Debug, Clone, Copy)] +pub enum VariableType { + Argument, + Internal, +} + +#[derive(Debug, Clone)] +pub struct LocalContext { + pub signature: Signature, + + pub input: InputSet, + + pub substitutions: HashMap, + pub variables: HashMap, +} + +impl LocalContext { + pub fn new(input: InputSet, original: &Intrinsic) -> LocalContext { + LocalContext { + signature: original.signature.clone(), + input, + substitutions: HashMap::new(), + variables: HashMap::new(), + } + } + + pub fn provide_type_wildcard(&self, wildcard: &Wildcard) -> Result { + let err = || format!("wildcard {{{wildcard}}} not found"); + + let make_neon = |tuple_size| move |ty| TypeKind::make_vector(ty, false, tuple_size); + let make_sve = |tuple_size| move |ty| TypeKind::make_vector(ty, true, tuple_size); + + match wildcard { + Wildcard::Type(idx) => self.input.typekind(*idx).ok_or_else(err), + Wildcard::NEONType(idx, tuple_size) => self + .input + .typekind(*idx) + .ok_or_else(err) + .and_then(make_neon(*tuple_size)), + Wildcard::SVEType(idx, tuple_size) => self + .input + .typekind(*idx) + .ok_or_else(err) + .and_then(make_sve(*tuple_size)), + Wildcard::Predicate(idx) => self.input.typekind(*idx).map_or_else( + || { + if idx.is_none() && self.input.types_len() == 1 { + Err(err()) + } else { + Err(format!( + "there is no type at index {} to infer the predicate from", + idx.unwrap_or(0) + )) + } + }, + |ref ty| TypeKind::make_predicate_from(ty), + ), + Wildcard::MaxPredicate => self + .input + .iter() + .filter_map(|arg| arg.typekind()) + .max_by(|x, y| { + x.base_type() + .and_then(|bt| bt.get_size().ok()) + .unwrap_or(0) + .cmp(&y.base_type().and_then(|bt| bt.get_size().ok()).unwrap_or(0)) + }) + .map_or_else( + || Err("there are no types available to infer the predicate from".to_string()), + TypeKind::make_predicate_from, + ), + Wildcard::Scale(w, as_ty) => { + let mut ty = self.provide_type_wildcard(w)?; + if let Some(vty) = ty.vector_mut() { + let base_ty = if let Some(w) = as_ty.wildcard() { + *self.provide_type_wildcard(w)?.base_type().unwrap() + } else { + *as_ty.base_type().unwrap() + }; + vty.cast_base_type_as(base_ty) + } + Ok(ty) + } + _ => Err(err()), + } + } + + pub fn provide_substitution_wildcard(&self, wildcard: &Wildcard) -> Result { + let err = || Err(format!("wildcard {{{wildcard}}} not found")); + + match wildcard { + Wildcard::SizeLiteral(idx) => self.input.typekind(*idx) + .map_or_else(err, |ty| Ok(ty.size_literal())), + Wildcard::Size(idx) => self.input.typekind(*idx) + .map_or_else(err, |ty| Ok(ty.size())), + Wildcard::SizeMinusOne(idx) => self.input.typekind(*idx) + .map_or_else(err, |ty| Ok((ty.size().parse::().unwrap()-1).to_string())), + Wildcard::SizeInBytesLog2(idx) => self.input.typekind(*idx) + .map_or_else(err, |ty| Ok(ty.size_in_bytes_log2())), + Wildcard::NVariant if self.substitutions.get(wildcard).is_none() => Ok(String::new()), + Wildcard::TypeKind(idx, opts) => { + self.input.typekind(*idx) + .map_or_else(err, |ty| { + let literal = if let Some(opts) = opts { + opts.contains(ty.base_type().map(|bt| *bt.kind()).ok_or_else(|| { + format!("cannot retrieve a type literal out of {ty}") + })?) + .then(|| ty.type_kind()) + .unwrap_or_default() + } else { + ty.type_kind() + }; + Ok(literal) + }) + } + Wildcard::PredicateForms(_) => self + .input + .iter() + .find_map(|arg| { + if let InputType::PredicateForm(pf) = arg { + Some(pf.get_suffix().to_string()) + } else { + None + } + }) + .ok_or_else(|| unreachable!("attempting to render a predicate form wildcard, but no predicate form was compiled for it")), + _ => self + .substitutions + .get(wildcard) + .map_or_else(err, |s| Ok(s.clone())), + } + } + + pub fn make_assertion_from_constraint(&self, constraint: &Constraint) -> Result { + match constraint { + Constraint::AnyI32 { + variable, + any_values, + } => { + let where_ex = any_values + .iter() + .map(|value| format!("{variable} == {value}")) + .join(" || "); + Ok(Expression::MacroCall("static_assert".to_string(), where_ex)) + } + Constraint::RangeI32 { + variable, + range: SizeMatchable::Matched(range), + } => Ok(Expression::MacroCall( + "static_assert_range".to_string(), + format!( + "{variable}, {min}, {max}", + min = range.start(), + max = range.end() + ), + )), + Constraint::SVEMaxElems { + variable, + sve_max_elems_type: ty, + } + | Constraint::VecMaxElems { + variable, + vec_max_elems_type: ty, + } => { + if !self.input.is_empty() { + let higher_limit = match constraint { + Constraint::SVEMaxElems { .. } => SVE_VECTOR_MAX_SIZE, + Constraint::VecMaxElems { .. } => VECTOR_REG_SIZE, + _ => unreachable!(), + }; + + let max = ty.base_type() + .map(|ty| ty.get_size()) + .transpose()? + .map_or_else( + || Err(format!("can't make an assertion out of constraint {self:?}: no valid type is present")), + |bitsize| Ok(higher_limit / bitsize - 1))?; + Ok(Expression::MacroCall( + "static_assert_range".to_string(), + format!("{variable}, 0, {max}"), + )) + } else { + Err(format!("can't make an assertion out of constraint {self:?}: no types are being used")) + } + } + _ => unreachable!("constraints were not built successfully!"), + } + } + + pub fn predicate_form(&self) -> Option<&PredicateForm> { + self.input.iter().find_map(|arg| arg.predicate_form()) + } + + pub fn n_variant_op(&self) -> Option<&WildString> { + self.input.iter().find_map(|arg| arg.n_variant_op()) + } +} + +pub struct Context<'ctx> { + pub local: &'ctx mut LocalContext, + pub group: &'ctx mut GroupContext, + pub global: &'ctx GlobalContext, +} diff --git a/crates/stdarch-gen2/src/expression.rs b/crates/stdarch-gen2/src/expression.rs new file mode 100644 index 0000000000..4434ae276e --- /dev/null +++ b/crates/stdarch-gen2/src/expression.rs @@ -0,0 +1,546 @@ +use itertools::Itertools; +use lazy_static::lazy_static; +use proc_macro2::{Literal, TokenStream}; +use quote::{format_ident, quote, ToTokens, TokenStreamExt}; +use regex::Regex; +use serde::de::{self, MapAccess, Visitor}; +use serde::{Deserialize, Deserializer, Serialize}; +use std::fmt; +use std::str::FromStr; + +use crate::intrinsic::Intrinsic; +use crate::{ + context::{self, Context, VariableType}, + intrinsic::{Argument, LLVMLink, StaticDefinition}, + matching::{MatchKindValues, MatchSizeValues}, + typekinds::{BaseType, BaseTypeKind, TypeKind}, + wildcards::Wildcard, + wildstring::WildString, +}; + +#[derive(Debug, Clone, Copy, Serialize, Deserialize)] +pub enum IdentifierType { + Variable, + Symbol, +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged)] +pub enum LetVariant { + Basic(WildString, Box), + WithType(WildString, TypeKind, Box), +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +pub struct FnCall( + /// Function pointer + pub Box, + /// Function arguments + pub Vec, + /// Function turbofish arguments + #[serde(default)] + pub Vec, +); + +impl FnCall { + pub fn new_expression(fn_ptr: Expression, arguments: Vec) -> Expression { + FnCall(Box::new(fn_ptr), arguments, Vec::new()).into() + } + + pub fn is_llvm_link_call(&self, llvm_link_name: &String) -> bool { + if let Expression::Identifier(fn_name, IdentifierType::Symbol) = self.0.as_ref() { + &fn_name.to_string() == llvm_link_name + } else { + false + } + } + + pub fn pre_build(&mut self, ctx: &mut Context) -> context::Result { + self.0.pre_build(ctx)?; + self.1 + .iter_mut() + .chain(self.2.iter_mut()) + .try_for_each(|ex| ex.pre_build(ctx)) + } + + pub fn build(&mut self, intrinsic: &Intrinsic, ctx: &mut Context) -> context::Result { + self.0.build(intrinsic, ctx)?; + self.1 + .iter_mut() + .chain(self.2.iter_mut()) + .try_for_each(|ex| ex.build(intrinsic, ctx)) + } +} + +impl ToTokens for FnCall { + fn to_tokens(&self, tokens: &mut TokenStream) { + let FnCall(fn_ptr, arguments, turbofish) = self; + + fn_ptr.to_tokens(tokens); + + if !turbofish.is_empty() { + tokens.append_all(quote! {::<#(#turbofish),*>}); + } + + tokens.append_all(quote! { (#(#arguments),*) }) + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(remote = "Self", deny_unknown_fields)] +pub enum Expression { + /// (Re)Defines a variable + Let(LetVariant), + /// Performs a variable assignment operation + Assign(String, Box), + /// Performs a macro call + MacroCall(String, String), + /// Performs a function call + FnCall(FnCall), + /// Performs a method call. The following: + /// `MethodCall: ["$object", "to_string", []]` + /// is tokenized as: + /// `object.to_string()`. + MethodCall(Box, String, Vec), + /// Symbol identifier name, prepend with a `$` to treat it as a scope variable + /// which engages variable tracking and enables inference. + /// E.g. `my_function_name` for a generic symbol or `$my_variable` for + /// a variable. + Identifier(WildString, IdentifierType), + /// Constant signed integer number expression + IntConstant(i32), + /// Constant floating point number expression + FloatConstant(f32), + /// Constant boolean expression, either `true` or `false` + BoolConstant(bool), + /// Array expression + Array(Vec), + + // complex expressions + /// Makes an LLVM link. + /// + /// It stores the link's function name in the wildcard `{llvm_link}`, for use in + /// subsequent expressions. + LLVMLink(LLVMLink), + /// Casts the given expression to the specified (unchecked) type + CastAs(Box, String), + /// Returns the LLVM `undef` symbol + SvUndef, + /// Multiplication + Multiply(Box, Box), + /// Converts the specified constant to the specified type's kind + ConvertConst(TypeKind, i32), + /// Yields the given type in the Rust representation + Type(TypeKind), + + MatchSize(TypeKind, MatchSizeValues>), + MatchKind(TypeKind, MatchKindValues>), +} + +impl Expression { + pub fn pre_build(&mut self, ctx: &mut Context) -> context::Result { + match self { + Self::FnCall(fn_call) => fn_call.pre_build(ctx), + Self::MethodCall(cl_ptr_ex, _, arg_exs) => { + cl_ptr_ex.pre_build(ctx)?; + arg_exs.iter_mut().try_for_each(|ex| ex.pre_build(ctx)) + } + Self::Let(LetVariant::Basic(_, ex) | LetVariant::WithType(_, _, ex)) => { + ex.pre_build(ctx) + } + Self::CastAs(ex, _) => ex.pre_build(ctx), + Self::Multiply(lhs, rhs) => { + lhs.pre_build(ctx)?; + rhs.pre_build(ctx) + } + Self::MatchSize(match_ty, values) => { + *self = *values.get(match_ty, ctx.local)?.to_owned(); + self.pre_build(ctx) + } + Self::MatchKind(match_ty, values) => { + *self = *values.get(match_ty, ctx.local)?.to_owned(); + self.pre_build(ctx) + } + _ => Ok(()), + } + } + + pub fn build(&mut self, intrinsic: &Intrinsic, ctx: &mut Context) -> context::Result { + match self { + Self::LLVMLink(link) => link.build_and_save(ctx), + Self::Identifier(identifier, id_type) => { + identifier.build_acle(ctx.local)?; + + if let IdentifierType::Variable = id_type { + ctx.local + .variables + .get(&identifier.to_string()) + .map(|_| ()) + .ok_or_else(|| format!("invalid variable {identifier} being referenced")) + } else { + Ok(()) + } + } + Self::FnCall(fn_call) => { + fn_call.build(intrinsic, ctx)?; + + if let Some(llvm_link_name) = ctx.local.substitutions.get(&Wildcard::LLVMLink) { + if fn_call.is_llvm_link_call(llvm_link_name) { + *self = intrinsic + .llvm_link() + .expect("got LLVMLink wildcard without a LLVM link in `compose`") + .apply_conversions_to_call(fn_call.clone(), ctx.local)? + } + } + + Ok(()) + } + Self::MethodCall(cl_ptr_ex, _, arg_exs) => { + cl_ptr_ex.build(intrinsic, ctx)?; + arg_exs + .iter_mut() + .try_for_each(|ex| ex.build(intrinsic, ctx)) + } + Self::Let(variant) => { + let (var_name, ex, ty) = match variant { + LetVariant::Basic(var_name, ex) => (var_name, ex, None), + LetVariant::WithType(var_name, ty, ex) => { + if let Some(w) = ty.wildcard() { + ty.populate_wildcard(ctx.local.provide_type_wildcard(w)?)?; + } + (var_name, ex, Some(ty.to_owned())) + } + }; + + var_name.build_acle(ctx.local)?; + ctx.local.variables.insert( + var_name.to_string(), + ( + ty.unwrap_or_else(|| TypeKind::Custom("unknown".to_string())), + VariableType::Internal, + ), + ); + ex.build(intrinsic, ctx) + } + Self::CastAs(ex, _) => ex.build(intrinsic, ctx), + Self::Multiply(lhs, rhs) => { + lhs.build(intrinsic, ctx)?; + rhs.build(intrinsic, ctx) + } + Self::ConvertConst(ty, num) => { + if let Some(w) = ty.wildcard() { + *ty = ctx.local.provide_type_wildcard(w)? + } + + if let Some(BaseType::Sized(BaseTypeKind::Float, _)) = ty.base() { + *self = Expression::FloatConstant(*num as f32) + } else { + *self = Expression::IntConstant(*num) + } + Ok(()) + } + Self::Type(ty) => { + if let Some(w) = ty.wildcard() { + *ty = ctx.local.provide_type_wildcard(w)? + } + + Ok(()) + } + _ => Ok(()), + } + } + + /// True if the expression requires an `unsafe` context in a safe function. + /// + /// The classification is somewhat fuzzy, based on actual usage (e.g. empirical function names) + /// rather than a full parse. This is a reasonable approach because mistakes here will usually + /// be caught at build time: + /// + /// - Missing an `unsafe` is a build error. + /// - An unnecessary `unsafe` is a warning, made into an error by the CI's `-D warnings`. + /// + /// This **panics** if it encounters an expression that shouldn't appear in a safe function at + /// all (such as `SvUndef`). + pub fn requires_unsafe_wrapper(&self, ctx_fn: &str) -> bool { + match self { + // The call will need to be unsafe, but the declaration does not. + Self::LLVMLink(..) => false, + // Identifiers, literals and type names are never unsafe. + Self::Identifier(..) => false, + Self::IntConstant(..) => false, + Self::FloatConstant(..) => false, + Self::BoolConstant(..) => false, + Self::Type(..) => false, + Self::ConvertConst(..) => false, + // Nested structures that aren't inherently unsafe, but could contain other expressions + // that might be. + Self::Assign(_var, exp) => exp.requires_unsafe_wrapper(ctx_fn), + Self::Let(LetVariant::Basic(_, exp) | LetVariant::WithType(_, _, exp)) => { + exp.requires_unsafe_wrapper(ctx_fn) + } + Self::Array(exps) => exps.iter().any(|exp| exp.requires_unsafe_wrapper(ctx_fn)), + Self::Multiply(lhs, rhs) => { + lhs.requires_unsafe_wrapper(ctx_fn) || rhs.requires_unsafe_wrapper(ctx_fn) + } + Self::CastAs(exp, _ty) => exp.requires_unsafe_wrapper(ctx_fn), + // Functions and macros can be unsafe, but can also contain other expressions. + Self::FnCall(FnCall(fn_exp, args, turbo_args)) => { + let fn_name = fn_exp.to_string(); + fn_exp.requires_unsafe_wrapper(ctx_fn) + || fn_name.starts_with("_sv") + || fn_name.starts_with("simd_") + || fn_name.ends_with("transmute") + || args.iter().any(|exp| exp.requires_unsafe_wrapper(ctx_fn)) + || turbo_args + .iter() + .any(|exp| exp.requires_unsafe_wrapper(ctx_fn)) + } + Self::MethodCall(exp, fn_name, args) => match fn_name.as_str() { + // `as_signed` and `as_unsigned` are unsafe because they're trait methods with + // target features to allow use on feature-dependent types (such as SVE vectors). + // We can safely wrap them here. + "as_signed" => true, + "as_unsigned" => true, + _ => { + exp.requires_unsafe_wrapper(ctx_fn) + || args.iter().any(|exp| exp.requires_unsafe_wrapper(ctx_fn)) + } + }, + // We only use macros to check const generics (using static assertions). + Self::MacroCall(_name, _args) => false, + // Materialising uninitialised values is always unsafe, and we avoid it in safe + // functions. + Self::SvUndef => panic!("Refusing to wrap unsafe SvUndef in safe function '{ctx_fn}'."), + // Variants that aren't tokenised. We shouldn't encounter these here. + Self::MatchKind(..) => { + unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.") + } + Self::MatchSize(..) => { + unimplemented!("The unsafety of {self:?} cannot be determined in '{ctx_fn}'.") + } + } + } +} + +impl FromStr for Expression { + type Err = String; + + fn from_str(s: &str) -> Result { + lazy_static! { + static ref MACRO_RE: Regex = + Regex::new(r"^(?P[\w\d_]+)!\((?P.*?)\);?$").unwrap(); + } + + if s == "SvUndef" { + Ok(Expression::SvUndef) + } else if MACRO_RE.is_match(s) { + let c = MACRO_RE.captures(s).unwrap(); + let ex = c["ex"].to_string(); + let _: TokenStream = ex + .parse() + .map_err(|e| format!("could not parse macro call expression: {e:#?}"))?; + Ok(Expression::MacroCall(c["name"].to_string(), ex)) + } else { + let (s, id_type) = if let Some(varname) = s.strip_prefix('$') { + (varname, IdentifierType::Variable) + } else { + (s, IdentifierType::Symbol) + }; + let identifier = s.trim().parse()?; + Ok(Expression::Identifier(identifier, id_type)) + } + } +} + +impl From for Expression { + fn from(fn_call: FnCall) -> Self { + Expression::FnCall(fn_call) + } +} + +impl From for Expression { + fn from(ws: WildString) -> Self { + Expression::Identifier(ws, IdentifierType::Symbol) + } +} + +impl From<&Argument> for Expression { + fn from(a: &Argument) -> Self { + Expression::Identifier(a.name.to_owned(), IdentifierType::Variable) + } +} + +impl TryFrom<&StaticDefinition> for Expression { + type Error = String; + + fn try_from(sd: &StaticDefinition) -> Result { + match sd { + StaticDefinition::Constant(imm) => Ok(imm.into()), + StaticDefinition::Generic(t) => t.parse(), + } + } +} + +impl fmt::Display for Expression { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Identifier(identifier, kind) => { + write!( + f, + "{}{identifier}", + matches!(kind, IdentifierType::Variable) + .then_some("$") + .unwrap_or_default() + ) + } + Self::MacroCall(name, expression) => { + write!(f, "{name}!({expression})") + } + _ => Err(fmt::Error), + } + } +} + +impl ToTokens for Expression { + fn to_tokens(&self, tokens: &mut TokenStream) { + match self { + Self::Let(LetVariant::Basic(var_name, exp)) => { + let var_ident = format_ident!("{}", var_name.to_string()); + tokens.append_all(quote! { let #var_ident = #exp }) + } + Self::Let(LetVariant::WithType(var_name, ty, exp)) => { + let var_ident = format_ident!("{}", var_name.to_string()); + tokens.append_all(quote! { let #var_ident: #ty = #exp }) + } + Self::Assign(var_name, exp) => { + let var_ident = format_ident!("{}", var_name); + tokens.append_all(quote! { #var_ident = #exp }) + } + Self::MacroCall(name, ex) => { + let name = format_ident!("{name}"); + let ex: TokenStream = ex.parse().unwrap(); + tokens.append_all(quote! { #name!(#ex) }) + } + Self::FnCall(fn_call) => fn_call.to_tokens(tokens), + Self::MethodCall(exp, fn_name, args) => { + let fn_ident = format_ident!("{}", fn_name); + tokens.append_all(quote! { #exp.#fn_ident(#(#args),*) }) + } + Self::Identifier(identifier, _) => { + assert!( + !identifier.has_wildcards(), + "expression {self:#?} was not built before calling to_tokens" + ); + identifier + .to_string() + .parse::() + .expect("invalid syntax") + .to_tokens(tokens); + } + Self::IntConstant(n) => tokens.append(Literal::i32_unsuffixed(*n)), + Self::FloatConstant(n) => tokens.append(Literal::f32_unsuffixed(*n)), + Self::BoolConstant(true) => tokens.append(format_ident!("true")), + Self::BoolConstant(false) => tokens.append(format_ident!("false")), + Self::Array(vec) => tokens.append_all(quote! { [ #(#vec),* ] }), + Self::LLVMLink(link) => link.to_tokens(tokens), + Self::CastAs(ex, ty) => { + let ty: TokenStream = ty.parse().expect("invalid syntax"); + tokens.append_all(quote! { #ex as #ty }) + } + Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }), + Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }), + Self::Type(ty) => ty.to_tokens(tokens), + _ => unreachable!("{self:?} cannot be converted to tokens."), + } + } +} + +impl Serialize for Expression { + fn serialize(&self, serializer: S) -> Result + where + S: serde::Serializer, + { + match self { + Self::IntConstant(v) => serializer.serialize_i32(*v), + Self::FloatConstant(v) => serializer.serialize_f32(*v), + Self::BoolConstant(v) => serializer.serialize_bool(*v), + Self::Identifier(..) => serializer.serialize_str(&self.to_string()), + Self::MacroCall(..) => serializer.serialize_str(&self.to_string()), + _ => Expression::serialize(self, serializer), + } + } +} + +impl<'de> Deserialize<'de> for Expression { + fn deserialize(deserializer: D) -> Result + where + D: Deserializer<'de>, + { + struct CustomExpressionVisitor; + + impl<'de> Visitor<'de> for CustomExpressionVisitor { + type Value = Expression; + + fn expecting(&self, formatter: &mut fmt::Formatter) -> fmt::Result { + formatter.write_str("integer, float, boolean, string or map") + } + + fn visit_bool(self, v: bool) -> Result + where + E: de::Error, + { + Ok(Expression::BoolConstant(v)) + } + + fn visit_i64(self, v: i64) -> Result + where + E: de::Error, + { + Ok(Expression::IntConstant(v as i32)) + } + + fn visit_u64(self, v: u64) -> Result + where + E: de::Error, + { + Ok(Expression::IntConstant(v as i32)) + } + + fn visit_f64(self, v: f64) -> Result + where + E: de::Error, + { + Ok(Expression::FloatConstant(v as f32)) + } + + fn visit_str(self, value: &str) -> Result + where + E: de::Error, + { + FromStr::from_str(value).map_err(de::Error::custom) + } + + fn visit_seq(self, mut seq: A) -> Result + where + A: de::SeqAccess<'de>, + { + let arr = std::iter::from_fn(|| seq.next_element::().transpose()) + .try_collect()?; + Ok(Expression::Array(arr)) + } + + fn visit_map(self, map: M) -> Result + where + M: MapAccess<'de>, + { + // `MapAccessDeserializer` is a wrapper that turns a `MapAccess` + // into a `Deserializer`, allowing it to be used as the input to T's + // `Deserialize` implementation. T then deserializes itself using + // the entries from the map visitor. + Expression::deserialize(de::value::MapAccessDeserializer::new(map)) + } + } + + deserializer.deserialize_any(CustomExpressionVisitor) + } +} diff --git a/crates/stdarch-gen2/src/input.rs b/crates/stdarch-gen2/src/input.rs new file mode 100644 index 0000000000..bb2414adec --- /dev/null +++ b/crates/stdarch-gen2/src/input.rs @@ -0,0 +1,432 @@ +use itertools::Itertools; +use serde::{de, Deserialize, Deserializer, Serialize}; + +use crate::{ + context::{self, GlobalContext}, + intrinsic::Intrinsic, + predicate_forms::{PredicateForm, PredicationMask, PredicationMethods}, + typekinds::TypeKind, + wildstring::WildString, +}; + +#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)] +#[serde(untagged)] +pub enum InputType { + /// PredicateForm variant argument + #[serde(skip)] // Predicate forms have their own dedicated deserialization field. Skip. + PredicateForm(PredicateForm), + /// Operand from which to generate an N variant + #[serde(skip)] + NVariantOp(Option), + /// TypeKind variant argument + Type(TypeKind), +} + +impl InputType { + /// Optionally unwraps as a PredicateForm. + pub fn predicate_form(&self) -> Option<&PredicateForm> { + match self { + InputType::PredicateForm(pf) => Some(pf), + _ => None, + } + } + + /// Optionally unwraps as a mutable PredicateForm + pub fn predicate_form_mut(&mut self) -> Option<&mut PredicateForm> { + match self { + InputType::PredicateForm(pf) => Some(pf), + _ => None, + } + } + + /// Optionally unwraps as a TypeKind. + pub fn typekind(&self) -> Option<&TypeKind> { + match self { + InputType::Type(ty) => Some(ty), + _ => None, + } + } + + /// Optionally unwraps as a NVariantOp + pub fn n_variant_op(&self) -> Option<&WildString> { + match self { + InputType::NVariantOp(Some(op)) => Some(op), + _ => None, + } + } +} + +impl PartialOrd for InputType { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for InputType { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + use std::cmp::Ordering::*; + + match (self, other) { + (InputType::PredicateForm(pf1), InputType::PredicateForm(pf2)) => pf1.cmp(pf2), + (InputType::Type(ty1), InputType::Type(ty2)) => ty1.cmp(ty2), + + (InputType::NVariantOp(None), InputType::NVariantOp(Some(..))) => Less, + (InputType::NVariantOp(Some(..)), InputType::NVariantOp(None)) => Greater, + (InputType::NVariantOp(_), InputType::NVariantOp(_)) => Equal, + + (InputType::Type(..), InputType::PredicateForm(..)) => Less, + (InputType::PredicateForm(..), InputType::Type(..)) => Greater, + + (InputType::Type(..), InputType::NVariantOp(..)) => Less, + (InputType::NVariantOp(..), InputType::Type(..)) => Greater, + + (InputType::PredicateForm(..), InputType::NVariantOp(..)) => Less, + (InputType::NVariantOp(..), InputType::PredicateForm(..)) => Greater, + } + } +} + +mod many_or_one { + use serde::{de::Deserializer, ser::Serializer, Deserialize, Serialize}; + + pub fn serialize(vec: &Vec, serializer: S) -> Result + where + T: Serialize, + S: Serializer, + { + if vec.len() == 1 { + vec.first().unwrap().serialize(serializer) + } else { + vec.serialize(serializer) + } + } + + pub fn deserialize<'de, T, D>(deserializer: D) -> Result, D::Error> + where + T: Deserialize<'de>, + D: Deserializer<'de>, + { + #[derive(Debug, Clone, Serialize, Deserialize)] + #[serde(untagged)] + enum ManyOrOne { + Many(Vec), + One(T), + } + + match ManyOrOne::deserialize(deserializer)? { + ManyOrOne::Many(vec) => Ok(vec), + ManyOrOne::One(val) => Ok(vec![val]), + } + } +} + +#[derive(Debug, Clone, Default, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] +pub struct InputSet(#[serde(with = "many_or_one")] Vec); + +impl InputSet { + pub fn get(&self, idx: usize) -> Option<&InputType> { + self.0.get(idx) + } + + pub fn is_empty(&self) -> bool { + self.0.is_empty() + } + + pub fn iter(&self) -> impl Iterator + '_ { + self.0.iter() + } + + pub fn iter_mut(&mut self) -> impl Iterator + '_ { + self.0.iter_mut() + } + + pub fn into_iter(self) -> impl Iterator + Clone { + self.0.into_iter() + } + + pub fn types_len(&self) -> usize { + self.iter().filter_map(|arg| arg.typekind()).count() + } + + pub fn typekind(&self, idx: Option) -> Option { + let types_len = self.types_len(); + self.get(idx.unwrap_or(0)).and_then(move |arg: &InputType| { + if (idx.is_none() && types_len != 1) || (idx.is_some() && types_len == 1) { + None + } else { + arg.typekind().cloned() + } + }) + } +} + +#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)] +pub struct InputSetEntry(#[serde(with = "many_or_one")] Vec); + +impl InputSetEntry { + pub fn new(input: Vec) -> Self { + Self(input) + } + + pub fn get(&self, idx: usize) -> Option<&InputSet> { + self.0.get(idx) + } +} + +fn validate_types<'de, D>(deserializer: D) -> Result, D::Error> +where + D: Deserializer<'de>, +{ + let v: Vec = Vec::deserialize(deserializer)?; + + let mut it = v.iter(); + if let Some(first) = it.next() { + it.try_fold(first, |last, cur| { + if last.0.len() == cur.0.len() { + Ok(cur) + } else { + Err("the length of the InputSets and the product lists must match".to_string()) + } + }) + .map_err(de::Error::custom)?; + } + + Ok(v) +} + +#[derive(Debug, Clone, Default, Serialize, Deserialize)] +pub struct IntrinsicInput { + #[serde(default)] + #[serde(deserialize_with = "validate_types")] + pub types: Vec, + + #[serde(flatten)] + pub predication_methods: PredicationMethods, + + /// Generates a _n variant where the specified operand is a primitive type + /// that requires conversion to an SVE one. The `{_n}` wildcard is required + /// in the intrinsic's name, otherwise an error will be thrown. + #[serde(default)] + pub n_variant_op: WildString, +} + +impl IntrinsicInput { + /// Extracts all the possible variants as an iterator. + pub fn variants( + &self, + intrinsic: &Intrinsic, + ) -> context::Result + '_> { + let mut top_product = vec![]; + + if !self.types.is_empty() { + top_product.push( + self.types + .iter() + .flat_map(|ty_in| { + ty_in + .0 + .iter() + .map(|v| v.clone().into_iter()) + .multi_cartesian_product() + }) + .collect_vec(), + ) + } + + if let Ok(mask) = PredicationMask::try_from(&intrinsic.signature.name) { + top_product.push( + PredicateForm::compile_list(&mask, &self.predication_methods)? + .into_iter() + .map(|pf| vec![InputType::PredicateForm(pf)]) + .collect_vec(), + ) + } + + if !self.n_variant_op.is_empty() { + top_product.push(vec![ + vec![InputType::NVariantOp(None)], + vec![InputType::NVariantOp(Some(self.n_variant_op.to_owned()))], + ]) + } + + let it = top_product + .into_iter() + .map(|v| v.into_iter()) + .multi_cartesian_product() + .map(|set| InputSet(set.into_iter().flatten().collect_vec())); + Ok(it) + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +pub struct GeneratorInput { + #[serde(flatten)] + pub ctx: GlobalContext, + pub intrinsics: Vec, +} + +#[cfg(test)] +mod tests { + use crate::{ + input::*, + predicate_forms::{DontCareMethod, ZeroingMethod}, + }; + + #[test] + fn test_empty() { + let str = r#"types: []"#; + let input: IntrinsicInput = serde_yaml::from_str(str).expect("failed to parse"); + let mut variants = input.variants(&Intrinsic::default()).unwrap().into_iter(); + assert_eq!(variants.next(), None); + } + + #[test] + fn test_product() { + let str = r#"types: +- [f64, f32] +- [i64, [f64, f32]] +"#; + let input: IntrinsicInput = serde_yaml::from_str(str).expect("failed to parse"); + let mut intrinsic = Intrinsic::default(); + intrinsic.signature.name = "test_intrinsic{_mx}".parse().unwrap(); + let mut variants = input.variants(&intrinsic).unwrap().into_iter(); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("f64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::PredicateForm(PredicateForm::Merging), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("f64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::PredicateForm(PredicateForm::DontCare(DontCareMethod::AsMerging)), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::Type("f64".parse().unwrap()), + InputType::PredicateForm(PredicateForm::Merging), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::Type("f64".parse().unwrap()), + InputType::PredicateForm(PredicateForm::DontCare(DontCareMethod::AsMerging)), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::PredicateForm(PredicateForm::Merging), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::PredicateForm(PredicateForm::DontCare(DontCareMethod::AsMerging)), + ])), + ); + assert_eq!(variants.next(), None); + } + + #[test] + fn test_n_variant() { + let str = r#"types: +- [f64, f32] +n_variant_op: op2 +"#; + let input: IntrinsicInput = serde_yaml::from_str(str).expect("failed to parse"); + let mut variants = input.variants(&Intrinsic::default()).unwrap().into_iter(); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("f64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::NVariantOp(None), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("f64".parse().unwrap()), + InputType::Type("f32".parse().unwrap()), + InputType::NVariantOp(Some("op2".parse().unwrap())), + ])) + ); + assert_eq!(variants.next(), None) + } + + #[test] + fn test_invalid_length() { + let str = r#"types: [i32, [[u64], [u32]]]"#; + serde_yaml::from_str::(str).expect_err("failure expected"); + } + + #[test] + fn test_invalid_predication() { + let str = "types: []"; + let input: IntrinsicInput = serde_yaml::from_str(str).expect("failed to parse"); + let mut intrinsic = Intrinsic::default(); + intrinsic.signature.name = "test_intrinsic{_mxz}".parse().unwrap(); + input + .variants(&intrinsic) + .map(|v| v.collect_vec()) + .expect_err("failure expected"); + } + + #[test] + fn test_invalid_predication_mask() { + "test_intrinsic{_mxy}" + .parse::() + .expect_err("failure expected"); + "test_intrinsic{_}" + .parse::() + .expect_err("failure expected"); + } + + #[test] + fn test_zeroing_predication() { + let str = r#"types: [i64] +zeroing_method: { drop: inactive }"#; + let input: IntrinsicInput = serde_yaml::from_str(str).expect("failed to parse"); + let mut intrinsic = Intrinsic::default(); + intrinsic.signature.name = "test_intrinsic{_mxz}".parse().unwrap(); + let mut variants = input.variants(&intrinsic).unwrap(); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::PredicateForm(PredicateForm::Merging), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::PredicateForm(PredicateForm::DontCare(DontCareMethod::AsZeroing)), + ])) + ); + assert_eq!( + variants.next(), + Some(InputSet(vec![ + InputType::Type("i64".parse().unwrap()), + InputType::PredicateForm(PredicateForm::Zeroing(ZeroingMethod::Drop { + drop: "inactive".parse().unwrap() + })), + ])) + ); + assert_eq!(variants.next(), None) + } +} diff --git a/crates/stdarch-gen2/src/intrinsic.rs b/crates/stdarch-gen2/src/intrinsic.rs new file mode 100644 index 0000000000..d05b71e44d --- /dev/null +++ b/crates/stdarch-gen2/src/intrinsic.rs @@ -0,0 +1,1498 @@ +use itertools::Itertools; +use proc_macro2::{Punct, Spacing, TokenStream}; +use quote::{format_ident, quote, ToTokens, TokenStreamExt}; +use serde::{Deserialize, Serialize}; +use serde_with::{DeserializeFromStr, SerializeDisplay}; +use std::collections::{HashMap, HashSet}; +use std::fmt; +use std::ops::RangeInclusive; +use std::str::FromStr; + +use crate::assert_instr::InstructionAssertionsForBaseType; +use crate::context::{GlobalContext, GroupContext}; +use crate::input::{InputSet, InputSetEntry}; +use crate::predicate_forms::{DontCareMethod, PredicateForm, PredicationMask, ZeroingMethod}; +use crate::{ + assert_instr::InstructionAssertionMethod, + context::{self, ArchitectureSettings, Context, LocalContext, VariableType}, + expression::{Expression, FnCall, IdentifierType}, + input::IntrinsicInput, + matching::{KindMatchable, SizeMatchable}, + typekinds::*, + wildcards::Wildcard, + wildstring::WildString, +}; + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged)] +pub enum SubstitutionType { + MatchSize(SizeMatchable), + MatchKind(KindMatchable), +} + +impl SubstitutionType { + pub fn get(&mut self, ctx: &LocalContext) -> context::Result { + match self { + Self::MatchSize(smws) => { + smws.perform_match(ctx)?; + Ok(smws.as_ref().clone()) + } + Self::MatchKind(kmws) => { + kmws.perform_match(ctx)?; + Ok(kmws.as_ref().clone()) + } + } + } +} + +/// Mutability level +#[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)] +pub enum AccessLevel { + /// Immutable + R, + /// Mutable + RW, +} + +/// Function signature argument. +/// +/// Prepend the `mut` keyword for a mutable argument. Separate argument name +/// and type with a semicolon `:`. Usage examples: +/// - Mutable argument: `mut arg1: *u64` +/// - Immutable argument: `arg2: u32` +#[derive(Debug, Clone, SerializeDisplay, DeserializeFromStr)] +pub struct Argument { + /// Argument name + pub name: WildString, + /// Mutability level + pub rw: AccessLevel, + /// Argument type + pub kind: TypeKind, +} + +impl Argument { + pub fn populate_variables(&self, vars: &mut HashMap) { + vars.insert( + self.name.to_string(), + (self.kind.clone(), VariableType::Argument), + ); + } +} + +impl FromStr for Argument { + type Err = String; + + fn from_str(s: &str) -> Result { + let mut it = s.splitn(2, ':').map(::trim); + if let Some(mut lhs) = it.next().map(|s| s.split_whitespace()) { + let lhs_len = lhs.clone().count(); + match (lhs_len, lhs.next(), it.next()) { + (2, Some("mut"), Some(kind)) => Ok(Argument { + name: lhs.next().unwrap().parse()?, + rw: AccessLevel::RW, + kind: kind.parse()?, + }), + (2, Some(ident), _) => Err(format!("invalid {ident:#?} keyword")), + (1, Some(name), Some(kind)) => Ok(Argument { + name: name.parse()?, + rw: AccessLevel::R, + kind: kind.parse()?, + }), + _ => Err(format!("invalid argument `{s}` provided")), + } + } else { + Err(format!("invalid argument `{s}` provided")) + } + } +} + +impl fmt::Display for Argument { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + if let AccessLevel::RW = &self.rw { + write!(f, "mut ")?; + } + + write!(f, "{}: {}", self.name, self.kind) + } +} + +impl ToTokens for Argument { + fn to_tokens(&self, tokens: &mut TokenStream) { + if let AccessLevel::RW = &self.rw { + tokens.append(format_ident!("mut")) + } + + let (name, kind) = (format_ident!("{}", self.name.to_string()), &self.kind); + tokens.append_all(quote! { #name: #kind }) + } +} + +/// Static definition part of the signature. It may evaluate to a constant +/// expression with e.g. `const imm: u64`, or a generic `T: Into`. +#[derive(Debug, Clone, SerializeDisplay, DeserializeFromStr)] +pub enum StaticDefinition { + /// Constant expression + Constant(Argument), + /// Generic type + Generic(String), +} + +impl StaticDefinition { + pub fn as_variable(&self) -> Option<(String, (TypeKind, VariableType))> { + match self { + StaticDefinition::Constant(arg) => Some(( + arg.name.to_string(), + (arg.kind.clone(), VariableType::Argument), + )), + StaticDefinition::Generic(..) => None, + } + } +} + +impl FromStr for StaticDefinition { + type Err = String; + + fn from_str(s: &str) -> Result { + match s.trim() { + s if s.starts_with("const ") => Ok(StaticDefinition::Constant(s[6..].trim().parse()?)), + s => Ok(StaticDefinition::Generic(s.to_string())), + } + } +} + +impl fmt::Display for StaticDefinition { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + StaticDefinition::Constant(arg) => write!(f, "const {arg}"), + StaticDefinition::Generic(generic) => write!(f, "{generic}"), + } + } +} + +impl ToTokens for StaticDefinition { + fn to_tokens(&self, tokens: &mut TokenStream) { + tokens.append_all(match self { + StaticDefinition::Constant(arg) => quote! { const #arg }, + StaticDefinition::Generic(generic) => { + let generic: TokenStream = generic.parse().expect("invalid Rust code"); + quote! { #generic } + } + }) + } +} + +/// Function constraints +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged)] +pub enum Constraint { + /// Asserts that the given variable equals to any of the given integer values + AnyI32 { + variable: String, + any_values: Vec, + }, + /// WildString version of RangeI32. If the string values given for the range + /// are valid, this gets built into a RangeI32. + RangeWildstring { + variable: String, + range: (WildString, WildString), + }, + /// Asserts that the given variable's value falls in the specified range + RangeI32 { + variable: String, + range: SizeMatchable>, + }, + /// Asserts that the number of elements/lanes does not exceed the 2048-bit SVE constraint + SVEMaxElems { + variable: String, + sve_max_elems_type: TypeKind, + }, + /// Asserts that the number of elements/lanes does not exceed the 128-bit register constraint + VecMaxElems { + variable: String, + vec_max_elems_type: TypeKind, + }, +} + +impl Constraint { + fn variable(&self) -> &str { + match self { + Constraint::AnyI32 { variable, .. } + | Constraint::RangeWildstring { variable, .. } + | Constraint::RangeI32 { variable, .. } + | Constraint::SVEMaxElems { variable, .. } + | Constraint::VecMaxElems { variable, .. } => variable, + } + } + pub fn build(&mut self, ctx: &Context) -> context::Result { + if let Self::RangeWildstring { + variable, + range: (min, max), + } = self + { + min.build_acle(ctx.local)?; + max.build_acle(ctx.local)?; + let min = min.to_string(); + let max = max.to_string(); + let min: i32 = min + .parse() + .map_err(|_| format!("the minimum value `{min}` is not a valid number"))?; + let max: i32 = max + .parse() + .map_err(|_| format!("the maximum value `{max}` is not a valid number"))?; + *self = Self::RangeI32 { + variable: variable.to_owned(), + range: SizeMatchable::Matched(RangeInclusive::new(min, max)), + } + } + + if let Self::SVEMaxElems { + sve_max_elems_type: ty, + .. + } + | Self::VecMaxElems { + vec_max_elems_type: ty, + .. + } = self + { + if let Some(w) = ty.wildcard() { + ty.populate_wildcard(ctx.local.provide_type_wildcard(w)?)?; + } + } + + if let Self::RangeI32 { range, .. } = self { + range.perform_match(ctx.local)?; + } + + let variable = self.variable(); + ctx.local + .variables + .contains_key(variable) + .then_some(()) + .ok_or_else(|| format!("cannot build constraint, could not find variable {variable}")) + } +} + +/// Function signature +#[derive(Debug, Clone, Default, Serialize, Deserialize)] +pub struct Signature { + /// Function name + pub name: WildString, + /// List of function arguments, leave unset or empty for no arguments + pub arguments: Vec, + /// Function return type, leave unset for void + pub return_type: Option, + + /// List of static definitions, leave unset of empty if not required + #[serde(default)] + pub static_defs: Vec, + + /// **Internal use only.** + /// Condition for which the ultimate function is specific to predicates. + #[serde(skip)] + pub is_predicate_specific: bool, + + /// **Internal use only.** + /// Setting this property will trigger the signature builder to convert any `svbool*_t` to `svbool_t` in the input and output. + #[serde(skip)] + pub predicate_needs_conversion: bool, +} + +impl Signature { + pub fn drop_argument(&mut self, arg_name: &WildString) -> Result<(), String> { + if let Some(idx) = self + .arguments + .iter() + .position(|arg| arg.name.to_string() == arg_name.to_string()) + { + self.arguments.remove(idx); + Ok(()) + } else { + Err(format!("no argument {arg_name} found to drop")) + } + } + + pub fn build(&mut self, ctx: &LocalContext) -> context::Result { + self.name.build_acle(ctx)?; + + if let Some(ref mut return_type) = self.return_type { + if let Some(w) = return_type.clone().wildcard() { + return_type.populate_wildcard(ctx.provide_type_wildcard(w)?)?; + } + } + + self.arguments + .iter_mut() + .try_for_each(|arg| arg.name.build_acle(ctx))?; + + self.arguments + .iter_mut() + .filter_map(|arg| { + arg.kind + .clone() + .wildcard() + .map(|w| (&mut arg.kind, w.clone())) + }) + .try_for_each(|(ty, w)| ty.populate_wildcard(ctx.provide_type_wildcard(&w)?)) + } + + pub fn fn_name(&self) -> WildString { + self.name.replace(['[', ']'], "") + } + + pub fn doc_name(&self) -> String { + self.name.to_string() + } +} + +impl ToTokens for Signature { + fn to_tokens(&self, tokens: &mut TokenStream) { + let name_ident = format_ident!("{}", self.fn_name().to_string()); + let arguments = self + .arguments + .clone() + .into_iter() + .map(|mut arg| { + if arg + .kind + .vector() + .map_or(false, |ty| ty.base_type().is_bool()) + && self.predicate_needs_conversion + { + arg.kind = TypeKind::Vector(VectorType::make_predicate_from_bitsize(8)) + } + arg + }) + .collect_vec(); + let static_defs = &self.static_defs; + tokens.append_all(quote! { fn #name_ident<#(#static_defs),*>(#(#arguments),*) }); + + if let Some(ref return_type) = self.return_type { + if return_type + .vector() + .map_or(false, |ty| ty.base_type().is_bool()) + && self.predicate_needs_conversion + { + tokens.append_all(quote! { -> svbool_t }) + } else { + tokens.append_all(quote! { -> #return_type }) + } + } + } +} + +#[derive(Debug, Clone)] +pub struct LLVMLinkAttribute { + pub arch: String, + pub link: String, +} + +impl ToTokens for LLVMLinkAttribute { + fn to_tokens(&self, tokens: &mut TokenStream) { + let LLVMLinkAttribute { arch, link } = self; + tokens.append_all(quote! { + #[cfg_attr(target_arch = #arch, link_name = #link)] + }) + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +pub struct LLVMLink { + /// LLVM link function name without namespace and types, + /// e.g. `st1` in `llvm.aarch64.sve.st1.nxv4i32` + pub name: WildString, + + /// LLVM link signature arguments, leave unset if it inherits from intrinsic's signature + pub arguments: Option>, + /// LLVM link signature return type, leave unset if it inherits from intrinsic's signature + pub return_type: Option, + + /// **Internal use only. Do not set.** + /// Attribute LLVM links for the function. First element is the architecture it targets, + /// second element is the LLVM link itself. + #[serde(skip)] + pub links: Option>, + + /// **Internal use only. Do not set.** + /// Generated signature from these `arguments` and/or `return_type` if set, and the intrinsic's signature. + #[serde(skip)] + pub signature: Option>, +} + +impl LLVMLink { + pub fn resolve(&self, cfg: &ArchitectureSettings) -> String { + self.name + .starts_with("llvm") + .then(|| self.name.to_string()) + .unwrap_or_else(|| format!("{}.{}", cfg.llvm_link_prefix, self.name)) + } + + pub fn build_and_save(&mut self, ctx: &mut Context) -> context::Result { + self.build(ctx)?; + + // Save LLVM link to the group context + ctx.global.arch_cfgs.iter().for_each(|cfg| { + ctx.group + .links + .insert(self.resolve(cfg), ctx.local.input.clone()); + }); + + Ok(()) + } + + pub fn build(&mut self, ctx: &mut Context) -> context::Result { + let mut sig_name = ctx.local.signature.name.clone(); + sig_name.prepend_str("_"); + + let mut sig = Signature { + name: sig_name, + arguments: self + .arguments + .clone() + .unwrap_or_else(|| ctx.local.signature.arguments.clone()), + return_type: self + .return_type + .clone() + .or_else(|| ctx.local.signature.return_type.clone()), + static_defs: vec![], + is_predicate_specific: ctx.local.signature.is_predicate_specific, + predicate_needs_conversion: false, + }; + + sig.build(ctx.local)?; + self.name.build(ctx.local, TypeRepr::LLVMMachine)?; + + // Add link function name to context + ctx.local + .substitutions + .insert(Wildcard::LLVMLink, sig.fn_name().to_string()); + + self.signature = Some(Box::new(sig)); + self.links = Some( + ctx.global + .arch_cfgs + .iter() + .map(|cfg| LLVMLinkAttribute { + arch: cfg.arch_name.to_owned(), + link: self.resolve(cfg), + }) + .collect_vec(), + ); + + Ok(()) + } + + /// Alters all the unsigned types from the signature, as unsupported by LLVM. + pub fn sanitise_uints(&mut self) { + let transform = |tk: &mut TypeKind| { + if let Some(BaseType::Sized(BaseTypeKind::UInt, size)) = tk.base_type() { + *tk.base_type_mut().unwrap() = BaseType::Sized(BaseTypeKind::Int, *size) + } + }; + + if let Some(sig) = self.signature.as_mut() { + for arg in sig.arguments.iter_mut() { + transform(&mut arg.kind); + } + + sig.return_type.as_mut().map(transform); + } + } + + /// Make a function call to the LLVM link + pub fn make_fn_call(&self, intrinsic_sig: &Signature) -> context::Result { + let link_sig = self.signature.as_ref().ok_or_else(|| { + "cannot derive the LLVM link call, as it does not hold a valid function signature" + .to_string() + })?; + + if intrinsic_sig.arguments.len() != link_sig.arguments.len() { + return Err( + "cannot derive the LLVM link call, the number of arguments does not match" + .to_string(), + ); + } + + let call_args = intrinsic_sig + .arguments + .iter() + .zip(link_sig.arguments.iter()) + .map(|(intrinsic_arg, link_arg)| { + // Could also add a type check... + if intrinsic_arg.name == link_arg.name { + Ok(Expression::Identifier( + intrinsic_arg.name.to_owned(), + IdentifierType::Variable, + )) + } else { + Err("cannot derive the LLVM link call, the arguments do not match".to_string()) + } + }) + .try_collect()?; + + Ok(FnCall::new_expression(link_sig.fn_name().into(), call_args)) + } + + /// Given a FnCall, apply all the predicate and unsigned conversions as required. + pub fn apply_conversions_to_call( + &self, + mut fn_call: FnCall, + ctx: &LocalContext, + ) -> context::Result { + use BaseType::{Sized, Unsized}; + use BaseTypeKind::{Bool, UInt}; + use VariableType::Argument; + + let convert = + |method: &str, ex| Expression::MethodCall(Box::new(ex), method.to_string(), vec![]); + + fn_call.1 = fn_call + .1 + .into_iter() + .map(|arg| -> context::Result { + if let Expression::Identifier(ref var_name, IdentifierType::Variable) = arg { + let (kind, scope) = ctx + .variables + .get(&var_name.to_string()) + .ok_or_else(|| format!("invalid variable {var_name:?} being referenced"))?; + + match (scope, kind.base_type()) { + (Argument, Some(Sized(Bool, bitsize))) if *bitsize != 8 => { + Ok(convert("into", arg)) + } + (Argument, Some(Sized(UInt, _) | Unsized(UInt))) => { + Ok(convert("as_signed", arg)) + } + _ => Ok(arg), + } + } else { + Ok(arg) + } + }) + .try_collect()?; + + let return_type_requires_conversion = self + .signature + .as_ref() + .and_then(|sig| sig.return_type.as_ref()) + .and_then(|ty| { + if let Some(Sized(Bool, bitsize)) = ty.base_type() { + (*bitsize != 8).then_some(Bool) + } else if let Some(Sized(UInt, _) | Unsized(UInt)) = ty.base_type() { + Some(UInt) + } else { + None + } + }); + + let fn_call = Expression::FnCall(fn_call); + match return_type_requires_conversion { + Some(Bool) => Ok(convert("into", fn_call)), + Some(UInt) => Ok(convert("as_unsigned", fn_call)), + _ => Ok(fn_call), + } + } +} + +impl ToTokens for LLVMLink { + fn to_tokens(&self, tokens: &mut TokenStream) { + assert!( + self.signature.is_some() && self.links.is_some(), + "expression {self:#?} was not built before calling to_tokens" + ); + + let signature = self.signature.as_ref().unwrap(); + let links = self.links.as_ref().unwrap(); + tokens.append_all(quote! { + extern "C" { + #(#links),* + #signature; + } + }) + } +} + +#[derive(Debug, Clone, Default, Serialize, Deserialize)] +#[serde(rename_all = "snake_case")] +pub enum FunctionVisibility { + #[default] + Public, + Private, +} + +/// Whether to generate a load/store test, and which typeset index +/// represents the data type of the load/store target address +#[derive(Clone, Debug, Default, Serialize, Deserialize)] +#[serde(rename_all = "snake_case")] +pub enum Test { + #[default] + #[serde(skip)] + None, // Covered by `intrinsic-test` + Load(usize), + Store(usize), +} + +impl Test { + pub fn get_typeset_index(&self) -> Option { + match *self { + Test::Load(n) => Some(n), + Test::Store(n) => Some(n), + _ => None, + } + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(rename_all = "snake_case")] +pub enum Safety { + Safe, + Unsafe(Vec), +} + +impl Safety { + /// Return `Ok(Safety::Safe)` if safety appears reasonable for the given `intrinsic`'s name and + /// prototype. Otherwise, return `Err()` with a suitable diagnostic. + fn safe_checked(intrinsic: &Intrinsic) -> Result { + let name = intrinsic.signature.doc_name(); + if name.starts_with("sv") { + let handles_pointers = intrinsic + .signature + .arguments + .iter() + .any(|arg| matches!(arg.kind, TypeKind::Pointer(..))); + if name.starts_with("svld") + || name.starts_with("svst") + || name.starts_with("svprf") + || name.starts_with("svundef") + || handles_pointers + { + let doc = intrinsic.doc.as_ref().map(|s| s.to_string()); + let doc = doc.as_deref().unwrap_or("..."); + Err(format!( + "`{name}` has no safety specification, but it looks like it should be unsafe. \ + Consider specifying (un)safety explicitly: + + - name: {name} + doc: {doc} + safety: + unsafe: + - ... + ... +" + )) + } else { + Ok(Self::Safe) + } + } else { + Err(format!( + "Safety::safe_checked() for non-SVE intrinsic: {name}" + )) + } + } + + fn is_safe(&self) -> bool { + match self { + Self::Safe => true, + Self::Unsafe(..) => false, + } + } + + fn is_unsafe(&self) -> bool { + !self.is_safe() + } + + fn has_doc_comments(&self) -> bool { + match self { + Self::Safe => false, + Self::Unsafe(v) => !v.is_empty(), + } + } + + fn doc_comments(&self) -> &[UnsafetyComment] { + match self { + Self::Safe => &[], + Self::Unsafe(v) => v.as_slice(), + } + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(rename_all = "snake_case")] +pub enum UnsafetyComment { + Custom(String), + Uninitialized, + PointerOffset(GovernedBy), + PointerOffsetVnum(GovernedBy), + Dereference(GovernedBy), + UnpredictableOnFault, + NonTemporal, + NoProvenance(String), +} + +#[derive(Debug, Clone, Default, Serialize, Deserialize)] +#[serde(rename_all = "snake_case")] +pub enum GovernedBy { + #[default] + Predicated, + PredicatedNonFaulting, + PredicatedFirstFaulting, +} + +impl fmt::Display for GovernedBy { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Predicated => write!(f, " (governed by `pg`)"), + Self::PredicatedNonFaulting => write!( + f, + " (governed by `pg`, the first-fault register (`FFR`) \ + and non-faulting behaviour)" + ), + Self::PredicatedFirstFaulting => write!( + f, + " (governed by `pg`, the first-fault register (`FFR`) \ + and first-faulting behaviour)" + ), + } + } +} + +impl fmt::Display for UnsafetyComment { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Custom(s) => s.fmt(f), + Self::Uninitialized => write!( + f, + "This creates an uninitialized value, and may be unsound (like \ + [`core::mem::uninitialized`])." + ), + Self::PointerOffset(gov) => write!( + f, + "[`pointer::offset`](pointer#method.offset) safety constraints must \ + be met for the address calculation for each active element{gov}." + ), + Self::PointerOffsetVnum(gov) => write!( + f, + "[`pointer::offset`](pointer#method.offset) safety constraints must \ + be met for the address calculation for each active element{gov}. \ + In particular, note that `vnum` is scaled by the vector \ + length, `VL`, which is not known at compile time." + ), + Self::Dereference(gov) => write!( + f, + "This dereferences and accesses the calculated address for each \ + active element{gov}." + ), + Self::NonTemporal => write!( + f, + "Non-temporal accesses have special memory ordering rules, and \ + [explicit barriers may be required for some applications]\ + (https://developer.arm.com/documentation/den0024/a/Memory-Ordering/Barriers/Non-temporal-load-and-store-pair?lang=en)." + ), + Self::NoProvenance(arg) => write!( + f, + "Addresses passed in `{arg}` lack provenance, so this is similar to using a \ + `usize as ptr` cast (or [`core::ptr::from_exposed_addr`]) on each lane before \ + using it." + ), + Self::UnpredictableOnFault => write!( + f, + "Result lanes corresponding to inactive FFR lanes (either before or as a result \ + of this intrinsic) have \"CONSTRAINED UNPREDICTABLE\" values, irrespective of \ + predication. Refer to architectural documentation for details." + ), + } + } +} + +#[derive(Debug, Clone, Default, Serialize, Deserialize)] +pub struct Intrinsic { + #[serde(default)] + pub visibility: FunctionVisibility, + #[serde(default)] + pub doc: Option, + #[serde(flatten)] + pub signature: Signature, + /// Function sequential composition + pub compose: Vec, + /// Input to generate the intrinsic against. Leave empty if the intrinsic + /// does not have any variants. + /// Specific variants contain one InputSet + #[serde(flatten, default)] + pub input: IntrinsicInput, + #[serde(default)] + pub constraints: Vec, + /// Additional target features to add to the global settings + #[serde(default)] + pub target_features: Vec, + /// Should the intrinsic be `unsafe`? By default, the generator will try to guess from the + /// prototype, but it errs on the side of `unsafe`, and prints a warning in that case. + #[serde(default)] + pub safety: Option, + #[serde(default)] + pub substitutions: HashMap, + /// List of the only indices in a typeset that require conversion to signed + /// when deferring unsigned intrinsics to signed. (optional, default + /// behaviour is all unsigned types are converted to signed) + #[serde(default)] + pub defer_to_signed_only_indices: HashSet, + pub assert_instr: Vec, + /// Whether we should generate a test for this intrinsic + #[serde(default)] + pub test: Test, + /// Primary base type, used for instruction assertion. + #[serde(skip)] + pub base_type: Option, +} + +impl Intrinsic { + pub fn llvm_link(&self) -> Option<&LLVMLink> { + self.compose.iter().find_map(|ex| { + if let Expression::LLVMLink(llvm_link) = ex { + Some(llvm_link) + } else { + None + } + }) + } + + pub fn llvm_link_mut(&mut self) -> Option<&mut LLVMLink> { + self.compose.iter_mut().find_map(|ex| { + if let Expression::LLVMLink(llvm_link) = ex { + Some(llvm_link) + } else { + None + } + }) + } + + pub fn generate_variants(&self, global_ctx: &GlobalContext) -> context::Result> { + let wrap_err = |err| format!("{}: {err}", self.signature.name); + + let mut group_ctx = GroupContext::default(); + self.input + .variants(self) + .map_err(wrap_err)? + .map(|input| { + self.generate_variant(input.clone(), &mut group_ctx, global_ctx) + .map_err(wrap_err) + .map(|variant| (variant, input)) + }) + .collect::>>() + .and_then(|mut variants| { + variants.sort_by_cached_key(|(_, input)| input.to_owned()); + + if variants.is_empty() { + let standalone_variant = self + .generate_variant(InputSet::default(), &mut group_ctx, global_ctx) + .map_err(wrap_err)?; + + Ok(vec![standalone_variant]) + } else { + Ok(variants + .into_iter() + .map(|(variant, _)| variant) + .collect_vec()) + } + }) + } + + pub fn generate_variant( + &self, + input: InputSet, + group_ctx: &mut GroupContext, + global_ctx: &GlobalContext, + ) -> context::Result { + let mut variant = self.clone(); + + variant.input.types = vec![InputSetEntry::new(vec![input.clone()])]; + + let mut local_ctx = LocalContext::new(input, self); + let mut ctx = Context { + local: &mut local_ctx, + group: group_ctx, + global: global_ctx, + }; + + variant.pre_build(&mut ctx)?; + + match ctx.local.predicate_form().cloned() { + Some(PredicateForm::DontCare(method)) => { + variant.compose = variant.generate_dont_care_pass_through(&mut ctx, method)? + } + Some(PredicateForm::Zeroing(method)) => { + variant.compose = variant.generate_zeroing_pass_through(&mut ctx, method)? + } + _ => { + for idx in 0..variant.compose.len() { + let mut ex = variant.compose[idx].clone(); + ex.build(&variant, &mut ctx)?; + variant.compose[idx] = ex; + } + } + }; + + variant.post_build(&mut ctx)?; + + if let Some(n_variant_op) = ctx.local.n_variant_op().cloned() { + variant.generate_n_variant(n_variant_op, &mut ctx) + } else { + Ok(variant) + } + } + + /// Implement a "zeroing" (_z) method by calling an existing "merging" (_m) method, as required. + fn generate_zeroing_pass_through( + &mut self, + ctx: &mut Context, + method: ZeroingMethod, + ) -> context::Result> { + PredicationMask::try_from(&ctx.local.signature.name) + .ok() + .filter(|mask| mask.has_merging()) + .ok_or_else(|| format!("cannot generate zeroing passthrough for {}, no merging predicate form is specified", self.signature.name))?; + + // Determine the function to pass through to. + let mut target_ctx = ctx.local.clone(); + // Change target function predicate form to merging + *target_ctx.input.iter_mut() + .find_map(|arg| arg.predicate_form_mut()) + .expect("failed to generate zeroing pass through, could not find predicate form in the InputSet") = PredicateForm::Merging; + + let mut sig = target_ctx.signature.clone(); + sig.build(&target_ctx)?; + + let args_as_expressions = |arg: &Argument| -> context::Result { + let arg_name = arg.name.to_string(); + match &method { + ZeroingMethod::Drop { drop } if arg_name == drop.to_string() => { + Ok(PredicateForm::make_zeroinitializer(&arg.kind)) + } + ZeroingMethod::Select { select } if arg_name == select.to_string() => { + let pg = sig + .arguments + .iter() + .find_map(|arg| match arg.kind.vector() { + Some(ty) if ty.base_type().is_bool() => Some(arg.name.clone()), + _ => None, + }) + .ok_or_else(|| { + format!("cannot generate zeroing passthrough for {}, no predicate found in the signature for zero selection", self.signature.name) + })?; + Ok(PredicateForm::make_zeroselector( + pg, + select.clone(), + &arg.kind, + )) + } + _ => Ok(arg.into()), + } + }; + + let name: Expression = sig.fn_name().into(); + let args: Vec = sig + .arguments + .iter() + .map(args_as_expressions) + .try_collect()?; + let statics: Vec = sig + .static_defs + .iter() + .map(|sd| sd.try_into()) + .try_collect()?; + let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + call.build(self, ctx)?; + Ok(vec![call]) + } + + /// Implement a "don't care" (_x) method by calling an existing "merging" (_m). + fn generate_dont_care_pass_through( + &mut self, + ctx: &mut Context, + method: DontCareMethod, + ) -> context::Result> { + PredicationMask::try_from(&ctx.local.signature.name).and_then(|mask| match method { + DontCareMethod::AsMerging if mask.has_merging() => Ok(()), + DontCareMethod::AsZeroing if mask.has_zeroing() => Ok(()), + _ => Err(format!( + "cannot generate don't care passthrough for {}, no {} predicate form is specified", + self.signature.name, + match method { + DontCareMethod::AsMerging => "merging", + DontCareMethod::AsZeroing => "zeroing", + _ => unreachable!(), + } + )), + })?; + + // Determine the function to pass through to. + let mut target_ctx = ctx.local.clone(); + // Change target function predicate form to merging + *target_ctx.input.iter_mut() + .find_map(|arg| arg.predicate_form_mut()) + .expect("failed to generate don't care passthrough, could not find predicate form in the InputSet") = PredicateForm::Merging; + + let mut sig = target_ctx.signature.clone(); + sig.build(&target_ctx)?; + + // We might need to drop an argument for a zeroing pass-through. + let drop = match (method, &self.input.predication_methods.zeroing_method) { + (DontCareMethod::AsZeroing, Some(ZeroingMethod::Drop { drop })) => Some(drop), + _ => None, + }; + + let name: Expression = sig.fn_name().into(); + let args: Vec = sig + .arguments + .iter() + .map(|arg| { + if Some(arg.name.to_string()) == drop.as_ref().map(|v| v.to_string()) { + // This argument is present in the _m form, but missing from the _x form. Clang + // typically replaces these with an uninitialised vector, but to avoid + // materialising uninitialised values in Rust, we instead merge with a known + // vector. This usually results in the same code generation. + // TODO: In many cases, it'll be better to use an unpredicated (or zeroing) form. + sig.arguments + .iter() + .filter(|&other| arg.name.to_string() != other.name.to_string()) + .find_map(|other| { + arg.kind.express_reinterpretation_from(&other.kind, other) + }) + .unwrap_or_else(|| PredicateForm::make_zeroinitializer(&arg.kind)) + } else { + arg.into() + } + }) + .collect(); + let statics: Vec = sig + .static_defs + .iter() + .map(|sd| sd.try_into()) + .try_collect()?; + let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + call.build(self, ctx)?; + Ok(vec![call]) + } + + /// Implement a "_n" variant based on the given operand + fn generate_n_variant( + &self, + mut n_variant_op: WildString, + ctx: &mut Context, + ) -> context::Result { + let mut variant = self.clone(); + + n_variant_op.build_acle(ctx.local)?; + + let n_op_arg_idx = variant + .signature + .arguments + .iter_mut() + .position(|arg| arg.name.to_string() == n_variant_op.to_string()) + .ok_or_else(|| { + format!( + "cannot generate `_n` variant for {}, operand `{n_variant_op}` not found", + variant.signature.name + ) + })?; + + let has_n_wildcard = ctx + .local + .signature + .name + .wildcards() + .any(|w| matches!(w, Wildcard::NVariant)); + + if !has_n_wildcard { + return Err(format!("cannot generate `_n` variant for {}, no wildcard {{_n}} was specified in the intrinsic's name", variant.signature.name)); + } + + // Build signature + variant.signature = ctx.local.signature.clone(); + if let Some(pf) = ctx.local.predicate_form() { + // WARN: this may break in the future according to the underlying implementation + // Drops unwanted arguments if needed (required for the collection of arguments to pass to the function) + pf.post_build(&mut variant)?; + } + + let sig = &mut variant.signature; + + ctx.local + .substitutions + .insert(Wildcard::NVariant, "_n".to_owned()); + + let arg_kind = &mut sig.arguments.get_mut(n_op_arg_idx).unwrap().kind; + *arg_kind = match arg_kind { + TypeKind::Wildcard(Wildcard::SVEType(idx, None)) => { + TypeKind::Wildcard(Wildcard::Type(*idx)) + } + _ => { + return Err(format!( + "cannot generate `_n` variant for {}, the given operand is not a valid SVE type", + variant.signature.name + )) + } + }; + + sig.build(ctx.local)?; + + // Build compose + let name: Expression = self.signature.fn_name().into(); + let args: Vec = sig + .arguments + .iter() + .enumerate() + .map(|(idx, arg)| { + let ty = arg.kind.acle_notation_repr(); + if idx == n_op_arg_idx { + FnCall::new_expression( + WildString::from(format!("svdup_n_{ty}")).into(), + vec![arg.into()], + ) + } else { + arg.into() + } + }) + .collect(); + let statics: Vec = sig + .static_defs + .iter() + .map(|sd| sd.try_into()) + .try_collect()?; + let mut call: Expression = FnCall(Box::new(name), args, statics).into(); + call.build(self, ctx)?; + + variant.compose = vec![call]; + variant.signature.predicate_needs_conversion = true; + + Ok(variant) + } + + fn pre_build(&mut self, ctx: &mut Context) -> context::Result { + self.substitutions + .iter_mut() + .try_for_each(|(k, v)| -> context::Result { + let mut ws = v.get(ctx.local)?; + ws.build_acle(ctx.local)?; + ctx.local + .substitutions + .insert(Wildcard::Custom(k.to_owned()), ws.to_string()); + Ok(()) + })?; + + self.signature.build(ctx.local)?; + + if self.safety.is_none() { + self.safety = match Safety::safe_checked(self) { + Ok(safe) => Some(safe), + Err(err) => { + eprintln!("{err}"); + return Err(format!( + "Refusing to infer unsafety for {name}", + name = self.signature.doc_name() + )); + } + } + } + + if let Some(doc) = &mut self.doc { + doc.build_acle(ctx.local)? + } + + // Add arguments to variable tracking + self.signature + .arguments + .iter() + .for_each(|arg| arg.populate_variables(&mut ctx.local.variables)); + + // Add constant expressions to variable tracking + self.signature + .static_defs + .iter() + .filter_map(StaticDefinition::as_variable) + .for_each(|(var_name, var_properties)| { + ctx.local.variables.insert(var_name, var_properties); + }); + + // Pre-build compose expressions + for idx in 0..self.compose.len() { + let mut ex = self.compose[idx].clone(); + ex.pre_build(ctx)?; + self.compose[idx] = ex; + } + + if !ctx.local.input.is_empty() { + // We simplify the LLVM link transmute logic by deferring to a variant employing the same LLVM link where possible + if let Some(link) = self.compose.iter().find_map(|ex| match ex { + Expression::LLVMLink(link) => Some(link), + _ => None, + }) { + let mut link = link.clone(); + link.build(ctx)?; + + for cfg in ctx.global.arch_cfgs.iter() { + let expected_link = link.resolve(cfg); + if let Some(target_inputset) = ctx.group.links.get(&expected_link) { + self.defer_to_existing_llvm_link(ctx.local, target_inputset)?; + break; + } + } + } + } + + self.assert_instr + .iter_mut() + .try_for_each(|ai| ai.build(ctx))?; + + // Prepend constraint assertions + self.constraints.iter_mut().try_for_each(|c| c.build(ctx))?; + let assertions: Vec<_> = self + .constraints + .iter() + .map(|c| ctx.local.make_assertion_from_constraint(c)) + .try_collect()?; + self.compose.splice(0..0, assertions); + + Ok(()) + } + + fn post_build(&mut self, ctx: &mut Context) -> context::Result { + if let Some(Expression::LLVMLink(link)) = self.compose.last() { + let mut fn_call = link.make_fn_call(&self.signature)?; + // Required to inject conversions + fn_call.build(self, ctx)?; + self.compose.push(fn_call) + } + + if let Some(llvm_link) = self.llvm_link_mut() { + // Turn all Rust unsigned types into signed + llvm_link.sanitise_uints(); + } + + if let Some(predicate_form) = ctx.local.predicate_form() { + predicate_form.post_build(self)? + } + + // Set for ToTokens to display a generic svbool_t + self.signature.predicate_needs_conversion = true; + + // Set base type kind for instruction assertion + self.base_type = ctx + .local + .input + .get(0) + .and_then(|arg| arg.typekind()) + .and_then(|ty| ty.base_type()) + .map(BaseType::clone); + + // Add global target features + self.target_features = ctx + .global + .arch_cfgs + .iter() + .flat_map(|cfg| cfg.target_feature.clone()) + .chain(self.target_features.clone()) + .collect_vec(); + + Ok(()) + } + + fn defer_to_existing_llvm_link( + &mut self, + ctx: &LocalContext, + target_inputset: &InputSet, + ) -> context::Result { + let mut target_ctx = ctx.clone(); + target_ctx.input = target_inputset.clone(); + + let mut target_signature = target_ctx.signature.clone(); + target_signature.build(&target_ctx)?; + + let drop_var = if let Some(pred) = ctx.predicate_form().cloned() { + match pred { + PredicateForm::Zeroing(ZeroingMethod::Drop { drop }) => Some(drop), + PredicateForm::DontCare(DontCareMethod::AsZeroing) => { + if let Some(ZeroingMethod::Drop { drop }) = + self.input.predication_methods.zeroing_method.to_owned() + { + Some(drop) + } else { + None + } + } + _ => None, + } + } else { + None + }; + + let call_method = + |ex, method: &str| Expression::MethodCall(Box::new(ex), method.to_string(), vec![]); + let as_unsigned = |ex| call_method(ex, "as_unsigned"); + let as_signed = |ex| call_method(ex, "as_signed"); + let convert_if_required = |w: Option<&Wildcard>, from: &InputSet, to: &InputSet, ex| { + if let Some(w) = w { + if let Some(dest_idx) = w.get_typeset_index() { + let from_type = from.get(dest_idx); + let to_type = to.get(dest_idx); + + if from_type != to_type { + let from_base_type = from_type + .and_then(|in_arg| in_arg.typekind()) + .and_then(|ty| ty.base_type()) + .map(|bt| bt.kind()); + let to_base_type = to_type + .and_then(|in_arg| in_arg.typekind()) + .and_then(|ty| ty.base_type()) + .map(|bt| bt.kind()); + + match (from_base_type, to_base_type) { + // Use AsSigned for uint -> int + (Some(BaseTypeKind::UInt), Some(BaseTypeKind::Int)) => as_signed(ex), + // Use AsUnsigned for int -> uint + (Some(BaseTypeKind::Int), Some(BaseTypeKind::UInt)) => as_unsigned(ex), + (None, None) => ex, + _ => unreachable!("unsupported conversion case from {from_base_type:?} to {to_base_type:?} hit"), + } + } else { + ex + } + } else { + ex + } + } else { + ex + } + }; + + let args = ctx + .signature + .arguments + .iter() + .filter_map(|arg| { + let var = Expression::Identifier(arg.name.to_owned(), IdentifierType::Variable); + if drop_var.as_ref().map(|v| v.to_string()) != Some(arg.name.to_string()) { + Some(convert_if_required( + arg.kind.wildcard(), + &ctx.input, + target_inputset, + var, + )) + } else { + None + } + }) + .collect_vec(); + + let turbofish = self + .signature + .static_defs + .iter() + .map(|def| { + let name = match def { + StaticDefinition::Constant(Argument { name, .. }) => name.to_string(), + StaticDefinition::Generic(name) => name.to_string(), + }; + Expression::Identifier(name.into(), IdentifierType::Symbol) + }) + .collect_vec(); + + let ret_wildcard = ctx + .signature + .return_type + .as_ref() + .and_then(|t| t.wildcard()); + let call = FnCall(Box::new(target_signature.fn_name().into()), args, turbofish).into(); + + self.compose = vec![convert_if_required( + ret_wildcard, + target_inputset, + &ctx.input, + call, + )]; + + Ok(()) + } +} + +impl ToTokens for Intrinsic { + fn to_tokens(&self, tokens: &mut TokenStream) { + let signature = &self.signature; + let fn_name = signature.fn_name().to_string(); + let target_feature = self.target_features.join(","); + let safety = self + .safety + .as_ref() + .expect("safety should be determined during `pre_build`"); + + if let Some(doc) = &self.doc { + let mut doc = vec![doc.to_string()]; + + doc.push(String::new()); + doc.push(format!("[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/{})", &signature.doc_name())); + + if safety.has_doc_comments() { + doc.push(String::new()); + doc.push("## Safety".to_string()); + for comment in safety.doc_comments() { + doc.push(format!(" * {comment}")); + } + } else { + assert!( + safety.is_safe(), + "{fn_name} is both public and unsafe, and so needs safety documentation" + ); + } + + tokens.append_all(quote! { #(#[doc = #doc])* }); + } else { + assert!( + matches!(self.visibility, FunctionVisibility::Private), + "{fn_name} needs to be private, or to have documentation." + ); + assert!( + !safety.has_doc_comments(), + "{fn_name} needs a documentation section for its safety comments." + ); + } + + tokens.append_all(quote! { + #[inline] + #[target_feature(enable = #target_feature)] + }); + + if !self.assert_instr.is_empty() { + InstructionAssertionsForBaseType(&self.assert_instr, &self.base_type.as_ref()) + .to_tokens(tokens) + } + + match &self.visibility { + FunctionVisibility::Public => tokens.append_all(quote! { pub }), + FunctionVisibility::Private => {} + } + if safety.is_unsafe() { + tokens.append_all(quote! { unsafe }); + } + tokens.append_all(quote! { #signature }); + tokens.append(Punct::new('{', Spacing::Alone)); + + let mut body_unsafe = false; + let mut expressions = self.compose.iter().peekable(); + while let Some(ex) = expressions.next() { + if !body_unsafe && safety.is_safe() && ex.requires_unsafe_wrapper(&fn_name) { + body_unsafe = true; + tokens.append_all(quote! { unsafe }); + tokens.append(Punct::new('{', Spacing::Alone)); + } + // If it's not the last and not a LLVM link, add a trailing semicolon + if expressions.peek().is_some() && !matches!(ex, Expression::LLVMLink(_)) { + tokens.append_all(quote! { #ex; }) + } else { + ex.to_tokens(tokens) + } + } + if body_unsafe { + tokens.append(Punct::new('}', Spacing::Alone)); + } + + tokens.append(Punct::new('}', Spacing::Alone)); + } +} diff --git a/crates/stdarch-gen2/src/load_store_tests.rs b/crates/stdarch-gen2/src/load_store_tests.rs new file mode 100644 index 0000000000..d697a8d22d --- /dev/null +++ b/crates/stdarch-gen2/src/load_store_tests.rs @@ -0,0 +1,818 @@ +use std::fs::File; +use std::io::Write; +use std::path::PathBuf; +use std::str::FromStr; + +use crate::format_code; +use crate::input::InputType; +use crate::intrinsic::Intrinsic; +use crate::typekinds::BaseType; +use crate::typekinds::{ToRepr, TypeKind}; + +use itertools::Itertools; +use lazy_static::lazy_static; +use proc_macro2::TokenStream; +use quote::{format_ident, quote}; + +// Number of vectors in our buffers - the maximum tuple size, 4, plus 1 as we set the vnum +// argument to 1. +const NUM_VECS: usize = 5; +// The maximum vector length (in bits) +const VL_MAX_BITS: usize = 2048; +// The maximum vector length (in bytes) +const VL_MAX_BYTES: usize = VL_MAX_BITS / 8; +// The maximum number of elements in each vector type +const LEN_F32: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_F64: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_I8: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_I16: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_I32: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_I64: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_U8: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_U16: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_U32: usize = VL_MAX_BYTES / core::mem::size_of::(); +const LEN_U64: usize = VL_MAX_BYTES / core::mem::size_of::(); + +/// `load_intrinsics` and `store_intrinsics` is a vector of intrinsics +/// variants, while `out_path` is a file to write to. +pub fn generate_load_store_tests( + load_intrinsics: Vec, + store_intrinsics: Vec, + out_path: Option<&PathBuf>, +) -> Result<(), String> { + let output = match out_path { + Some(out) => { + Box::new(File::create(out).map_err(|e| format!("couldn't create tests file: {e}"))?) + as Box + } + None => Box::new(std::io::stdout()) as Box, + }; + let mut used_stores = vec![false; store_intrinsics.len()]; + let tests: Vec<_> = load_intrinsics + .iter() + .map(|load| { + let store_candidate = load + .signature + .fn_name() + .to_string() + .replace("svld1s", "svst1") + .replace("svld1u", "svst1") + .replace("svldnt1s", "svstnt1") + .replace("svldnt1u", "svstnt1") + .replace("svld", "svst") + .replace("gather", "scatter"); + + let store_index = store_intrinsics + .iter() + .position(|i| i.signature.fn_name().to_string() == store_candidate); + if let Some(i) = store_index { + used_stores[i] = true; + } + + generate_single_test( + load.clone(), + store_index.map(|i| store_intrinsics[i].clone()), + ) + }) + .try_collect()?; + + assert!(used_stores.into_iter().all(|b| b), "Not all store tests have been paired with a load. Consider generating specifc store-only tests"); + + let preamble = + TokenStream::from_str(&PREAMBLE).map_err(|e| format!("Preamble is invalid: {e}"))?; + // Only output manual tests for the SVE set + let manual_tests = match &load_intrinsics[0].target_features[..] { + [s] if s == "sve" => TokenStream::from_str(&MANUAL_TESTS) + .map_err(|e| format!("Manual tests are invalid: {e}"))?, + _ => quote!(), + }; + format_code( + output, + format!( + "// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen2/spec/sve` and run the following command to re-generate this +// file: +// +// ``` +// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// ``` +{}", + quote! { #preamble #(#tests)* #manual_tests } + ), + ) + .map_err(|e| format!("couldn't write tests: {e}")) +} + +/// A test looks like this: +/// ``` +/// let data = [scalable vector]; +/// +/// let mut storage = [0; N]; +/// +/// store_intrinsic([true_predicate], storage.as_mut_ptr(), data); +/// [test contents of storage] +/// +/// let loaded == load_intrinsic([true_predicate], storage.as_ptr()) +/// assert!(loaded == data); +/// ``` +/// We intialise our data such that the value stored matches the index it's stored to. +/// By doing this we can validate scatters by checking that each value in the storage +/// array is either 0 or the same as its index. +fn generate_single_test( + load: Intrinsic, + store: Option, +) -> Result { + let chars = LdIntrCharacteristics::new(&load)?; + let fn_name = load.signature.fn_name().to_string(); + + if let Some(ty) = &chars.gather_bases_type { + if ty.base_type().unwrap().get_size() == Ok(32) + && chars.gather_index_type.is_none() + && chars.gather_offset_type.is_none() + { + // We lack a way to ensure data is in the bottom 32 bits of the address space + println!("Skipping test for {fn_name}"); + return Ok(quote!()); + } + } + + if fn_name.starts_with("svldff1") && fn_name.contains("gather") { + // TODO: We can remove this check when first-faulting gathers are fixed in CI's QEMU + // https://gitlab.com/qemu-project/qemu/-/issues/1612 + println!("Skipping test for {fn_name}"); + return Ok(quote!()); + } + + let fn_ident = format_ident!("{fn_name}"); + let test_name = format_ident!( + "test_{fn_name}{}", + if let Some(ref store) = store { + format!("_with_{}", store.signature.fn_name()) + } else { + String::new() + } + ); + + let load_type = &chars.load_type; + let acle_type = load_type.acle_notation_repr(); + + // If there's no return type, fallback to the load type for things that depend on it + let ret_type = &load + .signature + .return_type + .as_ref() + .and_then(TypeKind::base_type) + .unwrap_or(load_type); + + let pred_fn = format_ident!("svptrue_b{}", load_type.size()); + + let load_type_caps = load_type.rust_repr().to_uppercase(); + let data_array = format_ident!("{load_type_caps}_DATA"); + + let size_fn = format_ident!("svcnt{}", ret_type.size_literal()); + + let rust_ret_type = ret_type.rust_repr(); + let assert_fn = format_ident!("assert_vector_matches_{rust_ret_type}"); + + // Use vnum=1, so adjust all values by one vector length + let (length_call, vnum_arg) = if chars.vnum { + if chars.is_prf { + (quote!(), quote!(, 1)) + } else { + (quote!(let len = #size_fn() as usize;), quote!(, 1)) + } + } else { + (quote!(), quote!()) + }; + + let (bases_load, bases_arg) = if let Some(ty) = &chars.gather_bases_type { + // Bases is a vector of (sometimes 32-bit) pointers + // When we combine bases with an offset/index argument, we load from the data arrays + // starting at 1 + let base_ty = ty.base_type().unwrap(); + let rust_type = format_ident!("{}", base_ty.rust_repr()); + let index_fn = format_ident!("svindex_{}", base_ty.acle_notation_repr()); + let size_in_bytes = chars.load_type.get_size().unwrap() / 8; + + if base_ty.get_size().unwrap() == 32 { + // Treat bases as a vector of offsets here - we don't test this without an offset or + // index argument + ( + Some(quote!( + let bases = #index_fn(0, #size_in_bytes.try_into().unwrap()); + )), + quote!(, bases), + ) + } else { + // Treat bases as a vector of pointers + let base_fn = format_ident!("svdup_n_{}", base_ty.acle_notation_repr()); + let data_array = if store.is_some() { + format_ident!("storage") + } else { + format_ident!("{}_DATA", chars.load_type.rust_repr().to_uppercase()) + }; + + let add_fn = format_ident!("svadd_{}_x", base_ty.acle_notation_repr()); + ( + Some(quote! { + let bases = #base_fn(#data_array.as_ptr() as #rust_type); + let offsets = #index_fn(0, #size_in_bytes.try_into().unwrap()); + let bases = #add_fn(#pred_fn(), bases, offsets); + }), + quote!(, bases), + ) + } + } else { + (None, quote!()) + }; + + let index_arg = if let Some(ty) = &chars.gather_index_type { + let rust_type = format_ident!("{}", ty.rust_repr()); + if chars + .gather_bases_type + .as_ref() + .and_then(TypeKind::base_type) + .map_or(Err(String::new()), BaseType::get_size) + .unwrap() + == 32 + { + // Let index be the base of the data array + let data_array = if store.is_some() { + format_ident!("storage") + } else { + format_ident!("{}_DATA", chars.load_type.rust_repr().to_uppercase()) + }; + let size_in_bytes = chars.load_type.get_size().unwrap() / 8; + quote!(, #data_array.as_ptr() as #rust_type / (#size_in_bytes as #rust_type) + 1) + } else { + quote!(, 1.try_into().unwrap()) + } + } else { + quote!() + }; + + let offset_arg = if let Some(ty) = &chars.gather_offset_type { + let size_in_bytes = chars.load_type.get_size().unwrap() / 8; + if chars + .gather_bases_type + .as_ref() + .and_then(TypeKind::base_type) + .map_or(Err(String::new()), BaseType::get_size) + .unwrap() + == 32 + { + // Let offset be the base of the data array + let rust_type = format_ident!("{}", ty.rust_repr()); + let data_array = if store.is_some() { + format_ident!("storage") + } else { + format_ident!("{}_DATA", chars.load_type.rust_repr().to_uppercase()) + }; + quote!(, #data_array.as_ptr() as #rust_type + #size_in_bytes as #rust_type) + } else { + quote!(, #size_in_bytes.try_into().unwrap()) + } + } else { + quote!() + }; + + let (offsets_load, offsets_arg) = if let Some(ty) = &chars.gather_offsets_type { + // Offsets is a scalable vector of per-element offsets in bytes. We re-use the contiguous + // data for this, then multiply to get indices + let offsets_fn = format_ident!("svindex_{}", ty.base_type().unwrap().acle_notation_repr()); + let size_in_bytes = chars.load_type.get_size().unwrap() / 8; + ( + Some(quote! { + let offsets = #offsets_fn(0, #size_in_bytes.try_into().unwrap()); + }), + quote!(, offsets), + ) + } else { + (None, quote!()) + }; + + let (indices_load, indices_arg) = if let Some(ty) = &chars.gather_indices_type { + // There's no need to multiply indices by the load type width + let base_ty = ty.base_type().unwrap(); + let indices_fn = format_ident!("svindex_{}", base_ty.acle_notation_repr()); + ( + Some(quote! { + let indices = #indices_fn(0, 1); + }), + quote! {, indices}, + ) + } else { + (None, quote!()) + }; + + let ptr = if chars.gather_bases_type.is_some() { + quote!() + } else if chars.is_prf { + quote!(, I64_DATA.as_ptr()) + } else { + quote!(, #data_array.as_ptr()) + }; + + let tuple_len = &chars.tuple_len; + let expecteds = if chars.is_prf { + // No return value for prefetches + vec![] + } else { + (0..*tuple_len) + .map(|i| get_expected_range(i, &chars)) + .collect() + }; + let asserts: Vec<_> = + if *tuple_len > 1 { + let svget = format_ident!("svget{tuple_len}_{acle_type}"); + expecteds.iter().enumerate().map(|(i, expected)| { + quote! (#assert_fn(#svget::<{ #i as i32 }>(loaded), #expected);) + }).collect() + } else { + expecteds + .iter() + .map(|expected| quote! (#assert_fn(loaded, #expected);)) + .collect() + }; + + let function = if chars.is_prf { + if fn_name.contains("gather") && fn_name.contains("base") && !fn_name.starts_with("svprf_") + { + // svprf(b|h|w|d)_gather base intrinsics do not have a generic type parameter + quote!(#fn_ident::<{ svprfop::SV_PLDL1KEEP }>) + } else { + quote!(#fn_ident::<{ svprfop::SV_PLDL1KEEP }, i64>) + } + } else { + quote!(#fn_ident) + }; + + let octaword_guard = if chars.replicate_width == Some(256) { + let msg = format!("Skipping {test_name} due to SVE vector length"); + quote! { + if svcntb() < 32 { + println!(#msg); + return; + } + } + } else { + quote!() + }; + + let feats = load.target_features.join(","); + + if let Some(store) = store { + let data_init = if *tuple_len == 1 { + quote!(#(#expecteds)*) + } else { + let create = format_ident!("svcreate{tuple_len}_{acle_type}"); + quote!(#create(#(#expecteds),*)) + }; + let input = store.input.types.get(0).unwrap().get(0).unwrap(); + let store_type = input + .get(store.test.get_typeset_index().unwrap()) + .and_then(InputType::typekind) + .and_then(TypeKind::base_type) + .unwrap(); + + let store_type = format_ident!("{}", store_type.rust_repr()); + let storage_len = NUM_VECS * VL_MAX_BITS / chars.load_type.get_size()? as usize; + let store_fn = format_ident!("{}", store.signature.fn_name().to_string()); + let load_type = format_ident!("{}", chars.load_type.rust_repr()); + let (store_ptr, store_mut_ptr) = if chars.gather_bases_type.is_none() { + ( + quote!(, storage.as_ptr() as *const #load_type), + quote!(, storage.as_mut_ptr()), + ) + } else { + (quote!(), quote!()) + }; + let args = quote!(#pred_fn() #store_ptr #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg); + let call = if chars.uses_ffr { + // Doing a normal load first maximises the number of elements our ff/nf test loads + let non_ffr_fn_name = format_ident!( + "{}", + fn_name + .replace("svldff1", "svld1") + .replace("svldnf1", "svld1") + ); + quote! { + svsetffr(); + let _ = #non_ffr_fn_name(#args); + let loaded = #function(#args); + } + } else { + // Note that the FFR must be set for all tests as the assert functions mask against it + quote! { + svsetffr(); + let loaded = #function(#args); + } + }; + + Ok(quote! { + #[simd_test(enable = #feats)] + unsafe fn #test_name() { + #octaword_guard + #length_call + let mut storage = [0 as #store_type; #storage_len]; + let data = #data_init; + #bases_load + #offsets_load + #indices_load + + #store_fn(#pred_fn() #store_mut_ptr #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg, data); + for (i, &val) in storage.iter().enumerate() { + assert!(val == 0 as #store_type || val == i as #store_type); + } + + #call + #(#asserts)* + + } + }) + } else { + let args = quote!(#pred_fn() #ptr #vnum_arg #bases_arg #offset_arg #index_arg #offsets_arg #indices_arg); + let call = if chars.uses_ffr { + // Doing a normal load first maximises the number of elements our ff/nf test loads + let non_ffr_fn_name = format_ident!( + "{}", + fn_name + .replace("svldff1", "svld1") + .replace("svldnf1", "svld1") + ); + quote! { + svsetffr(); + let _ = #non_ffr_fn_name(#args); + let loaded = #function(#args); + } + } else { + // Note that the FFR must be set for all tests as the assert functions mask against it + quote! { + svsetffr(); + let loaded = #function(#args); + } + }; + Ok(quote! { + #[simd_test(enable = #feats)] + unsafe fn #test_name() { + #octaword_guard + #bases_load + #offsets_load + #indices_load + #call + #length_call + + #(#asserts)* + } + }) + } +} + +/// Assumes chars.ret_type is not None +fn get_expected_range(tuple_idx: usize, chars: &LdIntrCharacteristics) -> proc_macro2::TokenStream { + // vnum=1 + let vnum_adjust = if chars.vnum { quote!(len+) } else { quote!() }; + + let bases_adjust = + (chars.gather_index_type.is_some() || chars.gather_offset_type.is_some()) as usize; + + let tuple_len = chars.tuple_len; + let size = chars + .ret_type + .as_ref() + .and_then(TypeKind::base_type) + .unwrap_or(&chars.load_type) + .get_size() + .unwrap() as usize; + + if chars.replicate_width == Some(128) { + // svld1rq + let ty_rust = format_ident!( + "{}", + chars + .ret_type + .as_ref() + .unwrap() + .base_type() + .unwrap() + .rust_repr() + ); + let args: Vec<_> = (0..(128 / size)).map(|i| quote!(#i as #ty_rust)).collect(); + let dup = format_ident!( + "svdupq_n_{}", + chars.ret_type.as_ref().unwrap().acle_notation_repr() + ); + quote!(#dup(#(#args,)*)) + } else if chars.replicate_width == Some(256) { + // svld1ro - we use two interleaved svdups to create a repeating 256-bit pattern + let ty_rust = format_ident!( + "{}", + chars + .ret_type + .as_ref() + .unwrap() + .base_type() + .unwrap() + .rust_repr() + ); + let ret_acle = chars.ret_type.as_ref().unwrap().acle_notation_repr(); + let args: Vec<_> = (0..(128 / size)).map(|i| quote!(#i as #ty_rust)).collect(); + let args2: Vec<_> = ((128 / size)..(256 / size)) + .map(|i| quote!(#i as #ty_rust)) + .collect(); + let dup = format_ident!("svdupq_n_{ret_acle}"); + let interleave = format_ident!("svtrn1q_{ret_acle}"); + quote!(#interleave(#dup(#(#args,)*), #dup(#(#args2,)*))) + } else { + let start = bases_adjust + tuple_idx; + if chars + .ret_type + .as_ref() + .unwrap() + .base_type() + .unwrap() + .is_float() + { + // Use svcvt to create a linear sequence of floats + let cvt_fn = format_ident!("svcvt_f{size}_s{size}_x"); + let pred_fn = format_ident!("svptrue_b{size}"); + let svindex_fn = format_ident!("svindex_s{size}"); + quote! { #cvt_fn(#pred_fn(), #svindex_fn((#vnum_adjust #start).try_into().unwrap(), #tuple_len.try_into().unwrap()))} + } else { + let ret_acle = chars.ret_type.as_ref().unwrap().acle_notation_repr(); + let svindex = format_ident!("svindex_{ret_acle}"); + quote!(#svindex((#vnum_adjust #start).try_into().unwrap(), #tuple_len.try_into().unwrap())) + } + } +} + +struct LdIntrCharacteristics { + // The data type to load from (not necessarily the data type returned) + load_type: BaseType, + // The data type to return (None for unit) + ret_type: Option, + // The size of tuple to load/store + tuple_len: usize, + // Whether a vnum argument is present + vnum: bool, + // Is the intrinsic first/non-faulting? + uses_ffr: bool, + // Is it a prefetch? + is_prf: bool, + // The size of data loaded with svld1ro/q intrinsics + replicate_width: Option, + // Scalable vector of pointers to load from + gather_bases_type: Option, + // Scalar offset, paired with bases + gather_offset_type: Option, + // Scalar index, paired with bases + gather_index_type: Option, + // Scalable vector of offsets + gather_offsets_type: Option, + // Scalable vector of indices + gather_indices_type: Option, +} + +impl LdIntrCharacteristics { + fn new(intr: &Intrinsic) -> Result { + let input = intr.input.types.get(0).unwrap().get(0).unwrap(); + let load_type = input + .get(intr.test.get_typeset_index().unwrap()) + .and_then(InputType::typekind) + .and_then(TypeKind::base_type) + .unwrap(); + + let ret_type = intr.signature.return_type.clone(); + + let name = intr.signature.fn_name().to_string(); + let tuple_len = name + .chars() + .find(|c| c.is_numeric()) + .and_then(|c| c.to_digit(10)) + .unwrap_or(1) as usize; + + let uses_ffr = name.starts_with("svldff") || name.starts_with("svldnf"); + + let is_prf = name.starts_with("svprf"); + + let replicate_width = if name.starts_with("svld1ro") { + Some(256) + } else if name.starts_with("svld1rq") { + Some(128) + } else { + None + }; + + let get_ty_of_arg = |name: &str| { + intr.signature + .arguments + .iter() + .find(|a| a.name.to_string() == name) + .map(|a| a.kind.clone()) + }; + + let gather_bases_type = get_ty_of_arg("bases"); + let gather_offset_type = get_ty_of_arg("offset"); + let gather_index_type = get_ty_of_arg("index"); + let gather_offsets_type = get_ty_of_arg("offsets"); + let gather_indices_type = get_ty_of_arg("indices"); + + Ok(LdIntrCharacteristics { + load_type: *load_type, + ret_type, + tuple_len, + vnum: name.contains("vnum"), + uses_ffr, + is_prf, + replicate_width, + gather_bases_type, + gather_offset_type, + gather_index_type, + gather_offsets_type, + gather_indices_type, + }) + } +} + +lazy_static! { + static ref PREAMBLE: String = format!( + r#"#![allow(unused)] + +use super::*; +use std::boxed::Box; +use std::convert::{{TryFrom, TryInto}}; +use std::sync::LazyLock; +use std::vec::Vec; +use stdarch_test::simd_test; + +static F32_DATA: LazyLock<[f32; {LEN_F32} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_F32} * {NUM_VECS}) + .map(|i| i as f32) + .collect::>() + .try_into() + .expect("f32 data incorrectly initialised") +}}); +static F64_DATA: LazyLock<[f64; {LEN_F64} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_F64} * {NUM_VECS}) + .map(|i| i as f64) + .collect::>() + .try_into() + .expect("f64 data incorrectly initialised") +}}); +static I8_DATA: LazyLock<[i8; {LEN_I8} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_I8} * {NUM_VECS}) + .map(|i| ((i + 128) % 256 - 128) as i8) + .collect::>() + .try_into() + .expect("i8 data incorrectly initialised") +}}); +static I16_DATA: LazyLock<[i16; {LEN_I16} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_I16} * {NUM_VECS}) + .map(|i| i as i16) + .collect::>() + .try_into() + .expect("i16 data incorrectly initialised") +}}); +static I32_DATA: LazyLock<[i32; {LEN_I32} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_I32} * {NUM_VECS}) + .map(|i| i as i32) + .collect::>() + .try_into() + .expect("i32 data incorrectly initialised") +}}); +static I64_DATA: LazyLock<[i64; {LEN_I64} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_I64} * {NUM_VECS}) + .map(|i| i as i64) + .collect::>() + .try_into() + .expect("i64 data incorrectly initialised") +}}); +static U8_DATA: LazyLock<[u8; {LEN_U8} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_U8} * {NUM_VECS}) + .map(|i| i as u8) + .collect::>() + .try_into() + .expect("u8 data incorrectly initialised") +}}); +static U16_DATA: LazyLock<[u16; {LEN_U16} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_U16} * {NUM_VECS}) + .map(|i| i as u16) + .collect::>() + .try_into() + .expect("u16 data incorrectly initialised") +}}); +static U32_DATA: LazyLock<[u32; {LEN_U32} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_U32} * {NUM_VECS}) + .map(|i| i as u32) + .collect::>() + .try_into() + .expect("u32 data incorrectly initialised") +}}); +static U64_DATA: LazyLock<[u64; {LEN_U64} * {NUM_VECS}]> = LazyLock::new(|| {{ + (0..{LEN_U64} * {NUM_VECS}) + .map(|i| i as u64) + .collect::>() + .try_into() + .expect("u64 data incorrectly initialised") +}}); + +#[target_feature(enable = "sve")] +fn assert_vector_matches_f32(vector: svfloat32_t, expected: svfloat32_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_f32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_f64(vector: svfloat64_t, expected: svfloat64_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_f64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_i8(vector: svint8_t, expected: svint8_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_s8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_i16(vector: svint16_t, expected: svint16_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_s16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_i32(vector: svint32_t, expected: svint32_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_s32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_i64(vector: svint64_t, expected: svint64_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_s64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_u8(vector: svuint8_t, expected: svuint8_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b8(), defined)); + let cmp = svcmpne_u8(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_u16(vector: svuint16_t, expected: svuint16_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b16(), defined)); + let cmp = svcmpne_u16(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_u32(vector: svuint32_t, expected: svuint32_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b32(), defined)); + let cmp = svcmpne_u32(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} + +#[target_feature(enable = "sve")] +fn assert_vector_matches_u64(vector: svuint64_t, expected: svuint64_t) {{ + let defined = svrdffr(); + assert!(svptest_first(svptrue_b64(), defined)); + let cmp = svcmpne_u64(defined, vector, expected); + assert!(!svptest_any(defined, cmp)) +}} +"# + ); +} + +lazy_static! { + static ref MANUAL_TESTS: String = format!( + "#[simd_test(enable = \"sve\")] +unsafe fn test_ffr() {{ + svsetffr(); + let ffr = svrdffr(); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svindex_u8(1, 0)); + let pred = svdupq_n_b8(true, false, true, false, true, false, true, false, + true, false, true, false, true, false, true, false); + svwrffr(pred); + let ffr = svrdffr_z(svptrue_b8()); + assert_vector_matches_u8(svdup_n_u8_z(ffr, 1), svdup_n_u8_z(pred, 1)); +}} +" + ); +} diff --git a/crates/stdarch-gen2/src/main.rs b/crates/stdarch-gen2/src/main.rs new file mode 100644 index 0000000000..5379d18404 --- /dev/null +++ b/crates/stdarch-gen2/src/main.rs @@ -0,0 +1,273 @@ +#![feature(pattern)] + +mod assert_instr; +mod context; +mod expression; +mod input; +mod intrinsic; +mod load_store_tests; +mod matching; +mod predicate_forms; +mod typekinds; +mod wildcards; +mod wildstring; + +use intrinsic::Test; +use itertools::Itertools; +use quote::quote; +use std::fs::File; +use std::io::Write; +use std::path::{Path, PathBuf}; +use std::process::{Command, Stdio}; +use walkdir::WalkDir; + +fn main() -> Result<(), String> { + parse_args() + .into_iter() + .map(|(filepath, out)| { + File::open(&filepath) + .map(|f| (f, filepath, out)) + .map_err(|e| format!("could not read input file: {e}")) + }) + .map(|res| { + let (file, filepath, out) = res?; + serde_yaml::from_reader(file) + .map(|input: input::GeneratorInput| (input, filepath, out)) + .map_err(|e| format!("could not parse input file: {e}")) + }) + .collect::, _>>()? + .into_iter() + .map(|(input, filepath, out)| { + let intrinsics = input.intrinsics.into_iter() + .map(|intrinsic| intrinsic.generate_variants(&input.ctx)) + .try_collect() + .map(|mut vv: Vec<_>| { + vv.sort_by_cached_key(|variants| { + variants.first().map_or_else(String::default, |variant| { + variant.signature.fn_name().to_string() + }) + }); + vv.into_iter().flatten().collect_vec() + })?; + + let loads = intrinsics.iter() + .filter_map(|i| { + if matches!(i.test, Test::Load(..)) { + Some(i.clone()) + } else { + None + } + }).collect(); + let stores = intrinsics.iter() + .filter_map(|i| { + if matches!(i.test, Test::Store(..)) { + Some(i.clone()) + } else { + None + } + }).collect(); + load_store_tests::generate_load_store_tests(loads, stores, out.as_ref().map(|o| make_tests_filepath(&filepath, o)).as_ref())?; + Ok(( + input::GeneratorInput { + intrinsics, + ctx: input.ctx, + }, + filepath, + out, + )) + }) + .try_for_each( + |result: context::Result<(input::GeneratorInput, PathBuf, Option)>| -> context::Result { + let (generated, filepath, out) = result?; + + let w = match out { + Some(out) => Box::new( + File::create(make_output_filepath(&filepath, &out)) + .map_err(|e| format!("could not create output file: {e}"))?, + ) as Box, + None => Box::new(std::io::stdout()) as Box, + }; + + generate_file(generated, w) + .map_err(|e| format!("could not generate output file: {e}")) + }, + ) +} + +fn parse_args() -> Vec<(PathBuf, Option)> { + let mut args_it = std::env::args().skip(1); + assert!( + 1 <= args_it.len() && args_it.len() <= 2, + "Usage: cargo run -p stdarch-gen2 -- INPUT_DIR [OUTPUT_DIR]" + ); + + let in_path = Path::new(args_it.next().unwrap().as_str()).to_path_buf(); + assert!( + in_path.exists() && in_path.is_dir(), + "invalid path {in_path:#?} given" + ); + + let out_dir = if let Some(dir) = args_it.next() { + let out_path = Path::new(dir.as_str()).to_path_buf(); + assert!( + out_path.exists() && out_path.is_dir(), + "invalid path {out_path:#?} given" + ); + Some(out_path) + } else { + std::env::current_exe() + .map(|mut f| { + f.pop(); + f.push("../../crates/core_arch/src/aarch64/"); + f.exists().then_some(f) + }) + .ok() + .flatten() + }; + + WalkDir::new(in_path) + .into_iter() + .filter_map(Result::ok) + .filter(|f| f.file_type().is_file()) + .map(|f| (f.into_path(), out_dir.clone())) + .collect() +} + +fn generate_file( + generated_input: input::GeneratorInput, + mut out: Box, +) -> std::io::Result<()> { + write!( + out, + r#"// This code is automatically generated. DO NOT MODIFY. +// +// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: +// +// ``` +// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec +// ``` +#![allow(improper_ctypes)] + +#[cfg(test)] +use stdarch_test::assert_instr; + +use super::*;{uses_neon} + +"#, + uses_neon = generated_input + .ctx + .uses_neon_types + .then_some("\nuse crate::core_arch::arch::aarch64::*;") + .unwrap_or_default(), + )?; + let intrinsics = generated_input.intrinsics; + format_code(out, quote! { #(#intrinsics)* })?; + Ok(()) +} + +pub fn format_code( + mut output: impl std::io::Write, + input: impl std::fmt::Display, +) -> std::io::Result<()> { + let proc = Command::new("rustfmt") + .stdin(Stdio::piped()) + .stdout(Stdio::piped()) + .spawn()?; + write!(proc.stdin.as_ref().unwrap(), "{input}")?; + output.write_all(proc.wait_with_output()?.stdout.as_slice()) +} + +/// Derive an output file name from an input file and an output directory. +/// +/// The name is formed by: +/// +/// - ... taking in_filepath.file_name() (dropping all directory components), +/// - ... dropping a .yml or .yaml extension (if present), +/// - ... then dropping a .spec extension (if present). +/// +/// Panics if the resulting name is empty, or if file_name() is not UTF-8. +fn make_output_filepath(in_filepath: &Path, out_dirpath: &Path) -> PathBuf { + make_filepath(in_filepath, out_dirpath, |name: &str| format!("{name}.rs")) +} + +fn make_tests_filepath(in_filepath: &Path, out_dirpath: &Path) -> PathBuf { + make_filepath(in_filepath, out_dirpath, |name: &str| { + format!("ld_st_tests_{name}.rs") + }) +} + +fn make_filepath String>( + in_filepath: &Path, + out_dirpath: &Path, + name_formatter: F, +) -> PathBuf { + let mut parts = in_filepath.iter(); + let name = parts + .next_back() + .and_then(|f| f.to_str()) + .expect("Inputs must have valid, UTF-8 file_name()"); + let dir = parts.next_back().unwrap(); + + let name = name + .trim_end_matches(".yml") + .trim_end_matches(".yaml") + .trim_end_matches(".spec"); + assert!(!name.is_empty()); + + let mut output = out_dirpath.to_path_buf(); + output.push(dir); + output.push(name_formatter(name)); + output +} + +#[cfg(test)] +mod tests { + use super::*; + + #[test] + fn infer_output_file() { + macro_rules! t { + ($src:expr, $outdir:expr, $dst:expr) => { + let src: PathBuf = $src.iter().collect(); + let outdir: PathBuf = $outdir.iter().collect(); + let dst: PathBuf = $dst.iter().collect(); + assert_eq!(make_output_filepath(&src, &outdir), dst); + }; + } + // Documented usage. + t!(["x", "NAME.spec.yml"], [""], ["x", "NAME.rs"]); + t!( + ["x", "NAME.spec.yml"], + ["a", "b"], + ["a", "b", "x", "NAME.rs"] + ); + t!( + ["x", "y", "NAME.spec.yml"], + ["out"], + ["out", "y", "NAME.rs"] + ); + t!(["x", "NAME.spec.yaml"], ["out"], ["out", "x", "NAME.rs"]); + t!(["x", "NAME.spec"], ["out"], ["out", "x", "NAME.rs"]); + t!(["x", "NAME.yml"], ["out"], ["out", "x", "NAME.rs"]); + t!(["x", "NAME.yaml"], ["out"], ["out", "x", "NAME.rs"]); + // Unrecognised extensions get treated as part of the stem. + t!( + ["x", "NAME.spac.yml"], + ["out"], + ["out", "x", "NAME.spac.rs"] + ); + t!(["x", "NAME.txt"], ["out"], ["out", "x", "NAME.txt.rs"]); + // Always take the top-level directory from the input path + t!( + ["x", "y", "z", "NAME.spec.yml"], + ["out"], + ["out", "z", "NAME.rs"] + ); + } + + #[test] + #[should_panic] + fn infer_output_file_no_stem() { + make_output_filepath(Path::new(".spec.yml"), Path::new("")); + } +} diff --git a/crates/stdarch-gen2/src/matching.rs b/crates/stdarch-gen2/src/matching.rs new file mode 100644 index 0000000000..0c48062042 --- /dev/null +++ b/crates/stdarch-gen2/src/matching.rs @@ -0,0 +1,170 @@ +use proc_macro2::TokenStream; +use quote::ToTokens; +use serde::{Deserialize, Serialize}; +use std::fmt; + +use crate::context::{self, LocalContext}; +use crate::typekinds::{BaseType, BaseTypeKind, TypeKind}; + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct MatchSizeValues { + pub default: T, + pub byte: Option, + pub halfword: Option, + pub doubleword: Option, +} + +impl MatchSizeValues { + pub fn get(&mut self, ty: &TypeKind, ctx: &LocalContext) -> context::Result<&T> { + let base_ty = if let Some(w) = ty.wildcard() { + ctx.provide_type_wildcard(w)? + } else { + ty.clone() + }; + + if let BaseType::Sized(_, bitsize) = base_ty.base_type().unwrap() { + match (bitsize, &self.byte, &self.halfword, &self.doubleword) { + (64, _, _, Some(v)) | (16, _, Some(v), _) | (8, Some(v), _, _) => Ok(v), + _ => Ok(&self.default), + } + } else { + Err(format!("cannot match bitsize to unsized type {ty:?}!")) + } + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(deny_unknown_fields)] +pub struct MatchKindValues { + pub default: T, + pub float: Option, + pub unsigned: Option, +} + +impl MatchKindValues { + pub fn get(&mut self, ty: &TypeKind, ctx: &LocalContext) -> context::Result<&T> { + let base_ty = if let Some(w) = ty.wildcard() { + ctx.provide_type_wildcard(w)? + } else { + ty.clone() + }; + + match ( + base_ty.base_type().unwrap().kind(), + &self.float, + &self.unsigned, + ) { + (BaseTypeKind::Float, Some(v), _) | (BaseTypeKind::UInt, _, Some(v)) => Ok(v), + _ => Ok(&self.default), + } + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged, deny_unknown_fields)] +pub enum SizeMatchable { + Matched(T), + Unmatched { + match_size: Option, + #[serde(flatten)] + values: MatchSizeValues>, + }, +} + +impl SizeMatchable { + pub fn perform_match(&mut self, ctx: &LocalContext) -> context::Result { + match self { + Self::Unmatched { + match_size: None, + values: MatchSizeValues { default, .. }, + } => *self = Self::Matched(*default.to_owned()), + Self::Unmatched { + match_size: Some(ty), + values, + } => *self = Self::Matched(*values.get(ty, ctx)?.to_owned()), + _ => {} + } + Ok(()) + } +} + +impl AsRef for SizeMatchable { + fn as_ref(&self) -> &T { + if let SizeMatchable::Matched(v) = self { + v + } else { + panic!("no match for {self:?} was performed"); + } + } +} + +impl AsMut for SizeMatchable { + fn as_mut(&mut self) -> &mut T { + if let SizeMatchable::Matched(v) = self { + v + } else { + panic!("no match for {self:?} was performed"); + } + } +} + +impl ToTokens for SizeMatchable { + fn to_tokens(&self, tokens: &mut TokenStream) { + self.as_ref().to_tokens(tokens) + } +} + +#[derive(Debug, Clone, Serialize, Deserialize)] +#[serde(untagged, deny_unknown_fields)] +pub enum KindMatchable { + Matched(T), + Unmatched { + match_kind: Option, + #[serde(flatten)] + values: MatchKindValues>, + }, +} + +impl KindMatchable { + pub fn perform_match(&mut self, ctx: &LocalContext) -> context::Result { + match self { + Self::Unmatched { + match_kind: None, + values: MatchKindValues { default, .. }, + } => *self = Self::Matched(*default.to_owned()), + Self::Unmatched { + match_kind: Some(ty), + values, + } => *self = Self::Matched(*values.get(ty, ctx)?.to_owned()), + _ => {} + } + Ok(()) + } +} + +impl AsRef for KindMatchable { + fn as_ref(&self) -> &T { + if let KindMatchable::Matched(v) = self { + v + } else { + panic!("no match for {self:?} was performed"); + } + } +} + +impl AsMut for KindMatchable { + fn as_mut(&mut self) -> &mut T { + if let KindMatchable::Matched(v) = self { + v + } else { + panic!("no match for {self:?} was performed"); + } + } +} + +impl ToTokens for KindMatchable { + fn to_tokens(&self, tokens: &mut TokenStream) { + self.as_ref().to_tokens(tokens) + } +} diff --git a/crates/stdarch-gen2/src/predicate_forms.rs b/crates/stdarch-gen2/src/predicate_forms.rs new file mode 100644 index 0000000000..02789bf7eb --- /dev/null +++ b/crates/stdarch-gen2/src/predicate_forms.rs @@ -0,0 +1,249 @@ +use serde::{Deserialize, Serialize}; +use serde_with::{DeserializeFromStr, SerializeDisplay}; +use std::fmt; +use std::str::FromStr; + +use crate::context; +use crate::expression::{Expression, FnCall, IdentifierType}; +use crate::intrinsic::Intrinsic; +use crate::typekinds::{ToRepr, TypeKind}; +use crate::wildcards::Wildcard; +use crate::wildstring::WildString; + +const ZEROING_SUFFIX: &str = "_z"; +const MERGING_SUFFIX: &str = "_m"; +const DONT_CARE_SUFFIX: &str = "_x"; + +#[derive(Debug, Clone, PartialEq, Eq, Serialize, Deserialize)] +#[serde(untagged)] +pub enum ZeroingMethod { + /// Drop the specified argument and replace it with a zeroinitializer + Drop { drop: WildString }, + /// Apply zero selection to the specified variable when zeroing + Select { select: WildString }, +} + +impl PartialOrd for ZeroingMethod { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for ZeroingMethod { + fn cmp(&self, _: &Self) -> std::cmp::Ordering { + std::cmp::Ordering::Equal + } +} + +#[derive(Debug, Clone, Copy, Default, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] +pub enum DontCareMethod { + #[default] + Inferred, + AsZeroing, + AsMerging, +} + +#[derive(Debug, Clone, Default, PartialEq, Eq, Deserialize, Serialize)] +pub struct PredicationMethods { + /// Zeroing method, if the zeroing predicate form is used + #[serde(default)] + pub zeroing_method: Option, + /// Don't care method, if the don't care predicate form is used + #[serde(default)] + pub dont_care_method: DontCareMethod, +} + +#[derive(Debug, Clone, PartialEq, Eq, PartialOrd, Ord, Serialize, Deserialize)] +pub enum PredicateForm { + /// Enables merging predicate form + Merging, + /// Enables "don't care" predicate form. + DontCare(DontCareMethod), + /// Enables zeroing predicate form. If LLVM zeroselection is performed, then + /// set the `select` field to the variable that gets set. Otherwise set the + /// `drop` field if the zeroinitializer replaces a predicate when merging. + Zeroing(ZeroingMethod), +} + +impl PredicateForm { + pub fn get_suffix(&self) -> &'static str { + match self { + PredicateForm::Zeroing { .. } => ZEROING_SUFFIX, + PredicateForm::Merging => MERGING_SUFFIX, + PredicateForm::DontCare { .. } => DONT_CARE_SUFFIX, + } + } + + pub fn make_zeroinitializer(ty: &TypeKind) -> Expression { + FnCall::new_expression( + format!("svdup_n_{}", ty.acle_notation_repr()) + .parse() + .unwrap(), + vec![if ty.base_type().unwrap().is_float() { + Expression::FloatConstant(0.0) + } else { + Expression::IntConstant(0) + }], + ) + } + + pub fn make_zeroselector(pg_var: WildString, op_var: WildString, ty: &TypeKind) -> Expression { + FnCall::new_expression( + format!("svsel_{}", ty.acle_notation_repr()) + .parse() + .unwrap(), + vec![ + Expression::Identifier(pg_var, IdentifierType::Variable), + Expression::Identifier(op_var, IdentifierType::Variable), + Self::make_zeroinitializer(ty), + ], + ) + } + + pub fn post_build(&self, intrinsic: &mut Intrinsic) -> context::Result { + // Drop the argument + match self { + PredicateForm::Zeroing(ZeroingMethod::Drop { drop: drop_var }) => { + intrinsic.signature.drop_argument(drop_var)? + } + PredicateForm::DontCare(DontCareMethod::AsZeroing) => { + if let ZeroingMethod::Drop { drop } = intrinsic + .input + .predication_methods + .zeroing_method + .to_owned() + .ok_or_else(|| { + "DontCareMethod::AsZeroing without zeroing method.".to_string() + })? + { + intrinsic.signature.drop_argument(&drop)? + } + } + _ => {} + } + + Ok(()) + } + + fn infer_dont_care(mask: &PredicationMask, methods: &PredicationMethods) -> PredicateForm { + let method = if methods.dont_care_method == DontCareMethod::Inferred { + if mask.has_zeroing() + && matches!(methods.zeroing_method, Some(ZeroingMethod::Drop { .. })) + { + DontCareMethod::AsZeroing + } else { + DontCareMethod::AsMerging + } + } else { + methods.dont_care_method + }; + + PredicateForm::DontCare(method) + } + + pub fn compile_list( + mask: &PredicationMask, + methods: &PredicationMethods, + ) -> context::Result> { + let mut forms = Vec::new(); + + if mask.has_merging() { + forms.push(PredicateForm::Merging) + } + + if mask.has_dont_care() { + forms.push(Self::infer_dont_care(mask, methods)) + } + + if mask.has_zeroing() { + if let Some(method) = methods.zeroing_method.to_owned() { + forms.push(PredicateForm::Zeroing(method)) + } else { + return Err( + "cannot create a zeroing variant without a zeroing method specified!" + .to_string(), + ); + } + } + + Ok(forms) + } +} + +#[derive( + Debug, Clone, Copy, Default, PartialEq, Eq, Hash, DeserializeFromStr, SerializeDisplay, +)] +pub struct PredicationMask { + /// Merging + m: bool, + /// Don't care + x: bool, + /// Zeroing + z: bool, +} + +impl PredicationMask { + pub fn has_merging(&self) -> bool { + self.m + } + + pub fn has_dont_care(&self) -> bool { + self.x + } + + pub fn has_zeroing(&self) -> bool { + self.z + } +} + +impl FromStr for PredicationMask { + type Err = String; + + fn from_str(s: &str) -> Result { + let mut result = Self::default(); + for kind in s.bytes() { + match kind { + b'm' => result.m = true, + b'x' => result.x = true, + b'z' => result.z = true, + _ => { + return Err(format!( + "unknown predicate form modifier: {}", + char::from(kind) + )); + } + } + } + + if result.m || result.x || result.z { + Ok(result) + } else { + Err("invalid predication mask".to_string()) + } + } +} + +impl fmt::Display for PredicationMask { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + self.m.then(|| write!(f, "m")).transpose()?; + self.x.then(|| write!(f, "x")).transpose()?; + self.z.then(|| write!(f, "z")).transpose().map(|_| ()) + } +} + +impl TryFrom<&WildString> for PredicationMask { + type Error = String; + + fn try_from(value: &WildString) -> Result { + value + .wildcards() + .find_map(|w| { + if let Wildcard::PredicateForms(mask) = w { + Some(*mask) + } else { + None + } + }) + .ok_or_else(|| "no predicate forms were specified in the name".to_string()) + } +} diff --git a/crates/stdarch-gen2/src/typekinds.rs b/crates/stdarch-gen2/src/typekinds.rs new file mode 100644 index 0000000000..71f6297d94 --- /dev/null +++ b/crates/stdarch-gen2/src/typekinds.rs @@ -0,0 +1,1024 @@ +use lazy_static::lazy_static; +use proc_macro2::TokenStream; +use quote::{quote, ToTokens, TokenStreamExt}; +use regex::Regex; +use serde_with::{DeserializeFromStr, SerializeDisplay}; +use std::fmt; +use std::str::FromStr; + +use crate::context; +use crate::expression::{Expression, FnCall}; +use crate::intrinsic::AccessLevel; +use crate::wildcards::Wildcard; + +const VECTOR_FULL_REGISTER_SIZE: u32 = 128; +const VECTOR_HALF_REGISTER_SIZE: u32 = VECTOR_FULL_REGISTER_SIZE / 2; + +#[derive(Debug, Clone, Copy)] +pub enum TypeRepr { + C, + Rust, + LLVMMachine, + ACLENotation, + Size, + SizeLiteral, + TypeKind, + SizeInBytesLog2, +} + +pub trait ToRepr { + fn repr(&self, repr: TypeRepr) -> String; + + fn c_repr(&self) -> String { + self.repr(TypeRepr::C) + } + + fn rust_repr(&self) -> String { + self.repr(TypeRepr::Rust) + } + + fn llvm_machine_repr(&self) -> String { + self.repr(TypeRepr::LLVMMachine) + } + + fn acle_notation_repr(&self) -> String { + self.repr(TypeRepr::ACLENotation) + } + + fn size(&self) -> String { + self.repr(TypeRepr::Size) + } + + fn size_literal(&self) -> String { + self.repr(TypeRepr::SizeLiteral) + } + + fn type_kind(&self) -> String { + self.repr(TypeRepr::TypeKind) + } + + fn size_in_bytes_log2(&self) -> String { + self.repr(TypeRepr::SizeInBytesLog2) + } +} + +#[derive(Debug, Clone, Copy, Default, PartialEq, Eq, Hash)] +pub struct TypeKindOptions { + f: bool, + s: bool, + u: bool, +} + +impl TypeKindOptions { + pub fn contains(&self, kind: BaseTypeKind) -> bool { + match kind { + BaseTypeKind::Float => self.f, + BaseTypeKind::Int => self.s, + BaseTypeKind::UInt => self.u, + BaseTypeKind::Bool => false, + } + } +} + +impl FromStr for TypeKindOptions { + type Err = String; + + fn from_str(s: &str) -> Result { + let mut result = Self::default(); + for kind in s.bytes() { + match kind { + b'f' => result.f = true, + b's' => result.s = true, + b'u' => result.u = true, + _ => { + return Err(format!("unknown type kind: {}", char::from(kind))); + } + } + } + Ok(result) + } +} + +impl fmt::Display for TypeKindOptions { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + self.f.then(|| write!(f, "f")).transpose()?; + self.s.then(|| write!(f, "s")).transpose()?; + self.u.then(|| write!(f, "u")).transpose().map(|_| ()) + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum BaseTypeKind { + Float, + Int, + UInt, + Bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub enum BaseType { + Sized(BaseTypeKind, u32), + Unsized(BaseTypeKind), +} + +#[derive( + Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash, SerializeDisplay, DeserializeFromStr, +)] +pub enum VectorTupleSize { + Two, + Three, + Four, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] +pub struct VectorType { + base_type: BaseType, + lanes: u32, + is_scalable: bool, + tuple_size: Option, +} + +#[derive(Debug, Clone, PartialEq, Eq, Hash, SerializeDisplay, DeserializeFromStr)] +pub enum TypeKind { + Vector(VectorType), + Base(BaseType), + Pointer(Box, AccessLevel), + Custom(String), + Wildcard(Wildcard), +} + +impl TypeKind { + pub fn base_type(&self) -> Option<&BaseType> { + match self { + Self::Vector(t) => Some(t.base_type()), + Self::Pointer(t, _) => t.base_type(), + Self::Base(t) => Some(t), + Self::Wildcard(..) => None, + Self::Custom(..) => None, + } + } + + pub fn base_type_mut(&mut self) -> Option<&mut BaseType> { + match self { + Self::Vector(t) => Some(t.base_type_mut()), + Self::Pointer(t, _) => t.base_type_mut(), + Self::Base(t) => Some(t), + Self::Wildcard(..) => None, + Self::Custom(..) => None, + } + } + + pub fn populate_wildcard(&mut self, type_kind: TypeKind) -> context::Result { + match self { + Self::Wildcard(..) => *self = type_kind, + Self::Pointer(t, _) => t.populate_wildcard(type_kind)?, + _ => return Err("no wildcard available to populate".to_string()), + } + Ok(()) + } + + pub fn base(&self) -> Option<&BaseType> { + match self { + Self::Base(ty) => Some(ty), + Self::Pointer(tk, _) => tk.base(), + _ => None, + } + } + + pub fn vector(&self) -> Option<&VectorType> { + match self { + Self::Vector(ty) => Some(ty), + _ => None, + } + } + + pub fn vector_mut(&mut self) -> Option<&mut VectorType> { + match self { + Self::Vector(ty) => Some(ty), + _ => None, + } + } + + pub fn wildcard(&self) -> Option<&Wildcard> { + match self { + Self::Wildcard(w) => Some(w), + Self::Pointer(w, _) => w.wildcard(), + _ => None, + } + } + + pub fn make_predicate_from(ty: &TypeKind) -> context::Result { + Ok(TypeKind::Vector(VectorType::make_predicate_from_bitsize( + ty.base_type() + .ok_or_else(|| format!("cannot infer predicate from type {ty}"))? + .get_size() + .map_err(|_| format!("cannot infer predicate from unsized type {ty}"))?, + ))) + } + + pub fn make_vector( + from: TypeKind, + is_scalable: bool, + tuple_size: Option, + ) -> context::Result { + from.base().cloned().map_or_else( + || Err(format!("cannot make a vector type out of {from}!")), + |base| { + let vt = VectorType::make_from_base(base, is_scalable, tuple_size); + Ok(TypeKind::Vector(vt)) + }, + ) + } + + /// Return a new expression that converts the provided `expr` from type `other` to `self`. + /// + /// Conversions are bitwise over the whole value, like `transmute`, though `transmute` + /// itself is only used as a last resort. + /// + /// This can fail (returning `None`) due to incompatible types, and many conversions are simply + /// unimplemented. + pub fn express_reinterpretation_from( + &self, + other: &TypeKind, + expr: impl Into, + ) -> Option { + if self == other { + Some(expr.into()) + } else if let (Some(self_vty), Some(other_vty)) = (self.vector(), other.vector()) { + if self_vty.is_scalable + && self_vty.tuple_size.is_none() + && other_vty.is_scalable + && other_vty.tuple_size.is_none() + { + // Plain scalable vectors. + use BaseTypeKind::*; + match (self_vty.base_type, other_vty.base_type) { + (BaseType::Sized(Int, self_size), BaseType::Sized(UInt, other_size)) + if self_size == other_size => + { + Some(Expression::MethodCall( + Box::new(expr.into()), + "as_signed".parse().unwrap(), + vec![], + )) + } + (BaseType::Sized(UInt, self_size), BaseType::Sized(Int, other_size)) + if self_size == other_size => + { + Some(Expression::MethodCall( + Box::new(expr.into()), + "as_unsigned".parse().unwrap(), + vec![], + )) + } + ( + BaseType::Sized(Float | Int | UInt, _), + BaseType::Sized(Float | Int | UInt, _), + ) => Some(FnCall::new_expression( + // Conversions between float and (u)int, or where the lane size changes. + "simd_reinterpret".parse().unwrap(), + vec![expr.into()], + )), + _ => None, + } + } else { + // Tuples and fixed-width vectors. + None + } + } else { + // Scalar types. + None + } + } +} + +impl FromStr for TypeKind { + type Err = String; + + fn from_str(s: &str) -> Result { + Ok(match s { + s if s.starts_with('{') && s.ends_with('}') => { + Self::Wildcard(s[1..s.len() - 1].trim().parse()?) + } + s if s.starts_with('*') => { + let mut split = s[1..].split_whitespace(); + let (ty, rw) = match (split.clone().count(), split.next(), split.next()) { + (2, Some("mut"), Some(ty)) => (ty, AccessLevel::RW), + (2, Some("const"), Some(ty)) => (ty, AccessLevel::R), + (1, Some(ty), None) => (ty, AccessLevel::R), + _ => return Err(format!("invalid pointer type {s:#?} given")), + }; + Self::Pointer(Box::new(ty.parse()?), rw) + } + _ => s + .parse::() + .map(TypeKind::Vector) + .or_else(|_| s.parse::().map(TypeKind::Base)) + .unwrap_or_else(|_| TypeKind::Custom(s.to_string())), + }) + } +} + +impl fmt::Display for TypeKind { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Vector(ty) => write!(f, "{ty}"), + Self::Pointer(ty, _) => write!(f, "{ty}"), + Self::Base(ty) => write!(f, "{ty}"), + Self::Wildcard(w) => write!(f, "{{{w}}}"), + Self::Custom(s) => write!(f, "{s}"), + } + } +} + +impl ToRepr for TypeKind { + fn repr(&self, repr: TypeRepr) -> String { + match self { + Self::Vector(ty) => ty.repr(repr), + Self::Pointer(ty, _) => ty.repr(repr), + Self::Base(ty) => ty.repr(repr), + Self::Wildcard(w) => format!("{w}"), + Self::Custom(s) => s.to_string(), + } + } +} + +impl ToTokens for TypeKind { + fn to_tokens(&self, tokens: &mut TokenStream) { + if let Self::Pointer(_, rw) = self { + tokens.append_all(match rw { + AccessLevel::RW => quote! { *mut }, + AccessLevel::R => quote! { *const }, + }) + } + + tokens.append_all( + self.to_string() + .parse::() + .expect("invalid syntax"), + ) + } +} + +impl PartialOrd for TypeKind { + fn partial_cmp(&self, other: &Self) -> Option { + Some(self.cmp(other)) + } +} + +impl Ord for TypeKind { + fn cmp(&self, other: &Self) -> std::cmp::Ordering { + use std::cmp::Ordering::*; + + impl From<&TypeKind> for usize { + fn from(ty: &TypeKind) -> Self { + match ty { + TypeKind::Base(_) => 1, + TypeKind::Pointer(_, _) => 2, + TypeKind::Vector(_) => 3, + TypeKind::Custom(_) => 4, + TypeKind::Wildcard(_) => 5, + } + } + } + + let self_int: usize = self.into(); + let other_int: usize = other.into(); + + if self_int == other_int { + match (self, other) { + (TypeKind::Base(ty1), TypeKind::Base(ty2)) => ty1.cmp(ty2), + (TypeKind::Pointer(ty1, _), TypeKind::Pointer(ty2, _)) => ty1.cmp(ty2), + (TypeKind::Vector(vt1), TypeKind::Vector(vt2)) => vt1.cmp(vt2), + (TypeKind::Custom(s1), TypeKind::Custom(s2)) => s1.cmp(s2), + (TypeKind::Wildcard(..), TypeKind::Wildcard(..)) => Equal, + _ => unreachable!(), + } + } else { + self_int.cmp(&other_int) + } + } +} + +impl VectorType { + pub fn base_type(&self) -> &BaseType { + &self.base_type + } + + pub fn base_type_mut(&mut self) -> &mut BaseType { + &mut self.base_type + } + + fn sanitise_lanes( + mut base_type: BaseType, + lanes: Option, + ) -> Result<(BaseType, u32), String> { + let lanes = match (base_type, lanes) { + (BaseType::Sized(BaseTypeKind::Bool, lanes), None) => { + base_type = BaseType::Sized(BaseTypeKind::Bool, VECTOR_FULL_REGISTER_SIZE / lanes); + lanes + } + (BaseType::Unsized(BaseTypeKind::Bool), None) => { + base_type = BaseType::Sized(BaseTypeKind::Bool, 8); + 16 + } + (BaseType::Sized(_, size), None) => VECTOR_FULL_REGISTER_SIZE / size, + (BaseType::Sized(_, size), Some(lanes)) => match size * lanes { + VECTOR_FULL_REGISTER_SIZE | VECTOR_HALF_REGISTER_SIZE => lanes, + _ => return Err("invalid number of lanes".to_string()), + }, + _ => return Err("cannot infer number of lanes".to_string()), + }; + + Ok((base_type, lanes)) + } + + pub fn make_from_base( + base_ty: BaseType, + is_scalable: bool, + tuple_size: Option, + ) -> VectorType { + if is_scalable { + if let BaseType::Sized(BaseTypeKind::Bool, size) = base_ty { + return Self::make_predicate_from_bitsize(size); + } + } + + let (base_type, lanes) = Self::sanitise_lanes(base_ty, None).unwrap(); + + VectorType { + base_type, + lanes, + is_scalable, + tuple_size, + } + } + + pub fn make_predicate_from_bitsize(size: u32) -> VectorType { + VectorType { + base_type: BaseType::Sized(BaseTypeKind::Bool, size), + lanes: (VECTOR_FULL_REGISTER_SIZE / size), + is_scalable: true, + tuple_size: None, + } + } + + pub fn cast_base_type_as(&mut self, ty: BaseType) { + self.base_type = ty + } +} + +impl FromStr for VectorType { + type Err = String; + + fn from_str(s: &str) -> Result { + lazy_static! { + static ref RE: Regex = Regex::new(r"^(?:(?:sv(?P(?:uint|int|bool|float)(?:\d+)?))|(?:(?P(?:uint|int|bool|float)(?:\d+)?)x(?P[0-9])))(?:x(?P2|3|4))?_t$").unwrap(); + } + + if let Some(c) = RE.captures(s) { + let (base_type, lanes) = Self::sanitise_lanes( + c.name("sv_ty") + .or_else(|| c.name("ty")) + .map(<&str>::from) + .map(BaseType::from_str) + .unwrap()?, + c.name("lanes") + .map(<&str>::from) + .map(u32::from_str) + .transpose() + .unwrap(), + ) + .map_err(|e| format!("invalid {s:#?} vector type: {e}"))?; + + let tuple_size = c + .name("tuple_size") + .map(<&str>::from) + .map(VectorTupleSize::from_str) + .transpose() + .unwrap(); + + Ok(VectorType { + base_type, + is_scalable: c.name("sv_ty").is_some(), + lanes, + tuple_size, + }) + } else { + Err(format!("invalid vector type {s:#?} given")) + } + } +} + +impl ToRepr for VectorType { + fn repr(&self, repr: TypeRepr) -> String { + let make_llvm_repr = |show_unsigned| { + format!( + "{}v{}{}", + if self.is_scalable { "nx" } else { "" }, + self.lanes * (self.tuple_size.map(usize::from).unwrap_or(1) as u32), + match self.base_type { + BaseType::Sized(BaseTypeKind::UInt, size) if show_unsigned => + format!("u{size}"), + _ => self.base_type.llvm_machine_repr(), + } + ) + }; + + if matches!(repr, TypeRepr::ACLENotation) { + self.base_type.acle_notation_repr() + } else if matches!(repr, TypeRepr::LLVMMachine) { + make_llvm_repr(false) + } else if self.is_scalable { + match (self.base_type, self.lanes, self.tuple_size) { + (BaseType::Sized(BaseTypeKind::Bool, _), 16, _) => "svbool_t".to_string(), + (BaseType::Sized(BaseTypeKind::Bool, _), lanes, _) => format!("svbool{lanes}_t"), + (BaseType::Sized(_, size), lanes, _) + if VECTOR_FULL_REGISTER_SIZE != (size * lanes) => + { + // Special internal type case + make_llvm_repr(true) + } + (ty, _, None) => format!("sv{}_t", ty.c_repr()), + (ty, _, Some(tuple_size)) => format!("sv{}x{tuple_size}_t", ty.c_repr()), + } + } else { + match self.tuple_size { + Some(tuple_size) => format!( + "{}x{}x{}_t", + self.base_type.c_repr(), + self.lanes, + tuple_size + ), + None => format!("{}x{}_t", self.base_type.c_repr(), self.lanes), + } + } + } +} + +impl fmt::Display for VectorType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}", self.c_repr()) + } +} + +impl From for usize { + fn from(t: VectorTupleSize) -> Self { + match t { + VectorTupleSize::Two => 2, + VectorTupleSize::Three => 3, + VectorTupleSize::Four => 4, + } + } +} + +impl FromStr for VectorTupleSize { + type Err = String; + + fn from_str(s: &str) -> Result { + match s { + "2" => Ok(Self::Two), + "3" => Ok(Self::Three), + "4" => Ok(Self::Four), + _ => Err(format!("invalid vector tuple size `{s}` provided")), + } + } +} + +impl TryFrom for VectorTupleSize { + type Error = String; + + fn try_from(value: usize) -> Result { + match value { + 2 => Ok(Self::Two), + 3 => Ok(Self::Three), + 4 => Ok(Self::Four), + _ => Err(format!("invalid vector tuple size `{value}` provided")), + } + } +} + +impl fmt::Display for VectorTupleSize { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}", usize::from(*self)) + } +} + +impl FromStr for BaseTypeKind { + type Err = String; + + fn from_str(s: &str) -> Result { + match s { + "float" | "f" => Ok(Self::Float), + "int" | "i" => Ok(Self::Int), + "uint" | "u" => Ok(Self::UInt), + "bool" | "b" => Ok(Self::Bool), + _ => Err(format!("no match for {s}")), + } + } +} + +impl ToRepr for BaseTypeKind { + fn repr(&self, repr: TypeRepr) -> String { + match (repr, self) { + (TypeRepr::C, Self::Float) => "float", + (TypeRepr::C, Self::Int) => "int", + (TypeRepr::C, Self::UInt) => "uint", + (TypeRepr::Rust | TypeRepr::LLVMMachine | TypeRepr::ACLENotation, Self::Float) => "f", + (TypeRepr::Rust, Self::Int) | (TypeRepr::LLVMMachine, Self::Int | Self::UInt) => "i", + (TypeRepr::Rust | TypeRepr::ACLENotation, Self::UInt) => "u", + (TypeRepr::ACLENotation, Self::Int) => "s", + (TypeRepr::ACLENotation, Self::Bool) => "b", + (_, Self::Bool) => "bool", + _ => { + unreachable!("no base type kind available for representation {repr:?}") + } + } + .to_string() + } +} + +impl fmt::Display for BaseTypeKind { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}", self.c_repr()) + } +} + +impl BaseType { + pub fn get_size(&self) -> Result { + match self { + Self::Sized(_, size) => Ok(*size), + _ => Err(format!("unexpected invalid base type given {self:#?}")), + } + } + + pub fn kind(&self) -> &BaseTypeKind { + match self { + BaseType::Sized(kind, _) | BaseType::Unsized(kind) => kind, + } + } + + pub fn is_bool(&self) -> bool { + self.kind() == &BaseTypeKind::Bool + } + + pub fn is_float(&self) -> bool { + self.kind() == &BaseTypeKind::Float + } +} + +impl FromStr for BaseType { + type Err = String; + + fn from_str(s: &str) -> Result { + lazy_static! { + static ref RE: Regex = Regex::new(r"^(?P[a-zA-Z]+)(?P\d+)?(_t)?$").unwrap(); + } + + if let Some(c) = RE.captures(s) { + let kind = c["kind"].parse()?; + let size = c + .name("size") + .map(<&str>::from) + .map(u32::from_str) + .transpose() + .unwrap(); + + match size { + Some(size) => Ok(Self::Sized(kind, size)), + None => Ok(Self::Unsized(kind)), + } + } else { + Err(format!("failed to parse type `{s}`")) + } + } +} + +impl ToRepr for BaseType { + fn repr(&self, repr: TypeRepr) -> String { + use BaseType::*; + use BaseTypeKind::*; + use TypeRepr::*; + match (self, &repr) { + (Sized(Bool, _) | Unsized(Bool), LLVMMachine) => "i1".to_string(), + (Sized(_, size), SizeLiteral) if *size == 8 => "b".to_string(), + (Sized(_, size), SizeLiteral) if *size == 16 => "h".to_string(), + (Sized(_, size), SizeLiteral) if *size == 32 => "w".to_string(), + (Sized(_, size), SizeLiteral) if *size == 64 => "d".to_string(), + (_, SizeLiteral) => unreachable!("cannot represent {self:#?} as size literal"), + (Sized(Float, _) | Unsized(Float), TypeKind) => "f".to_string(), + (Sized(Int, _) | Unsized(Int), TypeKind) => "s".to_string(), + (Sized(UInt, _) | Unsized(UInt), TypeKind) => "u".to_string(), + (Sized(_, size), Size) => size.to_string(), + (Sized(_, size), SizeInBytesLog2) => { + assert!(size.is_power_of_two() && *size >= 8); + (size >> 3).trailing_zeros().to_string() + } + (Sized(kind, size), _) => format!("{}{size}", kind.repr(repr)), + (Unsized(kind), _) => kind.repr(repr), + } + } +} + +impl fmt::Display for BaseType { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!(f, "{}", self.rust_repr()) + } +} + +#[cfg(test)] +mod tests { + use crate::typekinds::*; + + #[test] + fn test_predicate() { + assert_eq!( + "svbool_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::Bool, 8), + is_scalable: true, + lanes: 16, + tuple_size: None + }) + ); + } + + #[test] + fn test_llvm_internal_predicate() { + assert_eq!( + "svbool4_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::Bool, 32), + is_scalable: true, + lanes: 4, + tuple_size: None + }) + ); + } + + #[test] + fn test_llvm_internal_predicate_llvm() { + assert_eq!( + "svbool4_t".parse::().unwrap().llvm_machine_repr(), + "nxv4i1" + ); + } + + #[test] + fn test_llvm_internal_predicate_acle() { + assert_eq!( + "svbool4_t" + .parse::() + .unwrap() + .acle_notation_repr(), + "b32" + ); + } + + #[test] + fn test_predicate_from_bitsize() { + let pg = VectorType::make_predicate_from_bitsize(32); + assert_eq!(pg.acle_notation_repr(), "b32"); + assert_eq!(pg, "svbool4_t".parse().unwrap()); + assert_eq!(pg.lanes, 4); + assert_eq!(pg.base_type, BaseType::Sized(BaseTypeKind::Bool, 32)); + } + + #[test] + fn test_scalable_single() { + assert_eq!( + "svuint8_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 8), + is_scalable: true, + lanes: 16, + tuple_size: None + }) + ); + } + + #[test] + fn test_scalable_tuple() { + assert_eq!( + "svint64x3_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::Int, 64), + is_scalable: true, + lanes: 2, + tuple_size: Some(VectorTupleSize::Three), + }) + ); + } + + #[test] + fn test_scalable_single_llvm() { + assert_eq!( + "svuint32_t" + .parse::() + .unwrap() + .llvm_machine_repr(), + "nxv4i32" + ); + } + + #[test] + fn test_scalable_tuple_llvm() { + assert_eq!( + "svint32x4_t" + .parse::() + .unwrap() + .llvm_machine_repr(), + "nxv16i32" + ); + } + + #[test] + fn test_vector_single_full() { + assert_eq!( + "uint32x4_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 32), + is_scalable: false, + lanes: 4, + tuple_size: None, + }) + ); + } + + #[test] + fn test_vector_single_half() { + assert_eq!( + "uint32x2_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 32), + is_scalable: false, + lanes: 2, + tuple_size: None, + }) + ); + } + + #[test] + fn test_vector_tuple() { + assert_eq!( + "uint64x2x4_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 64), + is_scalable: false, + lanes: 2, + tuple_size: Some(VectorTupleSize::Four), + }) + ); + } + + #[test] + fn test_const_pointer() { + let p = "*u32".parse::().unwrap(); + assert_eq!( + p, + TypeKind::Pointer( + Box::new(TypeKind::Base(BaseType::Sized(BaseTypeKind::UInt, 32))), + AccessLevel::R + ) + ); + assert_eq!(p.to_token_stream().to_string(), "* const u32") + } + + #[test] + fn test_mut_pointer() { + let p = "*mut u32".parse::().unwrap(); + assert_eq!( + p, + TypeKind::Pointer( + Box::new(TypeKind::Base(BaseType::Sized(BaseTypeKind::UInt, 32))), + AccessLevel::RW + ) + ); + assert_eq!(p.to_token_stream().to_string(), "* mut u32") + } + + #[test] + #[should_panic] + fn test_invalid_vector_single() { + assert_eq!( + "uint32x8_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 32), + is_scalable: false, + lanes: 8, + tuple_size: None, + }) + ); + } + + #[test] + #[should_panic] + fn test_invalid_vector_tuple() { + assert_eq!( + "uint32x4x5_t".parse::().unwrap(), + TypeKind::Vector(VectorType { + base_type: BaseType::Sized(BaseTypeKind::UInt, 32), + is_scalable: false, + lanes: 8, + tuple_size: None, // cannot represent + }) + ); + } + + #[test] + fn test_base() { + assert_eq!( + "u32".parse::().unwrap(), + TypeKind::Base(BaseType::Sized(BaseTypeKind::UInt, 32)), + ) + } + + #[test] + fn test_custom() { + assert_eq!( + "svpattern".parse::().unwrap(), + TypeKind::Custom("svpattern".to_string()), + ) + } + + #[test] + fn test_wildcard_type() { + assert_eq!( + "{type}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::Type(None)), + ) + } + + #[test] + fn test_wildcard_typeset() { + assert_eq!( + "{type[0]}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::Type(Some(0))), + ) + } + + #[test] + fn test_wildcard_sve_type() { + assert_eq!( + "{sve_type}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::SVEType(None, None)), + ) + } + + #[test] + fn test_wildcard_sve_typeset() { + assert_eq!( + "{sve_type[0]}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::SVEType(Some(0), None)), + ) + } + + #[test] + fn test_wildcard_sve_tuple_type() { + assert_eq!( + "{sve_type_x2}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::SVEType(None, Some(VectorTupleSize::Two))), + ) + } + + #[test] + fn test_wildcard_sve_tuple_typeset() { + assert_eq!( + "{sve_type_x2[0]}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::SVEType(Some(0), Some(VectorTupleSize::Two))), + ) + } + + #[test] + fn test_wildcard_predicate() { + assert_eq!( + "{predicate}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::Predicate(None)) + ) + } + + #[test] + fn test_wildcard_scale() { + assert_eq!( + "{sve_type as i8}".parse::().unwrap(), + TypeKind::Wildcard(Wildcard::Scale( + Box::new(Wildcard::SVEType(None, None)), + Box::new(TypeKind::Base(BaseType::Sized(BaseTypeKind::Int, 8))) + )) + ) + } + + #[test] + fn test_size_in_bytes_log2() { + assert_eq!("i8".parse::().unwrap().size_in_bytes_log2(), "0"); + assert_eq!("i16".parse::().unwrap().size_in_bytes_log2(), "1"); + assert_eq!("i32".parse::().unwrap().size_in_bytes_log2(), "2"); + assert_eq!("i64".parse::().unwrap().size_in_bytes_log2(), "3") + } + + #[test] + #[should_panic] + fn test_invalid_size_in_bytes_log2() { + "i9".parse::().unwrap().size_in_bytes_log2(); + } +} diff --git a/crates/stdarch-gen2/src/wildcards.rs b/crates/stdarch-gen2/src/wildcards.rs new file mode 100644 index 0000000000..9d6194d517 --- /dev/null +++ b/crates/stdarch-gen2/src/wildcards.rs @@ -0,0 +1,179 @@ +use lazy_static::lazy_static; +use regex::Regex; +use serde_with::{DeserializeFromStr, SerializeDisplay}; +use std::fmt; +use std::str::FromStr; + +use crate::{ + predicate_forms::PredicationMask, + typekinds::{ToRepr, TypeKind, TypeKindOptions, VectorTupleSize}, +}; + +#[derive(Debug, Clone, PartialEq, Eq, Hash, SerializeDisplay, DeserializeFromStr)] +pub enum Wildcard { + Type(Option), + /// NEON type derivated by a base type + NEONType(Option, Option), + /// SVE type derivated by a base type + SVEType(Option, Option), + /// Integer representation of bitsize + Size(Option), + /// Integer representation of bitsize minus one + SizeMinusOne(Option), + /// Literal representation of the bitsize: b(yte), h(half), w(ord) or d(ouble) + SizeLiteral(Option), + /// Literal representation of the type kind: f(loat), s(igned), u(nsigned) + TypeKind(Option, Option), + /// Log2 of the size in bytes + SizeInBytesLog2(Option), + /// Predicate to be inferred from the specified type + Predicate(Option), + /// Predicate to be inferred from the greatest type + MaxPredicate, + + Scale(Box, Box), + + // Other wildcards + LLVMLink, + NVariant, + /// Predicate forms to use and placeholder for a predicate form function name modifier + PredicateForms(PredicationMask), + + /// User-set wildcard through `substitutions` + Custom(String), +} + +impl Wildcard { + pub fn is_nonpredicate_type(&self) -> bool { + matches!( + self, + Wildcard::Type(..) | Wildcard::NEONType(..) | Wildcard::SVEType(..) + ) + } + + pub fn get_typeset_index(&self) -> Option { + match self { + Wildcard::Type(idx) | Wildcard::NEONType(idx, ..) | Wildcard::SVEType(idx, ..) => { + Some(idx.unwrap_or(0)) + } + _ => None, + } + } +} + +impl FromStr for Wildcard { + type Err = String; + + fn from_str(s: &str) -> Result { + lazy_static! { + static ref RE: Regex = Regex::new(r"^(?P\w+?)(?:_x(?P[2-4]))?(?:\[(?P\d+)\])?(?:\.(?P\w+))?(?:\s+as\s+(?P.*?))?$").unwrap(); + } + + if let Some(c) = RE.captures(s) { + let wildcard_name = &c["wildcard"]; + let inputset_index = c + .name("index") + .map(<&str>::from) + .map(usize::from_str) + .transpose() + .map_err(|_| format!("{:#?} is not a valid type index", &c["index"]))?; + let tuple_size = c + .name("tuple_size") + .map(<&str>::from) + .map(VectorTupleSize::from_str) + .transpose() + .map_err(|_| format!("{:#?} is not a valid tuple size", &c["tuple_size"]))?; + let modifiers = c.name("modifiers").map(<&str>::from); + + let wildcard = match (wildcard_name, inputset_index, tuple_size, modifiers) { + ("type", index, None, None) => Ok(Wildcard::Type(index)), + ("neon_type", index, tuple, None) => Ok(Wildcard::NEONType(index, tuple)), + ("sve_type", index, tuple, None) => Ok(Wildcard::SVEType(index, tuple)), + ("size", index, None, None) => Ok(Wildcard::Size(index)), + ("size_minus_one", index, None, None) => Ok(Wildcard::SizeMinusOne(index)), + ("size_literal", index, None, None) => Ok(Wildcard::SizeLiteral(index)), + ("type_kind", index, None, modifiers) => Ok(Wildcard::TypeKind( + index, + modifiers.map(|modifiers| modifiers.parse()).transpose()?, + )), + ("size_in_bytes_log2", index, None, None) => Ok(Wildcard::SizeInBytesLog2(index)), + ("predicate", index, None, None) => Ok(Wildcard::Predicate(index)), + ("max_predicate", None, None, None) => Ok(Wildcard::MaxPredicate), + ("llvm_link", None, None, None) => Ok(Wildcard::LLVMLink), + ("_n", None, None, None) => Ok(Wildcard::NVariant), + (w, None, None, None) if w.starts_with('_') => { + // test for predicate forms + let pf_mask = PredicationMask::from_str(&w[1..]); + if let Ok(mask) = pf_mask { + if mask.has_merging() { + Ok(Wildcard::PredicateForms(mask)) + } else { + Err("cannot add predication without a Merging form".to_string()) + } + } else { + Err(format!("invalid wildcard `{s:#?}`")) + } + } + (cw, None, None, None) => Ok(Wildcard::Custom(cw.to_string())), + _ => Err(format!("invalid wildcard `{s:#?}`")), + }?; + + let scale_to = c + .name("scale_to") + .map(<&str>::from) + .map(TypeKind::from_str) + .transpose() + .map_err(|_| format!("{:#?} is not a valid type", &c["scale_to"]))?; + + if let Some(scale_to) = scale_to { + Ok(Wildcard::Scale(Box::new(wildcard), Box::new(scale_to))) + } else { + Ok(wildcard) + } + } else { + Err(format!("invalid wildcard `{s:#?}`")) + } + } +} + +impl fmt::Display for Wildcard { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + match self { + Self::Type(None) => write!(f, "type"), + Self::Type(Some(index)) => write!(f, "type[{index}]"), + Self::NEONType(None, None) => write!(f, "neon_type"), + Self::NEONType(Some(index), None) => write!(f, "neon_type[{index}]"), + Self::NEONType(None, Some(tuple_size)) => write!(f, "neon_type_x{tuple_size}"), + Self::NEONType(Some(index), Some(tuple_size)) => { + write!(f, "neon_type_x{tuple_size}[{index}]") + } + Self::SVEType(None, None) => write!(f, "sve_type"), + Self::SVEType(Some(index), None) => write!(f, "sve_type[{index}]"), + Self::SVEType(None, Some(tuple_size)) => write!(f, "sve_type_x{tuple_size}"), + Self::SVEType(Some(index), Some(tuple_size)) => { + write!(f, "sve_type_x{tuple_size}[{index}]") + } + Self::Size(None) => write!(f, "size"), + Self::Size(Some(index)) => write!(f, "size[{index}]"), + Self::SizeMinusOne(None) => write!(f, "size_minus_one"), + Self::SizeMinusOne(Some(index)) => write!(f, "size_minus_one[{index}]"), + Self::SizeLiteral(None) => write!(f, "size_literal"), + Self::SizeLiteral(Some(index)) => write!(f, "size_literal[{index}]"), + Self::TypeKind(None, None) => write!(f, "type_kind"), + Self::TypeKind(None, Some(opts)) => write!(f, "type_kind.{opts}"), + Self::TypeKind(Some(index), None) => write!(f, "type_kind[{index}]"), + Self::TypeKind(Some(index), Some(opts)) => write!(f, "type_kind[{index}].{opts}"), + Self::SizeInBytesLog2(None) => write!(f, "size_in_bytes_log2"), + Self::SizeInBytesLog2(Some(index)) => write!(f, "size_in_bytes_log2[{index}]"), + Self::Predicate(None) => write!(f, "predicate"), + Self::Predicate(Some(index)) => write!(f, "predicate[{index}]"), + Self::MaxPredicate => write!(f, "max_predicate"), + Self::LLVMLink => write!(f, "llvm_link"), + Self::NVariant => write!(f, "_n"), + Self::PredicateForms(mask) => write!(f, "_{mask}"), + + Self::Scale(wildcard, ty) => write!(f, "{wildcard} as {}", ty.rust_repr()), + Self::Custom(cw) => write!(f, "{cw}"), + } + } +} diff --git a/crates/stdarch-gen2/src/wildstring.rs b/crates/stdarch-gen2/src/wildstring.rs new file mode 100644 index 0000000000..1f9e6c9ada --- /dev/null +++ b/crates/stdarch-gen2/src/wildstring.rs @@ -0,0 +1,353 @@ +use itertools::Itertools; +use proc_macro2::TokenStream; +use quote::{quote, ToTokens, TokenStreamExt}; +use serde_with::{DeserializeFromStr, SerializeDisplay}; +use std::str::pattern::Pattern; +use std::{fmt, str::FromStr}; + +use crate::context::LocalContext; +use crate::typekinds::{ToRepr, TypeRepr}; +use crate::wildcards::Wildcard; + +#[derive(Debug, Clone, PartialEq, Eq)] +pub enum WildStringPart { + String(String), + Wildcard(Wildcard), +} + +/// Wildcard-able string +#[derive(Debug, Clone, PartialEq, Eq, Default, SerializeDisplay, DeserializeFromStr)] +pub struct WildString(Vec); + +impl WildString { + pub fn has_wildcards(&self) -> bool { + for part in self.0.iter() { + if let WildStringPart::Wildcard(..) = part { + return true; + } + } + + false + } + + pub fn wildcards(&self) -> impl Iterator + '_ { + self.0.iter().filter_map(|part| match part { + WildStringPart::Wildcard(w) => Some(w), + _ => None, + }) + } + + pub fn iter(&self) -> impl Iterator + '_ { + self.0.iter() + } + + pub fn iter_mut(&mut self) -> impl Iterator + '_ { + self.0.iter_mut() + } + + pub fn starts_with(&self, s2: &str) -> bool { + self.to_string().starts_with(s2) + } + + pub fn prepend_str(&mut self, s: impl Into) { + self.0.insert(0, WildStringPart::String(s.into())) + } + + pub fn push_str(&mut self, s: impl Into) { + self.0.push(WildStringPart::String(s.into())) + } + + pub fn push_wildcard(&mut self, w: Wildcard) { + self.0.push(WildStringPart::Wildcard(w)) + } + + pub fn is_empty(&self) -> bool { + self.0.is_empty() + } + + pub fn replace<'a, P>(&'a self, from: P, to: &str) -> WildString + where + P: Pattern<'a> + Copy, + { + WildString( + self.0 + .iter() + .map(|part| match part { + WildStringPart::String(s) => WildStringPart::String(s.replace(from, to)), + part => part.clone(), + }) + .collect_vec(), + ) + } + + pub fn build_acle(&mut self, ctx: &LocalContext) -> Result<(), String> { + self.build(ctx, TypeRepr::ACLENotation) + } + + pub fn build(&mut self, ctx: &LocalContext, repr: TypeRepr) -> Result<(), String> { + self.iter_mut().try_for_each(|wp| -> Result<(), String> { + if let WildStringPart::Wildcard(w) = wp { + let value = ctx + .provide_substitution_wildcard(w) + .or_else(|_| ctx.provide_type_wildcard(w).map(|ty| ty.repr(repr)))?; + *wp = WildStringPart::String(value); + } + Ok(()) + }) + } +} + +impl From for WildString { + fn from(s: String) -> Self { + WildString(vec![WildStringPart::String(s)]) + } +} + +impl FromStr for WildString { + type Err = String; + + fn from_str(s: &str) -> Result { + enum State { + Normal { start: usize }, + Wildcard { start: usize, count: usize }, + EscapeTokenOpen { start: usize, at: usize }, + EscapeTokenClose { start: usize, at: usize }, + } + + let mut ws = WildString::default(); + match s + .char_indices() + .try_fold(State::Normal { start: 0 }, |state, (idx, ch)| { + match (state, ch) { + (State::Normal { start }, '{') => Ok(State::EscapeTokenOpen { start, at: idx }), + (State::Normal { start }, '}') => { + Ok(State::EscapeTokenClose { start, at: idx }) + } + (State::EscapeTokenOpen { start, at }, '{') + | (State::EscapeTokenClose { start, at }, '}') => { + if start < at { + ws.push_str(&s[start..at]) + } + + Ok(State::Normal { start: idx }) + } + (State::EscapeTokenOpen { at, .. }, '}') => Err(format!( + "empty wildcard given in string {s:?} at position {at}" + )), + (State::EscapeTokenOpen { start, at }, _) => { + if start < at { + ws.push_str(&s[start..at]) + } + + Ok(State::Wildcard { + start: idx, + count: 0, + }) + } + (State::EscapeTokenClose { at, .. }, _) => Err(format!( + "closing a non-wildcard/bad escape in string {s:?} at position {at}" + )), + // Nesting wildcards is only supported for `{foo as {bar}}`, wildcards cannot be + // nested at the start of a WildString. + (State::Wildcard { start, count }, '{') => Ok(State::Wildcard { + start, + count: count + 1, + }), + (State::Wildcard { start, count: 0 }, '}') => { + ws.push_wildcard(s[start..idx].parse()?); + Ok(State::Normal { start: idx + 1 }) + } + (State::Wildcard { start, count }, '}') => Ok(State::Wildcard { + start, + count: count - 1, + }), + (state @ State::Normal { .. }, _) | (state @ State::Wildcard { .. }, _) => { + Ok(state) + } + } + })? { + State::Normal { start } => { + if start < s.len() { + ws.push_str(&s[start..]); + } + + Ok(ws) + } + State::EscapeTokenOpen { at, .. } | State::Wildcard { start: at, .. } => Err(format!( + "unclosed wildcard in string {s:?} at position {at}" + )), + State::EscapeTokenClose { at, .. } => Err(format!( + "closing a non-wildcard/bad escape in string {s:?} at position {at}" + )), + } + } +} + +impl fmt::Display for WildString { + fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { + write!( + f, + "{}", + self.0 + .iter() + .map(|part| match part { + WildStringPart::String(s) => s.to_owned(), + WildStringPart::Wildcard(w) => format!("{{{w}}}"), + }) + .join("") + ) + } +} + +impl ToTokens for WildString { + fn to_tokens(&self, tokens: &mut TokenStream) { + assert!( + !self.has_wildcards(), + "cannot convert string with wildcards {self:?} to TokenStream" + ); + let str = self.to_string(); + tokens.append_all(quote! { #str }) + } +} + +#[cfg(test)] +mod tests { + use crate::typekinds::*; + use crate::wildstring::*; + + #[test] + fn test_empty_string() { + let ws: WildString = "".parse().unwrap(); + assert_eq!(ws.0.len(), 0); + } + + #[test] + fn test_plain_string() { + let ws: WildString = "plain string".parse().unwrap(); + assert_eq!(ws.0.len(), 1); + assert_eq!( + ws, + WildString(vec![WildStringPart::String("plain string".to_string())]) + ) + } + + #[test] + fn test_escaped_curly_brackets() { + let ws: WildString = "VALUE = {{value}}".parse().unwrap(); + assert_eq!(ws.to_string(), "VALUE = {value}"); + assert!(!ws.has_wildcards()); + } + + #[test] + fn test_escaped_curly_brackets_wildcard() { + let ws: WildString = "TYPE = {{{type}}}".parse().unwrap(); + assert_eq!(ws.to_string(), "TYPE = {{type}}"); + assert_eq!(ws.0.len(), 4); + assert!(ws.has_wildcards()); + } + + #[test] + fn test_wildcard_right_boundary() { + let s = "string test {type}"; + let ws: WildString = s.parse().unwrap(); + assert_eq!(&ws.to_string(), s); + assert!(ws.has_wildcards()); + } + + #[test] + fn test_wildcard_left_boundary() { + let s = "{type} string test"; + let ws: WildString = s.parse().unwrap(); + assert_eq!(&ws.to_string(), s); + assert!(ws.has_wildcards()); + } + + #[test] + fn test_recursive_wildcard() { + let s = "string test {type[0] as {type[1]}}"; + let ws: WildString = s.parse().unwrap(); + + assert_eq!(ws.0.len(), 2); + assert_eq!( + ws, + WildString(vec![ + WildStringPart::String("string test ".to_string()), + WildStringPart::Wildcard(Wildcard::Scale( + Box::new(Wildcard::Type(Some(0))), + Box::new(TypeKind::Wildcard(Wildcard::Type(Some(1)))), + )) + ]) + ); + } + + #[test] + fn test_scale_wildcard() { + let s = "string {type[0] as i8} test"; + let ws: WildString = s.parse().unwrap(); + + assert_eq!(ws.0.len(), 3); + assert_eq!( + ws, + WildString(vec![ + WildStringPart::String("string ".to_string()), + WildStringPart::Wildcard(Wildcard::Scale( + Box::new(Wildcard::Type(Some(0))), + Box::new(TypeKind::Base(BaseType::Sized(BaseTypeKind::Int, 8))), + )), + WildStringPart::String(" test".to_string()) + ]) + ); + } + + #[test] + fn test_solitaire_wildcard() { + let ws: WildString = "{type}".parse().unwrap(); + assert_eq!(ws.0.len(), 1); + assert_eq!( + ws, + WildString(vec![WildStringPart::Wildcard(Wildcard::Type(None))]) + ) + } + + #[test] + fn test_empty_wildcard() { + "string {}" + .parse::() + .expect_err("expected parse error"); + } + + #[test] + fn test_invalid_open_wildcard_right() { + "string {" + .parse::() + .expect_err("expected parse error"); + } + + #[test] + fn test_invalid_close_wildcard_right() { + "string }" + .parse::() + .expect_err("expected parse error"); + } + + #[test] + fn test_invalid_open_wildcard_left() { + "{string" + .parse::() + .expect_err("expected parse error"); + } + + #[test] + fn test_invalid_close_wildcard_left() { + "}string" + .parse::() + .expect_err("expected parse error"); + } + + #[test] + fn test_consecutive_wildcards() { + let s = "svprf{size_literal[1]}_gather_{type[0]}{index_or_offset}"; + let ws: WildString = s.parse().unwrap(); + assert_eq!(ws.to_string(), s) + } +} From c9789c3bf6c157eb227d1599c14913487a6f7402 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Tue, 10 Dec 2024 09:04:13 +0000 Subject: [PATCH 3/8] Generator supports creating neon instructions from YAML --- Cargo.toml | 1 - .../core_arch/src/aarch64/neon/generated.rs | 38112 ++++---- .../src/arm_shared/neon/generated.rs | 78508 ++++++++-------- crates/core_arch/src/arm_shared/neon/mod.rs | 218 + .../stdarch-gen2/spec/neon/aarch64.spec.yml | 9852 ++ .../spec/neon/arm_shared.spec.yml | 9789 ++ crates/stdarch-gen2/src/context.rs | 24 +- crates/stdarch-gen2/src/expression.rs | 44 +- crates/stdarch-gen2/src/fn_suffix.rs | 308 + crates/stdarch-gen2/src/intrinsic.rs | 196 +- crates/stdarch-gen2/src/main.rs | 42 +- crates/stdarch-gen2/src/typekinds.rs | 59 +- crates/stdarch-gen2/src/wildcards.rs | 32 +- crates/stdarch-gen2/src/wildstring.rs | 60 +- 14 files changed, 77149 insertions(+), 60096 deletions(-) create mode 100644 crates/stdarch-gen2/spec/neon/aarch64.spec.yml create mode 100644 crates/stdarch-gen2/spec/neon/arm_shared.spec.yml create mode 100644 crates/stdarch-gen2/src/fn_suffix.rs diff --git a/Cargo.toml b/Cargo.toml index 36bd4a6a03..43b6dc1ea5 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -8,7 +8,6 @@ members = [ "crates/std_detect", "crates/stdarch-gen-arm", "crates/stdarch-gen-loongarch", - "crates/stdarch-gen", "crates/stdarch-gen2", "crates/intrinsic-test", "examples/" diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index d2a906604b..08f7aecdb6 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -1,199 +1,221 @@ // This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen-arm/neon.spec` and run the following command to re-generate this file: +// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: // // ``` -// OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-arm -- crates/stdarch-gen-arm/neon.spec +// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec // ``` -use super::*; +#![allow(improper_ctypes)] + #[cfg(test)] use stdarch_test::assert_instr; -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8) +use super::*; + +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3s.v16i8")] - fn veor3q_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; - } - veor3q_s8_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] +pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: int8x8_t = vabd_s8(d, e); + let f: uint8x8_t = simd_cast(f); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16) +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3s.v8i16")] - fn veor3q_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - veor3q_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] +pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + let f: int16x4_t = vabd_s16(d, e); + let f: uint16x4_t = simd_cast(f); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32) +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3s.v4i32")] - fn veor3q_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; - } - veor3q_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] +pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); + let f: int32x2_t = vabd_s32(d, e); + let f: uint32x2_t = simd_cast(f); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3s.v2i64")] - fn veor3q_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; - } - veor3q_s64_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] +pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: uint8x8_t = vabd_u8(d, e); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3u.v16i8")] - fn veor3q_u8_(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t; - } - veor3q_u8_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] +pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + let f: uint16x4_t = vabd_u16(d, e); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3u.v8i16")] - fn veor3q_u16_(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t; - } - veor3q_u16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] +pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + let f: uint32x2_t = vabd_u32(d, e); + simd_add(a, simd_cast(f)) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32) +#[doc = "Absolute difference between the arguments of Floating"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fabd))] +pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3u.v4i32")] - fn veor3q_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fabd.v1f64" + )] + fn _vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - veor3q_u32_(a, b, c) + _vabd_f64(a, b) } -/// Three-way exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64) +#[doc = "Absolute difference between the arguments of Floating"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(eor3))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fabd))] +pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.eor3u.v2i64")] - fn veor3q_u64_(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fabd.v2f64" + )] + fn _vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - veor3q_u64_(a, b, c) + _vabdq_f64(a, b) } -/// Absolute difference between the arguments of Floating -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64) +#[doc = "Floating-point absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fabd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabd_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fabd.v1f64")] - fn vabd_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - vabd_f64_(a, b) +#[cfg_attr(test, assert_instr(fabd))] +pub unsafe fn vabdd_f64(a: f64, b: f64) -> f64 { + simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Absolute difference between the arguments of Floating -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64) +#[doc = "Floating-point absolute difference"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] #[cfg_attr(test, assert_instr(fabd))] +pub unsafe fn vabds_f32(a: f32, b: f32) -> f32 { + simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +} + +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fabd.v2f64")] - fn vabdq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vabdq_f64_(a, b) +#[cfg_attr(test, assert_instr(sabdl))] +pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let e: uint16x4_t = simd_cast(vabd_s16(c, d)); + simd_cast(e) } -/// Floating-point absolute difference -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32) +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fabd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabds_f32(a: f32, b: f32) -> f32 { - simd_extract!(vabd_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +#[cfg_attr(test, assert_instr(sabdl))] +pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let e: uint32x2_t = simd_cast(vabd_s32(c, d)); + simd_cast(e) } -/// Floating-point absolute difference -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdd_f64) +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fabd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdd_f64(a: f64, b: f64) -> f64 { - simd_extract!(vabd_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +#[cfg_attr(test, assert_instr(sabdl))] +pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let e: uint8x8_t = simd_cast(vabd_s8(c, d)); + simd_cast(e) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] @@ -204,9 +226,10 @@ pub unsafe fn vabdl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { simd_cast(vabd_u8(c, d)) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] @@ -217,9 +240,10 @@ pub unsafe fn vabdl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { simd_cast(vabd_u16(c, d)) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(uabdl))] @@ -230,1131 +254,1457 @@ pub unsafe fn vabdl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { simd_cast(vabd_u32(c, d)) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8) +#[doc = "Floating-point absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sabdl))] +#[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_cast(vabd_s8(c, d)); - simd_cast(e) +pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { + simd_fabs(a) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16) +#[doc = "Floating-point absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sabdl))] +#[cfg_attr(test, assert_instr(fabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_cast(vabd_s16(c, d)); - simd_cast(e) +pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { + simd_fabs(a) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32) +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sabdl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabdl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_cast(vabd_s32(c, d)); - simd_cast(e) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { + a.wrapping_add(b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64) +#[doc = "Add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { + a.wrapping_add(b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64) +#[doc = "Signed Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(saddlv))] +pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlv.i32.v4i16" + )] + fn _vaddlv_s16(a: int16x4_t) -> i32; + } + _vaddlv_s16(a) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64) +#[doc = "Signed Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(saddlv))] +pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlv.i32.v8i16" + )] + fn _vaddlvq_s16(a: int16x8_t) -> i32; + } + _vaddlvq_s16(a) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64) +#[doc = "Signed Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(saddlv))] +pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlv.i64.v4i32" + )] + fn _vaddlvq_s32(a: int32x4_t) -> i64; + } + _vaddlvq_s32(a) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64) +#[doc = "Signed Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(saddlp))] +pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.saddlv.i64.v2i32" + )] + fn _vaddlv_s32(a: int32x2_t) -> i64; + } + _vaddlv_s32(a) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64) +#[doc = "Unsigned Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(uaddlv))] +pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlv.i32.v4i16" + )] + fn _vaddlv_u16(a: int16x4_t) -> i32; + } + _vaddlv_u16(a.as_signed()).as_unsigned() } -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64) +#[doc = "Unsigned Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(uaddlv))] +pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlv.i32.v8i16" + )] + fn _vaddlvq_u16(a: int16x8_t) -> i32; + } + _vaddlvq_u16(a.as_signed()).as_unsigned() } -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64) +#[doc = "Unsigned Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_eq(a, b) +#[cfg_attr(test, assert_instr(uaddlv))] +pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlv.i64.v4i32" + )] + fn _vaddlvq_u32(a: int32x4_t) -> i64; + } + _vaddlvq_u32(a.as_signed()).as_unsigned() } -/// Compare bitwise equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64) +#[doc = "Unsigned Add Long across Vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_s64(a: i64, b: i64) -> u64 { - transmute(vceq_s64(transmute(a), transmute(b))) +#[cfg_attr(test, assert_instr(uaddlp))] +pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uaddlv.i64.v2i32" + )] + fn _vaddlv_u32(a: int32x2_t) -> i64; + } + _vaddlv_u32(a.as_signed()).as_unsigned() } -/// Compare bitwise equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64) +#[doc = "Floating-point add across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_u64(a: u64, b: u64) -> u64 { - transmute(vceq_u64(transmute(a), transmute(b))) +#[cfg_attr(test, assert_instr(faddp))] +pub unsafe fn vaddv_f32(a: float32x2_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddv.f32.v2f32" + )] + fn _vaddv_f32(a: float32x2_t) -> f32; + } + _vaddv_f32(a) } -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32) +#[doc = "Floating-point add across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqs_f32(a: f32, b: f32) -> u32 { - simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +#[cfg_attr(test, assert_instr(faddp))] +pub unsafe fn vaddvq_f32(a: float32x4_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddv.f32.v4f32" + )] + fn _vaddvq_f32(a: float32x4_t) -> f32; + } + _vaddvq_f32(a) } -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64) +#[doc = "Floating-point add across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) -} - -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { - let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[cfg_attr(test, assert_instr(faddp))] +pub unsafe fn vaddvq_f64(a: float64x2_t) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddv.f64.v2f64" + )] + fn _vaddvq_f64(a: float64x2_t) -> f64; + } + _vaddvq_f64(a) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { - let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxs.v16i8" + )] + fn _vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + _vbcaxq_s8(a, b, c) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { - let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxs.v8i16" + )] + fn _vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + _vbcaxq_s16(a, b, c) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { - let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxs.v4i32" + )] + fn _vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vbcaxq_s32(a, b, c) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { - let b: i32x2 = i32x2::new(0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxs.v2i64" + )] + fn _vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _vbcaxq_s64(a, b, c) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { - let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxu.v16i8" + )] + fn _vbcaxq_u8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + _vbcaxq_u8(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { - let b: i64x1 = i64x1::new(0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxu.v8i16" + )] + fn _vbcaxq_u16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + _vbcaxq_u16(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { - let b: i64x2 = i64x2::new(0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxu.v4i32" + )] + fn _vbcaxq_u32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vbcaxq_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8) +#[doc = "Bit clear and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { - let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(bcax))] +pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.bcaxu.v2i64" + )] + fn _vbcaxq_u64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _vbcaxq_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { - let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32" + )] + fn _vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vcadd_rot270_f32(a, b) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { - let b: i64x1 = i64x1::new(0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32" + )] + fn _vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vcaddq_rot270_f32(a, b) } -/// Signed compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { - let b: i64x2 = i64x2::new(0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64" + )] + fn _vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vcaddq_rot270_f64(a, b) } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { - let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32" + )] + fn _vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vcadd_rot90_f32(a, b) } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { - let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32" + )] + fn _vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vcaddq_rot90_f32(a, b) } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16) +#[doc = "Floating-point complex add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { - let b: u16x4 = u16x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcadd))] +pub unsafe fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64" + )] + fn _vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vcaddq_rot90_f64(a, b) } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { - let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_eq(a, transmute(b)) +pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.v1i64.v1f64" + )] + fn _vcage_f64(a: float64x1_t, b: float64x1_t) -> int64x1_t; + } + _vcage_f64(a, b).as_unsigned() } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { - let b: u32x2 = u32x2::new(0, 0); - simd_eq(a, transmute(b)) +pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.v2i64.v2f64" + )] + fn _vcageq_f64(a: float64x2_t, b: float64x2_t) -> int64x2_t; + } + _vcageq_f64(a, b).as_unsigned() } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { - let b: u32x4 = u32x4::new(0, 0, 0, 0); - simd_eq(a, transmute(b)) +pub unsafe fn vcaged_f64(a: f64, b: f64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.i64.f64" + )] + fn _vcaged_f64(a: f64, b: f64) -> i64; + } + _vcaged_f64(a, b).as_unsigned() } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { - let b: u64x1 = u64x1::new(0); - simd_eq(a, transmute(b)) +pub unsafe fn vcages_f32(a: f32, b: f32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.i32.f32" + )] + fn _vcages_f32(a: f32, b: f32) -> i32; + } + _vcages_f32(a, b).as_unsigned() } -/// Unsigned compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmeq))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { - let b: u64x2 = u64x2::new(0, 0); - simd_eq(a, transmute(b)) +pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.v1i64.v1f64" + )] + fn _vcagt_f64(a: float64x1_t, b: float64x1_t) -> int64x1_t; + } + _vcagt_f64(a, b).as_unsigned() } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { - let b: f32x2 = f32x2::new(0.0, 0.0); - simd_eq(a, transmute(b)) +pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.v2i64.v2f64" + )] + fn _vcagtq_f64(a: float64x2_t, b: float64x2_t) -> int64x2_t; + } + _vcagtq_f64(a, b).as_unsigned() } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { - let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_eq(a, transmute(b)) +pub unsafe fn vcagtd_f64(a: f64, b: f64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.i64.f64" + )] + fn _vcagtd_f64(a: f64, b: f64) -> i64; + } + _vcagtd_f64(a, b).as_unsigned() } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { - let b: f64 = 0.0; - simd_eq(a, transmute(b)) +pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.i32.f32" + )] + fn _vcagts_f32(a: f32, b: f32) -> i32; + } + _vcagts_f32(a, b).as_unsigned() } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmeq))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { - let b: f64x2 = f64x2::new(0.0, 0.0); - simd_eq(a, transmute(b)) +pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + vcage_f64(b, a) } -/// Compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_s64(a: i64) -> u64 { - transmute(vceqz_s64(transmute(a))) +pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + vcageq_f64(b, a) } -/// Compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_u64(a: u64) -> u64 { - transmute(vceqz_u64(transmute(a))) +pub unsafe fn vcaled_f64(a: f64, b: f64) -> u64 { + vcaged_f64(b, a) } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(facge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzs_f32(a: f32) -> u32 { - simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) +pub unsafe fn vcales_f32(a: f32, b: f32) -> u32 { + vcages_f32(b, a) } -/// Floating-point compare bitwise equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vceqzd_f64(a: f64) -> u64 { - simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) +pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + vcagt_f64(b, a) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - let c: int64x1_t = simd_and(a, b); - let d: i64x1 = i64x1::new(0); - simd_ne(c, transmute(d)) +pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + vcagtq_f64(b, a) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - let c: int64x2_t = simd_and(a, b); - let d: i64x2 = i64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub unsafe fn vcaltd_f64(a: f64, b: f64) -> u64 { + vcagtd_f64(b, a) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(facgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { - let c: poly64x1_t = simd_and(a, b); - let d: i64x1 = i64x1::new(0); - simd_ne(c, transmute(d)) +pub unsafe fn vcalts_f32(a: f32, b: f32) -> u32 { + vcagts_f32(b, a) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { - let c: poly64x2_t = simd_and(a, b); - let d: i64x2 = i64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub unsafe fn vceq_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + simd_eq(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - let c: uint64x1_t = simd_and(a, b); - let d: u64x1 = u64x1::new(0); - simd_ne(c, transmute(d)) +pub unsafe fn vceqq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + simd_eq(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmtst))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - let c: uint64x2_t = simd_and(a, b); - let d: u64x2 = u64x2::new(0, 0); - simd_ne(c, transmute(d)) +pub unsafe fn vceq_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + simd_eq(a, b) } -/// Compare bitwise test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tst))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstd_s64(a: i64, b: i64) -> u64 { - transmute(vtst_s64(transmute(a), transmute(b))) +pub unsafe fn vceqq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + simd_eq(a, b) } -/// Compare bitwise test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(tst))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtstd_u64(a: u64, b: u64) -> u64 { - transmute(vtst_u64(transmute(a), transmute(b))) +pub unsafe fn vceq_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_eq(a, b) } -/// Signed saturating accumulate of unsigned value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(suqadd))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqadds_s32(a: i32, b: u32) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.suqadd.i32")] - fn vuqadds_s32_(a: i32, b: u32) -> i32; - } - vuqadds_s32_(a, b) +pub unsafe fn vceqq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_eq(a, b) } -/// Signed saturating accumulate of unsigned value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(suqadd))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddd_s64(a: i64, b: u64) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.suqadd.i64")] - fn vuqaddd_s64_(a: i64, b: u64) -> i64; - } - vuqaddd_s64_(a, b) +pub unsafe fn vceq_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { + simd_eq(a, b) } -/// Signed saturating accumulate of unsigned value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(suqadd))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddb_s8(a: i8, b: u8) -> i8 { - simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) +pub unsafe fn vceqq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { + simd_eq(a, b) } -/// Signed saturating accumulate of unsigned value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(suqadd))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuqaddh_s16(a: i16, b: u16) -> i16 { - simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) +pub unsafe fn vceqd_f64(a: f64, b: f64) -> u64 { + simd_extract!(vceq_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Floating-point absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fabs))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabs_f64(a: float64x1_t) -> float64x1_t { - simd_fabs(a) +pub unsafe fn vceqs_f32(a: f32, b: f32) -> u32 { + simd_extract!(vceq_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } -/// Floating-point absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64) +#[doc = "Compare bitwise equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fabs))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabsq_f64(a: float64x2_t) -> float64x2_t { - simd_fabs(a) +pub unsafe fn vceqd_s64(a: i64, b: i64) -> u64 { + transmute(vceq_s64(transmute(a), transmute(b))) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64) +#[doc = "Compare bitwise equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub unsafe fn vceqd_u64(a: u64, b: u64) -> u64 { + transmute(vceq_u64(transmute(a), transmute(b))) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub unsafe fn vceqz_f32(a: float32x2_t) -> uint32x2_t { + let b: f32x2 = f32x2::new(0.0, 0.0); + simd_eq(a, transmute(b)) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhi))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub unsafe fn vceqzq_f32(a: float32x4_t) -> uint32x4_t { + let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); + simd_eq(a, transmute(b)) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhi))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub unsafe fn vceqz_f64(a: float64x1_t) -> uint64x1_t { + let b: f64 = 0.0; + simd_eq(a, transmute(b)) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmgt))] +#[cfg_attr(test, assert_instr(fcmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_gt(a, b) +pub unsafe fn vceqzq_f64(a: float64x2_t) -> uint64x2_t { + let b: f64x2 = f64x2::new(0.0, 0.0); + simd_eq(a, transmute(b)) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmgt))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_gt(a, b) +pub unsafe fn vceqz_s8(a: int8x8_t) -> uint8x8_t { + let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_s64(a: i64, b: i64) -> u64 { - transmute(vcgt_s64(transmute(a), transmute(b))) +pub unsafe fn vceqzq_s8(a: int8x16_t) -> uint8x16_t { + let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_u64(a: u64, b: u64) -> u64 { - transmute(vcgt_u64(transmute(a), transmute(b))) +pub unsafe fn vceqz_s16(a: int16x4_t) -> uint16x4_t { + let b: i16x4 = i16x4::new(0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgts_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub unsafe fn vceqzq_s16(a: int16x8_t) -> uint16x8_t { + let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub unsafe fn vceqz_s32(a: int32x2_t) -> uint32x2_t { + let b: i32x2 = i32x2::new(0, 0); + simd_eq(a, transmute(b)) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub unsafe fn vceqzq_s32(a: int32x4_t) -> uint32x4_t { + let b: i32x4 = i32x4::new(0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub unsafe fn vceqz_s64(a: int64x1_t) -> uint64x1_t { + let b: i64x1 = i64x1::new(0); + simd_eq(a, transmute(b)) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhi))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub unsafe fn vceqzq_s64(a: int64x2_t) -> uint64x2_t { + let b: i64x2 = i64x2::new(0, 0); + simd_eq(a, transmute(b)) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhi))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub unsafe fn vceqz_p8(a: poly8x8_t) -> uint8x8_t { + let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmgt))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_lt(a, b) +pub unsafe fn vceqzq_p8(a: poly8x16_t) -> uint8x16_t { + let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmgt))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_lt(a, b) +pub unsafe fn vceqz_p64(a: poly64x1_t) -> uint64x1_t { + let b: i64x1 = i64x1::new(0); + simd_eq(a, transmute(b)) } -/// Compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64) +#[doc = "Signed compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_s64(a: i64, b: i64) -> u64 { - transmute(vclt_s64(transmute(a), transmute(b))) +pub unsafe fn vceqzq_p64(a: poly64x2_t) -> uint64x2_t { + let b: i64x2 = i64x2::new(0, 0); + simd_eq(a, transmute(b)) } -/// Compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64) +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_u64(a: u64, b: u64) -> u64 { - transmute(vclt_u64(transmute(a), transmute(b))) +pub unsafe fn vceqz_u8(a: uint8x8_t) -> uint8x8_t { + let b: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32) +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclts_f32(a: f32, b: f32) -> u32 { - simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub unsafe fn vceqzq_u8(a: uint8x16_t) -> uint8x16_t { + let b: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64) +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltd_f64(a: f64, b: f64) -> u64 { - simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub unsafe fn vceqz_u16(a: uint16x4_t) -> uint16x4_t { + let b: u16x4 = u16x4::new(0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64) +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmge))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_le(a, b) +pub unsafe fn vceqzq_u16(a: uint16x8_t) -> uint16x8_t { + let b: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_eq(a, transmute(b)) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64) +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmge))] +#[cfg_attr(test, assert_instr(cmeq))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_le(a, b) +pub unsafe fn vceqz_u32(a: uint32x2_t) -> uint32x2_t { + let b: u32x2 = u32x2::new(0, 0); + simd_eq(a, transmute(b)) +} + +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(cmeq))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vceqzq_u32(a: uint32x4_t) -> uint32x4_t { + let b: u32x4 = u32x4::new(0, 0, 0, 0); + simd_eq(a, transmute(b)) +} + +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqz_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(cmeq))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vceqz_u64(a: uint64x1_t) -> uint64x1_t { + let b: u64x1 = u64x1::new(0); + simd_eq(a, transmute(b)) +} + +#[doc = "Unsigned compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(cmeq))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vceqzq_u64(a: uint64x2_t) -> uint64x2_t { + let b: u64x2 = u64x2::new(0, 0); + simd_eq(a, transmute(b)) } -/// Compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64) +#[doc = "Compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_s64(a: i64, b: i64) -> u64 { - transmute(vcge_s64(transmute(a), transmute(b))) +pub unsafe fn vceqzd_s64(a: i64) -> u64 { + transmute(vceqz_s64(transmute(a))) } -/// Compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64) +#[doc = "Compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_u64(a: u64, b: u64) -> u64 { - transmute(vcge_u64(transmute(a), transmute(b))) +pub unsafe fn vceqzd_u64(a: u64) -> u64 { + transmute(vceqz_u64(transmute(a))) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcges_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub unsafe fn vceqzs_f32(a: f32) -> u32 { + simd_extract!(vceqz_f32(vdup_n_f32(a)), 0) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64) +#[doc = "Floating-point compare bitwise equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqzd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcged_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub unsafe fn vceqzd_f64(a: f64) -> u64 { + simd_extract!(vceqz_f64(vdup_n_f64(a)), 0) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhs))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_le(a, b) +pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + simd_ge(a, b) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhs))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_le(a, b) +pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + simd_ge(a, b) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] +#[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_le(a, b) +pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + simd_ge(a, b) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] +#[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_le(a, b) +pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + simd_ge(a, b) } -/// Compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_s64(a: i64, b: i64) -> u64 { - transmute(vcle_s64(transmute(a), transmute(b))) +pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_ge(a, b) } -/// Compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_u64(a: u64, b: u64) -> u64 { - transmute(vcle_u64(transmute(a), transmute(b))) +pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_ge(a, b) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcles_f32(a: f32, b: f32) -> u32 { - simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) +pub unsafe fn vcged_f64(a: f64, b: f64) -> u64 { + simd_extract!(vcge_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcled_f64(a: f64, b: f64) -> u64 { - simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) +pub unsafe fn vcges_f32(a: f32, b: f32) -> u32 { + simd_extract!(vcge_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64) +#[doc = "Compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmge))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub unsafe fn vcged_s64(a: i64, b: i64) -> u64 { + transmute(vcge_s64(transmute(a), transmute(b))) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64) +#[doc = "Compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcged_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmge))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub unsafe fn vcged_u64(a: u64, b: u64) -> u64 { + transmute(vcge_u64(transmute(a), transmute(b))) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhs))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { + let b: f32x2 = f32x2::new(0.0, 0.0); + simd_ge(a, transmute(b)) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmhs))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { + let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); + simd_ge(a, transmute(b)) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcge_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - simd_ge(a, b) +pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { + let b: f64 = 0.0; + simd_ge(a, transmute(b)) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgeq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - simd_ge(a, b) +pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { + let b: f64x2 = f64x2::new(0.0, 0.0); + simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1364,9 +1714,10 @@ pub unsafe fn vcgez_s8(a: int8x8_t) -> uint8x8_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1376,9 +1727,10 @@ pub unsafe fn vcgezq_s8(a: int8x16_t) -> uint8x16_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1388,9 +1740,10 @@ pub unsafe fn vcgez_s16(a: int16x4_t) -> uint16x4_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1400,9 +1753,10 @@ pub unsafe fn vcgezq_s16(a: int16x8_t) -> uint16x8_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1412,9 +1766,10 @@ pub unsafe fn vcgez_s32(a: int32x2_t) -> uint32x2_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1424,9 +1779,10 @@ pub unsafe fn vcgezq_s32(a: int32x4_t) -> uint32x4_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1436,9 +1792,10 @@ pub unsafe fn vcgez_s64(a: int64x1_t) -> uint64x1_t { simd_ge(a, transmute(b)) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmge))] @@ -1448,57 +1805,34 @@ pub unsafe fn vcgezq_s64(a: int64x2_t) -> uint64x2_t { simd_ge(a, transmute(b)) } -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_f32(a: float32x2_t) -> uint32x2_t { - let b: f32x2 = f32x2::new(0.0, 0.0); - simd_ge(a, transmute(b)) -} - -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_f32(a: float32x4_t) -> uint32x4_t { - let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_ge(a, transmute(b)) -} - -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgez_f64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgez_f64(a: float64x1_t) -> uint64x1_t { - let b: f64 = 0.0; - simd_ge(a, transmute(b)) +pub unsafe fn vcgezd_f64(a: f64) -> u64 { + simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) } -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezq_f64) +#[doc = "Floating-point compare greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmge))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezq_f64(a: float64x2_t) -> uint64x2_t { - let b: f64x2 = f64x2::new(0.0, 0.0); - simd_ge(a, transmute(b)) +pub unsafe fn vcgezs_f32(a: f32) -> u32 { + simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) } -/// Compare signed greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64) +#[doc = "Compare signed greater than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop))] @@ -1507,127 +1841,130 @@ pub unsafe fn vcgezd_s64(a: i64) -> u64 { transmute(vcgez_s64(transmute(a))) } -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezs_f32) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezs_f32(a: f32) -> u32 { - simd_extract!(vcgez_f32(vdup_n_f32(a)), 0) +pub unsafe fn vcgt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + simd_gt(a, b) } -/// Floating-point compare greater than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgezd_f64) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgezd_f64(a: f64) -> u64 { - simd_extract!(vcgez_f64(vdup_n_f64(a)), 0) +pub unsafe fn vcgtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + simd_gt(a, b) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { - let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + simd_gt(a, b) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { - let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgtq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + simd_gt(a, b) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { - let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_gt(a, b) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { - let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgtq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_gt(a, b) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { - let b: i32x2 = i32x2::new(0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgtd_f64(a: f64, b: f64) -> u64 { + simd_extract!(vcgt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { - let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgts_f32(a: f32, b: f32) -> u32 { + simd_extract!(vcgt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64) +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { - let b: i64x1 = i64x1::new(0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgtd_s64(a: i64, b: i64) -> u64 { + transmute(vcgt_s64(transmute(a), transmute(b))) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64) +#[doc = "Compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { - let b: i64x2 = i64x2::new(0, 0); - simd_gt(a, transmute(b)) +pub unsafe fn vcgtd_u64(a: u64, b: u64) -> u64 { + transmute(vcgt_u64(transmute(a), transmute(b))) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] @@ -1637,9 +1974,10 @@ pub unsafe fn vcgtz_f32(a: float32x2_t) -> uint32x2_t { simd_gt(a, transmute(b)) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] @@ -1649,9 +1987,10 @@ pub unsafe fn vcgtzq_f32(a: float32x4_t) -> uint32x4_t { simd_gt(a, transmute(b)) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] @@ -1661,9 +2000,10 @@ pub unsafe fn vcgtz_f64(a: float64x1_t) -> uint64x1_t { simd_gt(a, transmute(b)) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmgt))] @@ -1673,1332 +2013,1834 @@ pub unsafe fn vcgtzq_f64(a: float64x2_t) -> uint64x2_t { simd_gt(a, transmute(b)) } -/// Compare signed greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzd_s64(a: i64) -> u64 { - transmute(vcgtz_s64(transmute(a))) +pub unsafe fn vcgtz_s8(a: int8x8_t) -> uint8x8_t { + let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_gt(a, transmute(b)) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzs_f32(a: f32) -> u32 { - simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) +pub unsafe fn vcgtzq_s8(a: int8x16_t) -> uint8x16_t { + let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_gt(a, transmute(b)) } -/// Floating-point compare greater than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcgtzd_f64(a: f64) -> u64 { - simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) +pub unsafe fn vcgtz_s16(a: int16x4_t) -> uint16x4_t { + let b: i16x4 = i16x4::new(0, 0, 0, 0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { - let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzq_s16(a: int16x8_t) -> uint16x8_t { + let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { - let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtz_s32(a: int32x2_t) -> uint32x2_t { + let b: i32x2 = i32x2::new(0, 0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { - let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzq_s32(a: int32x4_t) -> uint32x4_t { + let b: i32x4 = i32x4::new(0, 0, 0, 0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtz_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { - let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtz_s64(a: int64x1_t) -> uint64x1_t { + let b: i64x1 = i64x1::new(0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { - let b: i32x2 = i32x2::new(0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzq_s64(a: int64x2_t) -> uint64x2_t { + let b: i64x2 = i64x2::new(0, 0); + simd_gt(a, transmute(b)) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { - let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzd_f64(a: f64) -> u64 { + simd_extract!(vcgtz_f64(vdup_n_f64(a)), 0) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64) +#[doc = "Floating-point compare greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { - let b: i64x1 = i64x1::new(0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzs_f32(a: f32) -> u32 { + simd_extract!(vcgtz_f32(vdup_n_f32(a)), 0) } -/// Compare signed less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64) +#[doc = "Compare signed greater than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtzd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmle))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { - let b: i64x2 = i64x2::new(0, 0); - simd_le(a, transmute(b)) +pub unsafe fn vcgtzd_s64(a: i64) -> u64 { + transmute(vcgtz_s64(transmute(a))) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmle))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { - let b: f32x2 = f32x2::new(0.0, 0.0); - simd_le(a, transmute(b)) +pub unsafe fn vcle_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + simd_le(a, b) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmle))] +#[cfg_attr(test, assert_instr(fcmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { - let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_le(a, transmute(b)) +pub unsafe fn vcleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + simd_le(a, b) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmle))] +#[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { - let b: f64 = 0.0; - simd_le(a, transmute(b)) +pub unsafe fn vcle_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + simd_le(a, b) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmle))] +#[cfg_attr(test, assert_instr(cmge))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { - let b: f64x2 = f64x2::new(0.0, 0.0); - simd_le(a, transmute(b)) +pub unsafe fn vcleq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + simd_le(a, b) } -/// Compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmp))] +#[cfg_attr(test, assert_instr(cmhs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezd_s64(a: i64) -> u64 { - transmute(vclez_s64(transmute(a))) +pub unsafe fn vcle_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_le(a, b) +} + +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(cmhs))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcleq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_le(a, b) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezs_f32(a: f32) -> u32 { - simd_extract!(vclez_f32(vdup_n_f32(a)), 0) +pub unsafe fn vcled_f64(a: f64, b: f64) -> u64 { + simd_extract!(vcle_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Floating-point compare less than or equal to zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vclezd_f64(a: f64) -> u64 { - simd_extract!(vclez_f64(vdup_n_f64(a)), 0) +pub unsafe fn vcles_f32(a: f32, b: f32) -> u32 { + simd_extract!(vcle_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8) +#[doc = "Compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { - let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vcled_u64(a: u64, b: u64) -> u64 { + transmute(vcle_u64(transmute(a), transmute(b))) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8) +#[doc = "Compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcled_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { - let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vcled_s64(a: i64, b: i64) -> u64 { + transmute(vcle_s64(transmute(a), transmute(b))) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { - let b: i16x4 = i16x4::new(0, 0, 0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vclez_f32(a: float32x2_t) -> uint32x2_t { + let b: f32x2 = f32x2::new(0.0, 0.0); + simd_le(a, transmute(b)) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { - let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vclezq_f32(a: float32x4_t) -> uint32x4_t { + let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); + simd_le(a, transmute(b)) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { - let b: i32x2 = i32x2::new(0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vclez_f64(a: float64x1_t) -> uint64x1_t { + let b: f64 = 0.0; + simd_le(a, transmute(b)) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(fcmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { - let b: i32x4 = i32x4::new(0, 0, 0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vclezq_f64(a: float64x2_t) -> uint64x2_t { + let b: f64x2 = f64x2::new(0.0, 0.0); + simd_le(a, transmute(b)) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { - let b: i64x1 = i64x1::new(0); - simd_lt(a, transmute(b)) +pub unsafe fn vclez_s8(a: int8x8_t) -> uint8x8_t { + let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_le(a, transmute(b)) } -/// Compare signed less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(cmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { - let b: i64x2 = i64x2::new(0, 0); - simd_lt(a, transmute(b)) +pub unsafe fn vclezq_s8(a: int8x16_t) -> uint8x16_t { + let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { - let b: f32x2 = f32x2::new(0.0, 0.0); - simd_lt(a, transmute(b)) +pub unsafe fn vclez_s16(a: int16x4_t) -> uint16x4_t { + let b: i16x4 = i16x4::new(0, 0, 0, 0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { - let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); - simd_lt(a, transmute(b)) +pub unsafe fn vclezq_s16(a: int16x8_t) -> uint16x8_t { + let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { - let b: f64 = 0.0; - simd_lt(a, transmute(b)) +pub unsafe fn vclez_s32(a: int32x2_t) -> uint32x2_t { + let b: i32x2 = i32x2::new(0, 0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmlt))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { - let b: f64x2 = f64x2::new(0.0, 0.0); - simd_lt(a, transmute(b)) +pub unsafe fn vclezq_s32(a: int32x4_t) -> uint32x4_t { + let b: i32x4 = i32x4::new(0, 0, 0, 0); + simd_le(a, transmute(b)) } -/// Compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclez_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(asr))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzd_s64(a: i64) -> u64 { - transmute(vcltz_s64(transmute(a))) +pub unsafe fn vclez_s64(a: int64x1_t) -> uint64x1_t { + let b: i64x1 = i64x1::new(0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32) +#[doc = "Compare signed less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcmp))] +#[cfg_attr(test, assert_instr(cmle))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzs_f32(a: f32) -> u32 { - simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) +pub unsafe fn vclezq_s64(a: int64x2_t) -> uint64x2_t { + let b: i64x2 = i64x2::new(0, 0); + simd_le(a, transmute(b)) } -/// Floating-point compare less than zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcltzd_f64(a: f64) -> u64 { - simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) +pub unsafe fn vclezd_f64(a: f64) -> u64 { + simd_extract!(vclez_f64(vdup_n_f64(a)), 0) } -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64) +#[doc = "Floating-point compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.v1i64.v1f64")] - fn vcagt_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; - } - vcagt_f64_(a, b) +pub unsafe fn vclezs_f32(a: f32) -> u32 { + simd_extract!(vclez_f32(vdup_n_f32(a)), 0) } -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64) +#[doc = "Compare less than or equal to zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclezd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagtq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.v2i64.v2f64")] - fn vcagtq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; - } - vcagtq_f64_(a, b) +pub unsafe fn vclezd_s64(a: i64) -> u64 { + transmute(vclez_s64(transmute(a))) } -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagts_f32(a: f32, b: f32) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.i32.f32")] - fn vcagts_f32_(a: f32, b: f32) -> u32; - } - vcagts_f32_(a, b) +pub unsafe fn vclt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { + simd_lt(a, b) } -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtd_f64) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(fcmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcagtd_f64(a: f64, b: f64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.i64.f64")] - fn vcagtd_f64_(a: f64, b: f64) -> u64; - } - vcagtd_f64_(a, b) +pub unsafe fn vcltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { + simd_lt(a, b) } -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcage_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.v1i64.v1f64")] - fn vcage_f64_(a: float64x1_t, b: float64x1_t) -> uint64x1_t; - } - vcage_f64_(a, b) +pub unsafe fn vclt_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + simd_lt(a, b) } -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(cmgt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcageq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.v2i64.v2f64")] - fn vcageq_f64_(a: float64x2_t, b: float64x2_t) -> uint64x2_t; - } - vcageq_f64_(a, b) +pub unsafe fn vcltq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + simd_lt(a, b) } -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcages_f32(a: f32, b: f32) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.i32.f32")] - fn vcages_f32_(a: f32, b: f32) -> u32; - } - vcages_f32_(a, b) +pub unsafe fn vclt_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_lt(a, b) } -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaged_f64) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(cmhi))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaged_f64(a: f64, b: f64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.i64.f64")] - fn vcaged_f64_(a: f64, b: f64) -> u64; - } - vcaged_f64_(a, b) +pub unsafe fn vcltq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_lt(a, b) } -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64) +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcalt_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - vcagt_f64(b, a) +pub unsafe fn vcltd_u64(a: u64, b: u64) -> u64 { + transmute(vclt_u64(transmute(a), transmute(b))) } -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64) +#[doc = "Compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(cmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaltq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - vcagtq_f64(b, a) +pub unsafe fn vcltd_s64(a: i64, b: i64) -> u64 { + transmute(vclt_s64(transmute(a), transmute(b))) } -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcalts_f32(a: f32, b: f32) -> u32 { - vcagts_f32(b, a) +pub unsafe fn vclts_f32(a: f32, b: f32) -> u32 { + simd_extract!(vclt_f32(vdup_n_f32(a), vdup_n_f32(b)), 0) } -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltd_f64) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facgt))] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaltd_f64(a: f64, b: f64) -> u64 { - vcagtd_f64(b, a) +pub unsafe fn vcltd_f64(a: f64, b: f64) -> u64 { + simd_extract!(vclt_f64(vdup_n_f64(a), vdup_n_f64(b)), 0) } -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcale_f64(a: float64x1_t, b: float64x1_t) -> uint64x1_t { - vcage_f64(b, a) +pub unsafe fn vcltz_f32(a: float32x2_t) -> uint32x2_t { + let b: f32x2 = f32x2::new(0.0, 0.0); + simd_lt(a, transmute(b)) } -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaleq_f64(a: float64x2_t, b: float64x2_t) -> uint64x2_t { - vcageq_f64(b, a) +pub unsafe fn vcltzq_f32(a: float32x4_t) -> uint32x4_t { + let b: f32x4 = f32x4::new(0.0, 0.0, 0.0, 0.0); + simd_lt(a, transmute(b)) } -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcales_f32(a: f32, b: f32) -> u32 { - vcages_f32(b, a) +pub unsafe fn vcltz_f64(a: float64x1_t) -> uint64x1_t { + let b: f64 = 0.0; + simd_lt(a, transmute(b)) } -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaled_f64) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(facge))] +#[cfg_attr(test, assert_instr(fcmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcaled_f64(a: f64, b: f64) -> u64 { - vcaged_f64(b, a) +pub unsafe fn vcltzq_f64(a: float64x2_t) -> uint64x2_t { + let b: f64x2 = f64x2::new(0.0, 0.0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltz_s8(a: int8x8_t) -> uint8x8_t { + let b: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzq_s8(a: int8x16_t) -> uint8x16_t { + let b: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltz_s16(a: int16x4_t) -> uint16x4_t { + let b: i16x4 = i16x4::new(0, 0, 0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzq_s16(a: int16x8_t) -> uint16x8_t { + let b: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltz_s32(a: int32x2_t) -> uint32x2_t { + let b: i32x2 = i32x2::new(0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzq_s32(a: int32x4_t) -> uint32x4_t { + let b: i32x4 = i32x4::new(0, 0, 0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltz_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltz_s64(a: int64x1_t) -> uint64x1_t { + let b: i64x1 = i64x1::new(0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8) +#[doc = "Compare signed less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(cmlt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzq_s64(a: int64x2_t) -> uint64x2_t { + let b: i64x2 = i64x2::new(0, 0); + simd_lt(a, transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzd_f64(a: f64) -> u64 { + simd_extract!(vcltz_f64(vdup_n_f64(a)), 0) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16) +#[doc = "Floating-point compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(fcmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzs_f32(a: f32) -> u32 { + simd_extract!(vcltz_f32(vdup_n_f32(a)), 0) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16) +#[doc = "Compare less than zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltzd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] +#[cfg_attr(test, assert_instr(asr))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +pub unsafe fn vcltzd_s64(a: i64) -> u64 { + transmute(vcltz_s64(transmute(a))) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32" + )] + fn _vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } + _vcmla_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32" + )] + fn _vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } + _vcmlaq_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64" + )] + fn _vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } + _vcmlaq_f64(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert!(LANE == 0); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 4); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert!(LANE == 0); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 3); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32" + )] + fn _vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } + _vcmla_rot180_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32" + )] + fn _vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } + _vcmlaq_rot180_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 2); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64" + )] + fn _vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } + _vcmlaq_rot180_f64(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 1); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot180_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert!(LANE == 0); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot180_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s8(a: int8x8_t, b: int8x16_t) -> int8x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 4); - let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), - } +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot180_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert!(LANE == 0); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 3); - let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot180_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot180_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot180_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot180_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32" + )] + fn _vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; } + _vcmla_rot270_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 2); - let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32" + )] + fn _vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; } + _vcmlaq_rot270_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u8(a: uint8x8_t, b: uint8x16_t) -> uint8x8_t { - static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 4); - let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64" + )] + fn _vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } + _vcmlaq_rot270_f64(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16) +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 3); - let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), - _ => unreachable_unchecked(), +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot270_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert!(LANE == 0); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot270_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot270_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert!(LANE == 0); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot270_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot270_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot270_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot270_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32" + )] + fn _vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + _vcmla_rot90_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32" + )] + fn _vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + _vcmlaq_rot90_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +#[cfg_attr(test, assert_instr(fcmla))] +pub unsafe fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64" + )] + fn _vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; } + _vcmlaq_rot90_f64(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot90_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert!(LANE == 0); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot90_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot90_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert!(LANE == 0); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmla_rot90_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); + vcmla_rot90_f32(a, b, c) +} + +#[doc = "Floating-point complex multiply accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,fcma")] +#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +pub unsafe fn vcmlaq_rot90_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: float32x4_t = simd_shuffle!( + c, + c, + [ + 2 * LANE as u32, + 2 * LANE as u32 + 1, + 2 * LANE as u32, + 2 * LANE as u32 + 1 + ] + ); + vcmlaq_rot90_f32(a, b, c) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { +pub unsafe fn vcopy_lane_f32( + a: float32x2_t, + b: float32x2_t, +) -> float32x2_t { static_assert_uimm_bits!(LANE1, 1); - static_assert_uimm_bits!(LANE2, 2); - let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + static_assert_uimm_bits!(LANE2, 1); match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_p8(a: poly8x8_t, b: poly8x16_t) -> poly8x8_t { +pub unsafe fn vcopy_lane_s8( + a: int8x8_t, + b: int8x8_t, +) -> int8x8_t { static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 4); - let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + static_assert_uimm_bits!(LANE2, 3); match LANE1 & 0b111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_p16(a: poly16x4_t, b: poly16x8_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE1, 2); +pub unsafe fn vcopyq_lane_s8( + a: int8x16_t, + b: int8x8_t, +) -> int8x16_t { + static_assert_uimm_bits!(LANE1, 4); static_assert_uimm_bits!(LANE2, 3); - let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopy_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE1, 1); +pub unsafe fn vcopy_lane_s16( + a: int16x4_t, + b: int16x4_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE1, 2); static_assert_uimm_bits!(LANE2, 2); - let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), - _ => unreachable_unchecked(), - } -} - -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] -#[rustc_legacy_const_generics(1, 3)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s8(a: int8x16_t, b: int8x8_t) -> int8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 3); - let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { +pub unsafe fn vcopyq_lane_s16( + a: int16x8_t, + b: int16x4_t, +) -> int16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); @@ -3015,72 +3857,68 @@ pub unsafe fn vcopyq_lane_s16(a: int16x8_t, } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE1, 2); +pub unsafe fn vcopy_lane_s32( + a: int32x2_t, + b: int32x2_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE1, 1); static_assert_uimm_bits!(LANE2, 1); - let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u8(a: uint8x16_t, b: uint8x8_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 3); - let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), +pub unsafe fn vcopyq_lane_s32( + a: int32x4_t, + b: int32x2_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 1); + let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { +pub unsafe fn vcopy_lane_u8( + a: uint8x8_t, + b: uint8x8_t, +) -> uint8x8_t { static_assert_uimm_bits!(LANE1, 3); - static_assert_uimm_bits!(LANE2, 2); - let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); + static_assert_uimm_bits!(LANE2, 3); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), @@ -3094,72 +3932,419 @@ pub unsafe fn vcopyq_lane_u16(a: uint16x8_t, } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 1); - let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); - match LANE1 & 0b11 { - 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), - 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), +pub unsafe fn vcopyq_lane_u8( + a: uint8x16_t, + b: uint8x8_t, +) -> uint8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 3); + let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p8(a: poly8x16_t, b: poly8x8_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE1, 4); - static_assert_uimm_bits!(LANE2, 3); - let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); - match LANE1 & 0b1111 { - 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), - 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), - 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), - 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), - 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), - 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), - 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), - 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), - 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), +pub unsafe fn vcopy_lane_u16( + a: uint16x4_t, + b: uint16x4_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 2); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p16(a: poly16x8_t, b: poly16x4_t) -> poly16x8_t { +pub unsafe fn vcopyq_lane_u16( + a: uint16x8_t, + b: uint16x4_t, +) -> uint16x8_t { static_assert_uimm_bits!(LANE1, 3); static_assert_uimm_bits!(LANE2, 2); - let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); + let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), @@ -3173,18 +4358,21 @@ pub unsafe fn vcopyq_lane_p16(a: poly16x8_t, } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_s64(a: int64x2_t, b: int64x1_t) -> int64x2_t { +pub unsafe fn vcopy_lane_u32( + a: uint32x2_t, + b: uint32x2_t, +) -> uint32x2_t { static_assert_uimm_bits!(LANE1, 1); - static_assert!(LANE2 == 0); - let b: int64x2_t = simd_shuffle!(b, b, [0, 1]); + static_assert_uimm_bits!(LANE2, 1); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), @@ -3192,56 +4380,447 @@ pub unsafe fn vcopyq_lane_s64(a: int64x2_t, } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_u64(a: uint64x2_t, b: uint64x1_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert!(LANE2 == 0); - let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), - _ => unreachable_unchecked(), +pub unsafe fn vcopyq_lane_u32( + a: uint32x4_t, + b: uint32x2_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 1); + let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_p64(a: poly64x2_t, b: poly64x1_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert!(LANE2 == 0); - let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), +pub unsafe fn vcopy_lane_p8( + a: poly8x8_t, + b: poly8x8_t, +) -> poly8x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 3); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcopyq_lane_p8( + a: poly8x16_t, + b: poly8x8_t, +) -> poly8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 3); + let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } +} + +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { +pub unsafe fn vcopy_lane_p16( + a: poly16x4_t, + b: poly16x4_t, +) -> poly16x4_t { static_assert_uimm_bits!(LANE1, 2); - static_assert_uimm_bits!(LANE2, 1); - let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); + static_assert_uimm_bits!(LANE2, 2); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), @@ -3251,25410 +4830,17501 @@ pub unsafe fn vcopyq_lane_f32(a: float32x4_t } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] #[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcopyq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { - static_assert_uimm_bits!(LANE1, 1); - static_assert!(LANE2 == 0); - let b: float64x2_t = simd_shuffle!(b, b, [0, 1]); - match LANE1 & 0b1 { - 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), - 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), +pub unsafe fn vcopyq_lane_p16( + a: poly16x8_t, + b: poly16x4_t, +) -> poly16x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 2); + let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), } } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { - transmute(a) +pub unsafe fn vcopy_laneq_f32( + a: float32x2_t, + b: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 2); + let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { - simd_cast(a) +pub unsafe fn vcopyq_laneq_f32( + a: float32x4_t, + b: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 2); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { - simd_cast(a) +pub unsafe fn vcopyq_laneq_f64( + a: float64x2_t, + b: float64x2_t, +) -> float64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { - simd_cast(a) +pub unsafe fn vcopy_laneq_s8( + a: int8x8_t, + b: int8x16_t, +) -> int8x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 4); + let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { - simd_cast(a) +pub unsafe fn vcopyq_laneq_s8( + a: int8x16_t, + b: int8x16_t, +) -> int8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 4); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to higher precision long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { - simd_cast(a) +pub unsafe fn vcopy_laneq_s16( + a: int16x4_t, + b: int16x8_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 3); + let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to higher precision long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtl))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { - let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); - simd_cast(b) +pub unsafe fn vcopyq_laneq_s16( + a: int16x8_t, + b: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 3); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to lower precision narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { - simd_cast(a) +pub unsafe fn vcopy_laneq_s32( + a: int32x2_t, + b: int32x4_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 2); + let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to lower precision narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtn))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) +pub unsafe fn vcopyq_laneq_s32( + a: int32x4_t, + b: int32x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 2); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to lower precision narrow, rounding to odd -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtxn.v2f32.v2f64")] - fn vcvtx_f32_f64_(a: float64x2_t) -> float32x2_t; +pub unsafe fn vcopyq_laneq_s64( + a: int64x2_t, + b: int64x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtx_f32_f64_(a) } -/// Floating-point convert to lower precision narrow, rounding to odd -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtxd_f32_f64(a: f64) -> f32 { - simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) +pub unsafe fn vcopy_laneq_u8( + a: uint8x8_t, + b: uint8x16_t, +) -> uint8x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 4); + let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), + } } -/// Floating-point convert to lower precision narrow, rounding to odd -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtxn))] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { - simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) +pub unsafe fn vcopyq_laneq_u8( + a: uint8x16_t, + b: uint8x16_t, +) -> uint8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 4); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), + } } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64")] - fn vcvt_n_f64_s64_(a: int64x1_t, n: i32) -> float64x1_t; +pub unsafe fn vcopy_laneq_u16( + a: uint16x4_t, + b: uint16x8_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 3); + let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvt_n_f64_s64_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64")] - fn vcvtq_n_f64_s64_(a: int64x2_t, n: i32) -> float64x2_t; +pub unsafe fn vcopyq_laneq_u16( + a: uint16x8_t, + b: uint16x8_t, +) -> uint16x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 3); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtq_n_f64_s64_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_f32_s32(a: i32) -> f32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.f32.i32")] - fn vcvts_n_f32_s32_(a: i32, n: i32) -> f32; +pub unsafe fn vcopy_laneq_u32( + a: uint32x2_t, + b: uint32x4_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 2); + let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvts_n_f32_s32_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_f64_s64(a: i64) -> f64 { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.f64.i64")] - fn vcvtd_n_f64_s64_(a: i64, n: i32) -> f64; +pub unsafe fn vcopyq_laneq_u32( + a: uint32x4_t, + b: uint32x4_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 2); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtd_n_f64_s64_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64")] - fn vcvt_n_f64_u64_(a: uint64x1_t, n: i32) -> float64x1_t; +pub unsafe fn vcopyq_laneq_u64( + a: uint64x2_t, + b: uint64x2_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvt_n_f64_u64_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64")] - fn vcvtq_n_f64_u64_(a: uint64x2_t, n: i32) -> float64x2_t; +pub unsafe fn vcopy_laneq_p8( + a: poly8x8_t, + b: poly8x16_t, +) -> poly8x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 4); + let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtq_n_f64_u64_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.f32.i32")] - fn vcvts_n_f32_u32_(a: u32, n: i32) -> f32; +pub unsafe fn vcopyq_laneq_p8( + a: poly8x16_t, + b: poly8x16_t, +) -> poly8x16_t { + static_assert_uimm_bits!(LANE1, 4); + static_assert_uimm_bits!(LANE2, 4); + match LANE1 & 0b1111 { + 0 => simd_shuffle!( + a, + b, + [ + 16 + LANE2 as u32, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 1 => simd_shuffle!( + a, + b, + [ + 0, + 16 + LANE2 as u32, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 2 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 16 + LANE2 as u32, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 3 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 16 + LANE2 as u32, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 4 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 16 + LANE2 as u32, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 5 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 16 + LANE2 as u32, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 6 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 16 + LANE2 as u32, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 7 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 16 + LANE2 as u32, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 8 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 16 + LANE2 as u32, + 9, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 9 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 16 + LANE2 as u32, + 10, + 11, + 12, + 13, + 14, + 15 + ] + ), + 10 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 16 + LANE2 as u32, + 11, + 12, + 13, + 14, + 15 + ] + ), + 11 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 16 + LANE2 as u32, + 12, + 13, + 14, + 15 + ] + ), + 12 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 16 + LANE2 as u32, + 13, + 14, + 15 + ] + ), + 13 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 16 + LANE2 as u32, + 14, + 15 + ] + ), + 14 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 16 + LANE2 as u32, + 15 + ] + ), + 15 => simd_shuffle!( + a, + b, + [ + 0, + 1, + 2, + 3, + 4, + 5, + 6, + 7, + 8, + 9, + 10, + 11, + 12, + 13, + 14, + 16 + LANE2 as u32 + ] + ), + _ => unreachable_unchecked(), } - vcvts_n_f32_u32_(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.f64.i64")] - fn vcvtd_n_f64_u64_(a: u64, n: i32) -> f64; +pub unsafe fn vcopy_laneq_p16( + a: poly16x4_t, + b: poly16x8_t, +) -> poly16x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 3); + let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtd_n_f64_u64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64")] - fn vcvt_n_s64_f64_(a: float64x1_t, n: i32) -> int64x1_t; +pub unsafe fn vcopyq_laneq_p16( + a: poly16x8_t, + b: poly16x8_t, +) -> poly16x8_t { + static_assert_uimm_bits!(LANE1, 3); + static_assert_uimm_bits!(LANE2, 3); + match LANE1 & 0b111 { + 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), + 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), + 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), + 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), + 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), + 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvt_n_s64_f64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 0, LANE2 = 1))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64")] - fn vcvtq_n_s64_f64_(a: float64x2_t, n: i32) -> int64x2_t; +pub unsafe fn vcopyq_laneq_p64( + a: poly64x2_t, + b: poly64x2_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert_uimm_bits!(LANE2, 1); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtq_n_s64_f64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_s32_f32(a: f32) -> i32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f32")] - fn vcvts_n_s32_f32_(a: f32, n: i32) -> i32; +pub unsafe fn vcopyq_lane_f32( + a: float32x4_t, + b: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE1, 2); + static_assert_uimm_bits!(LANE2, 1); + let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); + match LANE1 & 0b11 { + 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), + 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), + 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvts_n_s32_f32_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_s64_f64(a: f64) -> i64 { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f64")] - fn vcvtd_n_s64_f64_(a: f64, n: i32) -> i64; +pub unsafe fn vcopyq_lane_f64( + a: float64x2_t, + b: float64x1_t, +) -> float64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: float64x2_t = simd_shuffle!(b, b, [0, 1]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtd_n_s64_f64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64")] - fn vcvt_n_u64_f64_(a: float64x1_t, n: i32) -> uint64x1_t; +pub unsafe fn vcopyq_lane_s64( + a: int64x2_t, + b: int64x1_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: int64x2_t = simd_shuffle!(b, b, [0, 1]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvt_n_u64_f64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64")] - fn vcvtq_n_u64_f64_(a: float64x2_t, n: i32) -> uint64x2_t; +pub unsafe fn vcopyq_lane_u64( + a: uint64x2_t, + b: uint64x1_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvtq_n_u64_f64_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(mov, LANE1 = 1, LANE2 = 0))] +#[rustc_legacy_const_generics(1, 3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_n_u32_f32(a: f32) -> u32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f32")] - fn vcvts_n_u32_f32_(a: f32, n: i32) -> u32; +pub unsafe fn vcopyq_lane_p64( + a: poly64x2_t, + b: poly64x1_t, +) -> poly64x2_t { + static_assert_uimm_bits!(LANE1, 1); + static_assert!(LANE2 == 0); + let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]); + match LANE1 & 0b1 { + 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), + 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), + _ => unreachable_unchecked(), } - vcvts_n_u32_f32_(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { - static_assert!(N >= 1 && N <= 64); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f64")] - fn vcvtd_n_u64_f64_(a: f64, n: i32) -> u64; - } - vcvtd_n_u64_f64_(a, N) +pub unsafe fn vcreate_f64(a: u64) -> float64x1_t { + transmute(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32) +#[doc = "Floating-point convert to lower precision narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf))] +#[cfg_attr(test, assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { - a as f32 +pub unsafe fn vcvt_f32_f64(a: float64x2_t) -> float32x2_t { + simd_cast(a) +} + +#[doc = "Floating-point convert to higher precision long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fcvtl))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvt_f64_f32(a: float32x2_t) -> float64x2_t { + simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { - a as f64 +pub unsafe fn vcvt_f64_s64(a: int64x1_t) -> float64x1_t { + simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf))] +#[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { - a as f32 +pub unsafe fn vcvtq_f64_s64(a: int64x2_t) -> float64x2_t { + simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { - a as f64 +pub unsafe fn vcvt_f64_u64(a: uint64x1_t) -> float64x1_t { + simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs))] +#[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { - a as i32 +pub unsafe fn vcvtq_f64_u64(a: uint64x2_t) -> float64x2_t { + simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64) +#[doc = "Floating-point convert to lower precision narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs))] +#[cfg_attr(test, assert_instr(fcvtn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { - a as i64 +pub unsafe fn vcvt_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { + simd_shuffle!(a, simd_cast(b), [0, 1, 2, 3]) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32) +#[doc = "Floating-point convert to higher precision long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu))] +#[cfg_attr(test, assert_instr(fcvtl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { - a as u32 +pub unsafe fn vcvt_high_f64_f32(a: float32x4_t) -> float64x2_t { + let b: float32x2_t = simd_shuffle!(a, a, [2, 3]); + simd_cast(b) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu))] +#[cfg_attr(test, assert_instr(scvtf, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { - a as u64 +pub unsafe fn vcvt_n_f64_s64(a: int64x1_t) -> float64x1_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.v1f64.v1i64" + )] + fn _vcvt_n_f64_s64(a: int64x1_t, n: i32) -> float64x1_t; + } + _vcvt_n_f64_s64(a, N) +} + +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(scvtf, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_f64_s64(a: int64x2_t) -> float64x2_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f64.v2i64" + )] + fn _vcvtq_n_f64_s64(a: int64x2_t, n: i32) -> float64x2_t; + } + _vcvtq_n_f64_s64(a, N) +} + +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ucvtf, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvt_n_f64_u64(a: uint64x1_t) -> float64x1_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.v1f64.v1i64" + )] + fn _vcvt_n_f64_u64(a: int64x1_t, n: i32) -> float64x1_t; + } + _vcvt_n_f64_u64(a.as_signed(), N) +} + +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ucvtf, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_f64_u64(a: uint64x2_t) -> float64x2_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f64.v2i64" + )] + fn _vcvtq_n_f64_u64(a: int64x2_t, n: i32) -> float64x2_t; + } + _vcvtq_n_f64_u64(a.as_signed(), N) +} + +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvt_n_s64_f64(a: float64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.v1i64.v1f64" + )] + fn _vcvt_n_s64_f64(a: float64x1_t, n: i32) -> int64x1_t; + } + _vcvt_n_s64_f64(a, N) +} + +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_s64_f64(a: float64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i64.v2f64" + )] + fn _vcvtq_n_s64_f64(a: float64x2_t, n: i32) -> int64x2_t; + } + _vcvtq_n_s64_f64(a, N) +} + +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvt_n_u64_f64(a: float64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.v1i64.v1f64" + )] + fn _vcvt_n_u64_f64(a: float64x1_t, n: i32) -> int64x1_t; + } + _vcvt_n_u64_f64(a, N).as_unsigned() +} + +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_u64_f64(a: float64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i64.v2f64" + )] + fn _vcvtq_n_u64_f64(a: float64x2_t, n: i32) -> int64x2_t; + } + _vcvtq_n_u64_f64(a, N).as_unsigned() } -/// Floating-point convert to signed fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64) +#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvt_s64_f64(a: float64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptosi.sat.v1i64.v1f64")] - fn vcvt_s64_f64_(a: float64x1_t) -> int64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptosi.sat.v1i64.v1f64" + )] + fn _vcvt_s64_f64(a: float64x1_t) -> int64x1_t; } - vcvt_s64_f64_(a) + _vcvt_s64_f64(a) } -/// Floating-point convert to signed fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64) +#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtq_s64_f64(a: float64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptosi.sat.v2i64.v2f64")] - fn vcvtq_s64_f64_(a: float64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptosi.sat.v2i64.v2f64" + )] + fn _vcvtq_s64_f64(a: float64x2_t) -> int64x2_t; } - vcvtq_s64_f64_(a) + _vcvtq_s64_f64(a) } -/// Floating-point convert to unsigned fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64) +#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvt_u64_f64(a: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptoui.sat.v1i64.v1f64")] - fn vcvt_u64_f64_(a: float64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptoui.sat.v1i64.v1f64" + )] + fn _vcvt_u64_f64(a: float64x1_t) -> int64x1_t; } - vcvt_u64_f64_(a) + _vcvt_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64) +#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtq_u64_f64(a: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptoui.sat.v2i64.v2f64")] - fn vcvtq_u64_f64_(a: float64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptoui.sat.v2i64.v2f64" + )] + fn _vcvtq_u64_f64(a: float64x2_t) -> int64x2_t; } - vcvtq_u64_f64_(a) + _vcvtq_u64_f64(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvta_s32_f32(a: float32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32")] - fn vcvta_s32_f32_(a: float32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.v2i32.v2f32" + )] + fn _vcvta_s32_f32(a: float32x2_t) -> int32x2_t; } - vcvta_s32_f32_(a) + _vcvta_s32_f32(a) } -/// Floating-point convert to signed integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32")] - fn vcvtaq_s32_f32_(a: float32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.v4i32.v4f32" + )] + fn _vcvtaq_s32_f32(a: float32x4_t) -> int32x4_t; } - vcvtaq_s32_f32_(a) + _vcvtaq_s32_f32(a) } -/// Floating-point convert to signed integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvta_s64_f64(a: float64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64")] - fn vcvta_s64_f64_(a: float64x1_t) -> int64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.v1i64.v1f64" + )] + fn _vcvta_s64_f64(a: float64x1_t) -> int64x1_t; } - vcvta_s64_f64_(a) + _vcvta_s64_f64(a) } -/// Floating-point convert to signed integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64")] - fn vcvtaq_s64_f64_(a: float64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.v2i64.v2f64" + )] + fn _vcvtaq_s64_f64(a: float64x2_t) -> int64x2_t; } - vcvtaq_s64_f64_(a) + _vcvtaq_s64_f64(a) } -/// Floating-point convert to integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtas))] +#[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.i32.f32")] - fn vcvtas_s32_f32_(a: f32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.v2i32.v2f32" + )] + fn _vcvta_u32_f32(a: float32x2_t) -> int32x2_t; } - vcvtas_s32_f32_(a) + _vcvta_u32_f32(a).as_unsigned() } -/// Floating-point convert to integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtas))] +#[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtas.i64.f64")] - fn vcvtad_s64_f64_(a: f64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.v4i32.v4f32" + )] + fn _vcvtaq_u32_f32(a: float32x4_t) -> int32x4_t; } - vcvtad_s64_f64_(a) + _vcvtaq_u32_f32(a).as_unsigned() } -/// Floating-point convert to integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.i32.f32")] - fn vcvtas_u32_f32_(a: f32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.v1i64.v1f64" + )] + fn _vcvta_u64_f64(a: float64x1_t) -> int64x1_t; } - vcvtas_u32_f32_(a) + _vcvta_u64_f64(a).as_unsigned() } -/// Floating-point convert to integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.i64.f64")] - fn vcvtad_u64_f64_(a: f64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.v2i64.v2f64" + )] + fn _vcvtaq_u64_f64(a: float64x2_t) -> int64x2_t; } - vcvtad_u64_f64_(a) + _vcvtaq_u64_f64(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32) +#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtas_s32_f32(a: f32) -> i32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.v2i32.v2f32")] - fn vcvtn_s32_f32_(a: float32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.i32.f32" + )] + fn _vcvtas_s32_f32(a: f32) -> i32; } - vcvtn_s32_f32_(a) + _vcvtas_s32_f32(a) } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32) +#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(fcvtas))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtad_s64_f64(a: f64) -> i64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.v4i32.v4f32")] - fn vcvtnq_s32_f32_(a: float32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtas.i64.f64" + )] + fn _vcvtad_s64_f64(a: f64) -> i64; } - vcvtnq_s32_f32_(a) + _vcvtad_s64_f64(a) } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64) +#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtas_u32_f32(a: f32) -> u32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.v1i64.v1f64")] - fn vcvtn_s64_f64_(a: float64x1_t) -> int64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.i32.f32" + )] + fn _vcvtas_u32_f32(a: f32) -> i32; } - vcvtn_s64_f64_(a) + _vcvtas_u32_f32(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64) +#[doc = "Floating-point convert to integer, rounding to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtad_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(fcvtau))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtad_u64_f64(a: f64) -> u64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.v2i64.v2f64")] - fn vcvtnq_s64_f64_(a: float64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtau.i64.f64" + )] + fn _vcvtad_u64_f64(a: f64) -> i64; } - vcvtnq_s64_f64_(a) + _vcvtad_u64_f64(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.i32.f32")] - fn vcvtns_s32_f32_(a: f32) -> i32; - } - vcvtns_s32_f32_(a) +pub unsafe fn vcvtd_f64_s64(a: i64) -> f64 { + a as f64 } -/// Floating-point convert to signed integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtns))] +#[cfg_attr(test, assert_instr(scvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtns.i64.f64")] - fn vcvtnd_s64_f64_(a: f64) -> i64; - } - vcvtnd_s64_f64_(a) +pub unsafe fn vcvts_f32_s32(a: i32) -> f32 { + a as f32 } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtm_s32_f32(a: float32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.v2i32.v2f32")] - fn vcvtm_s32_f32_(a: float32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.v2i32.v2f32" + )] + fn _vcvtm_s32_f32(a: float32x2_t) -> int32x2_t; } - vcvtm_s32_f32_(a) + _vcvtm_s32_f32(a) } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.v4i32.v4f32")] - fn vcvtmq_s32_f32_(a: float32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.v4i32.v4f32" + )] + fn _vcvtmq_s32_f32(a: float32x4_t) -> int32x4_t; } - vcvtmq_s32_f32_(a) + _vcvtmq_s32_f32(a) } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtm_s64_f64(a: float64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.v1i64.v1f64")] - fn vcvtm_s64_f64_(a: float64x1_t) -> int64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.v1i64.v1f64" + )] + fn _vcvtm_s64_f64(a: float64x1_t) -> int64x1_t; } - vcvtm_s64_f64_(a) + _vcvtm_s64_f64(a) } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.v2i64.v2f64")] - fn vcvtmq_s64_f64_(a: float64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.v2i64.v2f64" + )] + fn _vcvtmq_s64_f64(a: float64x2_t) -> int64x2_t; } - vcvtmq_s64_f64_(a) + _vcvtmq_s64_f64(a) } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtms))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.i32.f32")] - fn vcvtms_s32_f32_(a: f32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.v2i32.v2f32" + )] + fn _vcvtm_u32_f32(a: float32x2_t) -> int32x2_t; } - vcvtms_s32_f32_(a) + _vcvtm_u32_f32(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtms))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtms.i64.f64")] - fn vcvtmd_s64_f64_(a: f64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.v4i32.v4f32" + )] + fn _vcvtmq_u32_f32(a: float32x4_t) -> int32x4_t; } - vcvtmd_s64_f64_(a) + _vcvtmq_u32_f32(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.v2i32.v2f32")] - fn vcvtp_s32_f32_(a: float32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.v1i64.v1f64" + )] + fn _vcvtm_u64_f64(a: float64x1_t) -> int64x1_t; } - vcvtp_s32_f32_(a) + _vcvtm_u64_f64(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.v4i32.v4f32")] - fn vcvtpq_s32_f32_(a: float32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.v2i64.v2f64" + )] + fn _vcvtmq_u64_f64(a: float64x2_t) -> int64x2_t; } - vcvtpq_s32_f32_(a) + _vcvtmq_u64_f64(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtms_s32_f32(a: f32) -> i32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.v1i64.v1f64")] - fn vcvtp_s64_f64_(a: float64x1_t) -> int64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.i32.f32" + )] + fn _vcvtms_s32_f32(a: f32) -> i32; } - vcvtp_s64_f64_(a) + _vcvtms_s32_f32(a) } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtms))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtmd_s64_f64(a: f64) -> i64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.v2i64.v2f64")] - fn vcvtpq_s64_f64_(a: float64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtms.i64.f64" + )] + fn _vcvtmd_s64_f64(a: f64) -> i64; } - vcvtpq_s64_f64_(a) + _vcvtmd_s64_f64(a) } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.i32.f32")] - fn vcvtps_s32_f32_(a: f32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.i32.f32" + )] + fn _vcvtms_u32_f32(a: f32) -> i32; } - vcvtps_s32_f32_(a) + _vcvtms_u32_f32(a).as_unsigned() } -/// Floating-point convert to signed integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtps))] +#[cfg_attr(test, assert_instr(fcvtmu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtps.i64.f64")] - fn vcvtpd_s64_f64_(a: f64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtmu.i64.f64" + )] + fn _vcvtmd_u64_f64(a: f64) -> i64; } - vcvtpd_s64_f64_(a) + _vcvtmd_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtau))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_u32_f32(a: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtn_s32_f32(a: float32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.v2i32.v2f32")] - fn vcvta_u32_f32_(a: float32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.v2i32.v2f32" + )] + fn _vcvtn_s32_f32(a: float32x2_t) -> int32x2_t; } - vcvta_u32_f32_(a) + _vcvtn_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtau))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_u32_f32(a: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.v4i32.v4f32")] - fn vcvtaq_u32_f32_(a: float32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.v4i32.v4f32" + )] + fn _vcvtnq_s32_f32(a: float32x4_t) -> int32x4_t; } - vcvtaq_u32_f32_(a) + _vcvtnq_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtau))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvta_u64_f64(a: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtn_s64_f64(a: float64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.v1i64.v1f64")] - fn vcvta_u64_f64_(a: float64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.v1i64.v1f64" + )] + fn _vcvtn_s64_f64(a: float64x1_t) -> int64x1_t; } - vcvta_u64_f64_(a) + _vcvtn_s64_f64(a) } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtau))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtaq_u64_f64(a: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtau.v2i64.v2f64")] - fn vcvtaq_u64_f64_(a: float64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.v2i64.v2f64" + )] + fn _vcvtnq_s64_f64(a: float64x2_t) -> int64x2_t; } - vcvtaq_u64_f64_(a) + _vcvtnq_s64_f64(a) } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtn_u32_f32(a: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.v2i32.v2f32")] - fn vcvtn_u32_f32_(a: float32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.v2i32.v2f32" + )] + fn _vcvtn_u32_f32(a: float32x2_t) -> int32x2_t; } - vcvtn_u32_f32_(a) + _vcvtn_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtnq_u32_f32(a: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.v4i32.v4f32")] - fn vcvtnq_u32_f32_(a: float32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.v4i32.v4f32" + )] + fn _vcvtnq_u32_f32(a: float32x4_t) -> int32x4_t; } - vcvtnq_u32_f32_(a) + _vcvtnq_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtn_u64_f64(a: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.v1i64.v1f64")] - fn vcvtn_u64_f64_(a: float64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.v1i64.v1f64" + )] + fn _vcvtn_u64_f64(a: float64x1_t) -> int64x1_t; } - vcvtn_u64_f64_(a) + _vcvtn_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtnq_u64_f64(a: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.v2i64.v2f64")] - fn vcvtnq_u64_f64_(a: float64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.v2i64.v2f64" + )] + fn _vcvtnq_u64_f64(a: float64x2_t) -> int64x2_t; } - vcvtnq_u64_f64_(a) + _vcvtnq_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtnu))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtns_s32_f32(a: f32) -> i32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.i32.f32")] - fn vcvtns_u32_f32_(a: f32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.i32.f32" + )] + fn _vcvtns_s32_f32(a: f32) -> i32; } - vcvtns_u32_f32_(a) + _vcvtns_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtnu))] +#[cfg_attr(test, assert_instr(fcvtns))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtnd_s64_f64(a: f64) -> i64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtnu.i64.f64")] - fn vcvtnd_u64_f64_(a: f64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtns.i64.f64" + )] + fn _vcvtnd_s64_f64(a: f64) -> i64; } - vcvtnd_u64_f64_(a) + _vcvtnd_s64_f64(a) } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_u32_f32(a: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtns_u32_f32(a: f32) -> u32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.v2i32.v2f32")] - fn vcvtm_u32_f32_(a: float32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.i32.f32" + )] + fn _vcvtns_u32_f32(a: f32) -> i32; } - vcvtm_u32_f32_(a) + _vcvtns_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnd_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtnu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_u32_f32(a: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtnd_u64_f64(a: f64) -> u64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.v4i32.v4f32")] - fn vcvtmq_u32_f32_(a: float32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtnu.i64.f64" + )] + fn _vcvtnd_u64_f64(a: f64) -> i64; } - vcvtmq_u32_f32_(a) + _vcvtnd_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtm_u64_f64(a: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtp_s32_f32(a: float32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.v1i64.v1f64")] - fn vcvtm_u64_f64_(a: float64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.v2i32.v2f32" + )] + fn _vcvtp_s32_f32(a: float32x2_t) -> int32x2_t; } - vcvtm_u64_f64_(a) + _vcvtp_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmq_u64_f64(a: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.v2i64.v2f64")] - fn vcvtmq_u64_f64_(a: float64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.v4i32.v4f32" + )] + fn _vcvtpq_s32_f32(a: float32x4_t) -> int32x4_t; } - vcvtmq_u64_f64_(a) + _vcvtpq_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtms_u32_f32(a: f32) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtp_s64_f64(a: float64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.i32.f32")] - fn vcvtms_u32_f32_(a: f32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.v1i64.v1f64" + )] + fn _vcvtp_s64_f64(a: float64x1_t) -> int64x1_t; } - vcvtms_u32_f32_(a) + _vcvtp_s64_f64(a) } -/// Floating-point convert to unsigned integer, rounding toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmd_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtmu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtmd_u64_f64(a: f64) -> u64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtmu.i64.f64")] - fn vcvtmd_u64_f64_(a: f64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.v2i64.v2f64" + )] + fn _vcvtpq_s64_f64(a: float64x2_t) -> int64x2_t; } - vcvtmd_u64_f64_(a) + _vcvtpq_s64_f64(a) } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtp_u32_f32(a: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.v2i32.v2f32")] - fn vcvtp_u32_f32_(a: float32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.v2i32.v2f32" + )] + fn _vcvtp_u32_f32(a: float32x2_t) -> int32x2_t; } - vcvtp_u32_f32_(a) + _vcvtp_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtpq_u32_f32(a: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.v4i32.v4f32")] - fn vcvtpq_u32_f32_(a: float32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.v4i32.v4f32" + )] + fn _vcvtpq_u32_f32(a: float32x4_t) -> int32x4_t; } - vcvtpq_u32_f32_(a) + _vcvtpq_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtp_u64_f64(a: float64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.v1i64.v1f64")] - fn vcvtp_u64_f64_(a: float64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.v1i64.v1f64" + )] + fn _vcvtp_u64_f64(a: float64x1_t) -> int64x1_t; } - vcvtp_u64_f64_(a) + _vcvtp_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtpq_u64_f64(a: float64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.v2i64.v2f64")] - fn vcvtpq_u64_f64_(a: float64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.v2i64.v2f64" + )] + fn _vcvtpq_u64_f64(a: float64x2_t) -> int64x2_t; } - vcvtpq_u64_f64_(a) + _vcvtpq_u64_f64(a).as_unsigned() } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtpu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtps_s32_f32(a: f32) -> i32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.i32.f32")] - fn vcvtps_u32_f32_(a: f32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.i32.f32" + )] + fn _vcvtps_s32_f32(a: f32) -> i32; } - vcvtps_u32_f32_(a) + _vcvtps_s32_f32(a) } -/// Floating-point convert to unsigned integer, rounding toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64) +#[doc = "Floating-point convert to signed integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtpu))] +#[cfg_attr(test, assert_instr(fcvtps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { - #[allow(improper_ctypes)] +pub unsafe fn vcvtpd_s64_f64(a: f64) -> i64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fcvtpu.i64.f64")] - fn vcvtpd_u64_f64_(a: f64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtps.i64.f64" + )] + fn _vcvtpd_s64_f64(a: f64) -> i64; } - vcvtpd_u64_f64_(a) + _vcvtpd_s64_f64(a) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(dup, N = 1))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +pub unsafe fn vcvtps_u32_f32(a: f32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.i32.f32" + )] + fn _vcvtps_u32_f32(a: f32) -> i32; + } + _vcvtps_u32_f32(a).as_unsigned() } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64) +#[doc = "Floating-point convert to unsigned integer, rounding toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpd_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(dup, N = 0))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtpu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { - static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) +pub unsafe fn vcvtpd_u64_f64(a: f64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtpu.i64.f64" + )] + fn _vcvtpd_u64_f64(a: f64) -> i64; + } + _vcvtpd_u64_f64(a).as_unsigned() } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(dup, N = 1))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +pub unsafe fn vcvts_f32_u32(a: u32) -> f32 { + a as f32 } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(dup, N = 0))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(ucvtf))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { - static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) -} +pub unsafe fn vcvtd_f64_u64(a: u64) -> f64 { + a as f64 +} -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 0))] +#[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { - static_assert!(N == 0); - a +pub unsafe fn vcvts_n_f32_s32(a: i32) -> f32 { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.f32.i32" + )] + fn _vcvts_n_f32_s32(a: i32, n: i32) -> f32; + } + _vcvts_n_f32_s32(a, N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 0))] +#[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { - static_assert!(N == 0); - a +pub unsafe fn vcvtd_n_f64_s64(a: i64) -> f64 { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.f64.i64" + )] + fn _vcvtd_n_f64_s64(a: i64, n: i32) -> f64; + } + _vcvtd_n_f64_s64(a, N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { - static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) +pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.f32.i32" + )] + fn _vcvts_n_f32_u32(a: i32, n: i32) -> f32; + } + _vcvts_n_f32_u32(a.as_signed(), N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { - static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) +pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.f64.i64" + )] + fn _vcvtd_n_f64_u64(a: i64, n: i32) -> f64; + } + _vcvtd_n_f64_u64(a.as_signed(), N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 4))] +#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_s8(a: int8x8_t) -> i8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) +pub unsafe fn vcvts_n_s32_f32(a: f32) -> i32 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.i32.f32" + )] + fn _vcvts_n_s32_f32(a: f32, n: i32) -> i32; + } + _vcvts_n_s32_f32(a, N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 8))] +#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_s8(a: int8x16_t) -> i8 { - static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) +pub unsafe fn vcvtd_n_s64_f64(a: f64) -> i64 { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.i64.f64" + )] + fn _vcvtd_n_s64_f64(a: f64, n: i32) -> i64; + } + _vcvtd_n_s64_f64(a, N) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_n_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] +#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_s16(a: int16x4_t) -> i16 { - static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) +pub unsafe fn vcvts_n_u32_f32(a: f32) -> u32 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.i32.f32" + )] + fn _vcvts_n_u32_f32(a: f32, n: i32) -> i32; + } + _vcvts_n_u32_f32(a, N).as_unsigned() } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_n_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 4))] +#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_s16(a: int16x8_t) -> i16 { - static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) +pub unsafe fn vcvtd_n_u64_f64(a: f64) -> u64 { + static_assert!(N >= 1 && N <= 64); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.i64.f64" + )] + fn _vcvtd_n_u64_f64(a: f64, n: i32) -> i64; + } + _vcvtd_n_u64_f64(a, N).as_unsigned() } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_s32(a: int32x2_t) -> i32 { - static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) +pub unsafe fn vcvts_s32_f32(a: f32) -> i32 { + a as i32 } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtzs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_s32(a: int32x4_t) -> i32 { - static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) +pub unsafe fn vcvtd_s64_f64(a: f64) -> i64 { + a as i64 } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 0))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_s64(a: int64x1_t) -> i64 { - static_assert!(N == 0); - simd_extract!(a, N as u32) +pub unsafe fn vcvts_u32_f32(a: f32) -> u32 { + a as u32 } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtd_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtzu))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_s64(a: int64x2_t) -> i64 { - static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) +pub unsafe fn vcvtd_u64_f64(a: f64) -> u64 { + a as u64 } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8) +#[doc = "Floating-point convert to lower precision narrow, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 4))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_u8(a: uint8x8_t) -> u8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) +pub unsafe fn vcvtx_f32_f64(a: float64x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fcvtxn.v2f32.v2f64" + )] + fn _vcvtx_f32_f64(a: float64x2_t) -> float32x2_t; + } + _vcvtx_f32_f64(a) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8) +#[doc = "Floating-point convert to lower precision narrow, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 8))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { - static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) +pub unsafe fn vcvtx_high_f32_f64(a: float32x2_t, b: float64x2_t) -> float32x4_t { + simd_shuffle!(a, vcvtx_f32_f64(b), [0, 1, 2, 3]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16) +#[doc = "Floating-point convert to lower precision narrow, rounding to odd"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtxd_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(fcvtxn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_u16(a: uint16x4_t) -> u16 { - static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) +pub unsafe fn vcvtxd_f32_f64(a: f64) -> f32 { + simd_extract!(vcvtx_f32_f64(vdupq_n_f64(a)), 0) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16) +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 4))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_u16(a: uint16x8_t) -> u16 { - static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) +#[cfg_attr(test, assert_instr(fdiv))] +pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_div(a, b) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32) +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_u32(a: uint32x2_t) -> u32 { - static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) +#[cfg_attr(test, assert_instr(fdiv))] +pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_div(a, b) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32) +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_u32(a: uint32x4_t) -> u32 { - static_assert_uimm_bits!(N, 2); - simd_extract!(a, N as u32) +#[cfg_attr(test, assert_instr(fdiv))] +pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + simd_div(a, b) +} + +#[doc = "Divide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fdiv))] +pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_div(a, b) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(test, assert_instr(sdot, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub unsafe fn vdot_laneq_s32( + a: int32x2_t, + b: int8x8_t, + c: int8x16_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(test, assert_instr(sdot, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub unsafe fn vdotq_laneq_s32( + a: int32x4_t, + b: int8x16_t, + c: int8x16_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x4_t = transmute(c); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(test, assert_instr(udot, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub unsafe fn vdot_laneq_u32( + a: uint32x2_t, + b: uint8x8_t, + c: uint8x16_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(test, assert_instr(udot, LANE = 0))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] +pub unsafe fn vdotq_laneq_u32( + a: uint32x4_t, + b: uint8x16_t, + c: uint8x16_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_u64(a: uint64x1_t) -> u64 { +pub unsafe fn vdup_lane_f64(a: float64x1_t) -> float64x1_t { static_assert!(N == 0); - simd_extract!(a, N as u32) + a } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(nop, N = 0))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { - static_assert_uimm_bits!(N, 1); - simd_extract!(a, N as u32) +pub unsafe fn vdup_lane_p64(a: poly64x1_t) -> poly64x1_t { + static_assert!(N == 0); + a } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 4))] +#[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_lane_p8(a: poly8x8_t) -> p8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(a, N as u32) +pub unsafe fn vdup_laneq_f64(a: float64x2_t) -> float64x1_t { + static_assert_uimm_bits!(N, 1); + transmute::(simd_extract!(a, N as u32)) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 8))] +#[cfg_attr(test, assert_instr(nop, N = 1))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { - static_assert_uimm_bits!(N, 4); - simd_extract!(a, N as u32) +pub unsafe fn vdup_laneq_p64(a: poly64x2_t) -> poly64x1_t { + static_assert_uimm_bits!(N, 1); + transmute::(simd_extract!(a, N as u32)) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] +#[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_lane_p16(a: poly16x4_t) -> p16 { - static_assert_uimm_bits!(N, 2); +pub unsafe fn vdupb_lane_s8(a: int8x8_t) -> i8 { + static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vduph_laneq_p16(a: poly16x8_t) -> p16 { +pub unsafe fn vduph_laneq_s16(a: int16x8_t) -> i16 { static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_lane_f32(a: float32x2_t) -> f32 { - static_assert_uimm_bits!(N, 1); +pub unsafe fn vdupb_lane_u8(a: uint8x8_t) -> u8 { + static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 2))] +#[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdups_laneq_f32(a: float32x4_t) -> f32 { - static_assert_uimm_bits!(N, 2); +pub unsafe fn vduph_laneq_u16(a: uint16x8_t) -> u16 { + static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 0))] +#[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_lane_f64(a: float64x1_t) -> f64 { - static_assert!(N == 0); +pub unsafe fn vdupb_lane_p8(a: poly8x8_t) -> p8 { + static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, N = 1))] +#[cfg_attr(test, assert_instr(nop, N = 4))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdupd_laneq_f64(a: float64x2_t) -> f64 { - static_assert_uimm_bits!(N, 1); +pub unsafe fn vduph_laneq_p16(a: poly16x8_t) -> p16 { + static_assert_uimm_bits!(N, 3); simd_extract!(a, N as u32) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(nop, N = 8))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } +pub unsafe fn vdupb_laneq_s8(a: int8x16_t) -> i8 { + static_assert_uimm_bits!(N, 4); + simd_extract!(a, N as u32) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(nop, N = 8))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } +pub unsafe fn vdupb_laneq_u8(a: uint8x16_t) -> u8 { + static_assert_uimm_bits!(N, 4); + simd_extract!(a, N as u32) } -/// Floating-point multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupb_laneq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] +#[cfg_attr(test, assert_instr(nop, N = 8))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - simd_add(a, simd_mul(b, c)) +pub unsafe fn vdupb_laneq_p8(a: poly8x16_t) -> p8 { + static_assert_uimm_bits!(N, 4); + simd_extract!(a, N as u32) } -/// Floating-point multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] +#[cfg_attr(test, assert_instr(nop, N = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - simd_add(a, simd_mul(b, c)) +pub unsafe fn vdupd_lane_f64(a: float64x1_t) -> f64 { + static_assert!(N == 0); + simd_extract!(a, N as u32) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(test, assert_instr(nop, N = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_s8(a, b, c) +pub unsafe fn vdupd_lane_s64(a: int64x1_t) -> i64 { + static_assert!(N == 0); + simd_extract!(a, N as u32) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(test, assert_instr(nop, N = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_s16(a, b, c) +pub unsafe fn vdupd_lane_u64(a: uint64x1_t) -> u64 { + static_assert!(N == 0); + simd_extract!(a, N as u32) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_s32(a, b, c) +pub unsafe fn vdupq_lane_f64(a: float64x1_t) -> float64x2_t { + static_assert!(N == 0); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(test, assert_instr(dup, N = 0))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlal_u8(a, b, c) +pub unsafe fn vdupq_lane_p64(a: poly64x1_t) -> poly64x2_t { + static_assert!(N == 0); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(test, assert_instr(dup, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlal_u16(a, b, c) +pub unsafe fn vdupq_laneq_f64(a: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(test, assert_instr(dup, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlal_u32(a, b, c) +pub unsafe fn vdupq_laneq_p64(a: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { - vmlal_high_s16(a, b, vdupq_n_s16(c)) +pub unsafe fn vdups_lane_f32(a: float32x2_t) -> f32 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2))] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { - vmlal_high_s32(a, b, vdupq_n_s32(c)) +pub unsafe fn vdupd_laneq_f64(a: float64x2_t) -> f64 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { - vmlal_high_u16(a, b, vdupq_n_u16(c)) +pub unsafe fn vdups_lane_s32(a: int32x2_t) -> i32 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2))] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { - vmlal_high_u32(a, b, vdupq_n_u32(c)) +pub unsafe fn vdupd_laneq_s64(a: int64x2_t) -> i64 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vdups_lane_u32(a: uint32x2_t) -> u32 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupd_laneq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 1))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlal_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vdupd_laneq_u64(a: uint64x2_t) -> u64 { + static_assert_uimm_bits!(N, 1); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vdups_laneq_f32(a: float32x4_t) -> f32 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vduph_lane_s16(a: int16x4_t) -> i16 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vdups_laneq_s32(a: int32x4_t) -> i32 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlal_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vduph_lane_u16(a: uint16x4_t) -> u16 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdups_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_lane_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vdups_laneq_u32(a: uint32x4_t) -> u32 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vduph_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(nop, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlal_high_laneq_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vduph_lane_p16(a: poly16x4_t) -> p16 { + static_assert_uimm_bits!(N, 2); + simd_extract!(a, N as u32) } -/// Floating-point multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - simd_sub(a, simd_mul(b, c)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3s.v16i8" + )] + fn _veor3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + _veor3q_s8(a, b, c) } -/// Floating-point multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - simd_sub(a, simd_mul(b, c)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3s.v8i16" + )] + fn _veor3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + _veor3q_s16(a, b, c) } -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_s8(a, b, c) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3s.v4i32" + )] + fn _veor3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _veor3q_s32(a, b, c) } -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_s16(a, b, c) -} - -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_s32(a, b, c) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3s.v2i64" + )] + fn _veor3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _veor3q_s64(a, b, c) } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - vmlsl_u8(a, b, c) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3u.v16i8" + )] + fn _veor3q_u8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; + } + _veor3q_u8(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - vmlsl_u16(a, b, c) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3u.v8i16" + )] + fn _veor3q_u16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + _veor3q_u16(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - vmlsl_u32(a, b, c) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3u.v4i32" + )] + fn _veor3q_u32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _veor3q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16) +#[doc = "Three-way exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor3q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { - vmlsl_high_s16(a, b, vdupq_n_s16(c)) +#[target_feature(enable = "neon,sha3")] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +#[cfg_attr(test, assert_instr(eor3))] +pub unsafe fn veor3q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.eor3u.v2i64" + )] + fn _veor3q_u64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _veor3q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2))] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { - vmlsl_high_s32(a, b, vdupq_n_s32(c)) +pub unsafe fn vextq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] +#[cfg_attr(test, assert_instr(ext, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { - vmlsl_high_u16(a, b, vdupq_n_u16(c)) +pub unsafe fn vextq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { - vmlsl_high_u32(a, b, vdupq_n_u32(c)) +#[cfg_attr(test, assert_instr(fmadd))] +pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.v1f64" + )] + fn _vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t; + } + _vfma_f64(b, c, a) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vfma_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlsl_high_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vfma_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { +pub unsafe fn vfmaq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) + vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { +pub unsafe fn vfmaq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - vmlsl_high_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) + vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vfmaq_laneq_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, +) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlsl_high_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vfma_lane_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, +) -> float64x1_t { + static_assert!(LANE == 0); + vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_lane_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x2_t) -> uint64x2_t { +pub unsafe fn vfma_laneq_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x2_t, +) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) + vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } -/// Multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] -#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmlsl_high_laneq_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_high_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(test, assert_instr(fmadd))] +pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { + vfma_f64(a, b, vdup_n_f64(c)) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - let c: int8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub unsafe fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.f64" + )] + fn _vfmad_lane_f64(a: f64, b: f64, c: f64) -> f64; + } + static_assert!(LANE == 0); + let c: f64 = simd_extract!(c, LANE as u32); + _vfmad_lane_f64(b, c, a) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - let c: int16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(fmla))] +pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.v2f64" + )] + fn _vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + } + _vfmaq_f64(b, c, a) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(test, assert_instr(fmla, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - let c: int32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) +pub unsafe fn vfmaq_lane_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x1_t, +) -> float64x2_t { + static_assert!(LANE == 0); + vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - let c: uint8x8_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(fmla))] +pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { + vfmaq_f64(a, b, vdupq_n_f64(c)) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - let c: uint16x4_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) +pub unsafe fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.f32" + )] + fn _vfmas_lane_f32(a: f32, b: f32, c: f32) -> f32; + } + static_assert_uimm_bits!(LANE, 1); + let c: f32 = simd_extract!(c, LANE as u32); + _vfmas_lane_f32(b, c, a) } -/// Extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(xtn2))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - let c: uint32x2_t = simd_cast(b); - simd_shuffle!(a, c, [0, 1, 2, 3]) +pub unsafe fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.f32" + )] + fn _vfmas_laneq_f32(a: f32, b: f32, c: f32) -> f32; + } + static_assert_uimm_bits!(LANE, 2); + let c: f32 = simd_extract!(c, LANE as u32); + _vfmas_laneq_f32(b, c, a) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64) +#[doc = "Floating-point fused multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(neg))] +#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { - simd_neg(a) +pub unsafe fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fma.f64" + )] + fn _vfmad_laneq_f64(a: f64, b: f64, c: f64) -> f64; + } + static_assert_uimm_bits!(LANE, 1); + let c: f64 = simd_extract!(c, LANE as u32); + _vfmad_laneq_f64(b, c, a) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64) +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(neg))] +#[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { - simd_neg(a) +pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + let b: float64x1_t = simd_neg(b); + vfma_f64(a, b, c) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(neg))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vnegd_s64(a: i64) -> i64 { - a.wrapping_neg() +pub unsafe fn vfms_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fneg))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { - simd_neg(a) +pub unsafe fn vfms_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fneg))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { - simd_neg(a) +pub unsafe fn vfmsq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v1i64")] - fn vqneg_s64_(a: int64x1_t) -> int64x1_t; - } - vqneg_s64_(a) +pub unsafe fn vfmsq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v2i64")] - fn vqnegq_s64_(a: int64x2_t) -> int64x2_t; - } - vqnegq_s64_(a) +pub unsafe fn vfmsq_laneq_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, +) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqnegb_s8(a: i8) -> i8 { - simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) +pub unsafe fn vfms_lane_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, +) -> float64x1_t { + static_assert!(LANE == 0); + vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqnegh_s16(a: i16) -> i16 { - simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) +pub unsafe fn vfms_laneq_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x2_t, +) -> float64x1_t { + static_assert_uimm_bits!(LANE, 1); + vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32) +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqnegs_s32(a: i32) -> i32 { - simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) +pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { + vfms_f64(a, b, vdup_n_f64(c)) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64) +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqneg))] +#[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqnegd_s64(a: i64) -> i64 { - simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) +pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + let b: float64x2_t = simd_neg(b); + vfmaq_f64(a, b, c) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqsub))] +#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { - let a: int8x8_t = vdup_n_s8(a); - let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqsub_s8(a, b), 0) +pub unsafe fn vfmsq_lane_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x1_t, +) -> float64x2_t { + static_assert!(LANE == 0); + vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16) +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqsub))] +#[cfg_attr(test, assert_instr(fmls))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqsub_s16(a, b), 0) +pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { + vfmsq_f64(a, b, vdupq_n_f64(c)) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqsub))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { - let a: uint8x8_t = vdup_n_u8(a); - let b: uint8x8_t = vdup_n_u8(b); - simd_extract!(vqsub_u8(a, b), 0) +pub unsafe fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { + vfmas_lane_f32::(a, -b, c) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqsub))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { - let a: uint16x4_t = vdup_n_u16(a); - let b: uint16x4_t = vdup_n_u16(b); - simd_extract!(vqsub_u16(a, b), 0) +pub unsafe fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { + vfmas_laneq_f32::(a, -b, c) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqsub))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.i32")] - fn vqsubs_u32_(a: u32, b: u32) -> u32; - } - vqsubs_u32_(a, b) +pub unsafe fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { + vfmad_lane_f64::(a, -b, c) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64) +#[doc = "Floating-point fused multiply-subtract to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqsub))] +#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.i64")] - fn vqsubd_u64_(a: u64, b: u64) -> u64; - } - vqsubd_u64_(a, b) +pub unsafe fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { + vfmad_laneq_f64::(a, -b, c) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.i32")] - fn vqsubs_s32_(a: i32, b: i32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0f64" + )] + fn _vld1_f64_x2(a: *const f64) -> float64x1x2_t; } - vqsubs_s32_(a, b) + _vld1_f64_x2(a) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqsub))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.i64")] - fn vqsubd_s64_(a: i64, b: i64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0f64" + )] + fn _vld1_f64_x3(a: *const f64) -> float64x1x3_t; } - vqsubd_s64_(a, b) + _vld1_f64_x3(a) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rbit.v8i8")] - fn vrbit_s8_(a: int8x8_t) -> int8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0f64" + )] + fn _vld1_f64_x4(a: *const f64) -> float64x1x4_t; } - vrbit_s8_(a) + _vld1_f64_x4(a) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rbit.v16i8")] - fn vrbitq_s8_(a: int8x16_t) -> int8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0f64" + )] + fn _vld1q_f64_x2(a: *const f64) -> float64x2x2_t; } - vrbitq_s8_(a) + _vld1q_f64_x2(a) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { - transmute(vrbit_s8(transmute(a))) +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0f64" + )] + fn _vld1q_f64_x3(a: *const f64) -> float64x2x3_t; + } + _vld1q_f64_x3(a) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { - transmute(vrbitq_s8(transmute(a))) +#[cfg_attr(test, assert_instr(ld1))] +pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0f64" + )] + fn _vld1q_f64_x4(a: *const f64) -> float64x2x4_t; + } + _vld1q_f64_x4(a) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { - transmute(vrbit_s8(transmute(a))) +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v1f64.p0f64" + )] + fn _vld2_dup_f64(ptr: *const f64) -> float64x1x2_t; + } + _vld2_dup_f64(a as _) } -/// Reverse bit order -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rbit))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { - transmute(vrbitq_s8(transmute(a))) +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2f64.p0f64" + )] + fn _vld2q_dup_f64(ptr: *const f64) -> float64x2x2_t; + } + _vld2q_dup_f64(a as _) } -/// Floating-point round to integral exact, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.rint.v2f32")] - fn vrndx_f32_(a: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2i64.p0i64" + )] + fn _vld2q_dup_s64(ptr: *const i64) -> int64x2x2_t; } - vrndx_f32_(a) + _vld2q_dup_s64(a as _) } -/// Floating-point round to integral exact, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.rint.v4f32")] - fn vrndxq_f32_(a: float32x4_t) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v1f64.p0v1f64" + )] + fn _vld2_f64(ptr: *const float64x1_t) -> float64x1x2_t; } - vrndxq_f32_(a) + _vld2_f64(a as _) } -/// Floating-point round to integral exact, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintx))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> float64x1x2_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.rint.v1f64")] - fn vrndx_f64_(a: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v1f64.p0i8" + )] + fn _vld2_lane_f64(a: float64x1_t, b: float64x1_t, n: i64, ptr: *const i8) -> float64x1x2_t; } - vrndx_f64_(a) + _vld2_lane_f64(b.0, b.1, LANE as i64, a as _) } -/// Floating-point round to integral exact, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintx))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> int64x1x2_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.rint.v2f64")] - fn vrndxq_f64_(a: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v1i64.p0i8" + )] + fn _vld2_lane_s64(a: int64x1_t, b: int64x1_t, n: i64, ptr: *const i8) -> int64x1x2_t; } - vrndxq_f64_(a) + _vld2_lane_s64(b.0, b.1, LANE as i64, a as _) } -/// Floating-point round to integral, to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinta))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.round.v2f32")] - fn vrnda_f32_(a: float32x2_t) -> float32x2_t; - } - vrnda_f32_(a) +pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> poly64x1x2_t { + static_assert!(LANE == 0); + transmute(vld2_lane_s64::(transmute(a), transmute(b))) } -/// Floating-point round to integral, to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinta))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.round.v4f32")] - fn vrndaq_f32_(a: float32x4_t) -> float32x4_t; - } - vrndaq_f32_(a) +pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> uint64x1x2_t { + static_assert!(LANE == 0); + transmute(vld2_lane_s64::(transmute(a), transmute(b))) } -/// Floating-point round to integral, to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinta))] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.round.v1f64")] - fn vrnda_f64_(a: float64x1_t) -> float64x1_t; - } - vrnda_f64_(a) +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { + transmute(vld2q_dup_s64(transmute(a))) } -/// Floating-point round to integral, to nearest with ties to away -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinta))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.round.v2f64")] - fn vrndaq_f64_(a: float64x2_t) -> float64x2_t; - } - vrndaq_f64_(a) +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { + transmute(vld2q_dup_s64(transmute(a))) } -/// Floating-point round to integral, to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frintn.v1f64")] - fn vrndn_f64_(a: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v2f64.p0v2f64" + )] + fn _vld2q_f64(ptr: *const float64x2_t) -> float64x2x2_t; } - vrndn_f64_(a) + _vld2q_f64(a as _) } -/// Floating-point round to integral, to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintn))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frintn.v2f64")] - fn vrndnq_f64_(a: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v2i64.p0v2i64" + )] + fn _vld2q_s64(ptr: *const int64x2_t) -> int64x2x2_t; } - vrndnq_f64_(a) + _vld2q_s64(a as _) } -/// Floating-point round to integral, to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintn))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndns_f32(a: f32) -> f32 { - #[allow(improper_ctypes)] +pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) -> float64x2x2_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.roundeven.f32")] - fn vrndns_f32_(a: f32) -> f32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2f64.p0i8" + )] + fn _vld2q_lane_f64(a: float64x2_t, b: float64x2_t, n: i64, ptr: *const i8) + -> float64x2x2_t; } - vrndns_f32_(a) + _vld2q_lane_f64(b.0, b.1, LANE as i64, a as _) } -/// Floating-point round to integral, toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintm))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> int8x16x2_t { + static_assert_uimm_bits!(LANE, 4); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.floor.v2f32")] - fn vrndm_f32_(a: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v16i8.p0i8" + )] + fn _vld2q_lane_s8(a: int8x16_t, b: int8x16_t, n: i64, ptr: *const i8) -> int8x16x2_t; } - vrndm_f32_(a) + _vld2q_lane_s8(b.0, b.1, LANE as i64, a as _) } -/// Floating-point round to integral, toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintm))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> int64x2x2_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.floor.v4f32")] - fn vrndmq_f32_(a: float32x4_t) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2i64.p0i8" + )] + fn _vld2q_lane_s64(a: int64x2_t, b: int64x2_t, n: i64, ptr: *const i8) -> int64x2x2_t; } - vrndmq_f32_(a) + _vld2q_lane_s64(b.0, b.1, LANE as i64, a as _) } -/// Floating-point round to integral, toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintm))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.floor.v1f64")] - fn vrndm_f64_(a: float64x1_t) -> float64x1_t; - } - vrndm_f64_(a) +pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> poly64x2x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld2q_lane_s64::(transmute(a), transmute(b))) } -/// Floating-point round to integral, toward minus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintm))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.floor.v2f64")] - fn vrndmq_f64_(a: float64x2_t) -> float64x2_t; - } - vrndmq_f64_(a) +pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> uint8x16x2_t { + static_assert_uimm_bits!(LANE, 4); + transmute(vld2q_lane_s8::(transmute(a), transmute(b))) } -/// Floating-point round to integral, toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintp))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.ceil.v2f32")] - fn vrndp_f32_(a: float32x2_t) -> float32x2_t; - } - vrndp_f32_(a) +pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> uint64x2x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld2q_lane_s64::(transmute(a), transmute(b))) } -/// Floating-point round to integral, toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintp))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.ceil.v4f32")] - fn vrndpq_f32_(a: float32x4_t) -> float32x4_t; - } - vrndpq_f32_(a) +pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> poly8x16x2_t { + static_assert_uimm_bits!(LANE, 4); + transmute(vld2q_lane_s8::(transmute(a), transmute(b))) } -/// Floating-point round to integral, toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintp))] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.ceil.v1f64")] - fn vrndp_f64_(a: float64x1_t) -> float64x1_t; - } - vrndp_f64_(a) +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { + transmute(vld2q_s64(transmute(a))) } -/// Floating-point round to integral, toward plus infinity -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.ceil.v2f64")] - fn vrndpq_f64_(a: float64x2_t) -> float64x2_t; - } - vrndpq_f64_(a) +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { + transmute(vld2q_s64(transmute(a))) } -/// Floating-point round to integral, toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintz))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.trunc.v2f32")] - fn vrnd_f32_(a: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v1f64.p0f64" + )] + fn _vld3_dup_f64(ptr: *const f64) -> float64x1x3_t; } - vrnd_f32_(a) + _vld3_dup_f64(a as _) } -/// Floating-point round to integral, toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintz))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.trunc.v4f32")] - fn vrndq_f32_(a: float32x4_t) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2f64.p0f64" + )] + fn _vld3q_dup_f64(ptr: *const f64) -> float64x2x3_t; } - vrndq_f32_(a) + _vld3q_dup_f64(a as _) } -/// Floating-point round to integral, toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintz))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.trunc.v1f64")] - fn vrnd_f64_(a: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2i64.p0i64" + )] + fn _vld3q_dup_s64(ptr: *const i64) -> int64x2x3_t; } - vrnd_f64_(a) + _vld3q_dup_s64(a as _) } -/// Floating-point round to integral, toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frintz))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.trunc.v2f64")] - fn vrndq_f64_(a: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v1f64.p0v1f64" + )] + fn _vld3_f64(ptr: *const float64x1_t) -> float64x1x3_t; } - vrndq_f64_(a) + _vld3_f64(a as _) } -/// Floating-point round to integral, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinti))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> float64x1x3_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.nearbyint.v2f32")] - fn vrndi_f32_(a: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v1f64.p0i8" + )] + fn _vld3_lane_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, + n: i64, + ptr: *const i8, + ) -> float64x1x3_t; } - vrndi_f32_(a) + _vld3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Floating-point round to integral, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinti))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.nearbyint.v4f32")] - fn vrndiq_f32_(a: float32x4_t) -> float32x4_t; - } - vrndiq_f32_(a) +pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> poly64x1x3_t { + static_assert!(LANE == 0); + transmute(vld3_lane_s64::(transmute(a), transmute(b))) } -/// Floating-point round to integral, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinti))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> int64x1x3_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.nearbyint.v1f64")] - fn vrndi_f64_(a: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v1i64.p0i8" + )] + fn _vld3_lane_s64( + a: int64x1_t, + b: int64x1_t, + c: int64x1_t, + n: i64, + ptr: *const i8, + ) -> int64x1x3_t; } - vrndi_f64_(a) + _vld3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Floating-point round to integral, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frinti))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.nearbyint.v2f64")] - fn vrndiq_f64_(a: float64x2_t) -> float64x2_t; - } - vrndiq_f64_(a) +pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> uint64x1x3_t { + static_assert!(LANE == 0); + transmute(vld3_lane_s64::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqadd))] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { - let a: int8x8_t = vdup_n_s8(a); - let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqadd_s8(a, b), 0) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { + transmute(vld3q_dup_s64(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqadd_s16(a, b), 0) +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { + transmute(vld3q_dup_s64(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { - let a: uint8x8_t = vdup_n_u8(a); - let b: uint8x8_t = vdup_n_u8(b); - simd_extract!(vqadd_u8(a, b), 0) +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v2f64.p0v2f64" + )] + fn _vld3q_f64(ptr: *const float64x2_t) -> float64x2x3_t; + } + _vld3q_f64(a as _) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { - let a: uint16x4_t = vdup_n_u16(a); - let b: uint16x4_t = vdup_n_u16(b); - simd_extract!(vqadd_u16(a, b), 0) +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v2i64.p0v2i64" + )] + fn _vld3q_s64(ptr: *const int64x2_t) -> int64x2x3_t; + } + _vld3q_s64(a as _) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqadd))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) -> float64x2x3_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.i32")] - fn vqadds_u32_(a: u32, b: u32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v2f64.p0i8" + )] + fn _vld3q_lane_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, + n: i64, + ptr: *const i8, + ) -> float64x2x3_t; } - vqadds_u32_(a, b) + _vld3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqadd))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.i64")] - fn vqaddd_u64_(a: u64, b: u64) -> u64; - } - vqaddd_u64_(a, b) +pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> poly64x2x3_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld3q_lane_s64::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqadd))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { - #[allow(improper_ctypes)] +pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> int8x16x3_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.i32")] - fn vqadds_s32_(a: i32, b: i32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v16i8.p0i8" + )] + fn _vld3q_lane_s8( + a: int8x16_t, + b: int8x16_t, + c: int8x16_t, + n: i64, + ptr: *const i8, + ) -> int8x16x3_t; } - vqadds_s32_(a, b) + _vld3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqadd))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { - #[allow(improper_ctypes)] +pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> int64x2x3_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.i64")] - fn vqaddd_s64_(a: i64, b: i64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v2i64.p0i8" + )] + fn _vld3q_lane_s64( + a: int64x2_t, + b: int64x2_t, + c: int64x2_t, + n: i64, + ptr: *const i8, + ) -> int64x2x3_t; } - vqaddd_s64_(a, b) + _vld3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1_f64_x2(a: *const f64) -> float64x1x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v1f64.p0f64")] - fn vld1_f64_x2_(a: *const f64) -> float64x1x2_t; - } - vld1_f64_x2_(a) +pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> uint8x16x3_t { + static_assert_uimm_bits!(LANE, 4); + transmute(vld3q_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1q_f64_x2(a: *const f64) -> float64x2x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v2f64.p0f64")] - fn vld1q_f64_x2_(a: *const f64) -> float64x2x2_t; - } - vld1q_f64_x2_(a) +pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> uint64x2x3_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld3q_lane_s64::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1_f64_x3(a: *const f64) -> float64x1x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v1f64.p0f64")] - fn vld1_f64_x3_(a: *const f64) -> float64x1x3_t; - } - vld1_f64_x3_(a) +pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> poly8x16x3_t { + static_assert_uimm_bits!(LANE, 4); + transmute(vld3q_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1q_f64_x3(a: *const f64) -> float64x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v2f64.p0f64")] - fn vld1q_f64_x3_(a: *const f64) -> float64x2x3_t; - } - vld1q_f64_x3_(a) +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { + transmute(vld3q_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1_f64_x4(a: *const f64) -> float64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v1f64.p0f64")] - fn vld1_f64_x4_(a: *const f64) -> float64x1x4_t; - } - vld1_f64_x4_(a) +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { + transmute(vld3q_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64_x4) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld1))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld1q_f64_x4(a: *const f64) -> float64x2x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v2f64.p0f64")] - fn vld1q_f64_x4_(a: *const f64) -> float64x2x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v1f64.p0f64" + )] + fn _vld4_dup_f64(ptr: *const f64) -> float64x1x4_t; } - vld1q_f64_x4_(a) + _vld4_dup_f64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_s64(a: *const i64) -> int64x2x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v2i64.p0v2i64")] - fn vld2q_s64_(ptr: *const int64x2_t) -> int64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v2f64.p0f64" + )] + fn _vld4q_dup_f64(ptr: *const f64) -> float64x2x4_t; } - vld2q_s64_(a as _) + _vld4q_dup_f64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_u64(a: *const u64) -> uint64x2x2_t { - transmute(vld2q_s64(transmute(a))) +pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v2i64.p0i64" + )] + fn _vld4q_dup_s64(ptr: *const i64) -> int64x2x4_t; + } + _vld4q_dup_s64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld2))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_p64(a: *const p64) -> poly64x2x2_t { - transmute(vld2q_s64(transmute(a))) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v1f64.p0v1f64" + )] + fn _vld4_f64(ptr: *const float64x1_t) -> float64x1x4_t; + } + _vld4_f64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_f64(a: *const f64) -> float64x1x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> float64x1x4_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v1f64.p0v1f64")] - fn vld2_f64_(ptr: *const float64x1_t) -> float64x1x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v1f64.p0i8" + )] + fn _vld4_lane_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, + d: float64x1_t, + n: i64, + ptr: *const i8, + ) -> float64x1x4_t; } - vld2_f64_(a as _) + _vld4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_f64(a: *const f64) -> float64x2x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> int64x1x4_t { + static_assert!(LANE == 0); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v2f64.p0v2f64")] - fn vld2q_f64_(ptr: *const float64x2_t) -> float64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v1i64.p0i8" + )] + fn _vld4_lane_s64( + a: int64x1_t, + b: int64x1_t, + c: int64x1_t, + d: int64x1_t, + n: i64, + ptr: *const i8, + ) -> int64x1x4_t; } - vld2q_f64_(a as _) + _vld4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_s64(a: *const i64) -> int64x2x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v2i64.p0i64")] - fn vld2q_dup_s64_(ptr: *const i64) -> int64x2x2_t; - } - vld2q_dup_s64_(a as _) +pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> poly64x1x4_t { + static_assert!(LANE == 0); + transmute(vld4_lane_s64::(transmute(a), transmute(b))) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_u64(a: *const u64) -> uint64x2x2_t { - transmute(vld2q_dup_s64(transmute(a))) +pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> uint64x1x4_t { + static_assert!(LANE == 0); + transmute(vld4_lane_s64::(transmute(a), transmute(b))) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_p64(a: *const p64) -> poly64x2x2_t { - transmute(vld2q_dup_s64(transmute(a))) +pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { + transmute(vld4q_dup_s64(transmute(a))) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_f64(a: *const f64) -> float64x1x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v1f64.p0f64")] - fn vld2_dup_f64_(ptr: *const f64) -> float64x1x2_t; - } - vld2_dup_f64_(a as _) +pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { + transmute(vld4q_dup_s64(transmute(a))) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_f64(a: *const f64) -> float64x2x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v2f64.p0f64")] - fn vld2q_dup_f64_(ptr: *const f64) -> float64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v2f64.p0v2f64" + )] + fn _vld4q_f64(ptr: *const float64x2_t) -> float64x2x4_t; } - vld2q_dup_f64_(a as _) + _vld4q_f64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s8(a: *const i8, b: int8x16x2_t) -> int8x16x2_t { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v16i8.p0i8")] - fn vld2q_lane_s8_(a: int8x16_t, b: int8x16_t, n: i64, ptr: *const i8) -> int8x16x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v2i64.p0v2i64" + )] + fn _vld4q_s64(ptr: *const int64x2_t) -> int64x2x4_t; } - vld2q_lane_s8_(b.0, b.1, LANE as i64, a as _) + _vld4q_s64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s64(a: *const i64, b: int64x1x2_t) -> int64x1x2_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] +pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) -> float64x2x4_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v1i64.p0i8")] - fn vld2_lane_s64_(a: int64x1_t, b: int64x1_t, n: i64, ptr: *const i8) -> int64x1x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2f64.p0i8" + )] + fn _vld4q_lane_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, + d: float64x2_t, + n: i64, + ptr: *const i8, + ) -> float64x2x4_t; } - vld2_lane_s64_(b.0, b.1, LANE as i64, a as _) + _vld4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s64(a: *const i64, b: int64x2x2_t) -> int64x2x2_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> int8x16x4_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v2i64.p0i8")] - fn vld2q_lane_s64_(a: int64x2_t, b: int64x2_t, n: i64, ptr: *const i8) -> int64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v16i8.p0i8" + )] + fn _vld4q_lane_s8( + a: int8x16_t, + b: int8x16_t, + c: int8x16_t, + d: int8x16_t, + n: i64, + ptr: *const i8, + ) -> int8x16x4_t; } - vld2q_lane_s64_(b.0, b.1, LANE as i64, a as _) + _vld4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_p64(a: *const p64, b: poly64x1x2_t) -> poly64x1x2_t { - static_assert!(LANE == 0); - transmute(vld2_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> int64x2x4_t { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2i64.p0i8" + )] + fn _vld4q_lane_s64( + a: int64x2_t, + b: int64x2_t, + c: int64x2_t, + d: int64x2_t, + n: i64, + ptr: *const i8, + ) -> int64x2x4_t; + } + _vld4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_p64(a: *const p64, b: poly64x2x2_t) -> poly64x2x2_t { +pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> poly64x2x4_t { static_assert_uimm_bits!(LANE, 1); - transmute(vld2q_lane_s64::(transmute(a), transmute(b))) + transmute(vld4q_lane_s64::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_u8(a: *const u8, b: uint8x16x2_t) -> uint8x16x2_t { +pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> uint8x16x4_t { static_assert_uimm_bits!(LANE, 4); - transmute(vld2q_lane_s8::(transmute(a), transmute(b))) + transmute(vld4q_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_u64(a: *const u64, b: uint64x1x2_t) -> uint64x1x2_t { - static_assert!(LANE == 0); - transmute(vld2_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> uint64x2x4_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld4q_lane_s64::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_u64(a: *const u64, b: uint64x2x2_t) -> uint64x2x2_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld2q_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> poly8x16x4_t { + static_assert_uimm_bits!(LANE, 4); + transmute(vld4q_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_p8(a: *const p8, b: poly8x16x2_t) -> poly8x16x2_t { - static_assert_uimm_bits!(LANE, 4); - transmute(vld2q_lane_s8::(transmute(a), transmute(b))) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { + transmute(vld4q_s64(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_f64(a: *const f64, b: float64x1x2_t) -> float64x1x2_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v1f64.p0i8")] - fn vld2_lane_f64_(a: float64x1_t, b: float64x1_t, n: i64, ptr: *const i8) -> float64x1x2_t; - } - vld2_lane_f64_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { + transmute(vld4q_s64(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f64) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_f64(a: *const f64, b: float64x2x2_t) -> float64x2x2_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fmax))] +pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v2f64.p0i8")] - fn vld2q_lane_f64_(a: float64x2_t, b: float64x2_t, n: i64, ptr: *const i8) -> float64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v1f64" + )] + fn _vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - vld2q_lane_f64_(b.0, b.1, LANE as i64, a as _) + _vmax_f64(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s64) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_s64(a: *const i64) -> int64x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fmax))] +pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v2i64.p0v2i64")] - fn vld3q_s64_(ptr: *const int64x2_t) -> int64x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v2f64" + )] + fn _vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - vld3q_s64_(a as _) + _vmaxq_f64(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u64) +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_u64(a: *const u64) -> uint64x2x3_t { - transmute(vld3q_s64(transmute(a))) +#[cfg_attr(test, assert_instr(fmaxnm))] +pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v1f64" + )] + fn _vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + _vmaxnm_f64(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p64) +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld3))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_p64(a: *const p64) -> poly64x2x3_t { - transmute(vld3q_s64(transmute(a))) +#[cfg_attr(test, assert_instr(fmaxnm))] +pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f64" + )] + fn _vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vmaxnmq_f64(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f64) +#[doc = "Floating-point maximum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_f64(a: *const f64) -> float64x1x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub unsafe fn vmaxnmv_f32(a: float32x2_t) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v1f64.p0v1f64")] - fn vld3_f64_(ptr: *const float64x1_t) -> float64x1x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vmaxnmv_f32(a: float32x2_t) -> f32; } - vld3_f64_(a as _) + _vmaxnmv_f32(a) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f64) +#[doc = "Floating-point maximum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_f64(a: *const f64) -> float64x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fmaxnmp))] +pub unsafe fn vmaxnmvq_f64(a: float64x2_t) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v2f64.p0v2f64")] - fn vld3q_f64_(ptr: *const float64x2_t) -> float64x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vmaxnmvq_f64(a: float64x2_t) -> f64; } - vld3q_f64_(a as _) + _vmaxnmvq_f64(a) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s64) +#[doc = "Floating-point maximum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_s64(a: *const i64) -> int64x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fmaxnmv))] +pub unsafe fn vmaxnmvq_f32(a: float32x4_t) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v2i64.p0i64")] - fn vld3q_dup_s64_(ptr: *const i64) -> int64x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32" + )] + fn _vmaxnmvq_f32(a: float32x4_t) -> f32; } - vld3q_dup_s64_(a as _) + _vmaxnmvq_f32(a) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u64) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_u64(a: *const u64) -> uint64x2x3_t { - transmute(vld3q_dup_s64(transmute(a))) +#[cfg_attr(test, assert_instr(fmin))] +pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v1f64" + )] + fn _vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + _vmin_f64(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p64) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld3r))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_p64(a: *const p64) -> poly64x2x3_t { - transmute(vld3q_dup_s64(transmute(a))) +#[cfg_attr(test, assert_instr(fmin))] +pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v2f64" + )] + fn _vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vminq_f64(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f64) +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_f64(a: *const f64) -> float64x1x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fminnm))] +pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v1f64.p0f64")] - fn vld3_dup_f64_(ptr: *const f64) -> float64x1x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v1f64" + )] + fn _vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - vld3_dup_f64_(a as _) + _vminnm_f64(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f64) +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_f64(a: *const f64) -> float64x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fminnm))] +pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v2f64.p0f64")] - fn vld3q_dup_f64_(ptr: *const f64) -> float64x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f64" + )] + fn _vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - vld3q_dup_f64_(a as _) + _vminnmq_f64(a, b) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s8) +#[doc = "Floating-point minimum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s8(a: *const i8, b: int8x16x3_t) -> int8x16x3_t { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] +pub unsafe fn vminnmv_f32(a: float32x2_t) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v16i8.p0i8")] - fn vld3q_lane_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, n: i64, ptr: *const i8) -> int8x16x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vminnmv_f32(a: float32x2_t) -> f32; } - vld3q_lane_s8_(b.0, b.1, b.2, LANE as i64, a as _) + _vminnmv_f32(a) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s64) +#[doc = "Floating-point minimum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s64(a: *const i64, b: int64x1x3_t) -> int64x1x3_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] +pub unsafe fn vminnmvq_f64(a: float64x2_t) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v1i64.p0i8")] - fn vld3_lane_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, n: i64, ptr: *const i8) -> int64x1x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vminnmvq_f64(a: float64x2_t) -> f64; } - vld3_lane_s64_(b.0, b.1, b.2, LANE as i64, a as _) + _vminnmvq_f64(a) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s64) +#[doc = "Floating-point minimum number across vector"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fminnmv))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s64(a: *const i64, b: int64x2x3_t) -> int64x2x3_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v2i64.p0i8")] - fn vld3q_lane_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, n: i64, ptr: *const i8) -> int64x2x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32" + )] + fn _vminnmvq_f32(a: float32x4_t) -> f32; } - vld3q_lane_s64_(b.0, b.1, b.2, LANE as i64, a as _) + _vminnmvq_f32(a) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p64) +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_p64(a: *const p64, b: poly64x1x3_t) -> poly64x1x3_t { - static_assert!(LANE == 0); - transmute(vld3_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vmla_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p64) +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_p64(a: *const p64, b: poly64x2x3_t) -> poly64x2x3_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld3q_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p8) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_p8(a: *const p8, b: poly8x16x3_t) -> poly8x16x3_t { - static_assert_uimm_bits!(LANE, 4); - transmute(vld3q_lane_s8::(transmute(a), transmute(b))) -} - -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u8) +pub unsafe fn vmlal_high_lane_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_u8(a: *const u8, b: uint8x16x3_t) -> uint8x16x3_t { - static_assert_uimm_bits!(LANE, 4); - transmute(vld3q_lane_s8::(transmute(a), transmute(b))) -} - -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u64) +pub unsafe fn vmlal_high_laneq_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_u64(a: *const u64, b: uint64x1x3_t) -> uint64x1x3_t { - static_assert!(LANE == 0); - transmute(vld3_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vmlal_high_lane_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlal_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_u64(a: *const u64, b: uint64x2x3_t) -> uint64x2x3_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld3q_lane_s64::(transmute(a), transmute(b))) +pub unsafe fn vmlal_high_laneq_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_f64(a: *const f64, b: float64x1x3_t) -> float64x1x3_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v1f64.p0i8")] - fn vld3_lane_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, n: i64, ptr: *const i8) -> float64x1x3_t; - } - vld3_lane_f64_(b.0, b.1, b.2, LANE as i64, a as _) -} - -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f64) +pub unsafe fn vmlal_high_lane_u16( + a: uint32x4_t, + b: uint16x8_t, + c: uint16x4_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_f64(a: *const f64, b: float64x2x3_t) -> float64x2x3_t { +pub unsafe fn vmlal_high_laneq_u16( + a: uint32x4_t, + b: uint16x8_t, + c: uint16x8_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vmlal_high_lane_u32( + a: uint64x2_t, + b: uint32x4_t, + c: uint32x2_t, +) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v2f64.p0i8")] - fn vld3q_lane_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, n: i64, ptr: *const i8) -> float64x2x3_t; - } - vld3q_lane_f64_(b.0, b.1, b.2, LANE as i64, a as _) + vmlal_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] +#[cfg_attr(test, assert_instr(umlal2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_s64(a: *const i64) -> int64x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v2i64.p0v2i64")] - fn vld4q_s64_(ptr: *const int64x2_t) -> int64x2x4_t; - } - vld4q_s64_(a as _) +pub unsafe fn vmlal_high_laneq_u32( + a: uint64x2_t, + b: uint32x4_t, + c: uint32x4_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] +#[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_u64(a: *const u64) -> uint64x2x4_t { - transmute(vld4q_s64(transmute(a))) +pub unsafe fn vmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { + vmlal_high_s16(a, b, vdupq_n_s16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_p64(a: *const p64) -> poly64x2x4_t { - transmute(vld4q_s64(transmute(a))) +pub unsafe fn vmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { + vmlal_high_s32(a, b, vdupq_n_s32(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_f64(a: *const f64) -> float64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v1f64.p0v1f64")] - fn vld4_f64_(ptr: *const float64x1_t) -> float64x1x4_t; - } - vld4_f64_(a as _) +pub unsafe fn vmlal_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { + vmlal_high_u16(a, b, vdupq_n_u16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f64) +#[doc = "Multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] +#[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_f64(a: *const f64) -> float64x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v2f64.p0v2f64")] - fn vld4q_f64_(ptr: *const float64x2_t) -> float64x2x4_t; - } - vld4q_f64_(a as _) +pub unsafe fn vmlal_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { + vmlal_high_u32(a, b, vdupq_n_u32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s64) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s64(a: *const i64) -> int64x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v2i64.p0i64")] - fn vld4q_dup_s64_(ptr: *const i64) -> int64x2x4_t; - } - vld4q_dup_s64_(a as _) +pub unsafe fn vmlal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlal_s8(a, b, c) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u64) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_u64(a: *const u64) -> uint64x2x4_t { - transmute(vld4q_dup_s64(transmute(a))) +pub unsafe fn vmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlal_s16(a, b, c) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p64) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4r))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(smlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_p64(a: *const p64) -> poly64x2x4_t { - transmute(vld4q_dup_s64(transmute(a))) +pub unsafe fn vmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlal_s32(a, b, c) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f64) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_f64(a: *const f64) -> float64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v1f64.p0f64")] - fn vld4_dup_f64_(ptr: *const f64) -> float64x1x4_t; - } - vld4_dup_f64_(a as _) +pub unsafe fn vmlal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlal_u8(a, b, c) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f64) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] +#[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_f64(a: *const f64) -> float64x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v2f64.p0f64")] - fn vld4q_dup_f64_(ptr: *const f64) -> float64x2x4_t; - } - vld4q_dup_f64_(a as _) +pub unsafe fn vmlal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlal_u16(a, b, c) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s8) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s8(a: *const i8, b: int8x16x4_t) -> int8x16x4_t { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v16i8.p0i8")] - fn vld4q_lane_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, n: i64, ptr: *const i8) -> int8x16x4_t; - } - vld4q_lane_s8_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmlal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlal_u32(a, b, c) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s64) +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s64(a: *const i64, b: int64x1x4_t) -> int64x1x4_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v1i64.p0i8")] - fn vld4_lane_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, n: i64, ptr: *const i8) -> int64x1x4_t; - } - vld4_lane_s64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmls_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s64) +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s64(a: *const i64, b: int64x2x4_t) -> int64x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v2i64.p0i8")] - fn vld4q_lane_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, n: i64, ptr: *const i8) -> int64x2x4_t; - } - vld4q_lane_s64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmlsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p64) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_p64(a: *const p64, b: poly64x1x4_t) -> poly64x1x4_t { - static_assert!(LANE == 0); - transmute(vld4_lane_s64::(transmute(a), transmute(b))) -} - -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p64) +pub unsafe fn vmlsl_high_lane_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_p64(a: *const p64, b: poly64x2x4_t) -> poly64x2x4_t { +pub unsafe fn vmlsl_high_laneq_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlsl_high_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vmlsl_high_lane_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x2_t, +) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - transmute(vld4q_lane_s64::(transmute(a), transmute(b))) + vmlsl_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p8) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_p8(a: *const p8, b: poly8x16x4_t) -> poly8x16x4_t { - static_assert_uimm_bits!(LANE, 4); - transmute(vld4q_lane_s8::(transmute(a), transmute(b))) +pub unsafe fn vmlsl_high_laneq_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_high_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u8) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_u8(a: *const u8, b: uint8x16x4_t) -> uint8x16x4_t { - static_assert_uimm_bits!(LANE, 4); - transmute(vld4q_lane_s8::(transmute(a), transmute(b))) -} - -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u64) +pub unsafe fn vmlsl_high_lane_u16( + a: uint32x4_t, + b: uint16x8_t, + c: uint16x4_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_u64(a: *const u64, b: uint64x1x4_t) -> uint64x1x4_t { - static_assert!(LANE == 0); - transmute(vld4_lane_s64::(transmute(a), transmute(b))) -} - -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u64) +pub unsafe fn vmlsl_high_laneq_u16( + a: uint32x4_t, + b: uint16x8_t, + c: uint16x8_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlsl_high_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_u64(a: *const u64, b: uint64x2x4_t) -> uint64x2x4_t { +pub unsafe fn vmlsl_high_lane_u32( + a: uint64x2_t, + b: uint32x4_t, + c: uint32x2_t, +) -> uint64x2_t { static_assert_uimm_bits!(LANE, 1); - transmute(vld4q_lane_s64::(transmute(a), transmute(b))) + vmlsl_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f64) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlsl2, LANE = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_f64(a: *const f64, b: float64x1x4_t) -> float64x1x4_t { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v1f64.p0i8")] - fn vld4_lane_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, n: i64, ptr: *const i8) -> float64x1x4_t; - } - vld4_lane_f64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmlsl_high_laneq_u32( + a: uint64x2_t, + b: uint32x4_t, + c: uint32x4_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_high_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f64) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_f64(a: *const f64, b: float64x2x4_t) -> float64x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v2f64.p0i8")] - fn vld4q_lane_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, n: i64, ptr: *const i8) -> float64x2x4_t; - } - vld4q_lane_f64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { + vmlsl_high_s16(a, b, vdupq_n_s16(c)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { - static_assert!(LANE == 0); - *a = simd_extract!(b, LANE as u32); +pub unsafe fn vmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { + vmlsl_high_s32(a, b, vdupq_n_s32(c)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { - static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); +pub unsafe fn vmlsl_high_n_u16(a: uint32x4_t, b: uint16x8_t, c: u16) -> uint32x4_t { + vmlsl_high_u16(a, b, vdupq_n_u16(c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2) +#[doc = "Multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v1f64.p0f64")] - fn vst1_f64_x2_(a: float64x1_t, b: float64x1_t, ptr: *mut f64); - } - vst1_f64_x2_(b.0, b.1, a) +pub unsafe fn vmlsl_high_n_u32(a: uint64x2_t, b: uint32x4_t, c: u32) -> uint64x2_t { + vmlsl_high_u32(a, b, vdupq_n_u32(c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v2f64.p0f64")] - fn vst1q_f64_x2_(a: float64x2_t, b: float64x2_t, ptr: *mut f64); - } - vst1q_f64_x2_(b.0, b.1, a) +pub unsafe fn vmlsl_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlsl_s8(a, b, c) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v1f64.p0f64")] - fn vst1_f64_x3_(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut f64); - } - vst1_f64_x3_(b.0, b.1, b.2, a) +pub unsafe fn vmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlsl_s16(a, b, c) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(smlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v2f64.p0f64")] - fn vst1q_f64_x3_(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut f64); - } - vst1q_f64_x3_(b.0, b.1, b.2, a) +pub unsafe fn vmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: int32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlsl_s32(a, b, c) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v1f64.p0f64")] - fn vst1_f64_x4_(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut f64); - } - vst1_f64_x4_(b.0, b.1, b.2, b.3, a) +pub unsafe fn vmlsl_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let c: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); + vmlsl_u8(a, b, c) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] +#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v2f64.p0f64")] - fn vst1q_f64_x4_(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut f64); - } - vst1q_f64_x4_(b.0, b.1, b.2, b.3, a) +pub unsafe fn vmlsl_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let c: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); + vmlsl_u16(a, b, c) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] +#[cfg_attr(test, assert_instr(umlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v2i64.p0i8")] - fn vst2q_s64_(a: int64x2_t, b: int64x2_t, ptr: *mut i8); - } - vst2q_s64_(b.0, b.1, a as _) +pub unsafe fn vmlsl_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let c: uint32x2_t = simd_shuffle!(c, c, [2, 3]); + vmlsl_u32(a, b, c) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { - vst2q_s64(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(sxtl2))] +pub unsafe fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { + let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vmovl_s8(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st2))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { - vst2q_s64(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(sxtl2))] +pub unsafe fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vmovl_s16(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v1f64.p0i8")] - fn vst2_f64_(a: float64x1_t, b: float64x1_t, ptr: *mut i8); - } - vst2_f64_(b.0, b.1, a as _) +#[cfg_attr(test, assert_instr(sxtl2))] +pub unsafe fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + vmovl_s32(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v2f64.p0i8")] - fn vst2q_f64_(a: float64x2_t, b: float64x2_t, ptr: *mut i8); - } - vst2q_f64_(b.0, b.1, a as _) +#[cfg_attr(test, assert_instr(uxtl2))] +pub unsafe fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { + let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vmovl_u8(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v16i8.p0i8")] - fn vst2q_lane_s8_(a: int8x16_t, b: int8x16_t, n: i64, ptr: *mut i8); - } - vst2q_lane_s8_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(uxtl2))] +pub unsafe fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { + let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vmovl_u16(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64) +#[doc = "Vector move"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v1i64.p0i8")] - fn vst2_lane_s64_(a: int64x1_t, b: int64x1_t, n: i64, ptr: *mut i8); - } - vst2_lane_s64_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(uxtl2))] +pub unsafe fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { + let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + vmovl_u32(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v2i64.p0i8")] - fn vst2q_lane_s64_(a: int64x2_t, b: int64x2_t, n: i64, ptr: *mut i8); - } - vst2q_lane_s64_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + let c: int8x8_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { - static_assert_uimm_bits!(LANE, 4); - vst2q_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + let c: int16x4_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { - static_assert!(LANE == 0); - vst2_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + let c: int32x2_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - vst2q_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + let c: uint8x8_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { - static_assert_uimm_bits!(LANE, 4); - vst2q_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + let c: uint16x4_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64) +#[doc = "Extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { - static_assert!(LANE == 0); - vst2_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(xtn2))] +pub unsafe fn vmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + let c: uint32x2_t = simd_cast(b); + simd_shuffle!(a, c, [0, 1, 2, 3]) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - vst2q_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(fmul))] +pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + simd_mul(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v1f64.p0i8")] - fn vst2_lane_f64_(a: float64x1_t, b: float64x1_t, n: i64, ptr: *mut i8); - } - vst2_lane_f64_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(fmul))] +pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_mul(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v2f64.p0i8")] - fn vst2q_lane_f64_(a: float64x2_t, b: float64x2_t, n: i64, ptr: *mut i8); - } - vst2q_lane_f64_(b.0, b.1, LANE as i64, a as _) +pub unsafe fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + static_assert!(LANE == 0); + simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v2i64.p0i8")] - fn vst3q_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i8); - } - vst3q_s64_(b.0, b.1, b.2, a as _) +pub unsafe fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { - vst3q_s64(transmute(a), transmute(b)) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st3))] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { - vst3q_s64(transmute(a), transmute(b)) +pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { + simd_mul(a, vdup_n_f64(b)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v1f64.p0i8")] - fn vst3_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut i8); - } - vst3_f64_(b.0, b.1, b.2, a as _) +pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { + simd_mul(a, vdupq_n_f64(b)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v2f64.p0i8")] - fn vst3q_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut i8); - } - vst3q_f64_(b.0, b.1, b.2, a as _) +pub unsafe fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { + static_assert!(LANE == 0); + let b: f64 = simd_extract!(b, LANE as u32); + a * b } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v16i8.p0i8")] - fn vst3q_lane_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, n: i64, ptr: *mut i8); - } - vst3q_lane_s8_(b.0, b.1, b.2, LANE as i64, a as _) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64) +pub unsafe fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_high_s16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v1i64.p0i8")] - fn vst3_lane_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, n: i64, ptr: *mut i8); - } - vst3_lane_s64_(b.0, b.1, b.2, LANE as i64, a as _) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64) +pub unsafe fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_high_s16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { +pub unsafe fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v2i64.p0i8")] - fn vst3q_lane_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, n: i64, ptr: *mut i8); - } - vst3q_lane_s64_(b.0, b.1, b.2, LANE as i64, a as _) + vmull_high_s32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(smull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { - static_assert_uimm_bits!(LANE, 4); - vst3q_lane_s8::(transmute(a), transmute(b)) +pub unsafe fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_high_s32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { - static_assert!(LANE == 0); - vst3_lane_s64::(transmute(a), transmute(b)) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64) +pub unsafe fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_high_u16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - vst3q_lane_s64::(transmute(a), transmute(b)) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8) +pub unsafe fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_high_u16( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { - static_assert_uimm_bits!(LANE, 4); - vst3q_lane_s8::(transmute(a), transmute(b)) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { - static_assert!(LANE == 0); - vst3_lane_s64::(transmute(a), transmute(b)) +pub unsafe fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmull_high_u32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(umull2, LANE = 1))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - vst3q_lane_s64::(transmute(a), transmute(b)) +pub unsafe fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_high_u32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v1f64.p0i8")] - fn vst3_lane_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, n: i64, ptr: *mut i8); - } - vst3_lane_f64_(b.0, b.1, b.2, LANE as i64, a as _) +pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { + vmull_high_s16(a, vdupq_n_s16(b)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v2f64.p0i8")] - fn vst3q_lane_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, n: i64, ptr: *mut i8); - } - vst3q_lane_f64_(b.0, b.1, b.2, LANE as i64, a as _) +pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { + vmull_high_s32(a, vdupq_n_s32(b)) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] +#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v2i64.p0i8")] - fn vst4q_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i8); - } - vst4q_s64_(b.0, b.1, b.2, b.3, a as _) +pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { + vmull_high_u16(a, vdupq_n_u16(b)) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64) +#[doc = "Multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] +#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { - vst4q_s64(transmute(a), transmute(b)) +pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { + vmull_high_u32(a, vdupq_n_u32(b)) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64) +#[doc = "Polynomial multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st4))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { - vst4q_s64(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(pmull))] +pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { + vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64) +#[doc = "Polynomial multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v1f64.p0i8")] - fn vst4_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut i8); - } - vst4_f64_(b.0, b.1, b.2, b.3, a as _) +#[cfg_attr(test, assert_instr(pmull))] +pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { + let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_p8(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v2f64.p0i8")] - fn vst4q_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut i8); - } - vst4q_f64_(b.0, b.1, b.2, b.3, a as _) +#[cfg_attr(test, assert_instr(smull2))] +pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_s8(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { - static_assert_uimm_bits!(LANE, 4); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v16i8.p0i8")] - fn vst4q_lane_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, n: i64, ptr: *mut i8); - } - vst4q_lane_s8_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(smull2))] +pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vmull_s16(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v1i64.p0i8")] - fn vst4_lane_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, n: i64, ptr: *mut i8); - } - vst4_lane_s64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(smull2))] +pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + vmull_s32(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v2i64.p0i8")] - fn vst4q_lane_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, n: i64, ptr: *mut i8); - } - vst4q_lane_s64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(test, assert_instr(umull2))] +pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + vmull_u8(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { - static_assert_uimm_bits!(LANE, 4); - vst4q_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(umull2))] +pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vmull_u16(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { - static_assert!(LANE == 0); - vst4_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(umull2))] +pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + vmull_u32(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64) +#[doc = "Polynomial multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[target_feature(enable = "neon,aes")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - vst4q_lane_s64::(transmute(a), transmute(b)) +#[cfg_attr(test, assert_instr(pmull))] +pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmull64" + )] + fn _vmull_p64(a: p64, b: p64) -> int8x16_t; + } + transmute(_vmull_p64(a, b)) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { - static_assert_uimm_bits!(LANE, 4); - vst4q_lane_s8::(transmute(a), transmute(b)) +pub unsafe fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { + static_assert!(LANE == 0); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { - static_assert!(LANE == 0); - vst4_lane_s64::(transmute(a), transmute(b)) +pub unsafe fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { +pub unsafe fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { static_assert_uimm_bits!(LANE, 1); - vst4q_lane_s64::(transmute(a), transmute(b)) + let b: f32 = simd_extract!(b, LANE as u32); + a * b } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { - static_assert!(LANE == 0); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v1f64.p0i8")] - fn vst4_lane_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, n: i64, ptr: *mut i8); - } - vst4_lane_f64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +pub unsafe fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { + static_assert_uimm_bits!(LANE, 2); + let b: f32 = simd_extract!(b, LANE as u32); + a * b } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[cfg_attr(test, assert_instr(fmul, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { +pub unsafe fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v2f64.p0i8")] - fn vst4q_lane_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, n: i64, ptr: *mut i8); - } - vst4q_lane_f64_(b.0, b.1, b.2, b.3, LANE as i64, a as _) -} - -/// Dot product index form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32) -#[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vusdot_laneq_s32(a: int32x2_t, b: uint8x8_t, c: int8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) + let b: f64 = simd_extract!(b, LANE as u32); + a * b } -/// Dot product index form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(usdot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vusdotq_laneq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.v2f32" + )] + fn _vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vmulx_f32(a, b) } -/// Dot product index form with signed and unsigned integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vsudot_laneq_s32(a: int32x2_t, b: int8x8_t, c: uint8x16_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.v4f32" + )] + fn _vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vmulxq_f32(a, b) } -/// Dot product index form with signed and unsigned integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(test, assert_instr(sudot, LANE = 3))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] -pub unsafe fn vsudotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: uint8x16_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.v1f64" + )] + fn _vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + _vmulx_f64(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_mul(a, b) +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.v2f64" + )] + fn _vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vmulxq_f64(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_mul(a, b) +pub unsafe fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_n_f64(a: float64x1_t, b: f64) -> float64x1_t { - simd_mul(a, vdup_n_f64(b)) +pub unsafe fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_n_f64(a: float64x2_t, b: f64) -> float64x2_t { - simd_mul(a, vdupq_n_f64(b)) +pub unsafe fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmulxq_f32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - static_assert!(LANE == 0); - simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) +pub unsafe fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmulxq_f32( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmul_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { +pub unsafe fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, transmute::(simd_extract!(b, LANE as u32))) + vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { +pub unsafe fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { static_assert!(LANE == 0); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +pub unsafe fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) + vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuls_lane_f32(a: f32, b: float32x2_t) -> f32 { - static_assert_uimm_bits!(LANE, 1); - let b: f32 = simd_extract!(b, LANE as u32); - a * b +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.f64" + )] + fn _vmulxd_f64(a: f64, b: f64) -> f64; + } + _vmulxd_f64(a, b) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuls_laneq_f32(a: f32, b: float32x4_t) -> f32 { - static_assert_uimm_bits!(LANE, 2); - let b: f32 = simd_extract!(b, LANE as u32); - a * b +#[cfg_attr(test, assert_instr(fmulx))] +pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmulx.f32" + )] + fn _vmulxs_f32(a: f32, b: f32) -> f32; + } + _vmulxs_f32(a, b) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_lane_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuld_lane_f64(a: f64, b: float64x1_t) -> f64 { +pub unsafe fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { static_assert!(LANE == 0); - let b: f64 = simd_extract!(b, LANE as u32); - a * b + vmulxd_f64(a, simd_extract!(b, LANE as u32)) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmul, LANE = 0))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmuld_laneq_f64(a: f64, b: float64x2_t) -> f64 { +pub unsafe fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { static_assert_uimm_bits!(LANE, 1); - let b: f64 = simd_extract!(b, LANE as u32); - a * b + vmulxd_f64(a, simd_extract!(b, LANE as u32)) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_s8(a, b) +pub unsafe fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { + static_assert_uimm_bits!(LANE, 1); + vmulxs_f32(a, simd_extract!(b, LANE as u32)) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_s16(a, b) +pub unsafe fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { + static_assert_uimm_bits!(LANE, 2); + vmulxs_f32(a, simd_extract!(b, LANE as u32)) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32) +#[doc = "Floating-point multiply extended"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] +#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_s32(a, b) +pub unsafe fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { + static_assert!(LANE == 0); + vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_u8(a, b) +#[cfg_attr(test, assert_instr(fneg))] +pub unsafe fn vneg_f64(a: float64x1_t) -> float64x1_t { + simd_neg(a) } -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vmull_u16(a, b) +#[cfg_attr(test, assert_instr(fneg))] +pub unsafe fn vnegq_f64(a: float64x2_t) -> float64x2_t { + simd_neg(a) } -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - vmull_u32(a, b) +#[cfg_attr(test, assert_instr(neg))] +pub unsafe fn vneg_s64(a: int64x1_t) -> int64x1_t { + simd_neg(a) } -/// Polynomial multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(pmull))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_p64(a: p64, b: p64) -> p128 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.pmull64")] - fn vmull_p64_(a: p64, b: p64) -> int8x16_t; - } - transmute(vmull_p64_(a, b)) +#[cfg_attr(test, assert_instr(neg))] +pub unsafe fn vnegq_s64(a: int64x2_t) -> int64x2_t { + simd_neg(a) } -/// Polynomial multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(pmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_p8(a: poly8x16_t, b: poly8x16_t) -> poly16x8_t { - let a: poly8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let b: poly8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - vmull_p8(a, b) +#[cfg_attr(test, assert_instr(neg))] +pub unsafe fn vnegd_s64(a: i64) -> i64 { + a.wrapping_neg() } -/// Polynomial multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64) +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(test, assert_instr(pmull))] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_p64(a: poly64x2_t, b: poly64x2_t) -> p128 { - vmull_p64(simd_extract!(a, 1), simd_extract!(b, 1)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vpaddd_f64(a: float64x2_t) -> f64 { + let a1: f64 = simd_extract!(a, 0); + let a2: f64 = simd_extract!(a, 1); + a1 + a2 } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s16) +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { - vmull_high_s16(a, vdupq_n_s16(b)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vpadds_f32(a: float32x2_t) -> f32 { + let a1: f32 = simd_extract!(a, 0); + let a2: f32 = simd_extract!(a, 1); + a1 + a2 } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_s32) +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { - vmull_high_s32(a, vdupq_n_s32(b)) +#[cfg_attr(test, assert_instr(faddp))] +pub unsafe fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v4f32" + )] + fn _vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vpaddq_f32(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u16) +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_u16(a: uint16x8_t, b: u16) -> uint32x4_t { - vmull_high_u16(a, vdupq_n_u16(b)) +#[cfg_attr(test, assert_instr(faddp))] +pub unsafe fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v2f64" + )] + fn _vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vpaddq_f64(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_n_u32) +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2))] +#[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_n_u32(a: uint32x4_t, b: u32) -> uint64x2_t { - vmull_high_u32(a, vdupq_n_u32(b)) +pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v2f32" + )] + fn _vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vpmaxnm_f32(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16) +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v4f32" + )] + fn _vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vpmaxnmq_f32(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16) +#[doc = "Floating-point Maximum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmull_high_s16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmp.v2f64" + )] + fn _vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; + } + _vpmaxnmq_f64(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32) +#[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64" + )] + fn _vpmaxnmqd_f64(a: float64x2_t) -> f64; + } + _vpmaxnmqd_f64(a) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32) +#[doc = "Floating-point maximum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(smull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fmaxnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmull_high_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpmaxnms_f32(a: float32x2_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32" + )] + fn _vpmaxnms_f32(a: float32x2_t) -> f32; + } + _vpmaxnms_f32(a) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16) +#[doc = "Floating-point maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(test, assert_instr(fmaxp))] +pub unsafe fn vpmaxqd_f64(a: float64x2_t) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64" + )] + fn _vpmaxqd_f64(a: float64x2_t) -> f64; + } + _vpmaxqd_f64(a) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16) +#[doc = "Floating-point maximum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmull_high_u16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(test, assert_instr(fmaxp))] +pub unsafe fn vpmaxs_f32(a: float32x2_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32" + )] + fn _vpmaxs_f32(a: float32x2_t) -> f32; + } + _vpmaxs_f32(a) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32) +#[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f32" + )] + fn _vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vpminnm_f32(a, b) } -/// Multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32) +#[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(umull2, LANE = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmull_high_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmull_high_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v4f32" + )] + fn _vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vpminnmq_f32(a, b) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32) +#[doc = "Floating-point Minimum Number Pairwise (vector)."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.v2f32")] - fn vmulx_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmp.v2f64" + )] + fn _vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - vmulx_f32_(a, b) + _vpminnmq_f64(a, b) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32) +#[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] +pub unsafe fn vpminnmqd_f64(a: float64x2_t) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.v4f32")] - fn vmulxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64" + )] + fn _vpminnmqd_f64(a: float64x2_t) -> f64; } - vmulxq_f32_(a, b) + _vpminnmqd_f64(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64) +#[doc = "Floating-point minimum number pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] +#[cfg_attr(test, assert_instr(fminnmp))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +pub unsafe fn vpminnms_f32(a: float32x2_t) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.v1f64")] - fn vmulx_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32" + )] + fn _vpminnms_f32(a: float32x2_t) -> f32; } - vmulx_f64_(a, b) + _vpminnms_f32(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64) +#[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(fminp))] +pub unsafe fn vpminqd_f64(a: float64x2_t) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.v2f64")] - fn vmulxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f64.v2f64" + )] + fn _vpminqd_f64(a: float64x2_t) -> f64; } - vmulxq_f64_(a, b) + _vpminqd_f64(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f64) +#[doc = "Floating-point minimum pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_lane_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - static_assert!(LANE == 0); - vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) +#[cfg_attr(test, assert_instr(fminp))] +pub unsafe fn vpmins_f32(a: float32x2_t) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminv.f32.v2f32" + )] + fn _vpmins_f32(a: float32x2_t) -> f32; + } + _vpmins_f32(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f64) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_laneq_f64(a: float64x1_t, b: float64x2_t) -> float64x1_t { - static_assert_uimm_bits!(LANE, 1); - vmulx_f64(a, transmute::(simd_extract!(b, LANE as u32))) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v1i64" + )] + fn _vqabs_s64(a: int64x1_t) -> int64x1_t; + } + _vqabs_s64(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v2i64" + )] + fn _vqabsq_s64(a: int64x2_t) -> int64x2_t; + } + _vqabsq_s64(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32) +#[doc = "Signed saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulx_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmulx_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabsb_s8(a: i8) -> i8 { + simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32) +#[doc = "Signed saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabsh_s16(a: i16) -> i16 { + simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32) +#[doc = "Signed saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmulxq_f32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabss_s32(a: i32) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.i32" + )] + fn _vqabss_s32(a: i32) -> i32; + } + _vqabss_s32(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64) +#[doc = "Signed saturating absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_lane_f64(a: float64x2_t, b: float64x1_t) -> float64x2_t { - static_assert!(LANE == 0); - vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] +pub unsafe fn vqabsd_s64(a: i64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.i64" + )] + fn _vqabsd_s64(a: i64) -> i64; + } + _vqabsd_s64(a) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxq_laneq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmulxq_f64(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(test, assert_instr(sqadd))] +pub unsafe fn vqaddb_s8(a: i8, b: i8) -> i8 { + let a: int8x8_t = vdup_n_s8(a); + let b: int8x8_t = vdup_n_s8(b); + simd_extract!(vqadd_s8(a, b), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxs_f32(a: f32, b: f32) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.f32")] - fn vmulxs_f32_(a: f32, b: f32) -> f32; - } - vmulxs_f32_(a, b) -} - -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_f64) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxd_f64(a: f64, b: f64) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmulx.f64")] - fn vmulxd_f64_(a: f64, b: f64) -> f64; - } - vmulxd_f64_(a, b) +#[cfg_attr(test, assert_instr(sqadd))] +pub unsafe fn vqaddh_s16(a: i16, b: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqadd_s16(a, b), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxs_lane_f32(a: f32, b: float32x2_t) -> f32 { - static_assert_uimm_bits!(LANE, 1); - vmulxs_f32(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(uqadd))] +pub unsafe fn vqaddb_u8(a: u8, b: u8) -> u8 { + let a: uint8x8_t = vdup_n_u8(a); + let b: uint8x8_t = vdup_n_u8(b); + simd_extract!(vqadd_u8(a, b), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxs_laneq_f32(a: f32, b: float32x4_t) -> f32 { - static_assert_uimm_bits!(LANE, 2); - vmulxs_f32(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(uqadd))] +pub unsafe fn vqaddh_u16(a: u16, b: u16) -> u16 { + let a: uint16x4_t = vdup_n_u16(a); + let b: uint16x4_t = vdup_n_u16(b); + simd_extract!(vqadd_u16(a, b), 0) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_lane_f64) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxd_lane_f64(a: f64, b: float64x1_t) -> f64 { - static_assert!(LANE == 0); - vmulxd_f64(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(sqadd))] +pub unsafe fn vqadds_s32(a: i32, b: i32) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.i32" + )] + fn _vqadds_s32(a: i32, b: i32) -> i32; + } + _vqadds_s32(a, b) } -/// Floating-point multiply extended -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmulx, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmulxd_laneq_f64(a: f64, b: float64x2_t) -> f64 { - static_assert_uimm_bits!(LANE, 1); - vmulxd_f64(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(sqadd))] +pub unsafe fn vqaddd_s64(a: i64, b: i64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.i64" + )] + fn _vqaddd_s64(a: i64, b: i64) -> i64; + } + _vqaddd_s64(a, b) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(uqadd))] +pub unsafe fn vqadds_u32(a: u32, b: u32) -> u32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.v1f64")] - fn vfma_f64_(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.i32" + )] + fn _vqadds_u32(a: i32, b: i32) -> i32; } - vfma_f64_(b, c, a) + _vqadds_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(uqadd))] +pub unsafe fn vqaddd_u64(a: u64, b: u64) -> u64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.v2f64")] - fn vfmaq_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.i64" + )] + fn _vqaddd_u64(a: i64, b: i64) -> i64; } - vfmaq_f64_(b, c, a) + _vqaddd_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd))] +#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { - vfma_f64(a, b, vdup_n_f64(c)) +pub unsafe fn vqdmlal_high_lane_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqaddq_s32(a, vqdmull_high_lane_s16::(b, c)) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla))] +#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { - vfmaq_f64(a, b, vdupq_n_f64(c)) +pub unsafe fn vqdmlal_high_laneq_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + vqaddq_s32(a, vqdmull_high_laneq_s16::(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_lane_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqaddq_s64(a, vqdmull_high_lane_s32::(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - vfma_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_laneq_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + vqaddq_s64(a, vqdmull_high_laneq_s32::(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { + vqaddq_s32(a, vqdmull_high_n_s16(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - vfmaq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + vqaddq_s32(a, vqdmull_high_s16(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_lane_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - static_assert!(LANE == 0); - vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { + vqaddq_s64(a, vqdmull_high_n_s32(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlal2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfma_laneq_f64(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { - static_assert_uimm_bits!(LANE, 1); - vfma_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + vqaddq_s64(a, vqdmull_high_s32(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f64) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_lane_f64(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { - static_assert!(LANE == 0); - vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_laneq_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + vqaddq_s32(a, vqdmull_laneq_s16::(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmla, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmaq_laneq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(LANE, 1); - vfmaq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlal_laneq_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + vqaddq_s64(a, vqdmull_laneq_s32::(b, c)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmas_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.f32")] - fn vfmas_lane_f32_(a: f32, b: f32, c: f32) -> f32; - } - static_assert_uimm_bits!(LANE, 1); - let c: f32 = simd_extract!(c, LANE as u32); - vfmas_lane_f32_(b, c, a) +pub unsafe fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { + static_assert_uimm_bits!(LANE, 2); + vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmas_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.f32")] - fn vfmas_laneq_f32_(a: f32, b: f32, c: f32) -> f32; - } - static_assert_uimm_bits!(LANE, 2); - let c: f32 = simd_extract!(c, LANE as u32); - vfmas_laneq_f32_(b, c, a) +pub unsafe fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { + static_assert_uimm_bits!(LANE, 3); + vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_lane_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmad_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.f64")] - fn vfmad_lane_f64_(a: f64, b: f64, c: f64) -> f64; - } - static_assert!(LANE == 0); - let c: f64 = simd_extract!(c, LANE as u32); - vfmad_lane_f64_(b, c, a) +pub unsafe fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { + static_assert_uimm_bits!(LANE, 1); + vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmadd, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmad_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.f64")] - fn vfmad_laneq_f64_(a: f64, b: f64, c: f64) -> f64; - } - static_assert_uimm_bits!(LANE, 1); - let c: f64 = simd_extract!(c, LANE as u32); - vfmad_laneq_f64_(b, c, a) +pub unsafe fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { + static_assert_uimm_bits!(LANE, 2); + vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub))] +#[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - let b: float64x1_t = simd_neg(b); - vfma_f64(a, b, c) +pub unsafe fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { + let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); + vqadds_s32(a, simd_extract!(x, 0)) } -/// Floating-point fused multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls))] +#[cfg_attr(test, assert_instr(sqdmlal))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - let b: float64x2_t = simd_neg(b); - vfmaq_f64(a, b, c) +pub unsafe fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { + let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c)); + x as i64 } -/// Floating-point fused Multiply-subtract to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub))] +#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_n_f64(a: float64x1_t, b: float64x1_t, c: f64) -> float64x1_t { - vfms_f64(a, b, vdup_n_f64(c)) +pub unsafe fn vqdmlsl_high_lane_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqsubq_s32(a, vqdmull_high_lane_s16::(b, c)) } -/// Floating-point fused Multiply-subtract to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls))] +#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] +#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_n_f64(a: float64x2_t, b: float64x2_t, c: f64) -> float64x2_t { - vfmsq_f64(a, b, vdupq_n_f64(c)) +pub unsafe fn vqdmlsl_high_laneq_s16( + a: int32x4_t, + b: int16x8_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + vqsubq_s32(a, vqdmull_high_laneq_s16::(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_lane_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqsubq_s64(a, vqdmull_high_lane_s32::(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - vfms_f32(a, b, vdup_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_laneq_s32( + a: int64x2_t, + b: int32x4_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + vqsubq_s64(a, vqdmull_high_laneq_s32::(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { + vqsubq_s32(a, vqdmull_high_n_s16(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - vfmsq_f32(a, b, vdupq_n_f32(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { + vqsubq_s32(a, vqdmull_high_s16(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_lane_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t) -> float64x1_t { - static_assert!(LANE == 0); - vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { + vqsubq_s64(a, vqdmull_high_n_s32(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqdmlsl2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfms_laneq_f64(a: float64x1_t, b: float64x1_t, c: float64x2_t) -> float64x1_t { - static_assert_uimm_bits!(LANE, 1); - vfms_f64(a, b, vdup_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { + vqsubq_s64(a, vqdmull_high_s32(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f64) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_lane_f64(a: float64x2_t, b: float64x2_t, c: float64x1_t) -> float64x2_t { - static_assert!(LANE == 0); - vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_laneq_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + vqsubq_s32(a, vqdmull_laneq_s16::(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmls, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsq_laneq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - static_assert_uimm_bits!(LANE, 1); - vfmsq_f64(a, b, vdupq_n_f64(simd_extract!(c, LANE as u32))) +pub unsafe fn vqdmlsl_laneq_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + vqsubq_s64(a, vqdmull_laneq_s32::(b, c)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmss_lane_f32(a: f32, b: f32, c: float32x2_t) -> f32 { - vfmas_lane_f32::(a, -b, c) +pub unsafe fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { + static_assert_uimm_bits!(LANE, 2); + vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmss_laneq_f32(a: f32, b: f32, c: float32x4_t) -> f32 { - vfmas_laneq_f32::(a, -b, c) +pub unsafe fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { + static_assert_uimm_bits!(LANE, 3); + vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_lane_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsd_lane_f64(a: f64, b: f64, c: float64x1_t) -> f64 { - vfmad_lane_f64::(a, -b, c) +pub unsafe fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { + static_assert_uimm_bits!(LANE, 1); + vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point fused multiply-subtract to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmsub, LANE = 0))] +#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] #[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vfmsd_laneq_f64(a: f64, b: f64, c: float64x2_t) -> f64 { - vfmad_laneq_f64::(a, -b, c) +pub unsafe fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { + static_assert_uimm_bits!(LANE, 2); + vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Divide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fdiv))] +#[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdiv_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_div(a, b) +pub unsafe fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { + let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); + vqsubs_s32(a, simd_extract!(x, 0)) } -/// Divide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fdiv))] +#[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdivq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_div(a, b) +pub unsafe fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { + let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c)); + x as i64 } -/// Divide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fdiv))] +#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdiv_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_div(a, b) +pub unsafe fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } -/// Divide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fdiv))] +#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vdivq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_div(a, b) +pub unsafe fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsub))] +#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - simd_sub(a, b) +pub unsafe fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsub))] +#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_sub(a, b) +pub unsafe fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sqdmulh, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubd_s64(a: i64, b: i64) -> i64 { - a.wrapping_sub(b) +pub unsafe fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { + static_assert_uimm_bits!(N, 2); + let b: i16 = simd_extract!(b, N as u32); + vqdmulhh_s16(a, b) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sqdmulh, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubd_u64(a: u64, b: u64) -> u64 { - a.wrapping_sub(b) +pub unsafe fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { + static_assert_uimm_bits!(N, 3); + let b: i16 = simd_extract!(b, N as u32); + vqdmulhh_s16(a, b) } -/// Add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_s64) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddd_s64(a: i64, b: i64) -> i64 { - a.wrapping_add(b) +pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqdmulh_s16(a, b), 0) } -/// Add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddd_u64) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddd_u64(a: u64, b: u64) -> u64 { - a.wrapping_add(b) +pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { + let a: int32x2_t = vdup_n_s32(a); + let b: int32x2_t = vdup_n_s32(b); + simd_extract!(vqdmulh_s32(a, b), 0) } -/// Floating-point add across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_f32) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(faddp))] +#[cfg_attr(test, assert_instr(sqdmulh, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddv_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddv.f32.v2f32")] - fn vaddv_f32_(a: float32x2_t) -> f32; - } - vaddv_f32_(a) +pub unsafe fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { + static_assert_uimm_bits!(N, 1); + let b: i32 = simd_extract!(b, N as u32); + vqdmulhs_s32(a, b) } -/// Floating-point add across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f32) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(faddp))] +#[cfg_attr(test, assert_instr(sqdmulh, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddvq_f32(a: float32x4_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddv.f32.v4f32")] - fn vaddvq_f32_(a: float32x4_t) -> f32; - } - vaddvq_f32_(a) +pub unsafe fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { + static_assert_uimm_bits!(N, 2); + let b: i32 = simd_extract!(b, N as u32); + vqdmulhs_s32(a, b) } -/// Floating-point add across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_f64) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(faddp))] +#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddvq_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddv.f64.v2f64")] - fn vaddvq_f64_(a: float64x2_t) -> f64; - } - vaddvq_f64_(a) +pub unsafe fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) } -/// Signed Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(saddlv))] +#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlv_s16(a: int16x4_t) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.saddlv.i32.v4i16")] - fn vaddlv_s16_(a: int16x4_t) -> i32; - } - vaddlv_s16_(a) +pub unsafe fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) } -/// Signed Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(saddlv))] +#[cfg_attr(test, assert_instr(sqdmull2, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlvq_s16(a: int16x8_t) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.saddlv.i32.v8i16")] - fn vaddlvq_s16_(a: int16x8_t) -> i32; - } - vaddlvq_s16_(a) +pub unsafe fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) } -/// Signed Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(saddlp))] +#[cfg_attr(test, assert_instr(sqdmull2, N = 4))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlv_s32(a: int32x2_t) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.saddlv.i64.v2i32")] - fn vaddlv_s32_(a: int32x2_t) -> i64; - } - vaddlv_s32_(a) +pub unsafe fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) } -/// Signed Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(saddlv))] +#[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlvq_s32(a: int32x4_t) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.saddlv.i64.v4i32")] - fn vaddlvq_s32_(a: int32x4_t) -> i64; - } - vaddlvq_s32_(a) +pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = vdup_n_s16(b); + vqdmull_s16(a, b) } -/// Unsigned Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uaddlv))] +#[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlv_u16(a: uint16x4_t) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uaddlv.i32.v4i16")] - fn vaddlv_u16_(a: uint16x4_t) -> u32; - } - vaddlv_u16_(a) +pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = vdup_n_s32(b); + vqdmull_s32(a, b) } -/// Unsigned Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uaddlv))] +#[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlvq_u16(a: uint16x8_t) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uaddlv.i32.v8i16")] - fn vaddlvq_u16_(a: uint16x8_t) -> u32; - } - vaddlvq_u16_(a) +pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + vqdmull_s16(a, b) } -/// Unsigned Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uaddlp))] +#[cfg_attr(test, assert_instr(sqdmull2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlv_u32(a: uint32x2_t) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uaddlv.i64.v2i32")] - fn vaddlv_u32_(a: uint32x2_t) -> u64; - } - vaddlv_u32_(a) +pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); + vqdmull_s32(a, b) } -/// Unsigned Add Long across Vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32) +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uaddlv))] +#[cfg_attr(test, assert_instr(sqdmull, N = 4))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vaddlvq_u32(a: uint32x4_t) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uaddlv.i64.v4i32")] - fn vaddlvq_u32_(a: uint32x4_t) -> u64; - } - vaddlvq_u32_(a) +pub unsafe fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(N, 3); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8) +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubw))] +#[cfg_attr(test, assert_instr(sqdmull, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(N, 2); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubw))] +#[cfg_attr(test, assert_instr(sqdmull, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { + static_assert_uimm_bits!(N, 2); + let b: i16 = simd_extract!(b, N as u32); + vqdmullh_s16(a, b) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubw))] +#[cfg_attr(test, assert_instr(sqdmull, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { + static_assert_uimm_bits!(N, 2); + let b: i32 = simd_extract!(b, N as u32); + vqdmulls_s32(a, b) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubw))] +#[cfg_attr(test, assert_instr(sqdmull, N = 4))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { - let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { + static_assert_uimm_bits!(N, 3); + let b: i16 = simd_extract!(b, N as u32); + vqdmullh_s16(a, b) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubw))] +#[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { - let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqdmull_s16(a, b), 0) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubw))] +#[cfg_attr(test, assert_instr(sqdmull, N = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { - let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - simd_sub(a, simd_cast(c)) +pub unsafe fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { + static_assert_uimm_bits!(N, 1); + let b: i32 = simd_extract!(b, N as u32); + vqdmulls_s32(a, b) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubl))] +#[cfg_attr(test, assert_instr(sqdmull))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { - let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: int16x8_t = simd_cast(c); - let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int16x8_t = simd_cast(e); - simd_sub(d, f) +pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulls.scalar" + )] + fn _vqdmulls_s32(a: i32, b: i32) -> i64; + } + _vqdmulls_s32(a, b) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubl))] +#[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: int32x4_t = simd_cast(c); - let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: int32x4_t = simd_cast(e); - simd_sub(d, f) +pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + simd_shuffle!( + a, + vqmovn_s16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ssubl))] +#[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: int64x2_t = simd_cast(c); - let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: int64x2_t = simd_cast(e); - simd_sub(d, f) +pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubl))] +#[cfg_attr(test, assert_instr(sqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { - let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - let d: uint16x8_t = simd_cast(c); - let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint16x8_t = simd_cast(e); - simd_sub(d, f) +pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubl))] +#[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { - let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let d: uint32x4_t = simd_cast(c); - let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let f: uint32x4_t = simd_cast(e); - simd_sub(d, f) +pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + simd_shuffle!( + a, + vqmovn_u16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usubl))] +#[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { - let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - let d: uint64x2_t = simd_cast(c); - let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let f: uint64x2_t = simd_cast(e); - simd_sub(d, f) -} - -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s8) -#[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxs.v16i8")] - fn vbcaxq_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t; - } - vbcaxq_s8_(a, b, c) +pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s16) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxs.v8i16")] - fn vbcaxq_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - vbcaxq_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(uqxtn2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s32) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovnd_s64(a: i64) -> i32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxs.v4i32")] - fn vbcaxq_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.scalar.sqxtn.i32.i64" + )] + fn _vqmovnd_s64(a: i64) -> i32; } - vbcaxq_s32_(a, b, c) + _vqmovnd_s64(a) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_s64) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(uqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovnd_u64(a: u64) -> u32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxs.v2i64")] - fn vbcaxq_s64_(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.scalar.uqxtn.i32.i64" + )] + fn _vqmovnd_u64(a: i64) -> i32; } - vbcaxq_s64_(a, b, c) + _vqmovnd_u64(a.as_signed()).as_unsigned() } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u8) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxu.v16i8")] - fn vbcaxq_u8_(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t; - } - vbcaxq_u8_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovnh_s16(a: i16) -> i8 { + simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u16) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxu.v8i16")] - fn vbcaxq_u16_(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t; - } - vbcaxq_u16_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovns_s32(a: i32) -> i16 { + simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u32) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxu.v4i32")] - fn vbcaxq_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; - } - vbcaxq_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(uqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovnh_u16(a: u16) -> u8 { + simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) } -/// Bit clear and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbcaxq_u64) +#[doc = "Saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(bcax))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vbcaxq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.bcaxu.v2i64")] - fn vbcaxq_u64_(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; - } - vbcaxq_u64_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(uqxtn))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovns_u32(a: u32) -> u16 { + simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot270_f32) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcadd_rot270_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot270.v2f32")] - fn vcadd_rot270_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - vcadd_rot270_f32_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { + simd_shuffle!( + a, + vqmovun_s16(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f32) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcaddq_rot270_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot270.v4f32")] - fn vcaddq_rot270_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - vcaddq_rot270_f32_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { + simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot270_f64) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcaddq_rot270_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot270.v2f64")] - fn vcaddq_rot270_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vcaddq_rot270_f64_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { + simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcadd_rot90_f32) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcadd_rot90_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot90.v2f32")] - fn vcadd_rot90_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - vcadd_rot90_f32_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovunh_s16(a: i16) -> u8 { + simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f32) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcaddq_rot90_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot90.v4f32")] - fn vcaddq_rot90_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - vcaddq_rot90_f32_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovuns_s32(a: i32) -> u16 { + simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) } -/// Floating-point complex add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaddq_rot90_f64) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcadd))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcaddq_rot90_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcadd.rot90.v2f64")] - fn vcaddq_rot90_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vcaddq_rot90_f64_(a, b) +#[target_feature(enable = "neon")] +#[cfg_attr(test, assert_instr(sqxtun))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqmovund_s64(a: i64) -> u32 { + simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqneg_s64(a: int64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot0.v2f32")] - fn vcmla_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v1i64" + )] + fn _vqneg_s64(a: int64x1_t) -> int64x1_t; } - vcmla_f32_(a, b, c) + _vqneg_s64(a) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqnegq_s64(a: int64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot0.v4f32")] - fn vcmlaq_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v2i64" + )] + fn _vqnegq_s64(a: int64x2_t) -> int64x2_t; } - vcmlaq_f32_(a, b, c) + _vqnegq_s64(a) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_f64) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot0.v2f64")] - fn vcmlaq_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; - } - vcmlaq_f64_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqnegb_s8(a: i8) -> i8 { + simd_extract!(vqneg_s8(vdup_n_s8(a)), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot90_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot90.v2f32")] - fn vcmla_rot90_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; - } - vcmla_rot90_f32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqnegh_s16(a: i16) -> i16 { + simd_extract!(vqneg_s16(vdup_n_s16(a)), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot90.v4f32")] - fn vcmlaq_rot90_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; - } - vcmlaq_rot90_f32_(a, b, c) -} - -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_f64) -#[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot90.v2f64")] - fn vcmlaq_rot90_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; - } - vcmlaq_rot90_f64_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqnegs_s32(a: i32) -> i32 { + simd_extract!(vqneg_s32(vdup_n_s32(a)), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot180_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot180.v2f32")] - fn vcmla_rot180_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; - } - vcmla_rot180_f32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(sqneg))] +pub unsafe fn vqnegd_s64(a: i64) -> i64 { + simd_extract!(vqneg_s64(vdup_n_s64(a)), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot180.v4f32")] - fn vcmlaq_rot180_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; - } - vcmlaq_rot180_f32_(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlah_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_f64) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot180.v2f64")] - fn vcmlaq_rot180_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; - } - vcmlaq_rot180_f64_(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlah_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot270_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot270.v2f32")] - fn vcmla_rot270_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; - } - vcmla_rot270_f32_(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_laneq_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlah_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot270.v4f32")] - fn vcmlaq_rot270_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; - } - vcmlaq_rot270_f32_(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_laneq_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlah_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_f64) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla))] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcmla.rot270.v2f64")] - fn vcmlaq_rot270_f64_(a: float64x2_t, b: float64x2_t, c: float64x2_t) -> float64x2_t; - } - vcmlaq_rot270_f64_(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x4_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlahq_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x2_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlahq_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_laneq_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlahq_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_laneq_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlahq_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlah.v4i16" + )] + fn _vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; + } + _vqrdmlah_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot90_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlah.v8i16" + )] + fn _vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; + } + _vqrdmlahq_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot90_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot90_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot90_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlah.v2i32" + )] + fn _vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; + } + _vqrdmlah_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot90_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlah.v4i32" + )] + fn _vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vqrdmlahq_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot90_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot90_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot90_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { + static_assert_uimm_bits!(LANE, 2); + vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot180_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { + static_assert_uimm_bits!(LANE, 3); + vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot180_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot180_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot180_f32(a, b, c) + vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot180_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { + static_assert_uimm_bits!(LANE, 2); + vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot180_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot180_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot180_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + let c: int16x4_t = vdup_n_s16(c); + simd_extract!(vqrdmlah_s16(a, b, c), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_lane_f32) +#[doc = "Signed saturating rounding doubling multiply accumulate returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot270_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert!(LANE == 0); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlah))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { + let a: int32x2_t = vdup_n_s32(a); + let b: int32x2_t = vdup_n_s32(b); + let c: int32x2_t = vdup_n_s32(c); + simd_extract!(vqrdmlah_s32(a, b, c), 0) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmla_rot270_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmla_rot270_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x2_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmla_rot270_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlsh_s16(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_lane_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert!(LANE == 0); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot270_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vqrdmlsh_s32(a, b, c) } -/// Floating-point complex multiply accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcmlaq_rot270_laneq_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,fcma")] -#[cfg_attr(test, assert_instr(fcmla, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_fcma", issue = "117222")] -pub unsafe fn vcmlaq_rot270_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: float32x4_t = simd_shuffle!(c, c, [2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]); - vcmlaq_rot270_f32(a, b, c) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_laneq_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlsh_s16(a, b, c) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_s32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdot_laneq_s32(a: int32x2_t, b: int8x8_t, c: int8x16_t) -> int32x2_t { +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_laneq_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) + vqrdmlsh_s32(a, b, c) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_s32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(sdot, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdotq_laneq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x4_t, +) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = transmute(c); + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlshq_s16(a, b, c) +} + +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x2_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) + vqrdmlshq_s32(a, b, c) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_laneq_u32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdot_laneq_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x16_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_laneq_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + let c: int16x8_t = simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmlshq_s16(a, b, c) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_laneq_u32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(test, assert_instr(udot, LANE = 0))] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] #[rustc_legacy_const_generics(3)] -#[unstable(feature = "stdarch_neon_dotprod", issue = "117224")] -pub unsafe fn vdotq_laneq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_laneq_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, +) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - let c: uint32x4_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmlshq_s32(a, b, c) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmax))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmax_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmax.v1f64")] - fn vmax_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlsh.v4i16" + )] + fn _vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; } - vmax_f64_(a, b) + _vqrdmlsh_s16(a, b, c) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmax))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmax.v2f64")] - fn vmaxq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlsh.v8i16" + )] + fn _vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; } - vmaxq_f64_(a, b) + _vqrdmlshq_s16(a, b, c) } -/// Floating-point Maximum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnm))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnm.v1f64")] - fn vmaxnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlsh.v2i32" + )] + fn _vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; } - vmaxnm_f64_(a, b) + _vqrdmlsh_s32(a, b, c) } -/// Floating-point Maximum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnm))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnm.v2f64")] - fn vmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmlsh.v4i32" + )] + fn _vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; } - vmaxnmq_f64_(a, b) + _vqrdmlshq_s32(a, b, c) } -/// Floating-point maximum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmv_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxnmv_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32")] - fn vmaxnmv_f32_(a: float32x2_t) -> f32; - } - vmaxnmv_f32_(a) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { + static_assert_uimm_bits!(LANE, 2); + vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point maximum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxnmvq_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64")] - fn vmaxnmvq_f64_(a: float64x2_t) -> f64; - } - vmaxnmvq_f64_(a) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { + static_assert_uimm_bits!(LANE, 3); + vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point maximum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmv))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmaxnmvq_f32(a: float32x4_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmv.f32.v4f32")] - fn vmaxnmvq_f32_(a: float32x4_t) -> f32; - } - vmaxnmvq_f32_(a) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { + static_assert_uimm_bits!(LANE, 1); + vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point Maximum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmp.v2f32")] - fn vpmaxnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - vpmaxnm_f32_(a, b) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] +#[rustc_legacy_const_generics(3)] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { + static_assert_uimm_bits!(LANE, 2); + vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) } -/// Floating-point Maximum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmp.v2f64")] - fn vpmaxnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vpmaxnmq_f64_(a, b) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + let c: int16x4_t = vdup_n_s16(c); + simd_extract!(vqrdmlsh_s16(a, b, c), 0) } -/// Floating-point Maximum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32) +#[doc = "Signed saturating rounding doubling multiply subtract returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmp.v4f32")] - fn vpmaxnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - vpmaxnmq_f32_(a, b) +#[target_feature(enable = "rdm")] +#[cfg_attr(test, assert_instr(sqrdmlsh))] +#[stable(feature = "rdm_intrinsics", since = "1.62.0")] +pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { + let a: int32x2_t = vdup_n_s32(a); + let b: int32x2_t = vdup_n_s32(b); + let c: int32x2_t = vdup_n_s32(c); + simd_extract!(vqrdmlsh_s32(a, b, c), 0) } -/// Floating-point maximum number pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] +#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnms_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmv.f32.v2f32")] - fn vpmaxnms_f32_(a: float32x2_t) -> f32; - } - vpmaxnms_f32_(a) +pub unsafe fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { + static_assert_uimm_bits!(LANE, 2); + vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } -/// Floating-point maximum number pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxnmp))] +#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxnmqd_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnmv.f64.v2f64")] - fn vpmaxnmqd_f64_(a: float64x2_t) -> f64; - } - vpmaxnmqd_f64_(a) +pub unsafe fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { + static_assert_uimm_bits!(LANE, 3); + vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) } -/// Floating-point maximum pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxp))] +#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxs_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxv.f32.v2f32")] - fn vpmaxs_f32_(a: float32x2_t) -> f32; - } - vpmaxs_f32_(a) +pub unsafe fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { + static_assert_uimm_bits!(LANE, 1); + vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } -/// Floating-point maximum pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmaxp))] +#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmaxqd_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxv.f64.v2f64")] - fn vpmaxqd_f64_(a: float64x2_t) -> f64; - } - vpmaxqd_f64_(a) +pub unsafe fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { + static_assert_uimm_bits!(LANE, 2); + vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmin))] +#[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmin_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmin.v1f64")] - fn vmin_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - vmin_f64_(a, b) +pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { + simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fmin))] +#[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmin.v2f64")] - fn vminq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vminq_f64_(a, b) +pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { + simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) } -/// Floating-point Minimum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnm))] +#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnm_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnm.v1f64")] - fn vminnm_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - vminnm_f64_(a, b) +pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { + let a: int8x8_t = vdup_n_s8(a); + let b: int8x8_t = vdup_n_s8(b); + simd_extract!(vqrshl_s8(a, b), 0) } -/// Floating-point Minimum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnm))] +#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnm.v2f64")] - fn vminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vminnmq_f64_(a, b) +pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqrshl_s16(a, b), 0) } -/// Floating-point minimum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmv_f32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmv_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32")] - fn vminnmv_f32_(a: float32x2_t) -> f32; - } - vminnmv_f32_(a) +pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { + let a: uint8x8_t = vdup_n_u8(a); + let b: int8x8_t = vdup_n_s8(b); + simd_extract!(vqrshl_u8(a, b), 0) } -/// Floating-point minimum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f64) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmvq_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64")] - fn vminnmvq_f64_(a: float64x2_t) -> f64; - } - vminnmvq_f64_(a) +pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { + let a: uint16x4_t = vdup_n_u16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqrshl_u16(a, b), 0) } -/// Floating-point minimum number across vector -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmv))] +#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vminnmvq_f32(a: float32x4_t) -> f32 { - #[allow(improper_ctypes)] +pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmv.f32.v4f32")] - fn vminnmvq_f32_(a: float32x4_t) -> f32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.i64" + )] + fn _vqrshld_s64(a: i64, b: i64) -> i64; } - vminnmvq_f32_(a) + _vqrshld_s64(a, b) } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_s8(a: int8x16_t) -> int16x8_t { - let a: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_s8(a) +pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.i32" + )] + fn _vqrshls_s32(a: i32, b: i32) -> i32; + } + _vqrshls_s32(a, b) } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_s16(a: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_s16(a) +pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.i32" + )] + fn _vqrshls_u32(a: i32, b: i32) -> i32; + } + _vqrshls_u32(a.as_signed(), b).as_unsigned() } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sxtl2))] +#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_s32(a: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_s32(a) +pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.i64" + )] + fn _vqrshld_u64(a: i64, b: i64) -> i64; + } + _vqrshld_u64(a.as_signed(), b).as_unsigned() } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_u8(a: uint8x16_t) -> uint16x8_t { - let a: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vmovl_u8(a) +pub unsafe fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqrshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_u16(a: uint16x8_t) -> uint32x4_t { - let a: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vmovl_u16(a) +pub unsafe fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Vector move -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uxtl2))] +#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vmovl_high_u32(a: uint32x4_t) -> uint64x2_t { - let a: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vmovl_u32(a) +pub unsafe fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) } -/// Floating-point add pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(faddp))] +#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpaddq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddp.v4f32")] - fn vpaddq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - vpaddq_f32_(a, b) +pub unsafe fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqrshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Floating-point add pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(faddp))] +#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpaddq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddp.v2f64")] - fn vpaddq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vpaddq_f64_(a, b) +pub unsafe fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Floating-point add pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpadds_f32(a: float32x2_t) -> f32 { - let a1: f32 = simd_extract!(a, 0); - let a2: f32 = simd_extract!(a, 1); - a1 + a2 +pub unsafe fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) } -/// Floating-point add pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpaddd_f64(a: float64x2_t) -> f64 { - let a1: f64 = simd_extract!(a, 0); - let a2: f64 = simd_extract!(a, 1); - a1 + a2 +pub unsafe fn vqrshrnd_n_u64(a: u64) -> u32 { + static_assert!(N >= 1 && N <= 32); + let a: uint64x2_t = vdupq_n_u64(a); + simd_extract!(vqrshrn_n_u64::(a), 0) } -/// Floating-point Minimum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmp.v2f32")] - fn vpminnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } - vpminnm_f32_(a, b) +pub unsafe fn vqrshrnh_n_u16(a: u16) -> u8 { + static_assert!(N >= 1 && N <= 8); + let a: uint16x8_t = vdupq_n_u16(a); + simd_extract!(vqrshrn_n_u16::(a), 0) } -/// Floating-point Minimum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64) +#[doc = "Unsigned saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmp.v2f64")] - fn vpminnmq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vpminnmq_f64_(a, b) +pub unsafe fn vqrshrns_n_u32(a: u32) -> u16 { + static_assert!(N >= 1 && N <= 16); + let a: uint32x4_t = vdupq_n_u32(a); + simd_extract!(vqrshrn_n_u32::(a), 0) } -/// Floating-point Minimum Number Pairwise (vector). -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmp.v4f32")] - fn vpminnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } - vpminnmq_f32_(a, b) +pub unsafe fn vqrshrnh_n_s16(a: i16) -> i8 { + static_assert!(N >= 1 && N <= 8); + let a: int16x8_t = vdupq_n_s16(a); + simd_extract!(vqrshrn_n_s16::(a), 0) } -/// Floating-point minimum number pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnms_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmv.f32.v2f32")] - fn vpminnms_f32_(a: float32x2_t) -> f32; - } - vpminnms_f32_(a) +pub unsafe fn vqrshrns_n_s32(a: i32) -> i16 { + static_assert!(N >= 1 && N <= 16); + let a: int32x4_t = vdupq_n_s32(a); + simd_extract!(vqrshrn_n_s32::(a), 0) } -/// Floating-point minimum number pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminnmp))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminnmqd_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnmv.f64.v2f64")] - fn vpminnmqd_f64_(a: float64x2_t) -> f64; - } - vpminnmqd_f64_(a) +pub unsafe fn vqrshrnd_n_s64(a: i64) -> i32 { + static_assert!(N >= 1 && N <= 32); + let a: int64x2_t = vdupq_n_s64(a); + simd_extract!(vqrshrn_n_s64::(a), 0) } -/// Floating-point minimum pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminp))] +#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpmins_f32(a: float32x2_t) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminv.f32.v2f32")] - fn vpmins_f32_(a: float32x2_t) -> f32; - } - vpmins_f32_(a) +pub unsafe fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqrshrun_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Floating-point minimum pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fminp))] +#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vpminqd_f64(a: float64x2_t) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminv.f64.v2f64")] - fn vpminqd_f64_(a: float64x2_t) -> f64; - } - vpminqd_f64_(a) +pub unsafe fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_s16) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull))] +#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_s16(a: i16, b: i16) -> i32 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqdmull_s16(a, b), 0) +pub unsafe fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_s32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_s32(a: i32, b: i32) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmulls.scalar")] - fn vqdmulls_s32_(a: i32, b: i32) -> i64; - } - vqdmulls_s32_(a, b) +pub unsafe fn vqrshrund_n_s64(a: i64) -> u32 { + static_assert!(N >= 1 && N <= 32); + let a: int64x2_t = vdupq_n_s64(a); + simd_extract!(vqrshrun_n_s64::(a), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s16) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - vqdmull_s16(a, b) +pub unsafe fn vqrshrunh_n_s16(a: i16) -> u8 { + static_assert!(N >= 1 && N <= 8); + let a: int16x8_t = vdupq_n_s16(a); + simd_extract!(vqrshrun_n_s16::(a), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_s32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [2, 3]); - vqdmull_s32(a, b) +pub unsafe fn vqrshruns_n_s32(a: i32) -> u16 { + static_assert!(N >= 1 && N <= 16); + let a: int32x4_t = vdupq_n_s32(a); + simd_extract!(vqrshrun_n_s32::(a), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(test, assert_instr(sqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_n_s16(a: int16x8_t, b: i16) -> int32x4_t { - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = vdup_n_s16(b); - vqdmull_s16(a, b) +pub unsafe fn vqshlb_n_s8(a: i8) -> i8 { + static_assert_uimm_bits!(N, 3); + simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_n_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2))] +#[cfg_attr(test, assert_instr(sqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_n_s32(a: int32x4_t, b: i32) -> int64x2_t { - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = vdup_n_s32(b); - vqdmull_s32(a, b) +pub unsafe fn vqshld_n_s64(a: i64) -> i64 { + static_assert_uimm_bits!(N, 6); + simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) } -/// Vector saturating doubling long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 4))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(sqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(N, 3); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) +pub unsafe fn vqshlh_n_s16(a: i16) -> i16 { + static_assert_uimm_bits!(N, 4); + simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) } -/// Vector saturating doubling long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_laneq_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(sqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) +pub unsafe fn vqshls_n_s32(a: i32) -> i32 { + static_assert_uimm_bits!(N, 5); + simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_lane_s16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(uqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_lane_s16(a: i16, b: int16x4_t) -> i32 { - static_assert_uimm_bits!(N, 2); - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) +pub unsafe fn vqshlb_n_u8(a: u8) -> u8 { + static_assert_uimm_bits!(N, 3); + simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmullh_laneq_s16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 4))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(uqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmullh_laneq_s16(a: i16, b: int16x8_t) -> i32 { - static_assert_uimm_bits!(N, 3); - let b: i16 = simd_extract!(b, N as u32); - vqdmullh_s16(a, b) +pub unsafe fn vqshld_n_u64(a: u64) -> u64 { + static_assert_uimm_bits!(N, 6); + simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_lane_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(uqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_lane_s32(a: i32, b: int32x2_t) -> i64 { - static_assert_uimm_bits!(N, 1); - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) +pub unsafe fn vqshlh_n_u16(a: u16) -> u16 { + static_assert_uimm_bits!(N, 4); + simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulls_laneq_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(uqshl, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulls_laneq_s32(a: i32, b: int32x4_t) -> i64 { - static_assert_uimm_bits!(N, 2); - let b: i32 = simd_extract!(b, N as u32); - vqdmulls_s32(a, b) +pub unsafe fn vqshls_n_u32(a: u32) -> u32 { + static_assert_uimm_bits!(N, 5); + simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_lane_s16(a: int16x8_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) +pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { + let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_lane_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 1))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_lane_s32(a: int32x4_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) +pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { + let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 4))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_laneq_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(N, 3); - let a: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) +pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { + let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_high_laneq_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmull2, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmull_high_laneq_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - let a: int32x2_t = simd_shuffle!(a, a, [2, 3]); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) +pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { + let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - vqaddq_s32(a, vqdmull_high_s16(b, c)) +pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { + let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - vqaddq_s64(a, vqdmull_high_s32(b, c)) +pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { + let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); + simd_extract!(c, 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { - vqaddq_s32(a, vqdmull_high_n_s16(b, c)) +pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.i64" + )] + fn _vqshld_s64(a: i64, b: i64) -> i64; + } + _vqshld_s64(a, b) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_n_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2))] +#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { - vqaddq_s64(a, vqdmull_high_n_s32(b, c)) +pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.i64" + )] + fn _vqshld_u64(a: i64, b: i64) -> i64; + } + _vqshld_u64(a.as_signed(), b).as_unsigned() } -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 2))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { +pub unsafe fn vqshlub_n_s8(a: i8) -> u8 { static_assert_uimm_bits!(N, 3); - vqaddq_s32(a, vqdmull_laneq_s16::(b, c)) + simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) } -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_laneq_s32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - vqaddq_s64(a, vqdmull_laneq_s32::(b, c)) +pub unsafe fn vqshlud_n_s64(a: i64) -> u64 { + static_assert_uimm_bits!(N, 6); + simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqaddq_s32(a, vqdmull_high_lane_s16::(b, c)) +pub unsafe fn vqshluh_n_s16(a: i16) -> u16 { + static_assert_uimm_bits!(N, 4); + simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(N, 3); - vqaddq_s32(a, vqdmull_high_laneq_s16::(b, c)) +pub unsafe fn vqshlus_n_s32(a: i32) -> u32 { + static_assert_uimm_bits!(N, 5); + simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_lane_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqaddq_s64(a, vqdmull_high_lane_s32::(b, c)) +pub unsafe fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_high_laneq_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlal_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - vqaddq_s64(a, vqdmull_high_laneq_s32::(b, c)) +pub unsafe fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_s16) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal))] +#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_s16(a: i32, b: i16, c: i16) -> i32 { - let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - vqadds_s32(a, simd_extract!(x, 0)) +pub unsafe fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_s32) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal))] +#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_s32(a: i64, b: i32, c: i32) -> i64 { - let x: i64 = vqaddd_s64(a, vqdmulls_s32(b, c)); - x as i64 +pub unsafe fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_lane_s16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { - static_assert_uimm_bits!(LANE, 2); - vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) +pub unsafe fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlalh_laneq_s16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlalh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { - static_assert_uimm_bits!(LANE, 3); - vqdmlalh_s16(a, b, simd_extract!(c, LANE as u32)) +pub unsafe fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_lane_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { - static_assert_uimm_bits!(LANE, 1); - vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) +pub unsafe fn vqshrnd_n_s64(a: i64) -> i32 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.i32" + )] + fn _vqshrnd_n_s64(a: i64, n: i32) -> i32; + } + _vqshrnd_n_s64(a, N) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlals_laneq_s32) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlal, LANE = 0))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlals_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { - static_assert_uimm_bits!(LANE, 2); - vqdmlals_s32(a, b, simd_extract!(c, LANE as u32)) +pub unsafe fn vqshrnd_n_u64(a: u64) -> u32 { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.i32" + )] + fn _vqshrnd_n_u64(a: i64, n: i32) -> i32; + } + _vqshrnd_n_u64(a.as_signed(), N).as_unsigned() } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s16) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - vqsubq_s32(a, vqdmull_high_s16(b, c)) +pub unsafe fn vqshrnh_n_s16(a: i16) -> i8 { + static_assert!(N >= 1 && N <= 8); + simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - vqsubq_s64(a, vqdmull_high_s32(b, c)) +pub unsafe fn vqshrns_n_s32(a: i32) -> i16 { + static_assert!(N >= 1 && N <= 16); + simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_n_s16(a: int32x4_t, b: int16x8_t, c: i16) -> int32x4_t { - vqsubq_s32(a, vqdmull_high_n_s16(b, c)) +pub unsafe fn vqshrnh_n_u16(a: u16) -> u8 { + static_assert!(N >= 1 && N <= 8); + simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_n_s32) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_n_s32(a: int64x2_t, b: int32x4_t, c: i32) -> int64x2_t { - vqsubq_s64(a, vqdmull_high_n_s32(b, c)) +pub unsafe fn vqshrns_n_u32(a: u32) -> u16 { + static_assert!(N >= 1 && N <= 16); + simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s16) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 2))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(N, 3); - vqsubq_s32(a, vqdmull_laneq_s16::(b, c)) +pub unsafe fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vqshrun_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_laneq_s32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - vqsubq_s64(a, vqdmull_laneq_s32::(b, c)) +pub unsafe fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s16) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_lane_s16(a: int32x4_t, b: int16x8_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqsubq_s32(a, vqdmull_high_lane_s16::(b, c)) +pub unsafe fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s16) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_laneq_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(N, 3); - vqsubq_s32(a, vqdmull_high_laneq_s16::(b, c)) +pub unsafe fn vqshrund_n_s64(a: i64) -> u32 { + static_assert!(N >= 1 && N <= 32); + simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_lane_s32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_lane_s32(a: int64x2_t, b: int32x4_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqsubq_s64(a, vqdmull_high_lane_s32::(b, c)) +pub unsafe fn vqshrunh_n_s16(a: i16) -> u8 { + static_assert!(N >= 1 && N <= 8); + simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_high_laneq_s32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl2, N = 1))] -#[rustc_legacy_const_generics(3)] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsl_high_laneq_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(N, 2); - vqsubq_s64(a, vqdmull_high_laneq_s32::(b, c)) +pub unsafe fn vqshruns_n_s32(a: i32) -> u16 { + static_assert!(N >= 1 && N <= 16); + simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_s16(a: i32, b: i16, c: i16) -> i32 { - let x: int32x4_t = vqdmull_s16(vdup_n_s16(b), vdup_n_s16(c)); - vqsubs_s32(a, simd_extract!(x, 0)) +#[cfg_attr(test, assert_instr(sqsub))] +pub unsafe fn vqsubb_s8(a: i8, b: i8) -> i8 { + let a: int8x8_t = vdup_n_s8(a); + let b: int8x8_t = vdup_n_s8(b); + simd_extract!(vqsub_s8(a, b), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_s32(a: i64, b: i32, c: i32) -> i64 { - let x: i64 = vqsubd_s64(a, vqdmulls_s32(b, c)); - x as i64 +#[cfg_attr(test, assert_instr(sqsub))] +pub unsafe fn vqsubh_s16(a: i16, b: i16) -> i16 { + let a: int16x4_t = vdup_n_s16(a); + let b: int16x4_t = vdup_n_s16(b); + simd_extract!(vqsub_s16(a, b), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_lane_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] -#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_lane_s16(a: i32, b: i16, c: int16x4_t) -> i32 { - static_assert_uimm_bits!(LANE, 2); - vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) +#[cfg_attr(test, assert_instr(uqsub))] +pub unsafe fn vqsubb_u8(a: u8, b: u8) -> u8 { + let a: uint8x8_t = vdup_n_u8(a); + let b: uint8x8_t = vdup_n_u8(b); + simd_extract!(vqsub_u8(a, b), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlslh_laneq_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] -#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlslh_laneq_s16(a: i32, b: i16, c: int16x8_t) -> i32 { - static_assert_uimm_bits!(LANE, 3); - vqdmlslh_s16(a, b, simd_extract!(c, LANE as u32)) +#[cfg_attr(test, assert_instr(uqsub))] +pub unsafe fn vqsubh_u16(a: u16, b: u16) -> u16 { + let a: uint16x4_t = vdup_n_u16(a); + let b: uint16x4_t = vdup_n_u16(b); + simd_extract!(vqsub_u16(a, b), 0) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_lane_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] -#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_lane_s32(a: i64, b: i32, c: int32x2_t) -> i64 { - static_assert_uimm_bits!(LANE, 1); - vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) +#[cfg_attr(test, assert_instr(sqsub))] +pub unsafe fn vqsubs_s32(a: i32, b: i32) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.i32" + )] + fn _vqsubs_s32(a: i32, b: i32) -> i32; + } + _vqsubs_s32(a, b) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsls_laneq_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmlsl, LANE = 0))] -#[rustc_legacy_const_generics(3)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmlsls_laneq_s32(a: i64, b: i32, c: int32x4_t) -> i64 { - static_assert_uimm_bits!(LANE, 2); - vqdmlsls_s32(a, b, simd_extract!(c, LANE as u32)) +#[cfg_attr(test, assert_instr(sqsub))] +pub unsafe fn vqsubd_s64(a: i64, b: i64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.i64" + )] + fn _vqsubd_s64(a: i64, b: i64) -> i64; + } + _vqsubd_s64(a, b) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_s16(a: i16, b: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqdmulh_s16(a, b), 0) +#[cfg_attr(test, assert_instr(uqsub))] +pub unsafe fn vqsubs_u32(a: u32, b: u32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.i32" + )] + fn _vqsubs_u32(a: i32, b: i32) -> i32; + } + _vqsubs_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_s32(a: i32, b: i32) -> i32 { - let a: int32x2_t = vdup_n_s32(a); - let b: int32x2_t = vdup_n_s32(b); - simd_extract!(vqdmulh_s32(a, b), 0) +#[cfg_attr(test, assert_instr(uqsub))] +pub unsafe fn vqsubd_u64(a: u64, b: u64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.i64" + )] + fn _vqsubd_u64(a: i64, b: i64) -> i64; + } + _vqsubd_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_lane_s16) +#[doc = "Rotate and exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { - static_assert_uimm_bits!(N, 2); - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(rax1))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.rax1" + )] + fn _vrax1q_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vrax1q_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhh_laneq_s16) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { - static_assert_uimm_bits!(N, 3); - let b: i16 = simd_extract!(b, N as u32); - vqdmulhh_s16(a, b) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbit_s8(a: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rbit.v8i8" + )] + fn _vrbit_s8(a: int8x8_t) -> int8x8_t; + } + _vrbit_s8(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_lane_s32) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, N = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { - static_assert_uimm_bits!(N, 1); - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbitq_s8(a: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rbit.v16i8" + )] + fn _vrbitq_s8(a: int8x16_t) -> int8x16_t; + } + _vrbitq_s8(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhs_laneq_s32) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, N = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { - static_assert_uimm_bits!(N, 2); - let b: i32 = simd_extract!(b, N as u32); - vqdmulhs_s32(a, b) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbit_u8(a: uint8x8_t) -> uint8x8_t { + transmute(vrbit_s8(transmute(a))) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s16) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbitq_u8(a: uint8x16_t) -> uint8x16_t { + transmute(vrbitq_s8(transmute(a))) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s16) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbit_p8(a: poly8x8_t) -> poly8x8_t { + transmute(vrbit_s8(transmute(a))) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_lane_s32) +#[doc = "Reverse bit order"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) +#[cfg_attr(test, assert_instr(rbit))] +pub unsafe fn vrbitq_p8(a: poly8x16_t) -> poly8x16_t { + transmute(vrbitq_s8(transmute(a))) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_lane_s32) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) +pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v1f64" + )] + fn _vrecpe_f64(a: float64x1_t) -> float64x1_t; + } + _vrecpe_f64(a) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_s16) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn))] +#[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnh_s16(a: i16) -> i8 { - simd_extract!(vqmovn_s16(vdupq_n_s16(a)), 0) +pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v2f64" + )] + fn _vrecpeq_f64(a: float64x2_t) -> float64x2_t; + } + _vrecpeq_f64(a) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_s32) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn))] +#[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovns_s32(a: i32) -> i16 { - simd_extract!(vqmovn_s32(vdupq_n_s32(a)), 0) +pub unsafe fn vrecped_f64(a: f64) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.f64" + )] + fn _vrecped_f64(a: f64) -> f64; + } + _vrecped_f64(a) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnh_u16) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn))] +#[cfg_attr(test, assert_instr(frecpe))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnh_u16(a: u16) -> u8 { - simd_extract!(vqmovn_u16(vdupq_n_u16(a)), 0) +pub unsafe fn vrecpes_f32(a: f32) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.f32" + )] + fn _vrecpes_f32(a: f32) -> f32; + } + _vrecpes_f32(a) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovns_u32) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn))] +#[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovns_u32(a: u32) -> u16 { - simd_extract!(vqmovn_u32(vdupq_n_u32(a)), 0) +pub unsafe fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v1f64" + )] + fn _vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; + } + _vrecps_f64(a, b) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_s64) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn))] +#[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnd_s64(a: i64) -> i32 { - #[allow(improper_ctypes)] +pub unsafe fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.scalar.sqxtn.i32.i64")] - fn vqmovnd_s64_(a: i64) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v2f64" + )] + fn _vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - vqmovnd_s64_(a) + _vrecpsq_f64(a, b) } -/// Saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovnd_u64) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn))] +#[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovnd_u64(a: u64) -> u32 { - #[allow(improper_ctypes)] +pub unsafe fn vrecpsd_f64(a: f64, b: f64) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.scalar.uqxtn.i32.i64")] - fn vqmovnd_u64_(a: u64) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.f64" + )] + fn _vrecpsd_f64(a: f64, b: f64) -> f64; } - vqmovnd_u64_(a) + _vrecpsd_f64(a, b) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s16) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(test, assert_instr(frecps))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - simd_shuffle!(a, vqmovn_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub unsafe fn vrecpss_f32(a: f32, b: f32) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.f32" + )] + fn _vrecpss_f32(a: f32, b: f32) -> f32; + } + _vrecpss_f32(a, b) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s32) +#[doc = "Floating-point reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - simd_shuffle!(a, vqmovn_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +pub unsafe fn vrecpxd_f64(a: f64) -> f64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpx.f64" + )] + fn _vrecpxd_f64(a: f64) -> f64; + } + _vrecpxd_f64(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_s64) +#[doc = "Floating-point reciprocal exponent"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtn2))] +#[cfg_attr(test, assert_instr(frecpx))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - simd_shuffle!(a, vqmovn_s64(b), [0, 1, 2, 3]) +pub unsafe fn vrecpxs_f32(a: f32) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpx.f32" + )] + fn _vrecpxs_f32(a: f32) -> f32; + } + _vrecpxs_f32(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - simd_shuffle!(a, vqmovn_u16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { + transmute(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - simd_shuffle!(a, vqmovn_u32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { + transmute(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_high_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqxtn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovn_high_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - simd_shuffle!(a, vqmovn_u64(b), [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovunh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovunh_s16(a: i16) -> u8 { - simd_extract!(vqmovun_s16(vdupq_n_s16(a)), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovuns_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovuns_s32(a: i32) -> u16 { - simd_extract!(vqmovun_s32(vdupq_n_s32(a)), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovund_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovund_s64(a: i64) -> u32 { - simd_extract!(vqmovun_s64(vdupq_n_s64(a)), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { - simd_shuffle!(a, vqmovun_s16(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { - simd_shuffle!(a, vqmovun_s32(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_high_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqxtun2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqmovun_high_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { - simd_shuffle!(a, vqmovun_s64(b), [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_s16(a: i16, b: i16) -> i16 { - simd_extract!(vqrdmulh_s16(vdup_n_s16(a), vdup_n_s16(b)), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_s32(a: i32, b: i32) -> i32 { - simd_extract!(vqrdmulh_s32(vdup_n_s32(a), vdup_n_s32(b)), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_lane_s16(a: i16, b: int16x4_t) -> i16 { - static_assert_uimm_bits!(LANE, 2); - vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhh_laneq_s16(a: i16, b: int16x8_t) -> i16 { - static_assert_uimm_bits!(LANE, 3); - vqrdmulhh_s16(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_lane_s32(a: i32, b: int32x2_t) -> i32 { - static_assert_uimm_bits!(LANE, 1); - vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhs_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrdmulhs_laneq_s32(a: i32, b: int32x4_t) -> i32 { - static_assert_uimm_bits!(LANE, 2); - vqrdmulhs_s32(a, simd_extract!(b, LANE as u32)) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlah.v4i16")] - fn vqrdmlah_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; - } - vqrdmlah_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlah.v8i16")] - fn vqrdmlahq_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - vqrdmlahq_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlah.v2i32")] - fn vqrdmlah_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; - } - vqrdmlah_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlah.v4i32")] - fn vqrdmlahq_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; - } - vqrdmlahq_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_s16(a: i16, b: i16, c: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - let c: int16x4_t = vdup_n_s16(c); - simd_extract!(vqrdmlah_s16(a, b, c), 0) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_s32(a: i32, b: i32, c: i32) -> i32 { - let a: int32x2_t = vdup_n_s32(a); - let b: int32x2_t = vdup_n_s32(b); - let c: int32x2_t = vdup_n_s32(c); - simd_extract!(vqrdmlah_s32(a, b, c), 0) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlah_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlah_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlah_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlah_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahq_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlahq_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { - static_assert_uimm_bits!(LANE, 2); - vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { - static_assert_uimm_bits!(LANE, 3); - vqrdmlahh_s16(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { - static_assert_uimm_bits!(LANE, 1); - vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply accumulate returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlahs_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlah, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlahs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { - static_assert_uimm_bits!(LANE, 2); - vqrdmlahs_s32(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlsh.v4i16")] - fn vqrdmlsh_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t; - } - vqrdmlsh_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlsh.v8i16")] - fn vqrdmlshq_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t; - } - vqrdmlshq_s16_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlsh.v2i32")] - fn vqrdmlsh_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t; - } - vqrdmlsh_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmlsh.v4i32")] - fn vqrdmlshq_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; - } - vqrdmlshq_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_s16(a: i16, b: i16, c: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - let c: int16x4_t = vdup_n_s16(c); - simd_extract!(vqrdmlsh_s16(a, b, c), 0) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh))] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_s32(a: i32, b: i32, c: i32) -> i32 { - let a: int32x2_t = vdup_n_s32(a); - let b: int32x2_t = vdup_n_s32(b); - let c: int32x2_t = vdup_n_s32(c); - simd_extract!(vqrdmlsh_s32(a, b, c), 0) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - let c: int16x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlsh_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - let c: int16x8_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s16(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlsh_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlsh_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vqrdmlsh_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshq_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmlshq_s32(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_lane_s16(a: i16, b: i16, c: int16x4_t) -> i16 { - static_assert_uimm_bits!(LANE, 2); - vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshh_laneq_s16(a: i16, b: i16, c: int16x8_t) -> i16 { - static_assert_uimm_bits!(LANE, 3); - vqrdmlshh_s16(a, b, simd_extract!(c, LANE as u32)) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_lane_s32) -#[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_lane_s32(a: i32, b: i32, c: int32x2_t) -> i32 { - static_assert_uimm_bits!(LANE, 1); - vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) -} - -/// Signed saturating rounding doubling multiply subtract returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmlshs_laneq_s32) -#[inline] -#[target_feature(enable = "rdm")] -#[cfg_attr(test, assert_instr(sqrdmlsh, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[stable(feature = "rdm_intrinsics", since = "1.62.0")] -pub unsafe fn vqrdmlshs_laneq_s32(a: i32, b: i32, c: int32x4_t) -> i32 { - static_assert_uimm_bits!(LANE, 2); - vqrdmlshs_s32(a, b, simd_extract!(c, LANE as u32)) -} - -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshls_s32(a: i32, b: i32) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.i32")] - fn vqrshls_s32_(a: i32, b: i32) -> i32; - } - vqrshls_s32_(a, b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshld_s64(a: i64, b: i64) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.i64")] - fn vqrshld_s64_(a: i64, b: i64) -> i64; - } - vqrshld_s64_(a, b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlb_s8(a: i8, b: i8) -> i8 { - let a: int8x8_t = vdup_n_s8(a); - let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqrshl_s8(a, b), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlh_s16(a: i16, b: i16) -> i16 { - let a: int16x4_t = vdup_n_s16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqrshl_s16(a, b), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshls_u32(a: u32, b: i32) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.i32")] - fn vqrshls_u32_(a: u32, b: i32) -> u32; - } - vqrshls_u32_(a, b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshld_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshld_u64(a: u64, b: i64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.i64")] - fn vqrshld_u64_(a: u64, b: i64) -> u64; - } - vqrshld_u64_(a, b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlb_u8(a: u8, b: i8) -> u8 { - let a: uint8x8_t = vdup_n_u8(a); - let b: int8x8_t = vdup_n_s8(b); - simd_extract!(vqrshl_u8(a, b), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshlh_u16(a: u16, b: i16) -> u16 { - let a: uint16x4_t = vdup_n_u16(a); - let b: int16x4_t = vdup_n_s16(b); - simd_extract!(vqrshl_u16(a, b), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnh_n_s16(a: i16) -> i8 { - static_assert!(N >= 1 && N <= 8); - let a: int16x8_t = vdupq_n_s16(a); - simd_extract!(vqrshrn_n_s16::(a), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrns_n_s32(a: i32) -> i16 { - static_assert!(N >= 1 && N <= 16); - let a: int32x4_t = vdupq_n_s32(a); - simd_extract!(vqrshrn_n_s32::(a), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnd_n_s64(a: i64) -> i32 { - static_assert!(N >= 1 && N <= 32); - let a: int64x2_t = vdupq_n_s64(a); - simd_extract!(vqrshrn_n_s64::(a), 0) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqrshrn_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64) +#[doc = "Floating-point round to 32-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrn_n_s64::(b), [0, 1, 2, 3]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] +pub unsafe fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32x.v2f32" + )] + fn _vrnd32x_f32(a: float32x2_t) -> float32x2_t; + } + _vrnd32x_f32(a) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16) +#[doc = "Floating-point round to 32-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnh_n_u16(a: u16) -> u8 { - static_assert!(N >= 1 && N <= 8); - let a: uint16x8_t = vdupq_n_u16(a); - simd_extract!(vqrshrn_n_u16::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] +pub unsafe fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32x.v4f32" + )] + fn _vrnd32xq_f32(a: float32x4_t) -> float32x4_t; + } + _vrnd32xq_f32(a) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32) +#[doc = "Floating-point round to 32-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrns_n_u32(a: u32) -> u16 { - static_assert!(N >= 1 && N <= 16); - let a: uint32x4_t = vdupq_n_u32(a); - simd_extract!(vqrshrn_n_u32::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] +pub unsafe fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32x.v2f64" + )] + fn _vrnd32xq_f64(a: float64x2_t) -> float64x2_t; + } + _vrnd32xq_f64(a) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64) +#[doc = "Floating-point round to 32-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrnd_n_u64(a: u64) -> u32 { - static_assert!(N >= 1 && N <= 32); - let a: uint64x2_t = vdupq_n_u64(a); - simd_extract!(vqrshrn_n_u64::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] +pub unsafe fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.frint32x.f64" + )] + fn _vrnd32x_f64(a: f64) -> f64; + } + transmute(_vrnd32x_f64(simd_extract!(a, 0))) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16) +#[doc = "Floating-point round to 32-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqrshrn_n_u16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] +pub unsafe fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32z.v2f32" + )] + fn _vrnd32z_f32(a: float32x2_t) -> float32x2_t; + } + _vrnd32z_f32(a) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32) +#[doc = "Floating-point round to 32-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] +pub unsafe fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32z.v4f32" + )] + fn _vrnd32zq_f32(a: float32x4_t) -> float32x4_t; + } + _vrnd32zq_f32(a) } -/// Unsigned saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64) +#[doc = "Floating-point round to 32-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrn_n_u64::(b), [0, 1, 2, 3]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] +pub unsafe fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint32z.v2f64" + )] + fn _vrnd32zq_f64(a: float64x2_t) -> float64x2_t; + } + _vrnd32zq_f64(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16) +#[doc = "Floating-point round to 32-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrunh_n_s16(a: i16) -> u8 { - static_assert!(N >= 1 && N <= 8); - let a: int16x8_t = vdupq_n_s16(a); - simd_extract!(vqrshrun_n_s16::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] +pub unsafe fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.frint32z.f64" + )] + fn _vrnd32z_f64(a: f64) -> f64; + } + transmute(_vrnd32z_f64(simd_extract!(a, 0))) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32) +#[doc = "Floating-point round to 64-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshruns_n_s32(a: i32) -> u16 { - static_assert!(N >= 1 && N <= 16); - let a: int32x4_t = vdupq_n_s32(a); - simd_extract!(vqrshrun_n_s32::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] +pub unsafe fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64x.v2f32" + )] + fn _vrnd64x_f32(a: float32x2_t) -> float32x2_t; + } + _vrnd64x_f32(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64) +#[doc = "Floating-point round to 64-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrund_n_s64(a: i64) -> u32 { - static_assert!(N >= 1 && N <= 32); - let a: int64x2_t = vdupq_n_s64(a); - simd_extract!(vqrshrun_n_s64::(a), 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] +pub unsafe fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64x.v4f32" + )] + fn _vrnd64xq_f32(a: float32x4_t) -> float32x4_t; + } + _vrnd64xq_f32(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16) +#[doc = "Floating-point round to 64-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqrshrun_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] +pub unsafe fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64x.v2f64" + )] + fn _vrnd64xq_f64(a: float64x2_t) -> float64x2_t; + } + _vrnd64xq_f64(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32) +#[doc = "Floating-point round to 64-bit integer, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqrshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] +pub unsafe fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.frint64x.f64" + )] + fn _vrnd64x_f64(a: f64) -> f64; + } + transmute(_vrnd64x_f64(simd_extract!(a, 0))) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64) +#[doc = "Floating-point round to 64-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun2, N = 2))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqrshrun_n_s64::(b), [0, 1, 2, 3]) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] +pub unsafe fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64z.v2f32" + )] + fn _vrnd64z_f32(a: float32x2_t) -> float32x2_t; + } + _vrnd64z_f32(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_s64) +#[doc = "Floating-point round to 64-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_s64(a: i64, b: i64) -> i64 { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] +pub unsafe fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.i64")] - fn vqshld_s64_(a: i64, b: i64) -> i64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64z.v4f32" + )] + fn _vrnd64zq_f32(a: float32x4_t) -> float32x4_t; } - vqshld_s64_(a, b) + _vrnd64zq_f32(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8) +#[doc = "Floating-point round to 64-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_s8(a: i8, b: i8) -> i8 { - let c: int8x8_t = vqshl_s8(vdup_n_s8(a), vdup_n_s8(b)); - simd_extract!(c, 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] +pub unsafe fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frint64z.v2f64" + )] + fn _vrnd64zq_f64(a: float64x2_t) -> float64x2_t; + } + _vrnd64zq_f64(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16) +#[doc = "Floating-point round to 64-bit integer toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_s16(a: i16, b: i16) -> i16 { - let c: int16x4_t = vqshl_s16(vdup_n_s16(a), vdup_n_s16(b)); - simd_extract!(c, 0) +#[target_feature(enable = "neon,frintts")] +#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] +pub unsafe fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.frint64z.f64" + )] + fn _vrnd64z_f64(a: f64) -> f64; + } + transmute(_vrnd64z_f64(simd_extract!(a, 0))) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32) +#[doc = "Floating-point round to integral, toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_s32(a: i32, b: i32) -> i32 { - let c: int32x2_t = vqshl_s32(vdup_n_s32(a), vdup_n_s32(b)); - simd_extract!(c, 0) +#[cfg_attr(test, assert_instr(frintz))] +pub unsafe fn vrnd_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.trunc.v2f32" + )] + fn _vrnd_f32(a: float32x2_t) -> float32x2_t; + } + _vrnd_f32(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_u64) +#[doc = "Floating-point round to integral, toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_u64(a: u64, b: i64) -> u64 { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(frintz))] +pub unsafe fn vrndq_f32(a: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.i64")] - fn vqshld_u64_(a: u64, b: i64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.trunc.v4f32" + )] + fn _vrndq_f32(a: float32x4_t) -> float32x4_t; } - vqshld_u64_(a, b) + _vrndq_f32(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8) +#[doc = "Floating-point round to integral, toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_u8(a: u8, b: i8) -> u8 { - let c: uint8x8_t = vqshl_u8(vdup_n_u8(a), vdup_n_s8(b)); - simd_extract!(c, 0) +#[cfg_attr(test, assert_instr(frintz))] +pub unsafe fn vrnd_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.trunc.v1f64" + )] + fn _vrnd_f64(a: float64x1_t) -> float64x1_t; + } + _vrnd_f64(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16) +#[doc = "Floating-point round to integral, toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_u16(a: u16, b: i16) -> u16 { - let c: uint16x4_t = vqshl_u16(vdup_n_u16(a), vdup_n_s16(b)); - simd_extract!(c, 0) +#[cfg_attr(test, assert_instr(frintz))] +pub unsafe fn vrndq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.trunc.v2f64" + )] + fn _vrndq_f64(a: float64x2_t) -> float64x2_t; + } + _vrndq_f64(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32) +#[doc = "Floating-point round to integral, to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_u32(a: u32, b: i32) -> u32 { - let c: uint32x2_t = vqshl_u32(vdup_n_u32(a), vdup_n_s32(b)); - simd_extract!(c, 0) +#[cfg_attr(test, assert_instr(frinta))] +pub unsafe fn vrnda_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.round.v2f32" + )] + fn _vrnda_f32(a: float32x2_t) -> float32x2_t; + } + _vrnda_f32(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8) +#[doc = "Floating-point round to integral, to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_n_s8(a: i8) -> i8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(vqshl_n_s8::(vdup_n_s8(a)), 0) +#[cfg_attr(test, assert_instr(frinta))] +pub unsafe fn vrndaq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.round.v4f32" + )] + fn _vrndaq_f32(a: float32x4_t) -> float32x4_t; + } + _vrndaq_f32(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16) +#[doc = "Floating-point round to integral, to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_n_s16(a: i16) -> i16 { - static_assert_uimm_bits!(N, 4); - simd_extract!(vqshl_n_s16::(vdup_n_s16(a)), 0) +#[cfg_attr(test, assert_instr(frinta))] +pub unsafe fn vrnda_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.round.v1f64" + )] + fn _vrnda_f64(a: float64x1_t) -> float64x1_t; + } + _vrnda_f64(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32) +#[doc = "Floating-point round to integral, to nearest with ties to away"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_n_s32(a: i32) -> i32 { - static_assert_uimm_bits!(N, 5); - simd_extract!(vqshl_n_s32::(vdup_n_s32(a)), 0) +#[cfg_attr(test, assert_instr(frinta))] +pub unsafe fn vrndaq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.round.v2f64" + )] + fn _vrndaq_f64(a: float64x2_t) -> float64x2_t; + } + _vrndaq_f64(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_s64) +#[doc = "Floating-point round to integral, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_n_s64(a: i64) -> i64 { - static_assert_uimm_bits!(N, 6); - simd_extract!(vqshl_n_s64::(vdup_n_s64(a)), 0) +#[cfg_attr(test, assert_instr(frinti))] +pub unsafe fn vrndi_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.nearbyint.v2f32" + )] + fn _vrndi_f32(a: float32x2_t) -> float32x2_t; + } + _vrndi_f32(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8) +#[doc = "Floating-point round to integral, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlb_n_u8(a: u8) -> u8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(vqshl_n_u8::(vdup_n_u8(a)), 0) +#[cfg_attr(test, assert_instr(frinti))] +pub unsafe fn vrndiq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.nearbyint.v4f32" + )] + fn _vrndiq_f32(a: float32x4_t) -> float32x4_t; + } + _vrndiq_f32(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16) +#[doc = "Floating-point round to integral, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndi_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlh_n_u16(a: u16) -> u16 { - static_assert_uimm_bits!(N, 4); - simd_extract!(vqshl_n_u16::(vdup_n_u16(a)), 0) +#[cfg_attr(test, assert_instr(frinti))] +pub unsafe fn vrndi_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.nearbyint.v1f64" + )] + fn _vrndi_f64(a: float64x1_t) -> float64x1_t; + } + _vrndi_f64(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32) +#[doc = "Floating-point round to integral, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndiq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshls_n_u32(a: u32) -> u32 { - static_assert_uimm_bits!(N, 5); - simd_extract!(vqshl_n_u32::(vdup_n_u32(a)), 0) +#[cfg_attr(test, assert_instr(frinti))] +pub unsafe fn vrndiq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.nearbyint.v2f64" + )] + fn _vrndiq_f64(a: float64x2_t) -> float64x2_t; + } + _vrndiq_f64(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshld_n_u64) +#[doc = "Floating-point round to integral, toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshld_n_u64(a: u64) -> u64 { - static_assert_uimm_bits!(N, 6); - simd_extract!(vqshl_n_u64::(vdup_n_u64(a)), 0) +#[cfg_attr(test, assert_instr(frintm))] +pub unsafe fn vrndm_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.floor.v2f32" + )] + fn _vrndm_f32(a: float32x2_t) -> float32x2_t; + } + _vrndm_f32(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8) +#[doc = "Floating-point round to integral, toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlub_n_s8(a: i8) -> u8 { - static_assert_uimm_bits!(N, 3); - simd_extract!(vqshlu_n_s8::(vdup_n_s8(a)), 0) +#[cfg_attr(test, assert_instr(frintm))] +pub unsafe fn vrndmq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.floor.v4f32" + )] + fn _vrndmq_f32(a: float32x4_t) -> float32x4_t; + } + _vrndmq_f32(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16) +#[doc = "Floating-point round to integral, toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluh_n_s16(a: i16) -> u16 { - static_assert_uimm_bits!(N, 4); - simd_extract!(vqshlu_n_s16::(vdup_n_s16(a)), 0) +#[cfg_attr(test, assert_instr(frintm))] +pub unsafe fn vrndm_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.floor.v1f64" + )] + fn _vrndm_f64(a: float64x1_t) -> float64x1_t; + } + _vrndm_f64(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32) +#[doc = "Floating-point round to integral, toward minus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlus_n_s32(a: i32) -> u32 { - static_assert_uimm_bits!(N, 5); - simd_extract!(vqshlu_n_s32::(vdup_n_s32(a)), 0) +#[cfg_attr(test, assert_instr(frintm))] +pub unsafe fn vrndmq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.floor.v2f64" + )] + fn _vrndmq_f64(a: float64x2_t) -> float64x2_t; + } + _vrndmq_f64(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlud_n_s64) +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlud_n_s64(a: i64) -> u64 { - static_assert_uimm_bits!(N, 6); - simd_extract!(vqshlu_n_s64::(vdup_n_s64(a)), 0) +#[cfg_attr(test, assert_instr(frintn))] +pub unsafe fn vrndn_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frintn.v1f64" + )] + fn _vrndn_f64(a: float64x1_t) -> float64x1_t; + } + _vrndn_f64(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64) +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnd_n_s64(a: i64) -> i32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(frintn))] +pub unsafe fn vrndnq_f64(a: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrn.i32")] - fn vqshrnd_n_s64_(a: i64, n: i32) -> i32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frintn.v2f64" + )] + fn _vrndnq_f64(a: float64x2_t) -> float64x2_t; } - vqshrnd_n_s64_(a, N) + _vrndnq_f64(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16) +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnh_n_s16(a: i16) -> i8 { - static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrn_n_s16::(vdupq_n_s16(a)), 0) +#[cfg_attr(test, assert_instr(frintn))] +pub unsafe fn vrndns_f32(a: f32) -> f32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.roundeven.f32" + )] + fn _vrndns_f32(a: f32) -> f32; + } + _vrndns_f32(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32) +#[doc = "Floating-point round to integral, toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrns_n_s32(a: i32) -> i16 { - static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrn_n_s32::(vdupq_n_s32(a)), 0) +#[cfg_attr(test, assert_instr(frintp))] +pub unsafe fn vrndp_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.ceil.v2f32" + )] + fn _vrndp_f32(a: float32x2_t) -> float32x2_t; + } + _vrndp_f32(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16) +#[doc = "Floating-point round to integral, toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqshrn_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(frintp))] +pub unsafe fn vrndpq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.ceil.v4f32" + )] + fn _vrndpq_f32(a: float32x4_t) -> float32x4_t; + } + _vrndpq_f32(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32) +#[doc = "Floating-point round to integral, toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(frintp))] +pub unsafe fn vrndp_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.ceil.v1f64" + )] + fn _vrndp_f64(a: float64x1_t) -> float64x1_t; + } + _vrndp_f64(a) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64) +#[doc = "Floating-point round to integral, toward plus infinity"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrn_n_s64::(b), [0, 1, 2, 3]) -} - -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnd_n_u64(a: u64) -> u32 { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(frintp))] +pub unsafe fn vrndpq_f64(a: float64x2_t) -> float64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshrn.i32")] - fn vqshrnd_n_u64_(a: u64, n: i32) -> u32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.ceil.v2f64" + )] + fn _vrndpq_f64(a: float64x2_t) -> float64x2_t; } - vqshrnd_n_u64_(a, N) + _vrndpq_f64(a) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16) +#[doc = "Floating-point round to integral exact, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrnh_n_u16(a: u16) -> u8 { - static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrn_n_u16::(vdupq_n_u16(a)), 0) +#[cfg_attr(test, assert_instr(frintx))] +pub unsafe fn vrndx_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.rint.v2f32" + )] + fn _vrndx_f32(a: float32x2_t) -> float32x2_t; + } + _vrndx_f32(a) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32) +#[doc = "Floating-point round to integral exact, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrns_n_u32(a: u32) -> u16 { - static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrn_n_u32::(vdupq_n_u32(a)), 0) +#[cfg_attr(test, assert_instr(frintx))] +pub unsafe fn vrndxq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.rint.v4f32" + )] + fn _vrndxq_f32(a: float32x4_t) -> float32x4_t; + } + _vrndxq_f32(a) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16) +#[doc = "Floating-point round to integral exact, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndx_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqshrn_n_u16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(frintx))] +pub unsafe fn vrndx_f64(a: float64x1_t) -> float64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.rint.v1f64" + )] + fn _vrndx_f64(a: float64x1_t) -> float64x1_t; + } + _vrndx_f64(a) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32) +#[doc = "Floating-point round to integral exact, using current rounding mode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndxq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(frintx))] +pub unsafe fn vrndxq_f64(a: float64x2_t) -> float64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.rint.v2f64" + )] + fn _vrndxq_f64(a: float64x2_t) -> float64x2_t; + } + _vrndxq_f64(a) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(srshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrn_n_u64::(b), [0, 1, 2, 3]) +pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.i64" + )] + fn _vrshld_s64(a: i64, b: i64) -> i64; + } + _vrshld_s64(a, b) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(urshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrunh_n_s16(a: i16) -> u8 { - static_assert!(N >= 1 && N <= 8); - simd_extract!(vqshrun_n_s16::(vdupq_n_s16(a)), 0) +pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.i64" + )] + fn _vrshld_u64(a: i64, b: i64) -> i64; + } + _vrshld_u64(a.as_signed(), b).as_unsigned() } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[cfg_attr(test, assert_instr(srshr, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshruns_n_s32(a: i32) -> u16 { - static_assert!(N >= 1 && N <= 16); - simd_extract!(vqshrun_n_s32::(vdupq_n_s32(a)), 0) +pub unsafe fn vrshrd_n_s64(a: i64) -> i64 { + static_assert!(N >= 1 && N <= 64); + vrshld_s64(a, -N as i64) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[cfg_attr(test, assert_instr(urshr, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrund_n_s64(a: i64) -> u32 { - static_assert!(N >= 1 && N <= 32); - simd_extract!(vqshrun_n_s64::(vdupq_n_s64(a)), 0) +pub unsafe fn vrshrd_n_u64(a: u64) -> u64 { + static_assert!(N >= 1 && N <= 64); + vrshld_u64(a, -N as i64) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s16(a: uint8x8_t, b: int16x8_t) -> uint8x16_t { +pub unsafe fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vqshrun_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) + simd_shuffle!( + a, + vrshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s32(a: uint16x4_t, b: int32x4_t) -> uint16x8_t { +pub unsafe fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vqshrun_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) + simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun2, N = 2))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_high_n_s64(a: uint32x2_t, b: int64x2_t) -> uint32x4_t { +pub unsafe fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vqshrun_n_s64::(b), [0, 1, 2, 3]) -} - -/// Unsigned saturating accumulate of signed value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usqadd))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddb_u8(a: u8, b: i8) -> u8 { - simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) -} - -/// Unsigned saturating accumulate of signed value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usqadd))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddh_u16(a: u16, b: i16) -> u16 { - simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) -} - -/// Unsigned saturating accumulate of signed value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usqadd))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.usqadd.i32")] - fn vsqadds_u32_(a: u32, b: i32) -> u32; - } - vsqadds_u32_(a, b) -} - -/// Unsigned saturating accumulate of signed value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(usqadd))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqaddd_u64(a: u64, b: i64) -> u64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.usqadd.i64")] - fn vsqaddd_u64_(a: u64, b: i64) -> u64; - } - vsqaddd_u64_(a, b) -} - -/// Calculates the square root of each lane. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsqrt))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { - simd_fsqrt(a) + simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) } -/// Calculates the square root of each lane. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsqrt))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { - simd_fsqrt(a) +pub unsafe fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vrshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Calculates the square root of each lane. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsqrt))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { - simd_fsqrt(a) +pub unsafe fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Calculates the square root of each lane. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fsqrt))] +#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { - simd_fsqrt(a) +pub unsafe fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vrsqrte_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.v1f64")] - fn vrsqrte_f64_(a: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v1f64" + )] + fn _vrsqrte_f64(a: float64x1_t) -> float64x1_t; } - vrsqrte_f64_(a) + _vrsqrte_f64(a) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vrsqrteq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.v2f64")] - fn vrsqrteq_f64_(a: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v2f64" + )] + fn _vrsqrteq_f64(a: float64x2_t) -> float64x2_t; } - vrsqrteq_f64_(a) + _vrsqrteq_f64(a) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtes_f32(a: f32) -> f32 { - #[allow(improper_ctypes)] +pub unsafe fn vrsqrted_f64(a: f64) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.f32")] - fn vrsqrtes_f32_(a: f32) -> f32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.f64" + )] + fn _vrsqrted_f64(a: f64) -> f64; } - vrsqrtes_f32_(a) + _vrsqrted_f64(a) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrted_f64) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrte))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrted_f64(a: f64) -> f64 { - #[allow(improper_ctypes)] +pub unsafe fn vrsqrtes_f32(a: f32) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.f64")] - fn vrsqrted_f64_(a: f64) -> f64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.f32" + )] + fn _vrsqrtes_f32(a: f32) -> f32; } - vrsqrted_f64_(a) + _vrsqrtes_f32(a) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.v1f64")] - fn vrsqrts_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v1f64" + )] + fn _vrsqrts_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t; } - vrsqrts_f64_(a, b) + _vrsqrts_f64(a, b) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.v2f64")] - fn vrsqrtsq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v2f64" + )] + fn _vrsqrtsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t; } - vrsqrtsq_f64_(a, b) + _vrsqrtsq_f64(a, b) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtss_f32(a: f32, b: f32) -> f32 { - #[allow(improper_ctypes)] +pub unsafe fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.f32")] - fn vrsqrtss_f32_(a: f32, b: f32) -> f32; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.f64" + )] + fn _vrsqrtsd_f64(a: f64, b: f64) -> f64; } - vrsqrtss_f32_(a, b) + _vrsqrtsd_f64(a, b) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsd_f64) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(test, assert_instr(frsqrts))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsqrtsd_f64(a: f64, b: f64) -> f64 { - #[allow(improper_ctypes)] +pub unsafe fn vrsqrtss_f32(a: f32, b: f32) -> f32 { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.f64")] - fn vrsqrtsd_f64_(a: f64, b: f64) -> f64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.f32" + )] + fn _vrsqrtss_f32(a: f32, b: f32) -> f32; } - vrsqrtsd_f64_(a, b) + _vrsqrtss_f32(a, b) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64) +#[doc = "Signed rounding shift right and accumulate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpe))] +#[cfg_attr(test, assert_instr(srshr, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpe_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.v1f64")] - fn vrecpe_f64_(a: float64x1_t) -> float64x1_t; - } - vrecpe_f64_(a) +pub unsafe fn vrsrad_n_s64(a: i64, b: i64) -> i64 { + static_assert!(N >= 1 && N <= 64); + let b: i64 = vrshrd_n_s64::(b); + a.wrapping_add(b) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64) +#[doc = "Unsigned rounding shift right and accumulate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpe))] +#[cfg_attr(test, assert_instr(urshr, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpeq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.v2f64")] - fn vrecpeq_f64_(a: float64x2_t) -> float64x2_t; - } - vrecpeq_f64_(a) +pub unsafe fn vrsrad_n_u64(a: u64, b: u64) -> u64 { + static_assert!(N >= 1 && N <= 64); + let b: u64 = vrshrd_n_u64::(b); + a.wrapping_add(b) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpe))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpes_f32(a: f32) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.f32")] - fn vrecpes_f32_(a: f32) -> f32; - } - vrecpes_f32_(a) +pub unsafe fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { + let x: int8x8_t = vrsubhn_s16(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecped_f64) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpe))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecped_f64(a: f64) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.f64")] - fn vrecped_f64_(a: f64) -> f64; - } - vrecped_f64_(a) +pub unsafe fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { + let x: int16x4_t = vrsubhn_s32(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecps))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecps_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.v1f64")] - fn vrecps_f64_(a: float64x1_t, b: float64x1_t) -> float64x1_t; - } - vrecps_f64_(a, b) +pub unsafe fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { + let x: int32x2_t = vrsubhn_s64(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3]) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecps))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpsq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.v2f64")] - fn vrecpsq_f64_(a: float64x2_t, b: float64x2_t) -> float64x2_t; - } - vrecpsq_f64_(a, b) +pub unsafe fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { + let x: uint8x8_t = vrsubhn_u16(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecps))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpss_f32(a: f32, b: f32) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.f32")] - fn vrecpss_f32_(a: f32, b: f32) -> f32; - } - vrecpss_f32_(a, b) +pub unsafe fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + let x: uint16x4_t = vrsubhn_u32(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsd_f64) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecps))] +#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpsd_f64(a: f64, b: f64) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.f64")] - fn vrecpsd_f64_(a: f64, b: f64) -> f64; - } - vrecpsd_f64_(a, b) +pub unsafe fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { + let x: uint32x2_t = vrsubhn_u64(b, c); + simd_shuffle!(a, x, [0, 1, 2, 3]) } -/// Floating-point reciprocal exponent -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpx))] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpxs_f32(a: f32) -> f32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpx.f32")] - fn vrecpxs_f32_(a: f32) -> f32; - } - vrecpxs_f32_(a) +pub unsafe fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { + static_assert!(LANE == 0); + simd_insert!(b, LANE as u32, a) } -/// Floating-point reciprocal exponent -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(frecpx))] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrecpxd_f64(a: f64) -> f64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpx.f64")] - fn vrecpxd_f64_(a: f64) -> f64; - } - vrecpxd_f64_(a) -} +pub unsafe fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) +} -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p64) +#[doc = "SHA512 hash update part 2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_s64_p64(a: poly64x1_t) -> int64x1_t { - transmute(a) +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h2))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h2" + )] + fn _vsha512h2q_u64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _vsha512h2q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p64) +#[doc = "SHA512 hash update part 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_u64_p64(a: poly64x1_t) -> uint64x1_t { - transmute(a) +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512h))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512h" + )] + fn _vsha512hq_u64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _vsha512hq_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s64) +#[doc = "SHA512 schedule update 0"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p64_s64(a: int64x1_t) -> poly64x1_t { - transmute(a) +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su0))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su0" + )] + fn _vsha512su0q_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vsha512su0q_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u64) +#[doc = "SHA512 schedule update 1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p64_u64(a: uint64x1_t) -> poly64x1_t { - transmute(a) +#[target_feature(enable = "neon,sha3")] +#[cfg_attr(test, assert_instr(sha512su1))] +#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] +pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sha512su1" + )] + fn _vsha512su1q_u64(a: int64x2_t, b: int64x2_t, c: int64x2_t) -> int64x2_t; + } + _vsha512su1q_u64(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p64) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_s64_p64(a: poly64x2_t) -> int64x2_t { - transmute(a) +pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { + transmute(vshl_s64(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p64) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(ushl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_u64_p64(a: poly64x2_t) -> uint64x2_t { - transmute(a) +pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { + transmute(vshl_u64(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p64_s64(a: int64x2_t) -> poly64x2_t { - transmute(a) +pub unsafe fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { + static_assert!(N >= 0 && N <= 8); + let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vshll_n_s8::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p64_u64(a: uint64x2_t) -> poly64x2_t { - transmute(a) +pub unsafe fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { + static_assert!(N >= 0 && N <= 16); + let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vshll_n_s16::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(sshll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_s8_f64(a: float64x1_t) -> int8x8_t { - transmute(a) +pub unsafe fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { + static_assert!(N >= 0 && N <= 32); + let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); + vshll_n_s32::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_s16_f64(a: float64x1_t) -> int16x4_t { - transmute(a) +pub unsafe fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { + static_assert!(N >= 0 && N <= 8); + let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + vshll_n_u8::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_s32_f64(a: float64x1_t) -> int32x2_t { - transmute(a) +pub unsafe fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { + static_assert!(N >= 0 && N <= 16); + let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + vshll_n_u16::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f64) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(ushll2, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_s64_f64(a: float64x1_t) -> int64x1_t { - transmute(a) +pub unsafe fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { + static_assert!(N >= 0 && N <= 32); + let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + vshll_n_u32::(b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_s8_f64(a: float64x2_t) -> int8x16_t { - transmute(a) +pub unsafe fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vshrn_n_s16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_s16_f64(a: float64x2_t) -> int16x8_t { - transmute(a) +pub unsafe fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_s32_f64(a: float64x2_t) -> int32x4_t { - transmute(a) +pub unsafe fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_s64_f64(a: float64x2_t) -> int64x2_t { - transmute(a) +pub unsafe fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_shuffle!( + a, + vshrn_n_u16::(b), + [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] + ) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_u8_f64(a: float64x1_t) -> uint8x8_t { - transmute(a) +pub unsafe fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(shrn2, N = 2))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_u16_f64(a: float64x1_t) -> uint16x4_t { - transmute(a) +pub unsafe fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f64) +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_u32_f64(a: float64x1_t) -> uint32x2_t { - transmute(a) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] +pub unsafe fn vslid_n_s64(a: i64, b: i64) -> i64 { + static_assert!(N >= 0 && N <= 63); + transmute(vsli_n_s64::(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f64) +#[doc = "Shift left and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_u64_f64(a: float64x1_t) -> uint64x1_t { - transmute(a) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] +pub unsafe fn vslid_n_u64(a: u64, b: u64) -> u64 { + static_assert!(N >= 0 && N <= 63); + transmute(vsli_n_u64::(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f64) +#[doc = "SM3PARTW1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_u8_f64(a: float64x2_t) -> uint8x16_t { - transmute(a) +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub unsafe fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw1" + )] + fn _vsm3partw1q_u32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vsm3partw1q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f64) +#[doc = "SM3PARTW2"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_u16_f64(a: float64x2_t) -> uint16x8_t { - transmute(a) +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3partw2))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub unsafe fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3partw2" + )] + fn _vsm3partw2q_u32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vsm3partw2q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f64) +#[doc = "SM3SS1"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_u32_f64(a: float64x2_t) -> uint32x4_t { - transmute(a) +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm3ss1))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub unsafe fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm3ss1" + )] + fn _vsm3ss1q_u32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t; + } + _vsm3ss1q_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f64) +#[doc = "SM4 key"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_u64_f64(a: float64x2_t) -> uint64x2_t { - transmute(a) +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4ekey))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub unsafe fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4ekey" + )] + fn _vsm4ekeyq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vsm4ekeyq_u32(a.as_signed(), b.as_signed()).as_unsigned() +} + +#[doc = "SM4 encode"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,sm4")] +#[cfg_attr(test, assert_instr(sm4e))] +#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] +pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.crypto.sm4e" + )] + fn _vsm4eq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vsm4eq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f64) +#[doc = "Unsigned saturating accumulate of signed value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p8_f64(a: float64x1_t) -> poly8x8_t { - transmute(a) +pub unsafe fn vsqaddb_u8(a: u8, b: i8) -> u8 { + simd_extract!(vsqadd_u8(vdup_n_u8(a), vdup_n_s8(b)), 0) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f64) +#[doc = "Unsigned saturating accumulate of signed value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p16_f64(a: float64x1_t) -> poly16x4_t { - transmute(a) +pub unsafe fn vsqaddh_u16(a: u16, b: i16) -> u16 { + simd_extract!(vsqadd_u16(vdup_n_u16(a), vdup_n_s16(b)), 0) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f32) +#[doc = "Unsigned saturating accumulate of signed value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p64_f32(a: float32x2_t) -> poly64x1_t { - transmute(a) +pub unsafe fn vsqaddd_u64(a: u64, b: i64) -> u64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usqadd.i64" + )] + fn _vsqaddd_u64(a: i64, b: i64) -> i64; + } + _vsqaddd_u64(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_f64) +#[doc = "Unsigned saturating accumulate of signed value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(usqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_p64_f64(a: float64x1_t) -> poly64x1_t { - transmute(a) +pub unsafe fn vsqadds_u32(a: u32, b: i32) -> u32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usqadd.i32" + )] + fn _vsqadds_u32(a: i32, b: i32) -> i32; + } + _vsqadds_u32(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f64) +#[doc = "Calculates the square root of each lane."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p8_f64(a: float64x2_t) -> poly8x16_t { - transmute(a) +pub unsafe fn vsqrt_f32(a: float32x2_t) -> float32x2_t { + simd_fsqrt(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f64) +#[doc = "Calculates the square root of each lane."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p16_f64(a: float64x2_t) -> poly16x8_t { - transmute(a) +pub unsafe fn vsqrtq_f32(a: float32x4_t) -> float32x4_t { + simd_fsqrt(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f32) +#[doc = "Calculates the square root of each lane."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p64_f32(a: float32x4_t) -> poly64x2_t { - transmute(a) +pub unsafe fn vsqrt_f64(a: float64x1_t) -> float64x1_t { + simd_fsqrt(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_f64) +#[doc = "Calculates the square root of each lane."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(fsqrt))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p64_f64(a: float64x2_t) -> poly64x2_t { - transmute(a) +pub unsafe fn vsqrtq_f64(a: float64x2_t) -> float64x2_t { + simd_fsqrt(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f64) +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_p128_f64(a: float64x2_t) -> p128 { - transmute(a) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +pub unsafe fn vsrid_n_s64(a: i64, b: i64) -> i64 { + static_assert!(N >= 1 && N <= 64); + transmute(vsri_n_s64::(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s8) +#[doc = "Shift right and insert"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_s8(a: int8x8_t) -> float64x1_t { - transmute(a) +#[rustc_legacy_const_generics(2)] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] +pub unsafe fn vsrid_n_u64(a: u64, b: u64) -> u64 { + static_assert!(N >= 1 && N <= 64); + transmute(vsri_n_u64::(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_s16(a: int16x4_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst1_f64_x2(a: *mut f64, b: float64x1x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v1f64.p0f64" + )] + fn _vst1_f64_x2(a: float64x1_t, b: float64x1_t, ptr: *mut f64); + } + _vst1_f64_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_s32(a: int32x2_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst1q_f64_x2(a: *mut f64, b: float64x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v2f64.p0f64" + )] + fn _vst1q_f64_x2(a: float64x2_t, b: float64x2_t, ptr: *mut f64); + } + _vst1q_f64_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_s64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_s64(a: int64x1_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst1_f64_x3(a: *mut f64, b: float64x1x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v1f64.p0f64" + )] + fn _vst1_f64_x3(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut f64); + } + _vst1_f64_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s8) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_s8(a: int8x16_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst1q_f64_x3(a: *mut f64, b: float64x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v2f64.p0f64" + )] + fn _vst1q_f64_x3(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut f64); + } + _vst1q_f64_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_s16(a: int16x8_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst1_f64_x4(a: *mut f64, b: float64x1x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v1f64.p0f64" + )] + fn _vst1_f64_x4( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, + d: float64x1_t, + ptr: *mut f64, + ); + } + _vst1_f64_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_s32(a: int32x4_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst1q_f64_x4(a: *mut f64, b: float64x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v2f64.p0f64" + )] + fn _vst1q_f64_x4( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, + d: float64x2_t, + ptr: *mut f64, + ); + } + _vst1q_f64_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_s64(a: int64x2_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst1_lane_f64(a: *mut f64, b: float64x1_t) { + static_assert!(LANE == 0); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_p8(a: poly8x8_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst1q_lane_f64(a: *mut f64, b: float64x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_u16(a: uint16x4_t) -> float64x1_t { - transmute(a) +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst2_f64(a: *mut f64, b: float64x1x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v1f64.p0i8" + )] + fn _vst2_f64(a: float64x1_t, b: float64x1_t, ptr: *mut i8); + } + _vst2_f64(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_u32(a: uint32x2_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst2_lane_f64(a: *mut f64, b: float64x1x2_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v1f64.p0i8" + )] + fn _vst2_lane_f64(a: float64x1_t, b: float64x1_t, n: i64, ptr: *mut i8); + } + _vst2_lane_f64(b.0, b.1, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_u64(a: uint64x1_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst2_lane_s64(a: *mut i64, b: int64x1x2_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v1i64.p0i8" + )] + fn _vst2_lane_s64(a: int64x1_t, b: int64x1_t, n: i64, ptr: *mut i8); + } + _vst2_lane_s64(b.0, b.1, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_p8(a: poly8x16_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst2_lane_p64(a: *mut p64, b: poly64x1x2_t) { + static_assert!(LANE == 0); + vst2_lane_s64::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_u16(a: uint16x8_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst2_lane_u64(a: *mut u64, b: uint64x1x2_t) { + static_assert!(LANE == 0); + vst2_lane_s64::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_u32(a: uint32x4_t) -> float64x2_t { - transmute(a) +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_f64(a: *mut f64, b: float64x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v2f64.p0i8" + )] + fn _vst2q_f64(a: float64x2_t, b: float64x2_t, ptr: *mut i8); + } + _vst2q_f64(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_u64(a: uint64x2_t) -> float64x2_t { - transmute(a) +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_s64(a: *mut i64, b: int64x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v2i64.p0i8" + )] + fn _vst2q_s64(a: int64x2_t, b: int64x2_t, ptr: *mut i8); + } + _vst2q_s64(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_u8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_u8(a: uint8x8_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst2q_lane_f64(a: *mut f64, b: float64x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v2f64.p0i8" + )] + fn _vst2q_lane_f64(a: float64x2_t, b: float64x2_t, n: i64, ptr: *mut i8); + } + _vst2q_lane_f64(b.0, b.1, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_p16(a: poly16x4_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst2q_lane_s8(a: *mut i8, b: int8x16x2_t) { + static_assert_uimm_bits!(LANE, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v16i8.p0i8" + )] + fn _vst2q_lane_s8(a: int8x16_t, b: int8x16_t, n: i64, ptr: *mut i8); + } + _vst2q_lane_s8(b.0, b.1, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_p64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_p64(a: poly64x1_t) -> float64x1_t { - transmute(a) +pub unsafe fn vst2q_lane_s64(a: *mut i64, b: int64x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v2i64.p0i8" + )] + fn _vst2q_lane_s64(a: int64x2_t, b: int64x2_t, n: i64, ptr: *mut i8); + } + _vst2q_lane_s64(b.0, b.1, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f32_p64(a: poly64x1_t) -> float32x2_t { - transmute(a) +pub unsafe fn vst2q_lane_p64(a: *mut p64, b: poly64x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + vst2q_lane_s64::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_u8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_u8(a: uint8x16_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst2q_lane_u8(a: *mut u8, b: uint8x16x2_t) { + static_assert_uimm_bits!(LANE, 4); + vst2q_lane_s8::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_p16(a: poly16x8_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst2q_lane_u64(a: *mut u64, b: uint64x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + vst2q_lane_s64::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_p64(a: poly64x2_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst2q_lane_p8(a: *mut p8, b: poly8x16x2_t) { + static_assert_uimm_bits!(LANE, 4); + vst2q_lane_s8::(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f32_p64(a: poly64x2_t) -> float32x4_t { - transmute(a) +pub unsafe fn vst2q_p64(a: *mut p64, b: poly64x2x2_t) { + vst2q_s64(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_p128) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_p128(a: p128) -> float64x2_t { - transmute(a) +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_u64(a: *mut u64, b: uint64x2x2_t) { + vst2q_s64(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f64_f32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f64_f32(a: float32x2_t) -> float64x1_t { - transmute(a) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst3_f64(a: *mut f64, b: float64x1x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v1f64.p0i8" + )] + fn _vst3_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, ptr: *mut i8); + } + _vst3_f64(b.0, b.1, b.2, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_f64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpret_f32_f64(a: float64x1_t) -> float32x2_t { - transmute(a) +pub unsafe fn vst3_lane_f64(a: *mut f64, b: float64x1x3_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v1f64.p0i8" + )] + fn _vst3_lane_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, n: i64, ptr: *mut i8); + } + _vst3_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f64_f32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f64_f32(a: float32x4_t) -> float64x2_t { - transmute(a) +pub unsafe fn vst3_lane_s64(a: *mut i64, b: int64x1x3_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v1i64.p0i8" + )] + fn _vst3_lane_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, n: i64, ptr: *mut i8); + } + _vst3_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_f64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vreinterpretq_f32_f64(a: float64x2_t) -> float32x4_t { - transmute(a) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst3_lane_p64(a: *mut p64, b: poly64x1x3_t) { + static_assert!(LANE == 0); + vst3_lane_s64::(transmute(a), transmute(b)) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(srshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshld_s64(a: i64, b: i64) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.i64")] - fn vrshld_s64_(a: i64, b: i64) -> i64; - } - vrshld_s64_(a, b) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst3_lane_u64(a: *mut u64, b: uint64x1x3_t) { + static_assert!(LANE == 0); + vst3_lane_s64::(transmute(a), transmute(b)) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshld_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(urshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshld_u64(a: u64, b: i64) -> u64 { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_f64(a: *mut f64, b: float64x2x3_t) { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.i64")] - fn vrshld_u64_(a: u64, b: i64) -> u64; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v2f64.p0i8" + )] + fn _vst3q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, ptr: *mut i8); } - vrshld_u64_(a, b) + _vst3q_f64(b.0, b.1, b.2, a as _) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrd_n_s64(a: i64) -> i64 { - static_assert!(N >= 1 && N <= 64); - vrshld_s64(a, -N as i64) +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_s64(a: *mut i64, b: int64x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v2i64.p0i8" + )] + fn _vst3q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i8); + } + _vst3q_s64(b.0, b.1, b.2, a as _) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrd_n_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrd_n_u64(a: u64) -> u64 { - static_assert!(N >= 1 && N <= 64); - vrshld_u64(a, -N as i64) +pub unsafe fn vst3q_lane_f64(a: *mut f64, b: float64x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v2f64.p0i8" + )] + fn _vst3q_lane_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_f64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vrshrn_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub unsafe fn vst3q_lane_s8(a: *mut i8, b: int8x16x3_t) { + static_assert_uimm_bits!(LANE, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v16i8.p0i8" + )] + fn _vst3q_lane_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vrshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +pub unsafe fn vst3q_lane_s64(a: *mut i64, b: int64x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v2i64.p0i8" + )] + fn _vst3q_lane_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_s64(b.0, b.1, b.2, LANE as i64, a as _) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vrshrn_n_s64::(b), [0, 1, 2, 3]) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst3q_lane_p64(a: *mut p64, b: poly64x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + vst3q_lane_s64::(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] +pub unsafe fn vst3q_lane_u8(a: *mut u8, b: uint8x16x3_t) { + static_assert_uimm_bits!(LANE, 4); + vst3q_lane_s8::(transmute(a), transmute(b)) +} + +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vrshrn_n_u16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst3q_lane_u64(a: *mut u64, b: uint64x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + vst3q_lane_s64::(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3, LANE = 0))] #[rustc_legacy_const_generics(2)] +pub unsafe fn vst3q_lane_p8(a: *mut p8, b: poly8x16x3_t) { + static_assert_uimm_bits!(LANE, 4); + vst3q_lane_s8::(transmute(a), transmute(b)) +} + +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vrshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_p64(a: *mut p64, b: poly64x2x3_t) { + vst3q_s64(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vrshrn_n_u64::(b), [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_u64(a: *mut u64, b: uint64x2x3_t) { + vst3q_s64(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsrad_n_s64(a: i64, b: i64) -> i64 { - static_assert!(N >= 1 && N <= 64); - let b: i64 = vrshrd_n_s64::(b); - a.wrapping_add(b) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_f64(a: *mut f64, b: float64x1x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v1f64.p0i8" + )] + fn _vst4_f64(a: float64x1_t, b: float64x1_t, c: float64x1_t, d: float64x1_t, ptr: *mut i8); + } + _vst4_f64(b.0, b.1, b.2, b.3, a as _) } -/// Unsigned rounding shift right and accumulate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsrad_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(urshr, N = 2))] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsrad_n_u64(a: u64, b: u64) -> u64 { - static_assert!(N >= 1 && N <= 64); - let b: u64 = vrshrd_n_u64::(b); - a.wrapping_add(b) +pub unsafe fn vst4_lane_f64(a: *mut f64, b: float64x1x4_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v1f64.p0i8" + )] + fn _vst4_lane_f64( + a: float64x1_t, + b: float64x1_t, + c: float64x1_t, + d: float64x1_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let x: int8x8_t = vrsubhn_s16(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +pub unsafe fn vst4_lane_s64(a: *mut i64, b: int64x1x4_t) { + static_assert!(LANE == 0); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v1i64.p0i8" + )] + fn _vst4_lane_s64( + a: int64x1_t, + b: int64x1_t, + c: int64x1_t, + d: int64x1_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let x: int16x4_t = vrsubhn_s32(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4_lane_p64(a: *mut p64, b: poly64x1x4_t) { + static_assert!(LANE == 0); + vst4_lane_s64::(transmute(a), transmute(b)) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let x: int32x2_t = vrsubhn_s64(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4_lane_u64(a: *mut u64, b: uint64x1x4_t) { + static_assert!(LANE == 0); + vst4_lane_s64::(transmute(a), transmute(b)) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let x: uint8x8_t = vrsubhn_u16(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_f64(a: *mut f64, b: float64x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v2f64.p0i8" + )] + fn _vst4q_f64(a: float64x2_t, b: float64x2_t, c: float64x2_t, d: float64x2_t, ptr: *mut i8); + } + _vst4q_f64(b.0, b.1, b.2, b.3, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let x: uint16x4_t = vrsubhn_u32(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s64(a: *mut i64, b: int64x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v2i64.p0i8" + )] + fn _vst4q_s64(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i8); + } + _vst4q_s64(b.0, b.1, b.2, b.3, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rsubhn2))] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let x: uint32x2_t = vrsubhn_u64(b, c); - simd_shuffle!(a, x, [0, 1, 2, 3]) +pub unsafe fn vst4q_lane_f64(a: *mut f64, b: float64x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2f64.p0i8" + )] + fn _vst4q_lane_f64( + a: float64x2_t, + b: float64x2_t, + c: float64x2_t, + d: float64x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_f64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vset_lane_f64(a: f64, b: float64x1_t) -> float64x1_t { - static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) +pub unsafe fn vst4q_lane_s8(a: *mut i8, b: int8x16x4_t) { + static_assert_uimm_bits!(LANE, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v16i8.p0i8" + )] + fn _vst4q_lane_s8( + a: int8x16_t, + b: int8x16_t, + c: int8x16_t, + d: int8x16_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop, LANE = 0))] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsetq_lane_f64(a: f64, b: float64x2_t) -> float64x2_t { +pub unsafe fn vst4q_lane_s64(a: *mut i64, b: int64x2x4_t) { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2i64.p0i8" + )] + fn _vst4q_lane_s64( + a: int64x2_t, + b: int64x2_t, + c: int64x2_t, + d: int64x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s64(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_s64(a: i64, b: i64) -> i64 { - transmute(vshl_s64(transmute(a), transmute(b))) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4q_lane_p64(a: *mut p64, b: poly64x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + vst4q_lane_s64::(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshld_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushl))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshld_u64(a: u64, b: i64) -> u64 { - transmute(vshl_u64(transmute(a), transmute(b))) +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4q_lane_u8(a: *mut u8, b: uint8x16x4_t) { + static_assert_uimm_bits!(LANE, 4); + vst4q_lane_s8::(transmute(a), transmute(b)) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s8(a: int8x16_t) -> int16x8_t { - static_assert!(N >= 0 && N <= 8); - let b: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_s8::(b) +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4q_lane_u64(a: *mut u64, b: uint64x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + vst4q_lane_s64::(transmute(a), transmute(b)) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s16(a: int16x8_t) -> int32x4_t { - static_assert!(N >= 0 && N <= 16); - let b: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_s16::(b) +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +pub unsafe fn vst4q_lane_p8(a: *mut p8, b: poly8x16x4_t) { + static_assert_uimm_bits!(LANE, 4); + vst4q_lane_s8::(transmute(a), transmute(b)) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sshll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_s32(a: int32x4_t) -> int64x2_t { - static_assert!(N >= 0 && N <= 32); - let b: int32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_s32::(b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_p64(a: *mut p64, b: poly64x2x4_t) { + vst4q_s64(transmute(a), transmute(b)) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u8(a: uint8x16_t) -> uint16x8_t { - static_assert!(N >= 0 && N <= 8); - let b: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); - vshll_n_u8::(b) +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_u64(a: *mut u64, b: uint64x2x4_t) { + vst4q_s64(transmute(a), transmute(b)) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u16(a: uint16x8_t) -> uint32x4_t { - static_assert!(N >= 0 && N <= 16); - let b: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); - vshll_n_u16::(b) +#[cfg_attr(test, assert_instr(fsub))] +pub unsafe fn vsub_f64(a: float64x1_t, b: float64x1_t) -> float64x1_t { + simd_sub(a, b) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ushll2, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshll_high_n_u32(a: uint32x4_t) -> uint64x2_t { - static_assert!(N >= 0 && N <= 32); - let b: uint32x2_t = simd_shuffle!(a, a, [2, 3]); - vshll_n_u32::(b) +#[cfg_attr(test, assert_instr(fsub))] +pub unsafe fn vsubq_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_sub(a, b) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s16(a: int8x8_t, b: int16x8_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vshrn_n_s16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vsubd_s64(a: i64, b: i64) -> i64 { + a.wrapping_sub(b) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s32(a: int16x4_t, b: int32x4_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vshrn_n_s32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vsubd_u64(a: u64, b: u64) -> u64 { + a.wrapping_sub(b) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_s64(a: int32x2_t, b: int64x2_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vshrn_n_s64::(b), [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(ssubl))] +pub unsafe fn vsubl_high_s8(a: int8x16_t, b: int8x16_t) -> int16x8_t { + let c: int8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: int16x8_t = simd_cast(c); + let e: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: int16x8_t = simd_cast(e); + simd_sub(d, f) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u16(a: uint8x8_t, b: uint16x8_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_shuffle!(a, vshrn_n_u16::(b), [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(test, assert_instr(ssubl))] +pub unsafe fn vsubl_high_s16(a: int16x8_t, b: int16x8_t) -> int32x4_t { + let c: int16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: int32x4_t = simd_cast(c); + let e: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let f: int32x4_t = simd_cast(e); + simd_sub(d, f) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u32(a: uint16x4_t, b: uint32x4_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_shuffle!(a, vshrn_n_u32::(b), [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(test, assert_instr(ssubl))] +pub unsafe fn vsubl_high_s32(a: int32x4_t, b: int32x4_t) -> int64x2_t { + let c: int32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: int64x2_t = simd_cast(c); + let e: int32x2_t = simd_shuffle!(b, b, [2, 3]); + let f: int64x2_t = simd_cast(e); + simd_sub(d, f) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(shrn2, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vshrn_high_n_u64(a: uint32x2_t, b: uint64x2_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_shuffle!(a, vshrn_n_u64::(b), [0, 1, 2, 3]) +#[cfg_attr(test, assert_instr(usubl))] +pub unsafe fn vsubl_high_u8(a: uint8x16_t, b: uint8x16_t) -> uint16x8_t { + let c: uint8x8_t = simd_shuffle!(a, a, [8, 9, 10, 11, 12, 13, 14, 15]); + let d: uint16x8_t = simd_cast(c); + let e: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + let f: uint16x8_t = simd_cast(e); + simd_sub(d, f) } -/// SM3PARTW1 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw1q_u32) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sm4")] -#[cfg_attr(test, assert_instr(sm3partw1))] -#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3partw1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3partw1")] - fn vsm3partw1q_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; - } - vsm3partw1q_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(usubl))] +pub unsafe fn vsubl_high_u16(a: uint16x8_t, b: uint16x8_t) -> uint32x4_t { + let c: uint16x4_t = simd_shuffle!(a, a, [4, 5, 6, 7]); + let d: uint32x4_t = simd_cast(c); + let e: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + let f: uint32x4_t = simd_cast(e); + simd_sub(d, f) } -/// SM3PARTW2 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3partw2q_u32) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sm4")] -#[cfg_attr(test, assert_instr(sm3partw2))] -#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3partw2q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3partw2")] - fn vsm3partw2q_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; - } - vsm3partw2q_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(usubl))] +pub unsafe fn vsubl_high_u32(a: uint32x4_t, b: uint32x4_t) -> uint64x2_t { + let c: uint32x2_t = simd_shuffle!(a, a, [2, 3]); + let d: uint64x2_t = simd_cast(c); + let e: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + let f: uint64x2_t = simd_cast(e); + simd_sub(d, f) } -/// SM3SS1 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm3ss1q_u32) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sm4")] -#[cfg_attr(test, assert_instr(sm3ss1))] -#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm3ss1q_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm3ss1")] - fn vsm3ss1q_u32_(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t; - } - vsm3ss1q_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ssubw))] +pub unsafe fn vsubw_high_s8(a: int16x8_t, b: int8x16_t) -> int16x8_t { + let c: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_sub(a, simd_cast(c)) } -/// SM4 key -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4ekeyq_u32) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sm4")] -#[cfg_attr(test, assert_instr(sm4ekey))] -#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm4ekeyq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm4ekey")] - fn vsm4ekeyq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } - vsm4ekeyq_u32_(a, b) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ssubw))] +pub unsafe fn vsubw_high_s16(a: int32x4_t, b: int16x8_t) -> int32x4_t { + let c: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + simd_sub(a, simd_cast(c)) } -/// SM4 encode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsm4eq_u32) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sm4")] -#[cfg_attr(test, assert_instr(sm4e))] -#[unstable(feature = "stdarch_neon_sm4", issue = "117226")] -pub unsafe fn vsm4eq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sm4e")] - fn vsm4eq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } - vsm4eq_u32_(a, b) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ssubw))] +pub unsafe fn vsubw_high_s32(a: int64x2_t, b: int32x4_t) -> int64x2_t { + let c: int32x2_t = simd_shuffle!(b, b, [2, 3]); + simd_sub(a, simd_cast(c)) } -/// Rotate and exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrax1q_u64) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(rax1))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vrax1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.rax1")] - fn vrax1q_u64_(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; - } - vrax1q_u64_(a, b) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(usubw))] +pub unsafe fn vsubw_high_u8(a: uint16x8_t, b: uint8x16_t) -> uint16x8_t { + let c: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); + simd_sub(a, simd_cast(c)) } -/// SHA512 hash update part 1 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512hq_u64) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(sha512h))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512hq_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha512h")] - fn vsha512hq_u64_(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; - } - vsha512hq_u64_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(usubw))] +pub unsafe fn vsubw_high_u16(a: uint32x4_t, b: uint16x8_t) -> uint32x4_t { + let c: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); + simd_sub(a, simd_cast(c)) } -/// SHA512 hash update part 2 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512h2q_u64) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(sha512h2))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512h2q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha512h2")] - fn vsha512h2q_u64_(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; - } - vsha512h2q_u64_(a, b, c) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(usubw))] +pub unsafe fn vsubw_high_u32(a: uint64x2_t, b: uint32x4_t) -> uint64x2_t { + let c: uint32x2_t = simd_shuffle!(b, b, [2, 3]); + simd_sub(a, simd_cast(c)) } -/// SHA512 schedule update 0 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su0q_u64) +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(sha512su0))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512su0q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha512su0")] - fn vsha512su0q_u64_(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; - } - vsha512su0q_u64_(a, b) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(test, assert_instr(sudot, LANE = 3))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub unsafe fn vsudot_laneq_s32( + a: int32x2_t, + b: int8x8_t, + c: uint8x16_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c: uint32x4_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) } -/// SHA512 schedule update 1 -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha512su1q_u64) +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,sha3")] -#[cfg_attr(test, assert_instr(sha512su1))] -#[stable(feature = "stdarch_neon_sha3", since = "1.79.0")] -pub unsafe fn vsha512su1q_u64(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.crypto.sha512su1")] - fn vsha512su1q_u64_(a: uint64x2_t, b: uint64x2_t, c: uint64x2_t) -> uint64x2_t; - } - vsha512su1q_u64_(a, b, c) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(test, assert_instr(sudot, LANE = 3))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub unsafe fn vsudotq_laneq_s32( + a: int32x4_t, + b: int8x16_t, + c: uint8x16_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: uint32x4_t = transmute(c); + let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) } -/// Floating-point round to 32-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32x_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32x.v2f32")] - fn vrnd32x_f32_(a: float32x2_t) -> float32x2_t; - } - vrnd32x_f32_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 32-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32xq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32x.v4f32")] - fn vrnd32xq_f32_(a: float32x4_t) -> float32x4_t; - } - vrnd32xq_f32_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 32-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32xq_f64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32xq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32x.v2f64")] - fn vrnd32xq_f64_(a: float64x2_t) -> float64x2_t; - } - vrnd32xq_f64_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 32-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32x_f64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32x_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.frint32x.f64")] - fn vrnd32x_f64_(a: f64) -> f64; - } - transmute(vrnd32x_f64_(simd_extract!(a, 0))) -} - -/// Floating-point round to 32-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f32) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32z_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32z.v2f32")] - fn vrnd32z_f32_(a: float32x2_t) -> float32x2_t; - } - vrnd32z_f32_(a) -} - -/// Floating-point round to 32-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f32) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32zq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32z.v4f32")] - fn vrnd32zq_f32_(a: float32x4_t) -> float32x4_t; - } - vrnd32zq_f32_(a) -} - -/// Floating-point round to 32-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32zq_f64) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32zq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint32z.v2f64")] - fn vrnd32zq_f64_(a: float64x2_t) -> float64x2_t; - } - vrnd32zq_f64_(a) -} - -/// Floating-point round to 32-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd32z_f64) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint32z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd32z_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.frint32z.f64")] - fn vrnd32z_f64_(a: f64) -> f64; - } - transmute(vrnd32z_f64_(simd_extract!(a, 0))) -} - -/// Floating-point round to 64-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f32) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64x_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64x.v2f32")] - fn vrnd64x_f32_(a: float32x2_t) -> float32x2_t; - } - vrnd64x_f32_(a) -} - -/// Floating-point round to 64-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f32) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64xq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64x.v4f32")] - fn vrnd64xq_f32_(a: float32x4_t) -> float32x4_t; - } - vrnd64xq_f32_(a) -} - -/// Floating-point round to 64-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64xq_f64) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64xq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64x.v2f64")] - fn vrnd64xq_f64_(a: float64x2_t) -> float64x2_t; - } - vrnd64xq_f64_(a) -} - -/// Floating-point round to 64-bit integer, using current rounding mode -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64x_f64) -#[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64x))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64x_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.frint64x.f64")] - fn vrnd64x_f64_(a: f64) -> f64; - } - transmute(vrnd64x_f64_(simd_extract!(a, 0))) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 64-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64z_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64z.v2f32")] - fn vrnd64z_f32_(a: float32x2_t) -> float32x2_t; - } - vrnd64z_f32_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 64-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64zq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64z.v4f32")] - fn vrnd64zq_f32_(a: float32x4_t) -> float32x4_t; - } - vrnd64zq_f32_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 64-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64zq_f64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64zq_f64(a: float64x2_t) -> float64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frint64z.v2f64")] - fn vrnd64zq_f64_(a: float64x2_t) -> float64x2_t; - } - vrnd64zq_f64_(a) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Floating-point round to 64-bit integer toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd64z_f64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,frintts")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(frint64z))] -#[unstable(feature = "stdarch_neon_ftts", issue = "117227")] -pub unsafe fn vrnd64z_f64(a: float64x1_t) -> float64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.frint64z.f64")] - fn vrnd64z_f64_(a: f64) -> f64; - } - transmute(vrnd64z_f64_(simd_extract!(a, 0))) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] +pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]) + simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [0, 4, 2, 6]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] pub unsafe fn vtrn1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_p64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 4, 2, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]) + simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { simd_shuffle!(a, b, [1, 5, 3, 7]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16) +#[doc = "Transpose vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] pub unsafe fn vtrn2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtst_s64(a: int64x1_t, b: int64x1_t) -> uint64x1_t { + let c: int64x1_t = simd_and(a, b); + let d: i64x1 = i64x1::new(0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtstq_s64(a: int64x2_t, b: int64x2_t) -> uint64x2_t { + let c: int64x2_t = simd_and(a, b); + let d: i64x2 = i64x2::new(0, 0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtst_p64(a: poly64x1_t, b: poly64x1_t) -> uint64x1_t { + let c: poly64x1_t = simd_and(a, b); + let d: i64x1 = i64x1::new(0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u64) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [1, 3]) -} - -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_p64) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtstq_p64(a: poly64x2_t, b: poly64x2_t) -> uint64x2_t { + let c: poly64x2_t = simd_and(a, b); + let d: i64x2 = i64x2::new(0, 0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(trn2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [1, 5, 3, 7]) +pub unsafe fn vtst_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + let c: uint64x1_t = simd_and(a, b); + let d: u64x1 = u64x1::new(0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(cmtst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtstq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + let c: uint64x2_t = simd_and(a, b); + let d: u64x2 = u64x2::new(0, 0); + simd_ne(c, transmute(d)) } -/// Transpose vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64) +#[doc = "Compare bitwise test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +#[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vtrn2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) +pub unsafe fn vtstd_s64(a: i64, b: i64) -> u64 { + transmute(vtst_s64(transmute(a), transmute(b))) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8) +#[doc = "Compare bitwise test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr(test, assert_instr(tst))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub unsafe fn vtstd_u64(a: u64, b: u64) -> u64 { + transmute(vtst_u64(transmute(a), transmute(b))) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8) +#[doc = "Signed saturating accumulate of unsigned value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) +pub unsafe fn vuqaddb_s8(a: i8, b: u8) -> i8 { + simd_extract!(vuqadd_s8(vdup_n_s8(a), vdup_n_u8(b)), 0) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16) +#[doc = "Signed saturating accumulate of unsigned value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +pub unsafe fn vuqaddh_s16(a: i16, b: u16) -> i16 { + simd_extract!(vuqadd_s16(vdup_n_s16(a), vdup_n_u16(b)), 0) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16) +#[doc = "Signed saturating accumulate of unsigned value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +pub unsafe fn vuqaddd_s64(a: i64, b: u64) -> i64 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.suqadd.i64" + )] + fn _vuqaddd_s64(a: i64, b: i64) -> i64; + } + _vuqaddd_s64(a, b.as_signed()) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32) +#[doc = "Signed saturating accumulate of unsigned value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +#[cfg_attr(test, assert_instr(suqadd))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [0, 2]) +pub unsafe fn vuqadds_s32(a: i32, b: u32) -> i32 { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.suqadd.i32" + )] + fn _vuqadds_s32(a: i32, b: i32) -> i32; + } + _vuqadds_s32(a, b.as_signed()) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32) +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(test, assert_instr(usdot, LANE = 3))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub unsafe fn vusdot_laneq_s32( + a: int32x2_t, + b: uint8x8_t, + c: int8x16_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x4_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64) +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(test, assert_instr(usdot, LANE = 3))] +#[rustc_legacy_const_generics(3)] +#[unstable(feature = "stdarch_neon_i8mm", issue = "117223")] +pub unsafe fn vusdotq_laneq_s32( + a: int32x4_t, + b: uint8x16_t, + c: int8x16_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + let c: int32x4_t = transmute(c); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [0, 2]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 4, 1, 5]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + simd_shuffle!(a, b, [0, 2, 4, 6]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] +pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_shuffle!(a, b, [1, 3]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]) -} +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +} -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [2, 6, 3, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + simd_shuffle!(a, b, [1, 3, 5, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8) +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] +pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_p16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_p64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [0, 2, 4, 6]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [0, 2]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp1q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + simd_shuffle!(a, b, [0, 4, 1, 5]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip1))] +pub unsafe fn vzip1q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + simd_shuffle!(a, b, [0, 2]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_p16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { simd_shuffle!(a, b, [1, 3]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_shuffle!(a, b, [1, 3]) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { simd_shuffle!(a, b, [1, 3]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_shuffle!(a, b, [1, 3]) -} - -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_p64) -#[inline] -#[target_feature(enable = "neon")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_shuffle!(a, b, [1, 3]) -} - -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uzp2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_shuffle!(a, b, [1, 3, 5, 7]) +pub unsafe fn vzip2_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_shuffle!(a, b, [1, 3]) -} - -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64) -#[inline] -#[target_feature(enable = "neon")] #[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vuzp2q_f64(a: float64x2_t, b: float64x2_t) -> float64x2_t { - simd_shuffle!(a, b, [1, 3]) -} - -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_u8(a: uint16x8_t, b: uint8x16_t, c: uint8x16_t) -> uint16x8_t { - let d: uint8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: uint8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: uint8x8_t = vabd_u8(d, e); - simd_add(a, simd_cast(f)) -} - -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_u16(a: uint32x4_t, b: uint16x8_t, c: uint16x8_t) -> uint32x4_t { - let d: uint16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: uint16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: uint16x4_t = vabd_u16(d, e); - simd_add(a, simd_cast(f)) -} - -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(uabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_u32(a: uint64x2_t, b: uint32x4_t, c: uint32x4_t) -> uint64x2_t { - let d: uint32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: uint32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: uint32x2_t = vabd_u32(d, e); - simd_add(a, simd_cast(f)) -} - -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_s8(a: int16x8_t, b: int8x16_t, c: int8x16_t) -> int16x8_t { - let d: int8x8_t = simd_shuffle!(b, b, [8, 9, 10, 11, 12, 13, 14, 15]); - let e: int8x8_t = simd_shuffle!(c, c, [8, 9, 10, 11, 12, 13, 14, 15]); - let f: int8x8_t = vabd_s8(d, e); - let f: uint8x8_t = simd_cast(f); - simd_add(a, simd_cast(f)) -} - -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_s16(a: int32x4_t, b: int16x8_t, c: int16x8_t) -> int32x4_t { - let d: int16x4_t = simd_shuffle!(b, b, [4, 5, 6, 7]); - let e: int16x4_t = simd_shuffle!(c, c, [4, 5, 6, 7]); - let f: int16x4_t = vabd_s16(d, e); - let f: uint16x4_t = simd_cast(f); - simd_add(a, simd_cast(f)) -} - -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sabal))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vabal_high_s32(a: int64x2_t, b: int32x4_t, c: int32x4_t) -> int64x2_t { - let d: int32x2_t = simd_shuffle!(b, b, [2, 3]); - let e: int32x2_t = simd_shuffle!(c, c, [2, 3]); - let f: int32x2_t = vabd_s32(d, e); - let f: uint32x2_t = simd_cast(f); - simd_add(a, simd_cast(f)) +pub unsafe fn vzip2q_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabs_s64(a: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v1i64")] - fn vqabs_s64_(a: int64x1_t) -> int64x1_t; - } - vqabs_s64_(a) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabsq_s64(a: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v2i64")] - fn vqabsq_s64_(a: int64x2_t) -> int64x2_t; - } - vqabsq_s64_(a) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Signed saturating absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabsb_s8(a: i8) -> i8 { - simd_extract!(vqabs_s8(vdup_n_s8(a)), 0) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Signed saturating absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabsh_s16(a: i16) -> i16 { - simd_extract!(vqabs_s16(vdup_n_s16(a)), 0) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Signed saturating absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabss_s32(a: i32) -> i32 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.i32")] - fn vqabss_s32_(a: i32) -> i32; - } - vqabss_s32_(a) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_shuffle!(a, b, [1, 3]) } -/// Signed saturating absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sqabs))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqabsd_s64(a: i64) -> i64 { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.i64")] - fn vqabsd_s64_(a: i64) -> i64; - } - vqabsd_s64_(a) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Shift left and insert -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vslid_n_s64(a: i64, b: i64) -> i64 { - static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_s64::(transmute(a), transmute(b))) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ) } -/// Shift left and insert -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vslid_n_u64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sli, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vslid_n_u64(a: u64, b: u64) -> u64 { - static_assert!(N >= 0 && N <= 63); - transmute(vsli_n_u64::(transmute(a), transmute(b))) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + simd_shuffle!(a, b, [2, 6, 3, 7]) } -/// Shift right and insert -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_s64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsrid_n_s64(a: i64, b: i64) -> i64 { - static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_s64::(transmute(a), transmute(b))) +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]) } -/// Shift right and insert -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsrid_n_u64) +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(sri, N = 2))] -#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vsrid_n_u64(a: u64, b: u64) -> u64 { - static_assert!(N >= 1 && N <= 64); - transmute(vsri_n_u64::(transmute(a), transmute(b))) -} - -#[cfg(test)] -mod test { - use super::*; - use crate::core_arch::simd::*; - use std::mem::transmute; - use stdarch_test::simd_test; - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_s8() { - let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let c: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: i8x16 = transmute(veor3q_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_s16() { - let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let c: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i16x8 = transmute(veor3q_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_s32() { - let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let c: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let r: i32x4 = transmute(veor3q_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_s64() { - let a: i64x2 = i64x2::new(0x00, 0x01); - let b: i64x2 = i64x2::new(0x00, 0x00); - let c: i64x2 = i64x2::new(0x00, 0x00); - let e: i64x2 = i64x2::new(0x00, 0x01); - let r: i64x2 = transmute(veor3q_s64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_u8() { - let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let c: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: u8x16 = transmute(veor3q_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_u16() { - let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let c: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u16x8 = transmute(veor3q_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_u32() { - let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let c: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let r: u32x4 = transmute(veor3q_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_veor3q_u64() { - let a: u64x2 = u64x2::new(0x00, 0x01); - let b: u64x2 = u64x2::new(0x00, 0x00); - let c: u64x2 = u64x2::new(0x00, 0x00); - let e: u64x2 = u64x2::new(0x00, 0x01); - let r: u64x2 = transmute(veor3q_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_f64() { - let a: f64 = 1.0; - let b: f64 = 9.0; - let e: f64 = 8.0; - let r: f64 = transmute(vabd_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(9.0, 3.0); - let e: f64x2 = f64x2::new(8.0, 1.0); - let r: f64x2 = transmute(vabdq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabds_f32() { - let a: f32 = 1.0; - let b: f32 = 9.0; - let e: f32 = 8.0; - let r: f32 = vabds_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdd_f64() { - let a: f64 = 1.0; - let b: f64 = 9.0; - let e: f64 = 8.0; - let r: f64 = vabdd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); - let e: u16x8 = u16x8::new(1, 0, 1, 2, 3, 4, 5, 6); - let r: u16x8 = transmute(vabdl_high_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 8, 9, 11, 12); - let b: u16x8 = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: u32x4 = u32x4::new(2, 1, 1, 2); - let r: u32x4 = transmute(vabdl_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(10, 10, 10, 10); - let e: u64x2 = u64x2::new(7, 6); - let r: u64x2 = transmute(vabdl_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10); - let e: i16x8 = i16x8::new(1, 0, 1, 2, 3, 4, 5, 6); - let r: i16x8 = transmute(vabdl_high_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); - let b: i16x8 = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: i32x4 = i32x4::new(1, 0, 1, 2); - let r: i32x4 = transmute(vabdl_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_high_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(10, 10, 10, 10); - let e: i64x2 = i64x2::new(7, 6); - let r: i64x2 = transmute(vabdl_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_u64() { - let a: u64x1 = u64x1::new(0); - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u64x1 = u64x1::new(0); - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_u64() { - let a: u64x2 = u64x2::new(0, 0x01); - let b: u64x2 = u64x2::new(0, 0x01); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u64x2 = u64x2::new(0, 0); - let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vceqq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vceqq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_p64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_p64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x01); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x01); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x2 = i64x2::new(-9223372036854775808, -9223372036854775808); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vceqq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_f64() { - let a: f64 = 1.2; - let b: f64 = 1.2; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_f64() { - let a: f64x2 = f64x2::new(1.2, 3.4); - let b: f64x2 = f64x2::new(1.2, 3.4); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqd_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: u64 = 0; - let r: u64 = vceqd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqd_u64() { - let a: u64 = 1; - let b: u64 = 2; - let e: u64 = 0; - let r: u64 = vceqd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqs_f32() { - let a: f32 = 1.; - let b: f32 = 2.; - let e: u32 = 0; - let r: u32 = vceqs_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqd_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: u64 = 0; - let r: u64 = vceqd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_s8() { - let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vceqz_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_s8() { - let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vceqzq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_s16() { - let a: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); - let e: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); - let r: u16x4 = transmute(vceqz_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_s16() { - let a: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vceqzq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_s32() { - let a: i32x2 = i32x2::new(-2147483648, 0x00); - let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vceqz_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_s32() { - let a: i32x4 = i32x4::new(-2147483648, 0x00, 0x01, 0x02); - let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); - let r: u32x4 = transmute(vceqzq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vceqz_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqzq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_p8() { - let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vceqz_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_p8() { - let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let e: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vceqzq_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_p64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vceqz_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_p64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqzq_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_u8() { - let a: u8x8 = u8x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vceqz_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_u8() { - let a: u8x16 = u8x16::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0xFF); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vceqzq_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_u16() { - let a: u16x4 = u16x4::new(0, 0x00, 0x01, 0x02); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); - let r: u16x4 = transmute(vceqz_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_u16() { - let a: u16x8 = u16x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vceqzq_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_u32() { - let a: u32x2 = u32x2::new(0, 0x00); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vceqz_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_u32() { - let a: u32x4 = u32x4::new(0, 0x00, 0x01, 0x02); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); - let r: u32x4 = transmute(vceqzq_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_u64() { - let a: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceqz_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_u64() { - let a: u64x2 = u64x2::new(0, 0x00); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vceqzq_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_f32() { - let a: f32x2 = f32x2::new(0.0, 1.2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vceqz_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_f32() { - let a: f32x4 = f32x4::new(0.0, 1.2, 3.4, 5.6); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); - let r: u32x4 = transmute(vceqzq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqz_f64() { - let a: f64 = 0.0; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vceqz_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzq_f64() { - let a: f64x2 = f64x2::new(0.0, 1.2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vceqzq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzd_s64() { - let a: i64 = 1; - let e: u64 = 0; - let r: u64 = vceqzd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzd_u64() { - let a: u64 = 1; - let e: u64 = 0; - let r: u64 = vceqzd_u64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzs_f32() { - let a: f32 = 1.; - let e: u32 = 0; - let r: u32 = vceqzs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqzd_f64() { - let a: f64 = 1.; - let e: u64 = 0; - let r: u64 = vceqzd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vtst_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vtstq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_p64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let b: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vtst_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_p64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let b: i64x2 = i64x2::new(-9223372036854775808, 0x00); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vtstq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_u64() { - let a: u64x1 = u64x1::new(0); - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vtst_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_u64() { - let a: u64x2 = u64x2::new(0, 0x00); - let b: u64x2 = u64x2::new(0, 0x00); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vtstq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstd_s64() { - let a: i64 = 0; - let b: i64 = 0; - let e: u64 = 0; - let r: u64 = vtstd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstd_u64() { - let a: u64 = 0; - let b: u64 = 0; - let e: u64 = 0; - let r: u64 = vtstd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuqadds_s32() { - let a: i32 = 1; - let b: u32 = 1; - let e: i32 = 2; - let r: i32 = vuqadds_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuqaddd_s64() { - let a: i64 = 1; - let b: u64 = 1; - let e: i64 = 2; - let r: i64 = vuqaddd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuqaddb_s8() { - let a: i8 = 1; - let b: u8 = 2; - let e: i8 = 3; - let r: i8 = vuqaddb_s8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuqaddh_s16() { - let a: i16 = 1; - let b: u16 = 2; - let e: i16 = 3; - let r: i16 = vuqaddh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabs_f64() { - let a: f64 = -0.1; - let e: f64 = 0.1; - let r: f64 = transmute(vabs_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabsq_f64() { - let a: f64x2 = f64x2::new(-0.1, -2.2); - let e: f64x2 = f64x2::new(0.1, 2.2); - let r: f64x2 = transmute(vabsq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcgt_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(0, 1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgtq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcgt_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(0, 1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgtq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_f64() { - let a: f64 = 1.2; - let b: f64 = 0.1; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcgt_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_f64() { - let a: f64x2 = f64x2::new(1.2, 2.3); - let b: f64x2 = f64x2::new(0.1, 1.2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgtq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtd_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: u64 = 0; - let r: u64 = vcgtd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtd_u64() { - let a: u64 = 1; - let b: u64 = 2; - let e: u64 = 0; - let r: u64 = vcgtd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgts_f32() { - let a: f32 = 1.; - let b: f32 = 2.; - let e: u32 = 0; - let r: u32 = vcgts_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtd_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: u64 = 0; - let r: u64 = vcgtd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_s64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(1); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vclt_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_s64() { - let a: i64x2 = i64x2::new(0, 1); - let b: i64x2 = i64x2::new(1, 2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcltq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_u64() { - let a: u64x1 = u64x1::new(0); - let b: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vclt_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_u64() { - let a: u64x2 = u64x2::new(0, 1); - let b: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcltq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_f64() { - let a: f64 = 0.1; - let b: f64 = 1.2; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vclt_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_f64() { - let a: f64x2 = f64x2::new(0.1, 1.2); - let b: f64x2 = f64x2::new(1.2, 2.3); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcltq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltd_s64() { - let a: i64 = 2; - let b: i64 = 1; - let e: u64 = 0; - let r: u64 = vcltd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltd_u64() { - let a: u64 = 2; - let b: u64 = 1; - let e: u64 = 0; - let r: u64 = vcltd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclts_f32() { - let a: f32 = 2.; - let b: f32 = 1.; - let e: u32 = 0; - let r: u32 = vclts_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltd_f64() { - let a: f64 = 2.; - let b: f64 = 1.; - let e: u64 = 0; - let r: u64 = vcltd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_s64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(1); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcle_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_s64() { - let a: i64x2 = i64x2::new(0, 1); - let b: i64x2 = i64x2::new(1, 2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcleq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcged_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: u64 = 0; - let r: u64 = vcged_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcged_u64() { - let a: u64 = 1; - let b: u64 = 2; - let e: u64 = 0; - let r: u64 = vcged_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcges_f32() { - let a: f32 = 1.; - let b: f32 = 2.; - let e: u32 = 0; - let r: u32 = vcges_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcged_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: u64 = 0; - let r: u64 = vcged_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_u64() { - let a: u64x1 = u64x1::new(0); - let b: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcle_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_u64() { - let a: u64x2 = u64x2::new(0, 1); - let b: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcleq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_f64() { - let a: f64 = 0.1; - let b: f64 = 1.2; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcle_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_f64() { - let a: f64x2 = f64x2::new(0.1, 1.2); - let b: f64x2 = f64x2::new(1.2, 2.3); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcleq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcled_s64() { - let a: i64 = 2; - let b: i64 = 1; - let e: u64 = 0; - let r: u64 = vcled_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcled_u64() { - let a: u64 = 2; - let b: u64 = 1; - let e: u64 = 0; - let r: u64 = vcled_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcles_f32() { - let a: f32 = 2.; - let b: f32 = 1.; - let e: u32 = 0; - let r: u32 = vcles_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcled_f64() { - let a: f64 = 2.; - let b: f64 = 1.; - let e: u64 = 0; - let r: u64 = vcled_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcge_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(0, 1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgeq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcge_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(0, 1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgeq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_f64() { - let a: f64 = 1.2; - let b: f64 = 0.1; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcge_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_f64() { - let a: f64x2 = f64x2::new(1.2, 2.3); - let b: f64x2 = f64x2::new(0.1, 1.2); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgeq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u8x8 = u8x8::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcgez_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); - let e: u8x16 = u8x16::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgezq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); - let e: u16x4 = u16x4::new(0, 0, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcgez_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u16x8 = u16x8::new(0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgezq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vcgez_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); - let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgezq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcgez_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, -1); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vcgezq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcgez_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgezq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgez_f64() { - let a: f64 = -1.2; - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcgez_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcgezq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezd_s64() { - let a: i64 = -1; - let e: u64 = 0; - let r: u64 = vcgezd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezs_f32() { - let a: f32 = -1.; - let e: u32 = 0; - let r: u32 = vcgezs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgezd_f64() { - let a: f64 = -1.; - let e: u64 = 0; - let r: u64 = vcgezd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u8x8 = u8x8::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcgtz_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); - let e: u8x16 = u8x16::new(0, 0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgtzq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); - let e: u16x4 = u16x4::new(0, 0, 0, 0xFF_FF); - let r: u16x4 = transmute(vcgtz_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u16x8 = u16x8::new(0, 0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgtzq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vcgtz_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); - let e: u32x4 = u32x4::new(0, 0, 0, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgtzq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcgtz_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, -1); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vcgtzq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vcgtz_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgtzq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtz_f64() { - let a: f64 = -1.2; - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcgtz_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vcgtzq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzd_s64() { - let a: i64 = -1; - let e: u64 = 0; - let r: u64 = vcgtzd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzs_f32() { - let a: f32 = -1.; - let e: u32 = 0; - let r: u32 = vcgtzs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtzd_f64() { - let a: f64 = -1.; - let e: u64 = 0; - let r: u64 = vcgtzd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vclez_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vclezq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0); - let r: u16x4 = transmute(vclez_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vclezq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vclez_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vclezq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vclez_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, -1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vclezq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vclez_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); - let r: u32x4 = transmute(vclezq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclez_f64() { - let a: f64 = -1.2; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vclez_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vclezq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezd_s64() { - let a: i64 = 2; - let e: u64 = 0; - let r: u64 = vclezd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezs_f32() { - let a: f32 = 2.; - let e: u32 = 0; - let r: u32 = vclezs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclezd_f64() { - let a: f64 = 2.; - let e: u64 = 0; - let r: u64 = vclezd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vcltz_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vcltzq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0, 0); - let r: u16x4 = transmute(vcltz_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vcltzq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcltz_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0, 0); - let r: u32x4 = transmute(vcltzq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcltz_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, -1); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcltzq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vcltz_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0, 0); - let r: u32x4 = transmute(vcltzq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltz_f64() { - let a: f64 = -1.2; - let e: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x1 = transmute(vcltz_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let r: u64x2 = transmute(vcltzq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzd_s64() { - let a: i64 = 2; - let e: u64 = 0; - let r: u64 = vcltzd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzs_f32() { - let a: f32 = 2.; - let e: u32 = 0; - let r: u32 = vcltzs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltzd_f64() { - let a: f64 = 2.; - let e: u64 = 0; - let r: u64 = vcltzd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagt_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64x1 = u64x1::new(!0); - let r: u64x1 = transmute(vcagt_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagtq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let b: f64x2 = f64x2::new(-1.1, 0.0); - let e: u64x2 = u64x2::new(!0, 0); - let r: u64x2 = transmute(vcagtq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagts_f32() { - let a: f32 = -1.2; - let b: f32 = -1.1; - let e: u32 = !0; - let r: u32 = vcagts_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagtd_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64 = !0; - let r: u64 = vcagtd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcage_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64x1 = u64x1::new(!0); - let r: u64x1 = transmute(vcage_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcageq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let b: f64x2 = f64x2::new(-1.1, 0.0); - let e: u64x2 = u64x2::new(!0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcageq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcages_f32() { - let a: f32 = -1.2; - let b: f32 = -1.1; - let e: u32 = !0; - let r: u32 = vcages_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaged_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64 = !0; - let r: u64 = vcaged_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcalt_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcalt_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaltq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let b: f64x2 = f64x2::new(-1.1, 0.0); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vcaltq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcalts_f32() { - let a: f32 = -1.2; - let b: f32 = -1.1; - let e: u32 = 0; - let r: u32 = vcalts_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaltd_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64 = 0; - let r: u64 = vcaltd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcale_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vcale_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaleq_f64() { - let a: f64x2 = f64x2::new(-1.2, 0.0); - let b: f64x2 = f64x2::new(-1.1, 0.0); - let e: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcaleq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcales_f32() { - let a: f32 = -1.2; - let b: f32 = -1.1; - let e: u32 = 0; - let r: u32 = vcales_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaled_f64() { - let a: f64 = -1.2; - let b: f64 = -1.1; - let e: u64 = 0; - let r: u64 = vcaled_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); - let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vcopy_lane_s8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vcopyq_laneq_s8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); - let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); - let r: i16x4 = transmute(vcopy_lane_s16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vcopyq_laneq_s16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); - let r: i32x2 = transmute(vcopy_lane_s32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); - let r: i32x4 = transmute(vcopyq_laneq_s32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); - let r: i64x2 = transmute(vcopyq_laneq_s64::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); - let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vcopy_lane_u8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vcopyq_laneq_u8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); - let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); - let r: u16x4 = transmute(vcopy_lane_u16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); - let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vcopyq_laneq_u16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); - let r: u32x2 = transmute(vcopy_lane_u32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); - let r: u32x4 = transmute(vcopyq_laneq_u32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(0, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 2); - let r: u64x2 = transmute(vcopyq_laneq_u64::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_p8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); - let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vcopy_lane_p8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_p8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vcopyq_laneq_p8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_p16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); - let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); - let r: i16x4 = transmute(vcopy_lane_p16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_p16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vcopyq_laneq_p16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_p64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(0, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 2); - let r: i64x2 = transmute(vcopyq_laneq_p64::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_lane_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(0., 0.5); - let e: f32x2 = f32x2::new(0.5, 2.); - let r: f32x2 = transmute(vcopy_lane_f32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); - let e: f32x4 = f32x4::new(0.5, 2., 3., 4.); - let r: f32x4 = transmute(vcopyq_laneq_f32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_laneq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64x2 = f64x2::new(0., 0.5); - let e: f64x2 = f64x2::new(0.5, 2.); - let r: f64x2 = transmute(vcopyq_laneq_f64::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vcopy_laneq_s8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); - let r: i16x4 = transmute(vcopy_laneq_s16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 2); - let r: i32x2 = transmute(vcopy_laneq_s32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x16 = u8x16::new(0, 0xFF, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: u8x8 = u8x8::new(0xFF, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vcopy_laneq_u8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x8 = u16x8::new(0, 0xFF_FF, 0, 0, 0, 0, 0, 0); - let e: u16x4 = u16x4::new(0xFF_FF, 2, 3, 4); - let r: u16x4 = transmute(vcopy_laneq_u16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 2); - let r: u32x2 = transmute(vcopy_laneq_u32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_p8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x16 = i8x16::new(0, 0x7F, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: i8x8 = i8x8::new(0x7F, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vcopy_laneq_p8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_p16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 0x7F_FF, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(0x7F_FF, 2, 3, 4); - let r: i16x4 = transmute(vcopy_laneq_p16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopy_laneq_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x4 = f32x4::new(0., 0.5, 0., 0.); - let e: f32x2 = f32x2::new(0.5, 2.); - let r: f32x2 = transmute(vcopy_laneq_f32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); - let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vcopyq_lane_s8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); - let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vcopyq_lane_s16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 2, 3, 4); - let r: i32x4 = transmute(vcopyq_lane_s32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x8 = u8x8::new(0, 0xFF, 0, 0, 0, 0, 0, 0); - let e: u8x16 = u8x16::new(0xFF, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vcopyq_lane_u8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x4 = u16x4::new(0, 0xFF_FF, 0, 0); - let e: u16x8 = u16x8::new(0xFF_FF, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vcopyq_lane_u16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 2, 3, 4); - let r: u32x4 = transmute(vcopyq_lane_u32::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_p8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x8 = i8x8::new(0, 0x7F, 0, 0, 0, 0, 0, 0); - let e: i8x16 = i8x16::new(0x7F, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vcopyq_lane_p8::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_p16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x4 = i16x4::new(0, 0x7F_FF, 0, 0); - let e: i16x8 = i16x8::new(0x7F_FF, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vcopyq_lane_p16::<0, 1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x2 = transmute(vcopyq_lane_s64::<1, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x1 = u64x1::new(0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u64x2 = u64x2::new(1, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let r: u64x2 = transmute(vcopyq_lane_u64::<1, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_p64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i64x2 = i64x2::new(1, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x2 = transmute(vcopyq_lane_p64::<1, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x2 = f32x2::new(0.5, 0.); - let e: f32x4 = f32x4::new(1., 0.5, 3., 4.); - let r: f32x4 = transmute(vcopyq_lane_f32::<1, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcopyq_lane_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64 = 0.5; - let e: f64x2 = f64x2::new(1., 0.5); - let r: f64x2 = transmute(vcopyq_lane_f64::<1, 0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_f64() { - let a: u64 = 0; - let e: f64 = 0.; - let r: f64 = transmute(vcreate_f64(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f64_s64() { - let a: i64x1 = i64x1::new(1); - let e: f64 = 1.; - let r: f64 = transmute(vcvt_f64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_f64_s64() { - let a: i64x2 = i64x2::new(1, 2); - let e: f64x2 = f64x2::new(1., 2.); - let r: f64x2 = transmute(vcvtq_f64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f64_u64() { - let a: u64x1 = u64x1::new(1); - let e: f64 = 1.; - let r: f64 = transmute(vcvt_f64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_f64_u64() { - let a: u64x2 = u64x2::new(1, 2); - let e: f64x2 = f64x2::new(1., 2.); - let r: f64x2 = transmute(vcvtq_f64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f64_f32() { - let a: f32x2 = f32x2::new(-1.2, 1.2); - let e: f64x2 = f64x2::new(-1.2f32 as f64, 1.2f32 as f64); - let r: f64x2 = transmute(vcvt_f64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_high_f64_f32() { - let a: f32x4 = f32x4::new(-1.2, 1.2, 2.3, 3.4); - let e: f64x2 = f64x2::new(2.3f32 as f64, 3.4f32 as f64); - let r: f64x2 = transmute(vcvt_high_f64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f32_f64() { - let a: f64x2 = f64x2::new(-1.2, 1.2); - let e: f32x2 = f32x2::new(-1.2f64 as f32, 1.2f64 as f32); - let r: f32x2 = transmute(vcvt_f32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_high_f32_f64() { - let a: f32x2 = f32x2::new(-1.2, 1.2); - let b: f64x2 = f64x2::new(-2.3, 3.4); - let e: f32x4 = f32x4::new(-1.2, 1.2, -2.3f64 as f32, 3.4f64 as f32); - let r: f32x4 = transmute(vcvt_high_f32_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtx_f32_f64() { - let a: f64x2 = f64x2::new(-1.0, 2.0); - let e: f32x2 = f32x2::new(-1.0, 2.0); - let r: f32x2 = transmute(vcvtx_f32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtxd_f32_f64() { - let a: f64 = -1.0; - let e: f32 = -1.0; - let r: f32 = vcvtxd_f32_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtx_high_f32_f64() { - let a: f32x2 = f32x2::new(-1.0, 2.0); - let b: f64x2 = f64x2::new(-3.0, 4.0); - let e: f32x4 = f32x4::new(-1.0, 2.0, -3.0, 4.0); - let r: f32x4 = transmute(vcvtx_high_f32_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_f64_s64() { - let a: i64x1 = i64x1::new(1); - let e: f64 = 0.25; - let r: f64 = transmute(vcvt_n_f64_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_f64_s64() { - let a: i64x2 = i64x2::new(1, 2); - let e: f64x2 = f64x2::new(0.25, 0.5); - let r: f64x2 = transmute(vcvtq_n_f64_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_n_f32_s32() { - let a: i32 = 1; - let e: f32 = 0.25; - let r: f32 = vcvts_n_f32_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_n_f64_s64() { - let a: i64 = 1; - let e: f64 = 0.25; - let r: f64 = vcvtd_n_f64_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_f64_u64() { - let a: u64x1 = u64x1::new(1); - let e: f64 = 0.25; - let r: f64 = transmute(vcvt_n_f64_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_f64_u64() { - let a: u64x2 = u64x2::new(1, 2); - let e: f64x2 = f64x2::new(0.25, 0.5); - let r: f64x2 = transmute(vcvtq_n_f64_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_n_f32_u32() { - let a: u32 = 1; - let e: f32 = 0.25; - let r: f32 = vcvts_n_f32_u32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_n_f64_u64() { - let a: u64 = 1; - let e: f64 = 0.25; - let r: f64 = vcvtd_n_f64_u64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_s64_f64() { - let a: f64 = 0.25; - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vcvt_n_s64_f64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_s64_f64() { - let a: f64x2 = f64x2::new(0.25, 0.5); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vcvtq_n_s64_f64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_n_s32_f32() { - let a: f32 = 0.25; - let e: i32 = 1; - let r: i32 = vcvts_n_s32_f32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_n_s64_f64() { - let a: f64 = 0.25; - let e: i64 = 1; - let r: i64 = vcvtd_n_s64_f64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_u64_f64() { - let a: f64 = 0.25; - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vcvt_n_u64_f64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_u64_f64() { - let a: f64x2 = f64x2::new(0.25, 0.5); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vcvtq_n_u64_f64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_n_u32_f32() { - let a: f32 = 0.25; - let e: u32 = 1; - let r: u32 = vcvts_n_u32_f32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_n_u64_f64() { - let a: f64 = 0.25; - let e: u64 = 1; - let r: u64 = vcvtd_n_u64_f64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_f32_s32() { - let a: i32 = 1; - let e: f32 = 1.; - let r: f32 = vcvts_f32_s32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_f64_s64() { - let a: i64 = 1; - let e: f64 = 1.; - let r: f64 = vcvtd_f64_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_f32_u32() { - let a: u32 = 1; - let e: f32 = 1.; - let r: f32 = vcvts_f32_u32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_f64_u64() { - let a: u64 = 1; - let e: f64 = 1.; - let r: f64 = vcvtd_f64_u64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_s32_f32() { - let a: f32 = 1.; - let e: i32 = 1; - let r: i32 = vcvts_s32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_s64_f64() { - let a: f64 = 1.; - let e: i64 = 1; - let r: i64 = vcvtd_s64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvts_u32_f32() { - let a: f32 = 1.; - let e: u32 = 1; - let r: u32 = vcvts_u32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtd_u64_f64() { - let a: f64 = 1.; - let e: u64 = 1; - let r: u64 = vcvtd_u64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_s64_f64() { - let a: f64 = -1.1; - let e: i64x1 = i64x1::new(-1); - let r: i64x1 = transmute(vcvt_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_s64_f64() { - let a: f64x2 = f64x2::new(-1.1, 2.1); - let e: i64x2 = i64x2::new(-1, 2); - let r: i64x2 = transmute(vcvtq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_u64_f64() { - let a: f64 = 1.1; - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vcvt_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_u64_f64() { - let a: f64x2 = f64x2::new(1.1, 2.1); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vcvtq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvta_s32_f32() { - let a: f32x2 = f32x2::new(-1.1, 2.1); - let e: i32x2 = i32x2::new(-1, 2); - let r: i32x2 = transmute(vcvta_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtaq_s32_f32() { - let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); - let e: i32x4 = i32x4::new(-1, 2, -3, 4); - let r: i32x4 = transmute(vcvtaq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvta_s64_f64() { - let a: f64 = -1.1; - let e: i64x1 = i64x1::new(-1); - let r: i64x1 = transmute(vcvta_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtaq_s64_f64() { - let a: f64x2 = f64x2::new(-1.1, 2.1); - let e: i64x2 = i64x2::new(-1, 2); - let r: i64x2 = transmute(vcvtaq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtas_s32_f32() { - let a: f32 = 2.9; - let e: i32 = 3; - let r: i32 = vcvtas_s32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtad_s64_f64() { - let a: f64 = 2.9; - let e: i64 = 3; - let r: i64 = vcvtad_s64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtas_u32_f32() { - let a: f32 = 2.9; - let e: u32 = 3; - let r: u32 = vcvtas_u32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtad_u64_f64() { - let a: f64 = 2.9; - let e: u64 = 3; - let r: u64 = vcvtad_u64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtn_s32_f32() { - let a: f32x2 = f32x2::new(-1.5, 2.1); - let e: i32x2 = i32x2::new(-2, 2); - let r: i32x2 = transmute(vcvtn_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnq_s32_f32() { - let a: f32x4 = f32x4::new(-1.5, 2.1, -2.9, 3.9); - let e: i32x4 = i32x4::new(-2, 2, -3, 4); - let r: i32x4 = transmute(vcvtnq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtn_s64_f64() { - let a: f64 = -1.5; - let e: i64x1 = i64x1::new(-2); - let r: i64x1 = transmute(vcvtn_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnq_s64_f64() { - let a: f64x2 = f64x2::new(-1.5, 2.1); - let e: i64x2 = i64x2::new(-2, 2); - let r: i64x2 = transmute(vcvtnq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtns_s32_f32() { - let a: f32 = -1.5; - let e: i32 = -2; - let r: i32 = vcvtns_s32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnd_s64_f64() { - let a: f64 = -1.5; - let e: i64 = -2; - let r: i64 = vcvtnd_s64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtm_s32_f32() { - let a: f32x2 = f32x2::new(-1.1, 2.1); - let e: i32x2 = i32x2::new(-2, 2); - let r: i32x2 = transmute(vcvtm_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmq_s32_f32() { - let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); - let e: i32x4 = i32x4::new(-2, 2, -3, 3); - let r: i32x4 = transmute(vcvtmq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtm_s64_f64() { - let a: f64 = -1.1; - let e: i64x1 = i64x1::new(-2); - let r: i64x1 = transmute(vcvtm_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmq_s64_f64() { - let a: f64x2 = f64x2::new(-1.1, 2.1); - let e: i64x2 = i64x2::new(-2, 2); - let r: i64x2 = transmute(vcvtmq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtms_s32_f32() { - let a: f32 = -1.1; - let e: i32 = -2; - let r: i32 = vcvtms_s32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmd_s64_f64() { - let a: f64 = -1.1; - let e: i64 = -2; - let r: i64 = vcvtmd_s64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtp_s32_f32() { - let a: f32x2 = f32x2::new(-1.1, 2.1); - let e: i32x2 = i32x2::new(-1, 3); - let r: i32x2 = transmute(vcvtp_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpq_s32_f32() { - let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); - let e: i32x4 = i32x4::new(-1, 3, -2, 4); - let r: i32x4 = transmute(vcvtpq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtp_s64_f64() { - let a: f64 = -1.1; - let e: i64x1 = i64x1::new(-1); - let r: i64x1 = transmute(vcvtp_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpq_s64_f64() { - let a: f64x2 = f64x2::new(-1.1, 2.1); - let e: i64x2 = i64x2::new(-1, 3); - let r: i64x2 = transmute(vcvtpq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtps_s32_f32() { - let a: f32 = -1.1; - let e: i32 = -1; - let r: i32 = vcvtps_s32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpd_s64_f64() { - let a: f64 = -1.1; - let e: i64 = -1; - let r: i64 = vcvtpd_s64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvta_u32_f32() { - let a: f32x2 = f32x2::new(1.1, 2.1); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vcvta_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtaq_u32_f32() { - let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vcvtaq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvta_u64_f64() { - let a: f64 = 1.1; - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vcvta_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtaq_u64_f64() { - let a: f64x2 = f64x2::new(1.1, 2.1); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vcvtaq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtn_u32_f32() { - let a: f32x2 = f32x2::new(1.5, 2.1); - let e: u32x2 = u32x2::new(2, 2); - let r: u32x2 = transmute(vcvtn_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnq_u32_f32() { - let a: f32x4 = f32x4::new(1.5, 2.1, 2.9, 3.9); - let e: u32x4 = u32x4::new(2, 2, 3, 4); - let r: u32x4 = transmute(vcvtnq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtn_u64_f64() { - let a: f64 = 1.5; - let e: u64x1 = u64x1::new(2); - let r: u64x1 = transmute(vcvtn_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnq_u64_f64() { - let a: f64x2 = f64x2::new(1.5, 2.1); - let e: u64x2 = u64x2::new(2, 2); - let r: u64x2 = transmute(vcvtnq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtns_u32_f32() { - let a: f32 = 1.5; - let e: u32 = 2; - let r: u32 = vcvtns_u32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtnd_u64_f64() { - let a: f64 = 1.5; - let e: u64 = 2; - let r: u64 = vcvtnd_u64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtm_u32_f32() { - let a: f32x2 = f32x2::new(1.1, 2.1); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vcvtm_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmq_u32_f32() { - let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); - let e: u32x4 = u32x4::new(1, 2, 2, 3); - let r: u32x4 = transmute(vcvtmq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtm_u64_f64() { - let a: f64 = 1.1; - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vcvtm_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmq_u64_f64() { - let a: f64x2 = f64x2::new(1.1, 2.1); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vcvtmq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtms_u32_f32() { - let a: f32 = 1.1; - let e: u32 = 1; - let r: u32 = vcvtms_u32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtmd_u64_f64() { - let a: f64 = 1.1; - let e: u64 = 1; - let r: u64 = vcvtmd_u64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtp_u32_f32() { - let a: f32x2 = f32x2::new(1.1, 2.1); - let e: u32x2 = u32x2::new(2, 3); - let r: u32x2 = transmute(vcvtp_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpq_u32_f32() { - let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); - let e: u32x4 = u32x4::new(2, 3, 3, 4); - let r: u32x4 = transmute(vcvtpq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtp_u64_f64() { - let a: f64 = 1.1; - let e: u64x1 = u64x1::new(2); - let r: u64x1 = transmute(vcvtp_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpq_u64_f64() { - let a: f64x2 = f64x2::new(1.1, 2.1); - let e: u64x2 = u64x2::new(2, 3); - let r: u64x2 = transmute(vcvtpq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtps_u32_f32() { - let a: f32 = 1.1; - let e: u32 = 2; - let r: u32 = vcvtps_u32_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtpd_u64_f64() { - let a: f64 = 1.1; - let e: u64 = 2; - let r: u64 = vcvtpd_u64_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_p64() { - let a: i64x2 = i64x2::new(1, 1); - let e: i64x2 = i64x2::new(1, 1); - let r: i64x2 = transmute(vdupq_laneq_p64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_p64() { - let a: i64x1 = i64x1::new(1); - let e: i64x2 = i64x2::new(1, 1); - let r: i64x2 = transmute(vdupq_lane_p64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let e: f64x2 = f64x2::new(1., 1.); - let r: f64x2 = transmute(vdupq_laneq_f64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_f64() { - let a: f64 = 1.; - let e: f64x2 = f64x2::new(1., 1.); - let r: f64x2 = transmute(vdupq_lane_f64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_p64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vdup_lane_p64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_f64() { - let a: f64 = 0.; - let e: f64 = 0.; - let r: f64 = transmute(vdup_lane_f64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vdup_laneq_p64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_f64() { - let a: f64x2 = f64x2::new(0., 1.); - let e: f64 = 1.; - let r: f64 = transmute(vdup_laneq_f64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_lane_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i8 = 1; - let r: i8 = vdupb_lane_s8::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_laneq_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: i8 = 1; - let r: i8 = vdupb_laneq_s8::<8>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_lane_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: i16 = 1; - let r: i16 = vduph_lane_s16::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_laneq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i16 = 1; - let r: i16 = vduph_laneq_s16::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_lane_s32() { - let a: i32x2 = i32x2::new(1, 1); - let e: i32 = 1; - let r: i32 = vdups_lane_s32::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_laneq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 4); - let e: i32 = 1; - let r: i32 = vdups_laneq_s32::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_lane_s64() { - let a: i64x1 = i64x1::new(1); - let e: i64 = 1; - let r: i64 = vdupd_lane_s64::<0>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_laneq_s64() { - let a: i64x2 = i64x2::new(1, 1); - let e: i64 = 1; - let r: i64 = vdupd_laneq_s64::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_lane_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u8 = 1; - let r: u8 = vdupb_lane_u8::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_laneq_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: u8 = 1; - let r: u8 = vdupb_laneq_u8::<8>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_lane_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 4); - let e: u16 = 1; - let r: u16 = vduph_lane_u16::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_laneq_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u16 = 1; - let r: u16 = vduph_laneq_u16::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_lane_u32() { - let a: u32x2 = u32x2::new(1, 1); - let e: u32 = 1; - let r: u32 = vdups_lane_u32::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_laneq_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 4); - let e: u32 = 1; - let r: u32 = vdups_laneq_u32::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_lane_u64() { - let a: u64x1 = u64x1::new(1); - let e: u64 = 1; - let r: u64 = vdupd_lane_u64::<0>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_laneq_u64() { - let a: u64x2 = u64x2::new(1, 1); - let e: u64 = 1; - let r: u64 = vdupd_laneq_u64::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_lane_p8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: p8 = 1; - let r: p8 = vdupb_lane_p8::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupb_laneq_p8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: p8 = 1; - let r: p8 = vdupb_laneq_p8::<8>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_lane_p16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: p16 = 1; - let r: p16 = vduph_lane_p16::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vduph_laneq_p16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: p16 = 1; - let r: p16 = vduph_laneq_p16::<4>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_lane_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let e: f32 = 1.; - let r: f32 = vdups_lane_f32::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdups_laneq_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 4.); - let e: f32 = 1.; - let r: f32 = vdups_laneq_f32::<2>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_lane_f64() { - let a: f64 = 1.; - let e: f64 = 1.; - let r: f64 = vdupd_lane_f64::<0>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupd_laneq_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let e: f64 = 1.; - let r: f64 = vdupd_laneq_f64::<1>(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_p64() { - let a: i64x2 = i64x2::new(1, 1); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vextq_p64::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let b: f64x2 = f64x2::new(2., 2.); - let e: f64x2 = f64x2::new(1., 2.); - let r: f64x2 = transmute(vextq_f64::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_f64() { - let a: f64 = 0.; - let b: f64 = 2.; - let c: f64 = 3.; - let e: f64 = 6.; - let r: f64 = transmute(vmla_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_f64() { - let a: f64x2 = f64x2::new(0., 1.); - let b: f64x2 = f64x2::new(2., 2.); - let c: f64x2 = f64x2::new(3., 3.); - let e: f64x2 = f64x2::new(6., 7.); - let r: f64x2 = transmute(vmlaq_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_s8() { - let a: i16x8 = i16x8::new(8, 7, 6, 5, 4, 3, 2, 1); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); - let r: i16x8 = transmute(vmlal_high_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_s16() { - let a: i32x4 = i32x4::new(8, 7, 6, 5); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let e: i32x4 = i32x4::new(8, 9, 10, 11); - let r: i32x4 = transmute(vmlal_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_s32() { - let a: i64x2 = i64x2::new(8, 7); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(3, 3, 0, 1); - let e: i64x2 = i64x2::new(8, 9); - let r: i64x2 = transmute(vmlal_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_u8() { - let a: u16x8 = u16x8::new(8, 7, 6, 5, 4, 3, 2, 1); - let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); - let r: u16x8 = transmute(vmlal_high_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_u16() { - let a: u32x4 = u32x4::new(8, 7, 6, 5); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let e: u32x4 = u32x4::new(8, 9, 10, 11); - let r: u32x4 = transmute(vmlal_high_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_u32() { - let a: u64x2 = u64x2::new(8, 7); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(3, 3, 0, 1); - let e: u64x2 = u64x2::new(8, 9); - let r: u64x2 = transmute(vmlal_high_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_n_s16() { - let a: i32x4 = i32x4::new(8, 7, 6, 5); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16 = 2; - let e: i32x4 = i32x4::new(8, 9, 10, 11); - let r: i32x4 = transmute(vmlal_high_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_n_s32() { - let a: i64x2 = i64x2::new(8, 7); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32 = 2; - let e: i64x2 = i64x2::new(8, 9); - let r: i64x2 = transmute(vmlal_high_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_n_u16() { - let a: u32x4 = u32x4::new(8, 7, 6, 5); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16 = 2; - let e: u32x4 = u32x4::new(8, 9, 10, 11); - let r: u32x4 = transmute(vmlal_high_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_n_u32() { - let a: u64x2 = u64x2::new(8, 7); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32 = 2; - let e: u64x2 = u64x2::new(8, 9); - let r: u64x2 = transmute(vmlal_high_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_lane_s16() { - let a: i32x4 = i32x4::new(8, 7, 6, 5); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(8, 9, 10, 11); - let r: i32x4 = transmute(vmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_laneq_s16() { - let a: i32x4 = i32x4::new(8, 7, 6, 5); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(8, 9, 10, 11); - let r: i32x4 = transmute(vmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_lane_s32() { - let a: i64x2 = i64x2::new(8, 7); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(8, 9); - let r: i64x2 = transmute(vmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_laneq_s32() { - let a: i64x2 = i64x2::new(8, 7); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(8, 9); - let r: i64x2 = transmute(vmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_lane_u16() { - let a: u32x4 = u32x4::new(8, 7, 6, 5); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u32x4 = u32x4::new(8, 9, 10, 11); - let r: u32x4 = transmute(vmlal_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_laneq_u16() { - let a: u32x4 = u32x4::new(8, 7, 6, 5); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(8, 9, 10, 11); - let r: u32x4 = transmute(vmlal_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_lane_u32() { - let a: u64x2 = u64x2::new(8, 7); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32x2 = u32x2::new(0, 2); - let e: u64x2 = u64x2::new(8, 9); - let r: u64x2 = transmute(vmlal_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_high_laneq_u32() { - let a: u64x2 = u64x2::new(8, 7); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u64x2 = u64x2::new(8, 9); - let r: u64x2 = transmute(vmlal_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_f64() { - let a: f64 = 6.; - let b: f64 = 2.; - let c: f64 = 3.; - let e: f64 = 0.; - let r: f64 = transmute(vmls_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_f64() { - let a: f64x2 = f64x2::new(6., 7.); - let b: f64x2 = f64x2::new(2., 2.); - let c: f64x2 = f64x2::new(3., 3.); - let e: f64x2 = f64x2::new(0., 1.); - let r: f64x2 = transmute(vmlsq_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_s8() { - let a: i16x8 = i16x8::new(14, 15, 16, 17, 18, 19, 20, 21); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x16 = i8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(14, 13, 12, 11, 10, 9, 8, 7); - let r: i16x8 = transmute(vmlsl_high_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_s16() { - let a: i32x4 = i32x4::new(14, 15, 16, 17); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let e: i32x4 = i32x4::new(14, 13, 12, 11); - let r: i32x4 = transmute(vmlsl_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_s32() { - let a: i64x2 = i64x2::new(14, 15); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(3, 3, 0, 1); - let e: i64x2 = i64x2::new(14, 13); - let r: i64x2 = transmute(vmlsl_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_u8() { - let a: u16x8 = u16x8::new(14, 15, 16, 17, 18, 19, 20, 21); - let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x16 = u8x16::new(3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(14, 13, 12, 11, 10, 9, 8, 7); - let r: u16x8 = transmute(vmlsl_high_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_u16() { - let a: u32x4 = u32x4::new(14, 15, 16, 17); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let e: u32x4 = u32x4::new(14, 13, 12, 11); - let r: u32x4 = transmute(vmlsl_high_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_u32() { - let a: u64x2 = u64x2::new(14, 15); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(3, 3, 0, 1); - let e: u64x2 = u64x2::new(14, 13); - let r: u64x2 = transmute(vmlsl_high_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_n_s16() { - let a: i32x4 = i32x4::new(14, 15, 16, 17); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16 = 2; - let e: i32x4 = i32x4::new(14, 13, 12, 11); - let r: i32x4 = transmute(vmlsl_high_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_n_s32() { - let a: i64x2 = i64x2::new(14, 15); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32 = 2; - let e: i64x2 = i64x2::new(14, 13); - let r: i64x2 = transmute(vmlsl_high_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_n_u16() { - let a: u32x4 = u32x4::new(14, 15, 16, 17); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16 = 2; - let e: u32x4 = u32x4::new(14, 13, 12, 11); - let r: u32x4 = transmute(vmlsl_high_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_n_u32() { - let a: u64x2 = u64x2::new(14, 15); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32 = 2; - let e: u64x2 = u64x2::new(14, 13); - let r: u64x2 = transmute(vmlsl_high_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_lane_s16() { - let a: i32x4 = i32x4::new(14, 15, 16, 17); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(14, 13, 12, 11); - let r: i32x4 = transmute(vmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_laneq_s16() { - let a: i32x4 = i32x4::new(14, 15, 16, 17); - let b: i16x8 = i16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(14, 13, 12, 11); - let r: i32x4 = transmute(vmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_lane_s32() { - let a: i64x2 = i64x2::new(14, 15); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(14, 13); - let r: i64x2 = transmute(vmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_laneq_s32() { - let a: i64x2 = i64x2::new(14, 15); - let b: i32x4 = i32x4::new(3, 3, 0, 1); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(14, 13); - let r: i64x2 = transmute(vmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_lane_u16() { - let a: u32x4 = u32x4::new(14, 15, 16, 17); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u32x4 = u32x4::new(14, 13, 12, 11); - let r: u32x4 = transmute(vmlsl_high_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_laneq_u16() { - let a: u32x4 = u32x4::new(14, 15, 16, 17); - let b: u16x8 = u16x8::new(3, 3, 0, 1, 0, 1, 2, 3); - let c: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(14, 13, 12, 11); - let r: u32x4 = transmute(vmlsl_high_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_lane_u32() { - let a: u64x2 = u64x2::new(14, 15); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32x2 = u32x2::new(0, 2); - let e: u64x2 = u64x2::new(14, 13); - let r: u64x2 = transmute(vmlsl_high_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_high_laneq_u32() { - let a: u64x2 = u64x2::new(14, 15); - let b: u32x4 = u32x4::new(3, 3, 0, 1); - let c: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u64x2 = u64x2::new(14, 13); - let r: u64x2 = transmute(vmlsl_high_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_s16() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 4, 5); - let b: i16x8 = i16x8::new(2, 3, 4, 5, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); - let r: i8x16 = transmute(vmovn_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_s32() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 3, 4, 5); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 4, 5); - let r: i16x8 = transmute(vmovn_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_s64() { - let a: i32x2 = i32x2::new(0, 1); - let b: i64x2 = i64x2::new(2, 3); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmovn_high_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_u16() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 4, 5); - let b: u16x8 = u16x8::new(2, 3, 4, 5, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15); - let r: u8x16 = transmute(vmovn_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_u32() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(2, 3, 4, 5); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 4, 5); - let r: u16x8 = transmute(vmovn_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovn_high_u64() { - let a: u32x2 = u32x2::new(0, 1); - let b: u64x2 = u64x2::new(2, 3); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmovn_high_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_s64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vneg_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, -1); - let r: i64x2 = transmute(vnegq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegd_s64() { - let a: i64 = 1; - let e: i64 = -1; - let r: i64 = vnegd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_f64() { - let a: f64 = 0.; - let e: f64 = 0.; - let r: f64 = transmute(vneg_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_f64() { - let a: f64x2 = f64x2::new(0., 1.); - let e: f64x2 = f64x2::new(0., -1.); - let r: f64x2 = transmute(vnegq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqneg_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vqneg_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 0); - let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0); - let r: i64x2 = transmute(vqnegq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegb_s8() { - let a: i8 = 1; - let e: i8 = -1; - let r: i8 = vqnegb_s8(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegh_s16() { - let a: i16 = 1; - let e: i16 = -1; - let r: i16 = vqnegh_s16(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegs_s32() { - let a: i32 = 1; - let e: i32 = -1; - let r: i32 = vqnegs_s32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegd_s64() { - let a: i64 = 1; - let e: i64 = -1; - let r: i64 = vqnegd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubb_s8() { - let a: i8 = 42; - let b: i8 = 1; - let e: i8 = 41; - let r: i8 = vqsubb_s8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubh_s16() { - let a: i16 = 42; - let b: i16 = 1; - let e: i16 = 41; - let r: i16 = vqsubh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubb_u8() { - let a: u8 = 42; - let b: u8 = 1; - let e: u8 = 41; - let r: u8 = vqsubb_u8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubh_u16() { - let a: u16 = 42; - let b: u16 = 1; - let e: u16 = 41; - let r: u16 = vqsubh_u16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubs_u32() { - let a: u32 = 42; - let b: u32 = 1; - let e: u32 = 41; - let r: u32 = vqsubs_u32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubd_u64() { - let a: u64 = 42; - let b: u64 = 1; - let e: u64 = 41; - let r: u64 = vqsubd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubs_s32() { - let a: i32 = 42; - let b: i32 = 1; - let e: i32 = 41; - let r: i32 = vqsubs_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubd_s64() { - let a: i64 = 42; - let b: i64 = 1; - let e: i64 = 41; - let r: i64 = vqsubd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbit_s8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); - let r: i8x8 = transmute(vrbit_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbitq_s8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); - let r: i8x16 = transmute(vrbitq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbit_u8() { - let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let e: u8x8 = u8x8::new(0, 64, 32, 96, 16, 80, 48, 112); - let r: u8x8 = transmute(vrbit_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbitq_u8() { - let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let e: u8x16 = u8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); - let r: u8x16 = transmute(vrbitq_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbit_p8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let e: i8x8 = i8x8::new(0, 64, 32, 96, 16, 80, 48, 112); - let r: i8x8 = transmute(vrbit_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrbitq_p8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let e: i8x16 = i8x16::new(0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120); - let r: i8x16 = transmute(vrbitq_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndx_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-2.0, 0.0); - let r: f32x2 = transmute(vrndx_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndxq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); - let r: f32x4 = transmute(vrndxq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndx_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrndx_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndxq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-2.0, 0.0); - let r: f64x2 = transmute(vrndxq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrnda_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-2.0, 1.0); - let r: f32x2 = transmute(vrnda_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndaq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-2.0, 1.0, 2.0, 3.0); - let r: f32x4 = transmute(vrndaq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrnda_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnda_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndaq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-2.0, 1.0); - let r: f64x2 = transmute(vrndaq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndn_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrndn_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndnq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-2.0, 0.0); - let r: f64x2 = transmute(vrndnq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndns_f32() { - let a: f32 = -1.5; - let e: f32 = -2.0; - let r: f32 = vrndns_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndm_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-2.0, 0.0); - let r: f32x2 = transmute(vrndm_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndmq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-2.0, 0.0, 1.0, 2.0); - let r: f32x4 = transmute(vrndmq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndm_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrndm_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndmq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-2.0, 0.0); - let r: f64x2 = transmute(vrndmq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndp_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-1.0, 1.0); - let r: f32x2 = transmute(vrndp_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndpq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-1.0, 1.0, 2.0, 3.0); - let r: f32x4 = transmute(vrndpq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndp_f64() { - let a: f64 = -1.5; - let e: f64 = -1.0; - let r: f64 = transmute(vrndp_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndpq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-1.0, 1.0); - let r: f64x2 = transmute(vrndpq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrnd_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-1.0, 0.0); - let r: f32x2 = transmute(vrnd_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-1.0, 0.0, 1.0, 2.0); - let r: f32x4 = transmute(vrndq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrnd_f64() { - let a: f64 = -1.5; - let e: f64 = -1.0; - let r: f64 = transmute(vrnd_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-1.0, 0.0); - let r: f64x2 = transmute(vrndq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndi_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-2.0, 0.0); - let r: f32x2 = transmute(vrndi_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndiq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); - let r: f32x4 = transmute(vrndiq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndi_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrndi_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrndiq_f64() { - let a: f64x2 = f64x2::new(-1.5, 0.5); - let e: f64x2 = f64x2::new(-2.0, 0.0); - let r: f64x2 = transmute(vrndiq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddb_s8() { - let a: i8 = 42; - let b: i8 = 1; - let e: i8 = 43; - let r: i8 = vqaddb_s8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddh_s16() { - let a: i16 = 42; - let b: i16 = 1; - let e: i16 = 43; - let r: i16 = vqaddh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddb_u8() { - let a: u8 = 42; - let b: u8 = 1; - let e: u8 = 43; - let r: u8 = vqaddb_u8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddh_u16() { - let a: u16 = 42; - let b: u16 = 1; - let e: u16 = 43; - let r: u16 = vqaddh_u16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadds_u32() { - let a: u32 = 42; - let b: u32 = 1; - let e: u32 = 43; - let r: u32 = vqadds_u32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddd_u64() { - let a: u64 = 42; - let b: u64 = 1; - let e: u64 = 43; - let r: u64 = vqaddd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadds_s32() { - let a: i32 = 42; - let b: i32 = 1; - let e: i32 = 43; - let r: i32 = vqadds_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddd_s64() { - let a: i64 = 42; - let b: i64 = 1; - let e: i64 = 43; - let r: i64 = vqaddd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64_x2() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 2.]; - let r: [f64; 2] = transmute(vld1_f64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64_x2() { - let a: [f64; 5] = [0., 1., 2., 3., 4.]; - let e: [f64x2; 2] = [f64x2::new(1., 2.), f64x2::new(3., 4.)]; - let r: [f64x2; 2] = transmute(vld1q_f64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64_x3() { - let a: [f64; 4] = [0., 1., 2., 3.]; - let e: [f64; 3] = [1., 2., 3.]; - let r: [f64; 3] = transmute(vld1_f64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64_x3() { - let a: [f64; 7] = [0., 1., 2., 3., 4., 5., 6.]; - let e: [f64x2; 3] = [f64x2::new(1., 2.), f64x2::new(3., 4.), f64x2::new(5., 6.)]; - let r: [f64x2; 3] = transmute(vld1q_f64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f64_x4() { - let a: [f64; 5] = [0., 1., 2., 3., 4.]; - let e: [f64; 4] = [1., 2., 3., 4.]; - let r: [f64; 4] = transmute(vld1_f64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f64_x4() { - let a: [f64; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f64x2; 4] = [f64x2::new(1., 2.), f64x2::new(3., 4.), f64x2::new(5., 6.), f64x2::new(7., 8.)]; - let r: [f64x2; 4] = transmute(vld1q_f64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 3]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(2, 3)]; - let r: [i64x2; 2] = transmute(vld2q_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [u64x2; 2] = [u64x2::new(1, 2), u64x2::new(2, 3)]; - let r: [u64x2; 2] = transmute(vld2q_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(2, 3)]; - let r: [i64x2; 2] = transmute(vld2q_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_f64() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 2.]; - let r: [f64; 2] = transmute(vld2_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 3.]; - let e: [f64x2; 2] = [f64x2::new(1., 2.), f64x2::new(2., 3.)]; - let r: [f64x2; 2] = transmute(vld2q_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_s64() { - let a: [i64; 5] = [0, 1, 1, 2, 3]; - let e: [i64x2; 2] = [i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 2] = transmute(vld2q_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_u64() { - let a: [u64; 5] = [0, 1, 1, 2, 3]; - let e: [u64x2; 2] = [u64x2::new(1, 1), u64x2::new(1, 1)]; - let r: [u64x2; 2] = transmute(vld2q_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_p64() { - let a: [u64; 5] = [0, 1, 1, 2, 3]; - let e: [i64x2; 2] = [i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 2] = transmute(vld2q_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_f64() { - let a: [f64; 3] = [0., 1., 1.]; - let e: [f64; 2] = [1., 1.]; - let r: [f64; 2] = transmute(vld2_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_f64() { - let a: [f64; 5] = [0., 1., 1., 2., 3.]; - let e: [f64x2; 2] = [f64x2::new(1., 1.), f64x2::new(1., 1.)]; - let r: [f64x2; 2] = transmute(vld2q_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_s8() { - let a: [i8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x16; 2] = [i8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x16; 2] = transmute(vld2q_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_s64() { - let a: [i64; 3] = [0, 1, 2]; - let b: [i64x1; 2] = [i64x1::new(0), i64x1::new(2)]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld2_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_s64() { - let a: [i64; 5] = [0, 1, 2, 3, 4]; - let b: [i64x2; 2] = [i64x2::new(0, 2), i64x2::new(2, 14)]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(2, 14)]; - let r: [i64x2; 2] = transmute(vld2q_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_p64() { - let a: [u64; 3] = [0, 1, 2]; - let b: [i64x1; 2] = [i64x1::new(0), i64x1::new(2)]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld2_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_p64() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let b: [i64x2; 2] = [i64x2::new(0, 2), i64x2::new(2, 14)]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(2, 14)]; - let r: [i64x2; 2] = transmute(vld2q_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_u8() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u8x16; 2] = [u8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let e: [u8x16; 2] = [u8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let r: [u8x16; 2] = transmute(vld2q_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_u64() { - let a: [u64; 3] = [0, 1, 2]; - let b: [u64x1; 2] = [u64x1::new(0), u64x1::new(2)]; - let e: [u64x1; 2] = [u64x1::new(1), u64x1::new(2)]; - let r: [u64x1; 2] = transmute(vld2_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_u64() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let b: [u64x2; 2] = [u64x2::new(0, 2), u64x2::new(2, 14)]; - let e: [u64x2; 2] = [u64x2::new(1, 2), u64x2::new(2, 14)]; - let r: [u64x2; 2] = transmute(vld2q_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_p8() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x16; 2] = [i8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x16; 2] = transmute(vld2q_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_f64() { - let a: [f64; 3] = [0., 1., 2.]; - let b: [f64; 2] = [0., 2.]; - let e: [f64; 2] = [1., 2.]; - let r: [f64; 2] = transmute(vld2_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_f64() { - let a: [f64; 5] = [0., 1., 2., 3., 4.]; - let b: [f64x2; 2] = [f64x2::new(0., 2.), f64x2::new(2., 14.)]; - let e: [f64x2; 2] = [f64x2::new(1., 2.), f64x2::new(2., 14.)]; - let r: [f64x2; 2] = transmute(vld2q_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_s64() { - let a: [i64; 7] = [0, 1, 2, 2, 2, 4, 4]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(2, 4), i64x2::new(2, 4)]; - let r: [i64x2; 3] = transmute(vld3q_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_u64() { - let a: [u64; 7] = [0, 1, 2, 2, 2, 4, 4]; - let e: [u64x2; 3] = [u64x2::new(1, 2), u64x2::new(2, 4), u64x2::new(2, 4)]; - let r: [u64x2; 3] = transmute(vld3q_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_p64() { - let a: [u64; 7] = [0, 1, 2, 2, 2, 4, 4]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(2, 4), i64x2::new(2, 4)]; - let r: [i64x2; 3] = transmute(vld3q_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_f64() { - let a: [f64; 4] = [0., 1., 2., 2.]; - let e: [f64; 3] = [1., 2., 2.]; - let r: [f64; 3] = transmute(vld3_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_f64() { - let a: [f64; 7] = [0., 1., 2., 2., 2., 4., 4.]; - let e: [f64x2; 3] = [f64x2::new(1., 2.), f64x2::new(2., 4.), f64x2::new(2., 4.)]; - let r: [f64x2; 3] = transmute(vld3q_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_s64() { - let a: [i64; 7] = [0, 1, 1, 1, 3, 1, 4]; - let e: [i64x2; 3] = [i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 3] = transmute(vld3q_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_u64() { - let a: [u64; 7] = [0, 1, 1, 1, 3, 1, 4]; - let e: [u64x2; 3] = [u64x2::new(1, 1), u64x2::new(1, 1), u64x2::new(1, 1)]; - let r: [u64x2; 3] = transmute(vld3q_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_p64() { - let a: [u64; 7] = [0, 1, 1, 1, 3, 1, 4]; - let e: [i64x2; 3] = [i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 3] = transmute(vld3q_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_f64() { - let a: [f64; 4] = [0., 1., 1., 1.]; - let e: [f64; 3] = [1., 1., 1.]; - let r: [f64; 3] = transmute(vld3_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_f64() { - let a: [f64; 7] = [0., 1., 1., 1., 3., 1., 4.]; - let e: [f64x2; 3] = [f64x2::new(1., 1.), f64x2::new(1., 1.), f64x2::new(1., 1.)]; - let r: [f64x2; 3] = transmute(vld3q_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_s8() { - let a: [i8; 49] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x16; 3] = [i8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let r: [i8x16; 3] = transmute(vld3q_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_s64() { - let a: [i64; 4] = [0, 1, 2, 2]; - let b: [i64x1; 3] = [i64x1::new(0), i64x1::new(2), i64x1::new(2)]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 3] = transmute(vld3_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_s64() { - let a: [i64; 7] = [0, 1, 2, 2, 4, 5, 6]; - let b: [i64x2; 3] = [i64x2::new(0, 2), i64x2::new(2, 14), i64x2::new(2, 16)]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(2, 14), i64x2::new(2, 16)]; - let r: [i64x2; 3] = transmute(vld3q_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_p64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let b: [i64x1; 3] = [i64x1::new(0), i64x1::new(2), i64x1::new(2)]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 3] = transmute(vld3_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_p64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 5, 6]; - let b: [i64x2; 3] = [i64x2::new(0, 2), i64x2::new(2, 14), i64x2::new(2, 16)]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(2, 14), i64x2::new(2, 16)]; - let r: [i64x2; 3] = transmute(vld3q_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_p8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x16; 3] = [i8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let r: [i8x16; 3] = transmute(vld3q_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_u8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u8x16; 3] = [u8x16::new(0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let e: [u8x16; 3] = [u8x16::new(1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26), u8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8)]; - let r: [u8x16; 3] = transmute(vld3q_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_u64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let b: [u64x1; 3] = [u64x1::new(0), u64x1::new(2), u64x1::new(2)]; - let e: [u64x1; 3] = [u64x1::new(1), u64x1::new(2), u64x1::new(2)]; - let r: [u64x1; 3] = transmute(vld3_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_u64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 5, 6]; - let b: [u64x2; 3] = [u64x2::new(0, 2), u64x2::new(2, 14), u64x2::new(2, 16)]; - let e: [u64x2; 3] = [u64x2::new(1, 2), u64x2::new(2, 14), u64x2::new(2, 16)]; - let r: [u64x2; 3] = transmute(vld3q_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_f64() { - let a: [f64; 4] = [0., 1., 2., 2.]; - let b: [f64; 3] = [0., 2., 2.]; - let e: [f64; 3] = [1., 2., 2.]; - let r: [f64; 3] = transmute(vld3_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_f64() { - let a: [f64; 7] = [0., 1., 2., 2., 4., 5., 6.]; - let b: [f64x2; 3] = [f64x2::new(0., 2.), f64x2::new(2., 14.), f64x2::new(9., 16.)]; - let e: [f64x2; 3] = [f64x2::new(1., 2.), f64x2::new(2., 14.), f64x2::new(2., 16.)]; - let r: [f64x2; 3] = transmute(vld3q_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_s64() { - let a: [i64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(2, 6), i64x2::new(2, 6), i64x2::new(6, 8)]; - let r: [i64x2; 4] = transmute(vld4q_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_u64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u64x2; 4] = [u64x2::new(1, 2), u64x2::new(2, 6), u64x2::new(2, 6), u64x2::new(6, 8)]; - let r: [u64x2; 4] = transmute(vld4q_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_p64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(2, 6), i64x2::new(2, 6), i64x2::new(6, 8)]; - let r: [i64x2; 4] = transmute(vld4q_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 6.]; - let e: [f64; 4] = [1., 2., 2., 6.]; - let r: [f64; 4] = transmute(vld4_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_f64() { - let a: [f64; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f64x2; 4] = [f64x2::new(1., 2.), f64x2::new(2., 6.), f64x2::new(2., 6.), f64x2::new(6., 8.)]; - let r: [f64x2; 4] = transmute(vld4q_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_s64() { - let a: [i64; 9] = [0, 1, 1, 1, 1, 2, 4, 3, 5]; - let e: [i64x2; 4] = [i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 4] = transmute(vld4q_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_u64() { - let a: [u64; 9] = [0, 1, 1, 1, 1, 2, 4, 3, 5]; - let e: [u64x2; 4] = [u64x2::new(1, 1), u64x2::new(1, 1), u64x2::new(1, 1), u64x2::new(1, 1)]; - let r: [u64x2; 4] = transmute(vld4q_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_p64() { - let a: [u64; 9] = [0, 1, 1, 1, 1, 2, 4, 3, 5]; - let e: [i64x2; 4] = [i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1), i64x2::new(1, 1)]; - let r: [i64x2; 4] = transmute(vld4q_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_f64() { - let a: [f64; 5] = [0., 1., 1., 1., 1.]; - let e: [f64; 4] = [1., 1., 1., 1.]; - let r: [f64; 4] = transmute(vld4_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_f64() { - let a: [f64; 9] = [0., 1., 1., 1., 1., 6., 4., 3., 5.]; - let e: [f64x2; 4] = [f64x2::new(1., 1.), f64x2::new(1., 1.), f64x2::new(1., 1.), f64x2::new(1., 1.)]; - let r: [f64x2; 4] = transmute(vld4q_dup_f64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_s8() { - let a: [i8; 65] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16]; - let b: [i8x16; 4] = [i8x16::new(0, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), i8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), i8x16::new(2, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i8x16; 4] = transmute(vld4q_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 2]; - let b: [i64x1; 4] = [i64x1::new(0), i64x1::new(2), i64x1::new(2), i64x1::new(2)]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 4] = transmute(vld4_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_s64() { - let a: [i64; 9] = [0, 1, 2, 2, 2, 5, 6, 7, 8]; - let b: [i64x2; 4] = [i64x2::new(0, 2), i64x2::new(2, 2), i64x2::new(2, 16), i64x2::new(2, 18)]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(2, 2), i64x2::new(2, 16), i64x2::new(2, 18)]; - let r: [i64x2; 4] = transmute(vld4q_lane_s64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 2]; - let b: [i64x1; 4] = [i64x1::new(0), i64x1::new(2), i64x1::new(2), i64x1::new(2)]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 4] = transmute(vld4_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_p64() { - let a: [u64; 9] = [0, 1, 2, 2, 2, 5, 6, 7, 8]; - let b: [i64x2; 4] = [i64x2::new(0, 2), i64x2::new(2, 2), i64x2::new(2, 16), i64x2::new(2, 18)]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(2, 2), i64x2::new(2, 16), i64x2::new(2, 18)]; - let r: [i64x2; 4] = transmute(vld4q_lane_p64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_p8() { - let a: [u8; 65] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16]; - let b: [i8x16; 4] = [i8x16::new(0, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), i8x16::new(11, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), i8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), i8x16::new(2, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), i8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), i8x16::new(2, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i8x16; 4] = transmute(vld4q_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_u8() { - let a: [u8; 65] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16]; - let b: [u8x16; 4] = [u8x16::new(0, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), u8x16::new(11, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), u8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let e: [u8x16; 4] = [u8x16::new(1, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26), u8x16::new(2, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26), u8x16::new(2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8), u8x16::new(2, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [u8x16; 4] = transmute(vld4q_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 2]; - let b: [u64x1; 4] = [u64x1::new(0), u64x1::new(2), u64x1::new(2), u64x1::new(2)]; - let e: [u64x1; 4] = [u64x1::new(1), u64x1::new(2), u64x1::new(2), u64x1::new(2)]; - let r: [u64x1; 4] = transmute(vld4_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_u64() { - let a: [u64; 9] = [0, 1, 2, 2, 2, 5, 6, 7, 8]; - let b: [u64x2; 4] = [u64x2::new(0, 2), u64x2::new(2, 2), u64x2::new(2, 16), u64x2::new(2, 18)]; - let e: [u64x2; 4] = [u64x2::new(1, 2), u64x2::new(2, 2), u64x2::new(2, 16), u64x2::new(2, 18)]; - let r: [u64x2; 4] = transmute(vld4q_lane_u64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 2.]; - let b: [f64; 4] = [0., 2., 2., 2.]; - let e: [f64; 4] = [1., 2., 2., 2.]; - let r: [f64; 4] = transmute(vld4_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_f64() { - let a: [f64; 9] = [0., 1., 2., 2., 2., 5., 6., 7., 8.]; - let b: [f64x2; 4] = [f64x2::new(0., 2.), f64x2::new(2., 2.), f64x2::new(2., 16.), f64x2::new(2., 18.)]; - let e: [f64x2; 4] = [f64x2::new(1., 2.), f64x2::new(2., 2.), f64x2::new(2., 16.), f64x2::new(2., 18.)]; - let r: [f64x2; 4] = transmute(vld4q_lane_f64::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_f64() { - let a: [f64; 2] = [0., 1.]; - let e: [f64; 1] = [1.]; - let mut r: [f64; 1] = [0f64; 1]; - vst1_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_f64() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 0.]; - let mut r: [f64; 2] = [0f64; 2]; - vst1q_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64_x2() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 2.]; - let mut r: [f64; 2] = [0f64; 2]; - vst1_f64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64_x2() { - let a: [f64; 5] = [0., 1., 2., 3., 4.]; - let e: [f64; 4] = [1., 2., 3., 4.]; - let mut r: [f64; 4] = [0f64; 4]; - vst1q_f64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64_x3() { - let a: [f64; 4] = [0., 1., 2., 3.]; - let e: [f64; 3] = [1., 2., 3.]; - let mut r: [f64; 3] = [0f64; 3]; - vst1_f64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64_x3() { - let a: [f64; 7] = [0., 1., 2., 3., 4., 5., 6.]; - let e: [f64; 6] = [1., 2., 3., 4., 5., 6.]; - let mut r: [f64; 6] = [0f64; 6]; - vst1q_f64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f64_x4() { - let a: [f64; 5] = [0., 1., 2., 3., 4.]; - let e: [f64; 4] = [1., 2., 3., 4.]; - let mut r: [f64; 4] = [0f64; 4]; - vst1_f64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f64_x4() { - let a: [f64; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f64; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; - let mut r: [f64; 8] = [0f64; 8]; - vst1q_f64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 3]; - let e: [i64; 4] = [1, 2, 2, 3]; - let mut r: [i64; 4] = [0i64; 4]; - vst2q_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [u64; 4] = [1, 2, 2, 3]; - let mut r: [u64; 4] = [0u64; 4]; - vst2q_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [u64; 4] = [1, 2, 2, 3]; - let mut r: [u64; 4] = [0u64; 4]; - vst2q_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_f64() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 2.]; - let mut r: [f64; 2] = [0f64; 2]; - vst2_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 3.]; - let e: [f64; 4] = [1., 2., 2., 3.]; - let mut r: [f64; 4] = [0f64; 4]; - vst2q_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [i8; 32] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 32] = [0i8; 32]; - vst2q_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_s64() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64; 2] = [1, 2]; - let mut r: [i64; 2] = [0i64; 2]; - vst2_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 3]; - let e: [i64; 4] = [1, 2, 0, 0]; - let mut r: [i64; 4] = [0i64; 4]; - vst2q_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [u8; 32] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 32] = [0u8; 32]; - vst2q_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_u64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst2_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [u64; 4] = [1, 2, 0, 0]; - let mut r: [u64; 4] = [0u64; 4]; - vst2q_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [u8; 32] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 32] = [0u8; 32]; - vst2q_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_p64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst2_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 3]; - let e: [u64; 4] = [1, 2, 0, 0]; - let mut r: [u64; 4] = [0u64; 4]; - vst2q_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_f64() { - let a: [f64; 3] = [0., 1., 2.]; - let e: [f64; 2] = [1., 2.]; - let mut r: [f64; 2] = [0f64; 2]; - vst2_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 3.]; - let e: [f64; 4] = [1., 2., 0., 0.]; - let mut r: [f64; 4] = [0f64; 4]; - vst2q_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_s64() { - let a: [i64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [i64; 6] = [1, 2, 2, 2, 4, 4]; - let mut r: [i64; 6] = [0i64; 6]; - vst3q_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_u64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u64; 6] = [1, 2, 2, 2, 4, 4]; - let mut r: [u64; 6] = [0u64; 6]; - vst3q_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_p64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u64; 6] = [1, 2, 2, 2, 4, 4]; - let mut r: [u64; 6] = [0u64; 6]; - vst3q_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_f64() { - let a: [f64; 4] = [0., 1., 2., 2.]; - let e: [f64; 3] = [1., 2., 2.]; - let mut r: [f64; 3] = [0f64; 3]; - vst3_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_f64() { - let a: [f64; 7] = [0., 1., 2., 2., 4., 2., 4.]; - let e: [f64; 6] = [1., 2., 2., 2., 4., 4.]; - let mut r: [f64; 6] = [0f64; 6]; - vst3q_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_s8() { - let a: [i8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [i8; 48] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 48] = [0i8; 48]; - vst3q_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_s64() { - let a: [i64; 4] = [0, 1, 2, 2]; - let e: [i64; 3] = [1, 2, 2]; - let mut r: [i64; 3] = [0i64; 3]; - vst3_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_s64() { - let a: [i64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [i64; 6] = [1, 2, 2, 0, 0, 0]; - let mut r: [i64; 6] = [0i64; 6]; - vst3q_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_u8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [u8; 48] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 48] = [0u8; 48]; - vst3q_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_u64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [u64; 3] = [1, 2, 2]; - let mut r: [u64; 3] = [0u64; 3]; - vst3_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_u64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u64; 6] = [1, 2, 2, 0, 0, 0]; - let mut r: [u64; 6] = [0u64; 6]; - vst3q_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_p8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [u8; 48] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 48] = [0u8; 48]; - vst3q_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_p64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [u64; 3] = [1, 2, 2]; - let mut r: [u64; 3] = [0u64; 3]; - vst3_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_p64() { - let a: [u64; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u64; 6] = [1, 2, 2, 0, 0, 0]; - let mut r: [u64; 6] = [0u64; 6]; - vst3q_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_f64() { - let a: [f64; 4] = [0., 1., 2., 2.]; - let e: [f64; 3] = [1., 2., 2.]; - let mut r: [f64; 3] = [0f64; 3]; - vst3_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_f64() { - let a: [f64; 7] = [0., 1., 2., 2., 3., 2., 3.]; - let e: [f64; 6] = [1., 2., 2., 0., 0., 0.]; - let mut r: [f64; 6] = [0f64; 6]; - vst3q_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_s64() { - let a: [i64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i64; 8] = [1, 2, 2, 6, 2, 6, 6, 8]; - let mut r: [i64; 8] = [0i64; 8]; - vst4q_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_u64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u64; 8] = [1, 2, 2, 6, 2, 6, 6, 8]; - let mut r: [u64; 8] = [0u64; 8]; - vst4q_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_p64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u64; 8] = [1, 2, 2, 6, 2, 6, 6, 8]; - let mut r: [u64; 8] = [0u64; 8]; - vst4q_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 6.]; - let e: [f64; 4] = [1., 2., 2., 6.]; - let mut r: [f64; 4] = [0f64; 4]; - vst4_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_f64() { - let a: [f64; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f64; 8] = [1., 2., 2., 6., 2., 6., 6., 8.]; - let mut r: [f64; 8] = [0f64; 8]; - vst4q_f64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_s8() { - let a: [i8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [i8; 64] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 64] = [0i8; 64]; - vst4q_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 6]; - let e: [i64; 4] = [1, 2, 2, 6]; - let mut r: [i64; 4] = [0i64; 4]; - vst4_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_s64() { - let a: [i64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i64; 8] = [1, 2, 2, 6, 0, 0, 0, 0]; - let mut r: [i64; 8] = [0i64; 8]; - vst4q_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_u8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [u8; 64] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 64] = [0u8; 64]; - vst4q_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [u64; 4] = [1, 2, 2, 6]; - let mut r: [u64; 4] = [0u64; 4]; - vst4_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_u64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u64; 8] = [1, 2, 2, 6, 0, 0, 0, 0]; - let mut r: [u64; 8] = [0u64; 8]; - vst4q_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_p8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [u8; 64] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 64] = [0u8; 64]; - vst4q_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [u64; 4] = [1, 2, 2, 6]; - let mut r: [u64; 4] = [0u64; 4]; - vst4_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_p64() { - let a: [u64; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u64; 8] = [1, 2, 2, 6, 0, 0, 0, 0]; - let mut r: [u64; 8] = [0u64; 8]; - vst4q_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_f64() { - let a: [f64; 5] = [0., 1., 2., 2., 6.]; - let e: [f64; 4] = [1., 2., 2., 6.]; - let mut r: [f64; 4] = [0f64; 4]; - vst4_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_f64() { - let a: [f64; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f64; 8] = [1., 2., 2., 6., 0., 0., 0., 0.]; - let mut r: [f64; 8] = [0f64; 8]; - vst4q_lane_f64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdot_laneq_s32() { - let a: i32x2 = i32x2::new(1000, -4200); - let b: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let c: i8x16 = i8x16::new(4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11); - let e: i32x2 = i32x2::new(-3420, -10140); - let r: i32x2 = transmute(vusdot_laneq_s32::<3>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdotq_laneq_s32() { - let a: i32x4 = i32x4::new(1000, -4200, -1000, 2000); - let b: u8x16 = u8x16::new(100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250); - let c: i8x16 = i8x16::new(4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11); - let e: i32x4 = i32x4::new(-3420, -10140, -8460, -6980); - let r: i32x4 = transmute(vusdotq_laneq_s32::<3>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vsudot_laneq_s32() { - let a: i32x2 = i32x2::new(-2000, 4200); - let b: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let c: u8x16 = u8x16::new(100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250); - let e: i32x2 = i32x2::new(300, 2740); - let r: i32x2 = transmute(vsudot_laneq_s32::<3>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vsudotq_laneq_s32() { - let a: i32x4 = i32x4::new(-2000, 4200, -1000, 2000); - let b: i8x16 = i8x16::new(4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11); - let c: u8x16 = u8x16::new(100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250); - let e: i32x4 = i32x4::new(300, 2740, -6220, -6980); - let r: i32x4 = transmute(vsudotq_laneq_s32::<3>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_f64() { - let a: f64 = 1.0; - let b: f64 = 2.0; - let e: f64 = 2.0; - let r: f64 = transmute(vmul_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(2.0, 3.0); - let e: f64x2 = f64x2::new(2.0, 6.0); - let r: f64x2 = transmute(vmulq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: f64 = 2.; - let r: f64 = transmute(vmul_n_f64(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64 = 2.; - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulq_n_f64(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: f64 = 2.; - let r: f64 = transmute(vmul_lane_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(2., 0.); - let e: f64 = 2.; - let r: f64 = transmute(vmul_laneq_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64 = 2.; - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulq_lane_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64x2 = f64x2::new(2., 0.); - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulq_laneq_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmuls_lane_f32() { - let a: f32 = 1.; - let b: f32x2 = f32x2::new(2., 0.); - let e: f32 = 2.; - let r: f32 = vmuls_lane_f32::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmuls_laneq_f32() { - let a: f32 = 1.; - let b: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32 = 2.; - let r: f32 = vmuls_laneq_f32::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmuld_lane_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: f64 = 2.; - let r: f64 = vmuld_lane_f64::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmuld_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(2., 0.); - let e: f64 = 2.; - let r: f64 = vmuld_laneq_f64::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_s8() { - let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: i16x8 = i16x8::new(9, 20, 11, 24, 13, 28, 15, 32); - let r: i16x8 = transmute(vmull_high_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_s16() { - let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i32x4 = i32x4::new(9, 20, 11, 24); - let r: i32x4 = transmute(vmull_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_s32() { - let a: i32x4 = i32x4::new(1, 2, 9, 10); - let b: i32x4 = i32x4::new(1, 2, 1, 2); - let e: i64x2 = i64x2::new(9, 20); - let r: i64x2 = transmute(vmull_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_u8() { - let a: u8x16 = u8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: u16x8 = u16x8::new(9, 20, 11, 24, 13, 28, 15, 32); - let r: u16x8 = transmute(vmull_high_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_u16() { - let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u32x4 = u32x4::new(9, 20, 11, 24); - let r: u32x4 = transmute(vmull_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_u32() { - let a: u32x4 = u32x4::new(1, 2, 9, 10); - let b: u32x4 = u32x4::new(1, 2, 1, 2); - let e: u64x2 = u64x2::new(9, 20); - let r: u64x2 = transmute(vmull_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vmull_p64() { - let a: p64 = 15; - let b: p64 = 3; - let e: p128 = 17; - let r: p128 = vmull_p64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_p8() { - let a: i8x16 = i8x16::new(1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3); - let e: i16x8 = i16x8::new(9, 30, 11, 20, 13, 18, 15, 48); - let r: i16x8 = transmute(vmull_high_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vmull_high_p64() { - let a: i64x2 = i64x2::new(1, 15); - let b: i64x2 = i64x2::new(1, 3); - let e: p128 = 17; - let r: p128 = vmull_high_p64(transmute(a), transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_n_s16() { - let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: i16 = 2; - let e: i32x4 = i32x4::new(18, 20, 22, 24); - let r: i32x4 = transmute(vmull_high_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_n_s32() { - let a: i32x4 = i32x4::new(1, 2, 9, 10); - let b: i32 = 2; - let e: i64x2 = i64x2::new(18, 20); - let r: i64x2 = transmute(vmull_high_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_n_u16() { - let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: u16 = 2; - let e: u32x4 = u32x4::new(18, 20, 22, 24); - let r: u32x4 = transmute(vmull_high_n_u16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_n_u32() { - let a: u32x4 = u32x4::new(1, 2, 9, 10); - let b: u32 = 2; - let e: u64x2 = u64x2::new(18, 20); - let r: u64x2 = transmute(vmull_high_n_u32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_lane_s16() { - let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(18, 20, 22, 24); - let r: i32x4 = transmute(vmull_high_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_laneq_s16() { - let a: i16x8 = i16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(18, 20, 22, 24); - let r: i32x4 = transmute(vmull_high_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_lane_s32() { - let a: i32x4 = i32x4::new(1, 2, 9, 10); - let b: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(18, 20); - let r: i64x2 = transmute(vmull_high_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_laneq_s32() { - let a: i32x4 = i32x4::new(1, 2, 9, 10); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(18, 20); - let r: i64x2 = transmute(vmull_high_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_lane_u16() { - let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u32x4 = u32x4::new(18, 20, 22, 24); - let r: u32x4 = transmute(vmull_high_lane_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_laneq_u16() { - let a: u16x8 = u16x8::new(1, 2, 9, 10, 9, 10, 11, 12); - let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(18, 20, 22, 24); - let r: u32x4 = transmute(vmull_high_laneq_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_lane_u32() { - let a: u32x4 = u32x4::new(1, 2, 9, 10); - let b: u32x2 = u32x2::new(0, 2); - let e: u64x2 = u64x2::new(18, 20); - let r: u64x2 = transmute(vmull_high_lane_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_high_laneq_u32() { - let a: u32x4 = u32x4::new(1, 2, 9, 10); - let b: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u64x2 = u64x2::new(18, 20); - let r: u64x2 = transmute(vmull_high_laneq_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(2., 2.); - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmulx_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulxq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: f64 = 2.; - let r: f64 = transmute(vmulx_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64x2 = f64x2::new(2., 2.); - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulxq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_lane_f64() { - let a: f64 = 1.; - let b: f64 = 2.; - let e: f64 = 2.; - let r: f64 = transmute(vmulx_lane_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_laneq_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(2., 0.); - let e: f64 = 2.; - let r: f64 = transmute(vmulx_laneq_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_lane_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(2., 0.); - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmulx_lane_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulx_laneq_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmulx_laneq_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_lane_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x2 = f32x2::new(2., 0.); - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulxq_lane_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_laneq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulxq_laneq_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_lane_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64 = 2.; - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulxq_lane_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxq_laneq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64x2 = f64x2::new(2., 0.); - let e: f64x2 = f64x2::new(2., 4.); - let r: f64x2 = transmute(vmulxq_laneq_f64::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxs_f32() { - let a: f32 = 2.; - let b: f32 = 3.; - let e: f32 = 6.; - let r: f32 = vmulxs_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxd_f64() { - let a: f64 = 2.; - let b: f64 = 3.; - let e: f64 = 6.; - let r: f64 = vmulxd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxs_lane_f32() { - let a: f32 = 2.; - let b: f32x2 = f32x2::new(3., 0.); - let e: f32 = 6.; - let r: f32 = vmulxs_lane_f32::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxs_laneq_f32() { - let a: f32 = 2.; - let b: f32x4 = f32x4::new(3., 0., 0., 0.); - let e: f32 = 6.; - let r: f32 = vmulxs_laneq_f32::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxd_lane_f64() { - let a: f64 = 2.; - let b: f64 = 3.; - let e: f64 = 6.; - let r: f64 = vmulxd_lane_f64::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulxd_laneq_f64() { - let a: f64 = 2.; - let b: f64x2 = f64x2::new(3., 0.); - let e: f64 = 6.; - let r: f64 = vmulxd_laneq_f64::<0>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_f64() { - let a: f64 = 8.0; - let b: f64 = 6.0; - let c: f64 = 2.0; - let e: f64 = 20.0; - let r: f64 = transmute(vfma_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_f64() { - let a: f64x2 = f64x2::new(8.0, 18.0); - let b: f64x2 = f64x2::new(6.0, 4.0); - let c: f64x2 = f64x2::new(2.0, 3.0); - let e: f64x2 = f64x2::new(20.0, 30.0); - let r: f64x2 = transmute(vfmaq_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_n_f64() { - let a: f64 = 2.0; - let b: f64 = 6.0; - let c: f64 = 8.0; - let e: f64 = 50.0; - let r: f64 = transmute(vfma_n_f64(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_n_f64() { - let a: f64x2 = f64x2::new(2.0, 3.0); - let b: f64x2 = f64x2::new(6.0, 4.0); - let c: f64 = 8.0; - let e: f64x2 = f64x2::new(50.0, 35.0); - let r: f64x2 = transmute(vfmaq_n_f64(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_lane_f32() { - let a: f32x2 = f32x2::new(2., 3.); - let b: f32x2 = f32x2::new(6., 4.); - let c: f32x2 = f32x2::new(2., 0.); - let e: f32x2 = f32x2::new(14., 11.); - let r: f32x2 = transmute(vfma_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_laneq_f32() { - let a: f32x2 = f32x2::new(2., 3.); - let b: f32x2 = f32x2::new(6., 4.); - let c: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x2 = f32x2::new(14., 11.); - let r: f32x2 = transmute(vfma_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_lane_f32() { - let a: f32x4 = f32x4::new(2., 3., 4., 5.); - let b: f32x4 = f32x4::new(6., 4., 7., 8.); - let c: f32x2 = f32x2::new(2., 0.); - let e: f32x4 = f32x4::new(14., 11., 18., 21.); - let r: f32x4 = transmute(vfmaq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_laneq_f32() { - let a: f32x4 = f32x4::new(2., 3., 4., 5.); - let b: f32x4 = f32x4::new(6., 4., 7., 8.); - let c: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x4 = f32x4::new(14., 11., 18., 21.); - let r: f32x4 = transmute(vfmaq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_lane_f64() { - let a: f64 = 2.; - let b: f64 = 6.; - let c: f64 = 2.; - let e: f64 = 14.; - let r: f64 = transmute(vfma_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfma_laneq_f64() { - let a: f64 = 2.; - let b: f64 = 6.; - let c: f64x2 = f64x2::new(2., 0.); - let e: f64 = 14.; - let r: f64 = transmute(vfma_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_lane_f64() { - let a: f64x2 = f64x2::new(2., 3.); - let b: f64x2 = f64x2::new(6., 4.); - let c: f64 = 2.; - let e: f64x2 = f64x2::new(14., 11.); - let r: f64x2 = transmute(vfmaq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmaq_laneq_f64() { - let a: f64x2 = f64x2::new(2., 3.); - let b: f64x2 = f64x2::new(6., 4.); - let c: f64x2 = f64x2::new(2., 0.); - let e: f64x2 = f64x2::new(14., 11.); - let r: f64x2 = transmute(vfmaq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmas_lane_f32() { - let a: f32 = 2.; - let b: f32 = 6.; - let c: f32x2 = f32x2::new(3., 0.); - let e: f32 = 20.; - let r: f32 = vfmas_lane_f32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmas_laneq_f32() { - let a: f32 = 2.; - let b: f32 = 6.; - let c: f32x4 = f32x4::new(3., 0., 0., 0.); - let e: f32 = 20.; - let r: f32 = vfmas_laneq_f32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmad_lane_f64() { - let a: f64 = 2.; - let b: f64 = 6.; - let c: f64 = 3.; - let e: f64 = 20.; - let r: f64 = vfmad_lane_f64::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmad_laneq_f64() { - let a: f64 = 2.; - let b: f64 = 6.; - let c: f64x2 = f64x2::new(3., 0.); - let e: f64 = 20.; - let r: f64 = vfmad_laneq_f64::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_f64() { - let a: f64 = 20.0; - let b: f64 = 6.0; - let c: f64 = 2.0; - let e: f64 = 8.0; - let r: f64 = transmute(vfms_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_f64() { - let a: f64x2 = f64x2::new(20.0, 30.0); - let b: f64x2 = f64x2::new(6.0, 4.0); - let c: f64x2 = f64x2::new(2.0, 3.0); - let e: f64x2 = f64x2::new(8.0, 18.0); - let r: f64x2 = transmute(vfmsq_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_n_f64() { - let a: f64 = 50.0; - let b: f64 = 6.0; - let c: f64 = 8.0; - let e: f64 = 2.0; - let r: f64 = transmute(vfms_n_f64(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_n_f64() { - let a: f64x2 = f64x2::new(50.0, 35.0); - let b: f64x2 = f64x2::new(6.0, 4.0); - let c: f64 = 8.0; - let e: f64x2 = f64x2::new(2.0, 3.0); - let r: f64x2 = transmute(vfmsq_n_f64(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_lane_f32() { - let a: f32x2 = f32x2::new(14., 11.); - let b: f32x2 = f32x2::new(6., 4.); - let c: f32x2 = f32x2::new(2., 0.); - let e: f32x2 = f32x2::new(2., 3.); - let r: f32x2 = transmute(vfms_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_laneq_f32() { - let a: f32x2 = f32x2::new(14., 11.); - let b: f32x2 = f32x2::new(6., 4.); - let c: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x2 = f32x2::new(2., 3.); - let r: f32x2 = transmute(vfms_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_lane_f32() { - let a: f32x4 = f32x4::new(14., 11., 18., 21.); - let b: f32x4 = f32x4::new(6., 4., 7., 8.); - let c: f32x2 = f32x2::new(2., 0.); - let e: f32x4 = f32x4::new(2., 3., 4., 5.); - let r: f32x4 = transmute(vfmsq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_laneq_f32() { - let a: f32x4 = f32x4::new(14., 11., 18., 21.); - let b: f32x4 = f32x4::new(6., 4., 7., 8.); - let c: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x4 = f32x4::new(2., 3., 4., 5.); - let r: f32x4 = transmute(vfmsq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_lane_f64() { - let a: f64 = 14.; - let b: f64 = 6.; - let c: f64 = 2.; - let e: f64 = 2.; - let r: f64 = transmute(vfms_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfms_laneq_f64() { - let a: f64 = 14.; - let b: f64 = 6.; - let c: f64x2 = f64x2::new(2., 0.); - let e: f64 = 2.; - let r: f64 = transmute(vfms_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_lane_f64() { - let a: f64x2 = f64x2::new(14., 11.); - let b: f64x2 = f64x2::new(6., 4.); - let c: f64 = 2.; - let e: f64x2 = f64x2::new(2., 3.); - let r: f64x2 = transmute(vfmsq_lane_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsq_laneq_f64() { - let a: f64x2 = f64x2::new(14., 11.); - let b: f64x2 = f64x2::new(6., 4.); - let c: f64x2 = f64x2::new(2., 0.); - let e: f64x2 = f64x2::new(2., 3.); - let r: f64x2 = transmute(vfmsq_laneq_f64::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmss_lane_f32() { - let a: f32 = 14.; - let b: f32 = 6.; - let c: f32x2 = f32x2::new(2., 0.); - let e: f32 = 2.; - let r: f32 = vfmss_lane_f32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmss_laneq_f32() { - let a: f32 = 14.; - let b: f32 = 6.; - let c: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32 = 2.; - let r: f32 = vfmss_laneq_f32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsd_lane_f64() { - let a: f64 = 14.; - let b: f64 = 6.; - let c: f64 = 2.; - let e: f64 = 2.; - let r: f64 = vfmsd_lane_f64::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vfmsd_laneq_f64() { - let a: f64 = 14.; - let b: f64 = 6.; - let c: f64x2 = f64x2::new(2., 0.); - let e: f64 = 2.; - let r: f64 = vfmsd_laneq_f64::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdiv_f32() { - let a: f32x2 = f32x2::new(2.0, 6.0); - let b: f32x2 = f32x2::new(1.0, 2.0); - let e: f32x2 = f32x2::new(2.0, 3.0); - let r: f32x2 = transmute(vdiv_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdivq_f32() { - let a: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0); - let b: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0); - let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let r: f32x4 = transmute(vdivq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdiv_f64() { - let a: f64 = 2.0; - let b: f64 = 1.0; - let e: f64 = 2.0; - let r: f64 = transmute(vdiv_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdivq_f64() { - let a: f64x2 = f64x2::new(2.0, 6.0); - let b: f64x2 = f64x2::new(1.0, 2.0); - let e: f64x2 = f64x2::new(2.0, 3.0); - let r: f64x2 = transmute(vdivq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_f64() { - let a: f64 = 1.0; - let b: f64 = 1.0; - let e: f64 = 0.0; - let r: f64 = transmute(vsub_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_f64() { - let a: f64x2 = f64x2::new(1.0, 4.0); - let b: f64x2 = f64x2::new(1.0, 2.0); - let e: f64x2 = f64x2::new(0.0, 2.0); - let r: f64x2 = transmute(vsubq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubd_s64() { - let a: i64 = 3; - let b: i64 = 2; - let e: i64 = 1; - let r: i64 = vsubd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubd_u64() { - let a: u64 = 3; - let b: u64 = 2; - let e: u64 = 1; - let r: u64 = vsubd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddd_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: i64 = 3; - let r: i64 = vaddd_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddd_u64() { - let a: u64 = 1; - let b: u64 = 2; - let e: u64 = 3; - let r: u64 = vaddd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddv_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 3.; - let r: f32 = vaddv_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddvq_f32() { - let a: f32x4 = f32x4::new(1., 2., 0., 0.); - let e: f32 = 3.; - let r: f32 = vaddvq_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddvq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 3.; - let r: f64 = vaddvq_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlv_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i32 = 10; - let r: i32 = vaddlv_s16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlvq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i32 = 36; - let r: i32 = vaddlvq_s16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlv_s32() { - let a: i32x2 = i32x2::new(1, 2); - let e: i64 = 3; - let r: i64 = vaddlv_s32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlvq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i64 = 10; - let r: i64 = vaddlvq_s32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlv_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u32 = 10; - let r: u32 = vaddlv_u16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlvq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u32 = 36; - let r: u32 = vaddlvq_u16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlv_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: u64 = 3; - let r: u64 = vaddlv_u32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddlvq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u64 = 10; - let r: u64 = vaddlvq_u32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_s8() { - let a: i16x8 = i16x8::new(8, 9, 10, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vsubw_high_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_s16() { - let a: i32x4 = i32x4::new(8, 9, 10, 11); - let b: i16x8 = i16x8::new(0, 1, 2, 3, 8, 9, 10, 11); - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vsubw_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_s32() { - let a: i64x2 = i64x2::new(8, 9); - let b: i32x4 = i32x4::new(6, 7, 8, 9); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vsubw_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_u8() { - let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); - let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vsubw_high_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_u16() { - let a: u32x4 = u32x4::new(8, 9, 10, 11); - let b: u16x8 = u16x8::new(0, 1, 2, 3, 8, 9, 10, 11); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vsubw_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_high_u32() { - let a: u64x2 = u64x2::new(8, 9); - let b: u32x4 = u32x4::new(6, 7, 8, 9); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vsubw_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vsubl_high_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_s16() { - let a: i16x8 = i16x8::new(8, 9, 10, 11, 12, 13, 14, 15); - let b: i16x8 = i16x8::new(6, 6, 6, 6, 8, 8, 8, 8); - let e: i32x4 = i32x4::new(4, 5, 6, 7); - let r: i32x4 = transmute(vsubl_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_s32() { - let a: i32x4 = i32x4::new(12, 13, 14, 15); - let b: i32x4 = i32x4::new(6, 6, 8, 8); - let e: i64x2 = i64x2::new(6, 7); - let r: i64x2 = transmute(vsubl_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vsubl_high_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_u16() { - let a: u16x8 = u16x8::new(8, 9, 10, 11, 12, 13, 14, 15); - let b: u16x8 = u16x8::new(6, 6, 6, 6, 8, 8, 8, 8); - let e: u32x4 = u32x4::new(4, 5, 6, 7); - let r: u32x4 = transmute(vsubl_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_high_u32() { - let a: u32x4 = u32x4::new(12, 13, 14, 15); - let b: u32x4 = u32x4::new(6, 6, 8, 8); - let e: u64x2 = u64x2::new(6, 7); - let r: u64x2 = transmute(vsubl_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_s8() { - let a: i8x16 = i8x16::new(1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0); - let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let c: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let e: i8x16 = i8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14); - let r: i8x16 = transmute(vbcaxq_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_s16() { - let a: i16x8 = i16x8::new(1, 0, 1, 0, 1, 0, 1, 0); - let b: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let c: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let e: i16x8 = i16x8::new(1, 0, 3, 2, 5, 4, 7, 6); - let r: i16x8 = transmute(vbcaxq_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_s32() { - let a: i32x4 = i32x4::new(1, 0, 1, 0); - let b: i32x4 = i32x4::new(0, 1, 2, 3); - let c: i32x4 = i32x4::new(1, 1, 1, 1); - let e: i32x4 = i32x4::new(1, 0, 3, 2); - let r: i32x4 = transmute(vbcaxq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_s64() { - let a: i64x2 = i64x2::new(1, 0); - let b: i64x2 = i64x2::new(0, 1); - let c: i64x2 = i64x2::new(1, 1); - let e: i64x2 = i64x2::new(1, 0); - let r: i64x2 = transmute(vbcaxq_s64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_u8() { - let a: u8x16 = u8x16::new(1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0); - let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let c: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let e: u8x16 = u8x16::new(1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14); - let r: u8x16 = transmute(vbcaxq_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_u16() { - let a: u16x8 = u16x8::new(1, 0, 1, 0, 1, 0, 1, 0); - let b: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let c: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let e: u16x8 = u16x8::new(1, 0, 3, 2, 5, 4, 7, 6); - let r: u16x8 = transmute(vbcaxq_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_u32() { - let a: u32x4 = u32x4::new(1, 0, 1, 0); - let b: u32x4 = u32x4::new(0, 1, 2, 3); - let c: u32x4 = u32x4::new(1, 1, 1, 1); - let e: u32x4 = u32x4::new(1, 0, 3, 2); - let r: u32x4 = transmute(vbcaxq_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vbcaxq_u64() { - let a: u64x2 = u64x2::new(1, 0); - let b: u64x2 = u64x2::new(0, 1); - let c: u64x2 = u64x2::new(1, 1); - let e: u64x2 = u64x2::new(1, 0); - let r: u64x2 = transmute(vbcaxq_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcadd_rot270_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let e: f32x2 = f32x2::new(2., 0.); - let r: f32x2 = transmute(vcadd_rot270_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcaddq_rot270_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let e: f32x4 = f32x4::new(2., 0., 2., 0.); - let r: f32x4 = transmute(vcaddq_rot270_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcaddq_rot270_f64() { - let a: f64x2 = f64x2::new(1., -1.); - let b: f64x2 = f64x2::new(-1., 1.); - let e: f64x2 = f64x2::new(2., 0.); - let r: f64x2 = transmute(vcaddq_rot270_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcadd_rot90_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let e: f32x2 = f32x2::new(0., -2.); - let r: f32x2 = transmute(vcadd_rot90_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcaddq_rot90_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let e: f32x4 = f32x4::new(0., -2., 0., -2.); - let r: f32x4 = transmute(vcaddq_rot90_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcaddq_rot90_f64() { - let a: f64x2 = f64x2::new(1., -1.); - let b: f64x2 = f64x2::new(-1., 1.); - let e: f64x2 = f64x2::new(0., -2.); - let r: f64x2 = transmute(vcaddq_rot90_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(0., -2.); - let r: f32x2 = transmute(vcmla_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x4 = f32x4::new(0., -2., 2., 0.); - let r: f32x4 = transmute(vcmlaq_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_f64() { - let a: f64x2 = f64x2::new(1., -1.); - let b: f64x2 = f64x2::new(-1., 1.); - let c: f64x2 = f64x2::new(1., 1.); - let e: f64x2 = f64x2::new(0., -2.); - let r: f64x2 = transmute(vcmlaq_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot90_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let b: f32x2 = f32x2::new(1., -1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(2., 0.); - let r: f32x2 = transmute(vcmla_rot90_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot90_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 1.); - let b: f32x4 = f32x4::new(1., -1., 1., -1.); - let c: f32x4 = f32x4::new(1., 1., 1., 1.); - let e: f32x4 = f32x4::new(2., 0., 2., 0.); - let r: f32x4 = transmute(vcmlaq_rot90_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot90_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let b: f64x2 = f64x2::new(1., -1.); - let c: f64x2 = f64x2::new(1., 1.); - let e: f64x2 = f64x2::new(2., 0.); - let r: f64x2 = transmute(vcmlaq_rot90_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot180_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let b: f32x2 = f32x2::new(1., -1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vcmla_rot180_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot180_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 1.); - let b: f32x4 = f32x4::new(1., -1., 1., -1.); - let c: f32x4 = f32x4::new(1., 1., 1., 1.); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vcmlaq_rot180_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot180_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let b: f64x2 = f64x2::new(1., -1.); - let c: f64x2 = f64x2::new(1., 1.); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vcmlaq_rot180_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot270_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let b: f32x2 = f32x2::new(1., -1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(0., 2.); - let r: f32x2 = transmute(vcmla_rot270_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot270_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 1.); - let b: f32x4 = f32x4::new(1., -1., 1., -1.); - let c: f32x4 = f32x4::new(1., 1., 1., 1.); - let e: f32x4 = f32x4::new(0., 2., 0., 2.); - let r: f32x4 = transmute(vcmlaq_rot270_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot270_f64() { - let a: f64x2 = f64x2::new(1., 1.); - let b: f64x2 = f64x2::new(1., -1.); - let c: f64x2 = f64x2::new(1., 1.); - let e: f64x2 = f64x2::new(0., 2.); - let r: f64x2 = transmute(vcmlaq_rot270_f64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_lane_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(0., -2.); - let r: f32x2 = transmute(vcmla_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_laneq_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x2 = f32x2::new(0., -2.); - let r: f32x2 = transmute(vcmla_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_lane_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x4 = f32x4::new(0., -2., 0., -2.); - let r: f32x4 = transmute(vcmlaq_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_laneq_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x4 = f32x4::new(0., -2., 0., -2.); - let r: f32x4 = transmute(vcmlaq_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot90_lane_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vcmla_rot90_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot90_laneq_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vcmla_rot90_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot90_lane_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vcmlaq_rot90_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot90_laneq_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vcmlaq_rot90_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot180_lane_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(2., 0.); - let r: f32x2 = transmute(vcmla_rot180_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot180_laneq_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x2 = f32x2::new(2., 0.); - let r: f32x2 = transmute(vcmla_rot180_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot180_lane_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x4 = f32x4::new(2., 0., 2., 0.); - let r: f32x4 = transmute(vcmlaq_rot180_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot180_laneq_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x4 = f32x4::new(2., 0., 2., 0.); - let r: f32x4 = transmute(vcmlaq_rot180_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot270_lane_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(2., -2.); - let r: f32x2 = transmute(vcmla_rot270_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmla_rot270_laneq_f32() { - let a: f32x2 = f32x2::new(1., -1.); - let b: f32x2 = f32x2::new(-1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x2 = f32x2::new(2., -2.); - let r: f32x2 = transmute(vcmla_rot270_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot270_lane_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x2 = f32x2::new(1., 1.); - let e: f32x4 = f32x4::new(2., -2., 2., -2.); - let r: f32x4 = transmute(vcmlaq_rot270_lane_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,fcma")] - unsafe fn test_vcmlaq_rot270_laneq_f32() { - let a: f32x4 = f32x4::new(1., -1., 1., -1.); - let b: f32x4 = f32x4::new(-1., 1., -1., 1.); - let c: f32x4 = f32x4::new(1., 1., -1., -1.); - let e: f32x4 = f32x4::new(2., -2., 2., -2.); - let r: f32x4 = transmute(vcmlaq_rot270_laneq_f32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_laneq_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i8x8 = i8x8::new(-1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x2 = i32x2::new(29, 72); - let r: i32x2 = transmute(vdot_laneq_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 2, 1, 2); - let b: i8x16 = i8x16::new(-1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(29, 72, 31, 72); - let r: i32x4 = transmute(vdotq_laneq_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_laneq_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u8x8 = u8x8::new(255, 2, 3, 4, 5, 6, 7, 8); - let c: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x2 = u32x2::new(285, 72); - let r: u32x2 = transmute(vdot_laneq_u32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_laneq_u32() { - let a: u32x4 = u32x4::new(1, 2, 1, 2); - let b: u8x16 = u8x16::new(255, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x4 = u32x4::new(285, 72, 31, 72); - let r: u32x4 = transmute(vdotq_laneq_u32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_f64() { - let a: f64 = 1.0; - let b: f64 = 0.0; - let e: f64 = 1.0; - let r: f64 = transmute(vmax_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_f64() { - let a: f64x2 = f64x2::new(1.0, -2.0); - let b: f64x2 = f64x2::new(0.0, 3.0); - let e: f64x2 = f64x2::new(1.0, 3.0); - let r: f64x2 = transmute(vmaxq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxnm_f64() { - let a: f64 = 1.0; - let b: f64 = 8.0; - let e: f64 = 8.0; - let r: f64 = transmute(vmaxnm_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxnmq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(8.0, 16.0); - let e: f64x2 = f64x2::new(8.0, 16.0); - let r: f64x2 = transmute(vmaxnmq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxnmv_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 2.; - let r: f32 = vmaxnmv_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxnmvq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 2.; - let r: f64 = vmaxnmvq_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxnmvq_f32() { - let a: f32x4 = f32x4::new(1., 2., 0., 1.); - let e: f32 = 2.; - let r: f32 = vmaxnmvq_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxnm_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(6.0, -3.0); - let e: f32x2 = f32x2::new(2.0, 6.0); - let r: f32x2 = transmute(vpmaxnm_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxnmq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(6.0, -3.0); - let e: f64x2 = f64x2::new(2.0, 6.0); - let r: f64x2 = transmute(vpmaxnmq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxnmq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); - let e: f32x4 = f32x4::new(2.0, 3.0, 16.0, 6.0); - let r: f32x4 = transmute(vpmaxnmq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxnms_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 2.; - let r: f32 = vpmaxnms_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxnmqd_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 2.; - let r: f64 = vpmaxnmqd_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxs_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 2.; - let r: f32 = vpmaxs_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmaxqd_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 2.; - let r: f64 = vpmaxqd_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_f64() { - let a: f64 = 1.0; - let b: f64 = 0.0; - let e: f64 = 0.0; - let r: f64 = transmute(vmin_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_f64() { - let a: f64x2 = f64x2::new(1.0, -2.0); - let b: f64x2 = f64x2::new(0.0, 3.0); - let e: f64x2 = f64x2::new(0.0, -2.0); - let r: f64x2 = transmute(vminq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminnm_f64() { - let a: f64 = 1.0; - let b: f64 = 8.0; - let e: f64 = 1.0; - let r: f64 = transmute(vminnm_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminnmq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(8.0, 16.0); - let e: f64x2 = f64x2::new(1.0, 2.0); - let r: f64x2 = transmute(vminnmq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminnmv_f32() { - let a: f32x2 = f32x2::new(1., 0.); - let e: f32 = 0.; - let r: f32 = vminnmv_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminnmvq_f64() { - let a: f64x2 = f64x2::new(1., 0.); - let e: f64 = 0.; - let r: f64 = vminnmvq_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminnmvq_f32() { - let a: f32x4 = f32x4::new(1., 0., 2., 3.); - let e: f32 = 0.; - let r: f32 = vminnmvq_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 3, 4, 5, 6, 3, 4, 5, 6, 7, 8, 9, 10); - let e: i16x8 = i16x8::new(3, 4, 5, 6, 7, 8, 9, 10); - let r: i16x8 = transmute(vmovl_high_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 3, 4, 5, 6); - let e: i32x4 = i32x4::new(3, 4, 5, 6); - let r: i32x4 = transmute(vmovl_high_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i64x2 = i64x2::new(3, 4); - let r: i64x2 = transmute(vmovl_high_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 3, 4, 5, 6, 3, 4, 5, 6, 7, 8, 9, 10); - let e: u16x8 = u16x8::new(3, 4, 5, 6, 7, 8, 9, 10); - let r: u16x8 = transmute(vmovl_high_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 3, 4, 5, 6); - let e: u32x4 = u32x4::new(3, 4, 5, 6); - let r: u32x4 = transmute(vmovl_high_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmovl_high_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u64x2 = u64x2::new(3, 4); - let r: u64x2 = transmute(vmovl_high_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpaddq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(3., 4., 5., 6.); - let e: f32x4 = f32x4::new(3., 7., 7., 11.); - let r: f32x4 = transmute(vpaddq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpaddq_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let b: f64x2 = f64x2::new(3., 4.); - let e: f64x2 = f64x2::new(3., 7.); - let r: f64x2 = transmute(vpaddq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpadds_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 3.; - let r: f32 = vpadds_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpaddd_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 3.; - let r: f64 = vpaddd_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminnm_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(6.0, -3.0); - let e: f32x2 = f32x2::new(1.0, -3.0); - let r: f32x2 = transmute(vpminnm_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminnmq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(6.0, -3.0); - let e: f64x2 = f64x2::new(1.0, -3.0); - let r: f64x2 = transmute(vpminnmq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminnmq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); - let e: f32x4 = f32x4::new(1.0, -4.0, 8.0, -1.0); - let r: f32x4 = transmute(vpminnmq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminnms_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 1.; - let r: f32 = vpminnms_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminnmqd_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 1.; - let r: f64 = vpminnmqd_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpmins_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let e: f32 = 1.; - let r: f32 = vpmins_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpminqd_f64() { - let a: f64x2 = f64x2::new(1., 2.); - let e: f64 = 1.; - let r: f64 = vpminqd_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmullh_s16() { - let a: i16 = 2; - let b: i16 = 3; - let e: i32 = 12; - let r: i32 = vqdmullh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulls_s32() { - let a: i32 = 2; - let b: i32 = 3; - let e: i64 = 12; - let r: i64 = vqdmulls_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_s16() { - let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(40, 60, 84, 112); - let r: i32x4 = transmute(vqdmull_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_s32() { - let a: i32x4 = i32x4::new(0, 1, 4, 5); - let b: i32x4 = i32x4::new(1, 2, 5, 6); - let e: i64x2 = i64x2::new(40, 60); - let r: i64x2 = transmute(vqdmull_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_n_s16() { - let a: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); - let b: i16 = 2; - let e: i32x4 = i32x4::new(32, 40, 48, 56); - let r: i32x4 = transmute(vqdmull_high_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_n_s32() { - let a: i32x4 = i32x4::new(0, 2, 8, 10); - let b: i32 = 2; - let e: i64x2 = i64x2::new(32, 40); - let r: i64x2 = transmute(vqdmull_high_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_laneq_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vqdmull_laneq_s16::<4>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_laneq_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 2, 2, 0); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vqdmull_laneq_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmullh_lane_s16() { - let a: i16 = 2; - let b: i16x4 = i16x4::new(0, 2, 2, 0); - let e: i32 = 8; - let r: i32 = vqdmullh_lane_s16::<2>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmullh_laneq_s16() { - let a: i16 = 2; - let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); - let e: i32 = 8; - let r: i32 = vqdmullh_laneq_s16::<4>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulls_lane_s32() { - let a: i32 = 2; - let b: i32x2 = i32x2::new(0, 2); - let e: i64 = 8; - let r: i64 = vqdmulls_lane_s32::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulls_laneq_s32() { - let a: i32 = 2; - let b: i32x4 = i32x4::new(0, 2, 2, 0); - let e: i64 = 8; - let r: i64 = vqdmulls_laneq_s32::<2>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_lane_s16() { - let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let b: i16x4 = i16x4::new(0, 2, 2, 0); - let e: i32x4 = i32x4::new(16, 20, 24, 28); - let r: i32x4 = transmute(vqdmull_high_lane_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_lane_s32() { - let a: i32x4 = i32x4::new(0, 1, 4, 5); - let b: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(16, 20); - let r: i64x2 = transmute(vqdmull_high_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_laneq_s16() { - let a: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); - let e: i32x4 = i32x4::new(16, 20, 24, 28); - let r: i32x4 = transmute(vqdmull_high_laneq_s16::<4>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_high_laneq_s32() { - let a: i32x4 = i32x4::new(0, 1, 4, 5); - let b: i32x4 = i32x4::new(0, 2, 2, 0); - let e: i64x2 = i64x2::new(16, 20); - let r: i64x2 = transmute(vqdmull_high_laneq_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(41, 62, 87, 116); - let r: i32x4 = transmute(vqdmlal_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x4 = i32x4::new(1, 2, 5, 6); - let e: i64x2 = i64x2::new(41, 62); - let r: i64x2 = transmute(vqdmlal_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_n_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); - let c: i16 = 2; - let e: i32x4 = i32x4::new(33, 42, 51, 60); - let r: i32x4 = transmute(vqdmlal_high_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_n_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 2, 8, 10); - let c: i32 = 2; - let e: i64x2 = i64x2::new(33, 42); - let r: i64x2 = transmute(vqdmlal_high_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_laneq_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); - let e: i32x4 = i32x4::new(5, 10, 15, 20); - let r: i32x4 = transmute(vqdmlal_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_laneq_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x4 = i32x4::new(0, 2, 2, 0); - let e: i64x2 = i64x2::new(5, 10); - let r: i64x2 = transmute(vqdmlal_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_lane_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(17, 22, 27, 32); - let r: i32x4 = transmute(vqdmlal_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_laneq_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(17, 22, 27, 32); - let r: i32x4 = transmute(vqdmlal_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_lane_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(17, 22); - let r: i64x2 = transmute(vqdmlal_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_high_laneq_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(17, 22); - let r: i64x2 = transmute(vqdmlal_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlalh_s16() { - let a: i32 = 1; - let b: i16 = 1; - let c: i16 = 2; - let e: i32 = 5; - let r: i32 = vqdmlalh_s16(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlals_s32() { - let a: i64 = 1; - let b: i32 = 1; - let c: i32 = 2; - let e: i64 = 5; - let r: i64 = vqdmlals_s32(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlalh_lane_s16() { - let a: i32 = 1; - let b: i16 = 1; - let c: i16x4 = i16x4::new(2, 1, 1, 1); - let e: i32 = 5; - let r: i32 = vqdmlalh_lane_s16::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlalh_laneq_s16() { - let a: i32 = 1; - let b: i16 = 1; - let c: i16x8 = i16x8::new(2, 1, 1, 1, 1, 1, 1, 1); - let e: i32 = 5; - let r: i32 = vqdmlalh_laneq_s16::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlals_lane_s32() { - let a: i64 = 1; - let b: i32 = 1; - let c: i32x2 = i32x2::new(2, 1); - let e: i64 = 5; - let r: i64 = vqdmlals_lane_s32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlals_laneq_s32() { - let a: i64 = 1; - let b: i32 = 1; - let c: i32x4 = i32x4::new(2, 1, 1, 1); - let e: i64 = 5; - let r: i64 = vqdmlals_laneq_s32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_s16() { - let a: i32x4 = i32x4::new(39, 58, 81, 108); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_s32() { - let a: i64x2 = i64x2::new(39, 58); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x4 = i32x4::new(1, 2, 5, 6); - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_n_s16() { - let a: i32x4 = i32x4::new(31, 38, 45, 52); - let b: i16x8 = i16x8::new(0, 2, 8, 10, 8, 10, 12, 14); - let c: i16 = 2; - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_high_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_n_s32() { - let a: i64x2 = i64x2::new(31, 38); - let b: i32x4 = i32x4::new(0, 2, 8, 10); - let c: i32 = 2; - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_high_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_laneq_s16() { - let a: i32x4 = i32x4::new(3, 6, 9, 12); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x8 = i16x8::new(0, 2, 2, 0, 2, 0, 0, 0); - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_laneq_s16::<2>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_laneq_s32() { - let a: i64x2 = i64x2::new(3, 6); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x4 = i32x4::new(0, 2, 2, 0); - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_lane_s16() { - let a: i32x4 = i32x4::new(15, 18, 21, 24); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_high_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_laneq_s16() { - let a: i32x4 = i32x4::new(15, 18, 21, 24); - let b: i16x8 = i16x8::new(0, 1, 4, 5, 4, 5, 6, 7); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_high_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_lane_s32() { - let a: i64x2 = i64x2::new(15, 18); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_high_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_high_laneq_s32() { - let a: i64x2 = i64x2::new(15, 18); - let b: i32x4 = i32x4::new(0, 1, 4, 5); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_high_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlslh_s16() { - let a: i32 = 10; - let b: i16 = 1; - let c: i16 = 2; - let e: i32 = 6; - let r: i32 = vqdmlslh_s16(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsls_s32() { - let a: i64 = 10; - let b: i32 = 1; - let c: i32 = 2; - let e: i64 = 6; - let r: i64 = vqdmlsls_s32(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlslh_lane_s16() { - let a: i32 = 10; - let b: i16 = 1; - let c: i16x4 = i16x4::new(2, 1, 1, 1); - let e: i32 = 6; - let r: i32 = vqdmlslh_lane_s16::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlslh_laneq_s16() { - let a: i32 = 10; - let b: i16 = 1; - let c: i16x8 = i16x8::new(2, 1, 1, 1, 1, 1, 1, 1); - let e: i32 = 6; - let r: i32 = vqdmlslh_laneq_s16::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsls_lane_s32() { - let a: i64 = 10; - let b: i32 = 1; - let c: i32x2 = i32x2::new(2, 1); - let e: i64 = 6; - let r: i64 = vqdmlsls_lane_s32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsls_laneq_s32() { - let a: i64 = 10; - let b: i32 = 1; - let c: i32x4 = i32x4::new(2, 1, 1, 1); - let e: i64 = 6; - let r: i64 = vqdmlsls_laneq_s32::<0>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhh_s16() { - let a: i16 = 1; - let b: i16 = 2; - let e: i16 = 0; - let r: i16 = vqdmulhh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhs_s32() { - let a: i32 = 1; - let b: i32 = 2; - let e: i32 = 0; - let r: i32 = vqdmulhs_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhh_lane_s16() { - let a: i16 = 2; - let b: i16x4 = i16x4::new(0, 0, 0x7F_FF, 0); - let e: i16 = 1; - let r: i16 = vqdmulhh_lane_s16::<2>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhh_laneq_s16() { - let a: i16 = 2; - let b: i16x8 = i16x8::new(0, 0, 0x7F_FF, 0, 0, 0, 0, 0); - let e: i16 = 1; - let r: i16 = vqdmulhh_laneq_s16::<2>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhs_lane_s32() { - let a: i32 = 2; - let b: i32x2 = i32x2::new(0, 0x7F_FF_FF_FF); - let e: i32 = 1; - let r: i32 = vqdmulhs_lane_s32::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhs_laneq_s32() { - let a: i32 = 2; - let b: i32x4 = i32x4::new(0, 0x7F_FF_FF_FF, 0, 0); - let e: i32 = 1; - let r: i32 = vqdmulhs_laneq_s32::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_lane_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(2, 1, 1, 1); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vqdmulh_lane_s16::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_lane_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(2, 1, 1, 1); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vqdmulhq_lane_s16::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_lane_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(2, 1); - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vqdmulh_lane_s32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_lane_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(2, 1); - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vqdmulhq_lane_s32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovnh_s16() { - let a: i16 = 1; - let e: i8 = 1; - let r: i8 = vqmovnh_s16(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovns_s32() { - let a: i32 = 1; - let e: i16 = 1; - let r: i16 = vqmovns_s32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovnh_u16() { - let a: u16 = 1; - let e: u8 = 1; - let r: u8 = vqmovnh_u16(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovns_u32() { - let a: u32 = 1; - let e: u16 = 1; - let r: u16 = vqmovns_u32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovnd_s64() { - let a: i64 = 1; - let e: i32 = 1; - let r: i32 = vqmovnd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovnd_u64() { - let a: u64 = 1; - let e: u32 = 1; - let r: u32 = vqmovnd_u64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_s16() { - let a: i8x8 = i8x8::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let e: i8x16 = i8x16::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); - let r: i8x16 = transmute(vqmovn_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_s32() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let e: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let r: i16x8 = transmute(vqmovn_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_s64() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let r: i32x4 = transmute(vqmovn_high_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_u16() { - let a: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let b: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vqmovn_high_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_u32() { - let a: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vqmovn_high_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_high_u64() { - let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vqmovn_high_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovunh_s16() { - let a: i16 = 1; - let e: u8 = 1; - let r: u8 = vqmovunh_s16(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovuns_s32() { - let a: i32 = 1; - let e: u16 = 1; - let r: u16 = vqmovuns_s32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovund_s64() { - let a: i64 = 1; - let e: u32 = 1; - let r: u32 = vqmovund_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_high_s16() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let b: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vqmovun_high_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_high_s32() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let b: i32x4 = i32x4::new(-1, -1, -1, -1); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vqmovun_high_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_high_s64() { - let a: u32x2 = u32x2::new(0, 0); - let b: i64x2 = i64x2::new(-1, -1); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vqmovun_high_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhh_s16() { - let a: i16 = 1; - let b: i16 = 2; - let e: i16 = 0; - let r: i16 = vqrdmulhh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhs_s32() { - let a: i32 = 1; - let b: i32 = 2; - let e: i32 = 0; - let r: i32 = vqrdmulhs_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhh_lane_s16() { - let a: i16 = 1; - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16 = 0; - let r: i16 = vqrdmulhh_lane_s16::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhh_laneq_s16() { - let a: i16 = 1; - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16 = 0; - let r: i16 = vqrdmulhh_laneq_s16::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhs_lane_s32() { - let a: i32 = 1; - let b: i32x2 = i32x2::new(0, 2); - let e: i32 = 0; - let r: i32 = vqrdmulhs_lane_s32::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhs_laneq_s32() { - let a: i32 = 1; - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32 = 0; - let r: i32 = vqrdmulhs_laneq_s32::<1>(a, transmute(b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(3, 3, 3, 3); - let r: i16x4 = transmute(vqrdmlah_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let r: i16x8 = transmute(vqrdmlahq_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(3, 3); - let r: i32x2 = transmute(vqrdmlah_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(3, 3, 3, 3); - let r: i32x4 = transmute(vqrdmlahq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahh_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16 = 2; - let e: i16 = 1; - let r: i16 = vqrdmlahh_s16(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahs_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32 = 2; - let e: i32 = 1; - let r: i32 = vqrdmlahs_s32(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_lane_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x4 = i16x4::new(3, 3, 3, 3); - let r: i16x4 = transmute(vqrdmlah_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_laneq_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(3, 3, 3, 3); - let r: i16x4 = transmute(vqrdmlah_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_lane_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x8 = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let r: i16x8 = transmute(vqrdmlahq_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_laneq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let r: i16x8 = transmute(vqrdmlahq_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_lane_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(0, 2); - let e: i32x2 = i32x2::new(3, 3); - let r: i32x2 = transmute(vqrdmlah_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlah_laneq_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x2 = i32x2::new(3, 3); - let r: i32x2 = transmute(vqrdmlah_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_lane_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(0, 2); - let e: i32x4 = i32x4::new(3, 3, 3, 3); - let r: i32x4 = transmute(vqrdmlahq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(3, 3, 3, 3); - let r: i32x4 = transmute(vqrdmlahq_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahh_lane_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16 = 1; - let r: i16 = vqrdmlahh_lane_s16::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahh_laneq_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16 = 1; - let r: i16 = vqrdmlahh_laneq_s16::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahs_lane_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32x2 = i32x2::new(0, 2); - let e: i32 = 1; - let r: i32 = vqrdmlahs_lane_s32::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlahs_laneq_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32 = 1; - let r: i32 = vqrdmlahs_laneq_s32::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(-1, -1, -1, -1); - let r: i16x4 = transmute(vqrdmlsh_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); - let r: i16x8 = transmute(vqrdmlshq_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(-1, -1); - let r: i32x2 = transmute(vqrdmlsh_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(-1, -1, -1, -1); - let r: i32x4 = transmute(vqrdmlshq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshh_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16 = 2; - let e: i16 = 1; - let r: i16 = vqrdmlshh_s16(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshs_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32 = 2; - let e: i32 = 1; - let r: i32 = vqrdmlshs_s32(a, b, c); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_lane_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x4 = i16x4::new(-1, -1, -1, -1); - let r: i16x4 = transmute(vqrdmlsh_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_laneq_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(-1, -1, -1, -1); - let r: i16x4 = transmute(vqrdmlsh_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_lane_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); - let r: i16x8 = transmute(vqrdmlshq_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_laneq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); - let r: i16x8 = transmute(vqrdmlshq_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_lane_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(0, 2); - let e: i32x2 = i32x2::new(-1, -1); - let r: i32x2 = transmute(vqrdmlsh_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlsh_laneq_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x2 = i32x2::new(-1, -1); - let r: i32x2 = transmute(vqrdmlsh_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_lane_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x2 = i32x2::new(0, 2); - let e: i32x4 = i32x4::new(-1, -1, -1, -1); - let r: i32x4 = transmute(vqrdmlshq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(-1, -1, -1, -1); - let r: i32x4 = transmute(vqrdmlshq_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshh_lane_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16 = 1; - let r: i16 = vqrdmlshh_lane_s16::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshh_laneq_s16() { - let a: i16 = 1; - let b: i16 = 1; - let c: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16 = 1; - let r: i16 = vqrdmlshh_laneq_s16::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshs_lane_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32x2 = i32x2::new(0, 2); - let e: i32 = 1; - let r: i32 = vqrdmlshs_lane_s32::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "rdm")] - unsafe fn test_vqrdmlshs_laneq_s32() { - let a: i32 = 1; - let b: i32 = 1; - let c: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32 = 1; - let r: i32 = vqrdmlshs_laneq_s32::<1>(a, b, transmute(c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshls_s32() { - let a: i32 = 2; - let b: i32 = 2; - let e: i32 = 8; - let r: i32 = vqrshls_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshld_s64() { - let a: i64 = 2; - let b: i64 = 2; - let e: i64 = 8; - let r: i64 = vqrshld_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlb_s8() { - let a: i8 = 1; - let b: i8 = 2; - let e: i8 = 4; - let r: i8 = vqrshlb_s8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlh_s16() { - let a: i16 = 1; - let b: i16 = 2; - let e: i16 = 4; - let r: i16 = vqrshlh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshls_u32() { - let a: u32 = 2; - let b: i32 = 2; - let e: u32 = 8; - let r: u32 = vqrshls_u32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshld_u64() { - let a: u64 = 2; - let b: i64 = 2; - let e: u64 = 8; - let r: u64 = vqrshld_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlb_u8() { - let a: u8 = 1; - let b: i8 = 2; - let e: u8 = 4; - let r: u8 = vqrshlb_u8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlh_u16() { - let a: u16 = 1; - let b: i16 = 2; - let e: u16 = 4; - let r: u16 = vqrshlh_u16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrnh_n_s16() { - let a: i16 = 4; - let e: i8 = 1; - let r: i8 = vqrshrnh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrns_n_s32() { - let a: i32 = 4; - let e: i16 = 1; - let r: i16 = vqrshrns_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrnd_n_s64() { - let a: i64 = 4; - let e: i32 = 1; - let r: i32 = vqrshrnd_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_s16() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); - let r: i8x16 = transmute(vqrshrn_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_s32() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(8, 12, 24, 28); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let r: i16x8 = transmute(vqrshrn_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_s64() { - let a: i32x2 = i32x2::new(0, 1); - let b: i64x2 = i64x2::new(8, 12); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vqrshrn_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrnh_n_u16() { - let a: u16 = 4; - let e: u8 = 1; - let r: u8 = vqrshrnh_n_u16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrns_n_u32() { - let a: u32 = 4; - let e: u16 = 1; - let r: u16 = vqrshrns_n_u32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrnd_n_u64() { - let a: u64 = 4; - let e: u32 = 1; - let r: u32 = vqrshrnd_n_u64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_u16() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let b: u16x8 = u16x8::new(8, 12, 24, 28, 48, 52, 56, 60); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); - let r: u8x16 = transmute(vqrshrn_high_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_u32() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(8, 12, 24, 28); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let r: u16x8 = transmute(vqrshrn_high_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_high_n_u64() { - let a: u32x2 = u32x2::new(0, 1); - let b: u64x2 = u64x2::new(8, 12); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vqrshrn_high_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrunh_n_s16() { - let a: i16 = 4; - let e: u8 = 1; - let r: u8 = vqrshrunh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshruns_n_s32() { - let a: i32 = 4; - let e: u16 = 1; - let r: u16 = vqrshruns_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrund_n_s64() { - let a: i64 = 4; - let e: u32 = 1; - let r: u32 = vqrshrund_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_high_n_s16() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let b: i16x8 = i16x8::new(8, 12, 24, 28, 48, 52, 56, 60); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15); - let r: u8x16 = transmute(vqrshrun_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_high_n_s32() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(8, 12, 24, 28); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 2, 3, 6, 7); - let r: u16x8 = transmute(vqrshrun_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_high_n_s64() { - let a: u32x2 = u32x2::new(0, 1); - let b: i64x2 = i64x2::new(8, 12); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vqrshrun_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshld_s64() { - let a: i64 = 0; - let b: i64 = 2; - let e: i64 = 0; - let r: i64 = vqshld_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlb_s8() { - let a: i8 = 1; - let b: i8 = 2; - let e: i8 = 4; - let r: i8 = vqshlb_s8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlh_s16() { - let a: i16 = 1; - let b: i16 = 2; - let e: i16 = 4; - let r: i16 = vqshlh_s16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshls_s32() { - let a: i32 = 1; - let b: i32 = 2; - let e: i32 = 4; - let r: i32 = vqshls_s32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshld_u64() { - let a: u64 = 0; - let b: i64 = 2; - let e: u64 = 0; - let r: u64 = vqshld_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlb_u8() { - let a: u8 = 1; - let b: i8 = 2; - let e: u8 = 4; - let r: u8 = vqshlb_u8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlh_u16() { - let a: u16 = 1; - let b: i16 = 2; - let e: u16 = 4; - let r: u16 = vqshlh_u16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshls_u32() { - let a: u32 = 1; - let b: i32 = 2; - let e: u32 = 4; - let r: u32 = vqshls_u32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlb_n_s8() { - let a: i8 = 1; - let e: i8 = 4; - let r: i8 = vqshlb_n_s8::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlh_n_s16() { - let a: i16 = 1; - let e: i16 = 4; - let r: i16 = vqshlh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshls_n_s32() { - let a: i32 = 1; - let e: i32 = 4; - let r: i32 = vqshls_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshld_n_s64() { - let a: i64 = 1; - let e: i64 = 4; - let r: i64 = vqshld_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlb_n_u8() { - let a: u8 = 1; - let e: u8 = 4; - let r: u8 = vqshlb_n_u8::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlh_n_u16() { - let a: u16 = 1; - let e: u16 = 4; - let r: u16 = vqshlh_n_u16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshls_n_u32() { - let a: u32 = 1; - let e: u32 = 4; - let r: u32 = vqshls_n_u32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshld_n_u64() { - let a: u64 = 1; - let e: u64 = 4; - let r: u64 = vqshld_n_u64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlub_n_s8() { - let a: i8 = 1; - let e: u8 = 4; - let r: u8 = vqshlub_n_s8::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshluh_n_s16() { - let a: i16 = 1; - let e: u16 = 4; - let r: u16 = vqshluh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlus_n_s32() { - let a: i32 = 1; - let e: u32 = 4; - let r: u32 = vqshlus_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlud_n_s64() { - let a: i64 = 1; - let e: u64 = 4; - let r: u64 = vqshlud_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrnd_n_s64() { - let a: i64 = 0; - let e: i32 = 0; - let r: i32 = vqshrnd_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrnh_n_s16() { - let a: i16 = 4; - let e: i8 = 1; - let r: i8 = vqshrnh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrns_n_s32() { - let a: i32 = 4; - let e: i16 = 1; - let r: i16 = vqshrns_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_s16() { - let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); - let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vqshrn_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_s32() { - let a: i16x4 = i16x4::new(0, 1, 8, 9); - let b: i32x4 = i32x4::new(32, 36, 40, 44); - let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let r: i16x8 = transmute(vqshrn_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_s64() { - let a: i32x2 = i32x2::new(0, 1); - let b: i64x2 = i64x2::new(32, 36); - let e: i32x4 = i32x4::new(0, 1, 8, 9); - let r: i32x4 = transmute(vqshrn_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrnd_n_u64() { - let a: u64 = 0; - let e: u32 = 0; - let r: u32 = vqshrnd_n_u64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrnh_n_u16() { - let a: u16 = 4; - let e: u8 = 1; - let r: u8 = vqshrnh_n_u16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrns_n_u32() { - let a: u32 = 4; - let e: u16 = 1; - let r: u16 = vqshrns_n_u32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_u16() { - let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); - let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vqshrn_high_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_u32() { - let a: u16x4 = u16x4::new(0, 1, 8, 9); - let b: u32x4 = u32x4::new(32, 36, 40, 44); - let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let r: u16x8 = transmute(vqshrn_high_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_high_n_u64() { - let a: u32x2 = u32x2::new(0, 1); - let b: u64x2 = u64x2::new(32, 36); - let e: u32x4 = u32x4::new(0, 1, 8, 9); - let r: u32x4 = transmute(vqshrn_high_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrunh_n_s16() { - let a: i16 = 4; - let e: u8 = 1; - let r: u8 = vqshrunh_n_s16::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshruns_n_s32() { - let a: i32 = 4; - let e: u16 = 1; - let r: u16 = vqshruns_n_s32::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrund_n_s64() { - let a: i64 = 4; - let e: u32 = 1; - let r: u32 = vqshrund_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_high_n_s16() { - let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); - let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vqshrun_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_high_n_s32() { - let a: u16x4 = u16x4::new(0, 1, 8, 9); - let b: i32x4 = i32x4::new(32, 36, 40, 44); - let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let r: u16x8 = transmute(vqshrun_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_high_n_s64() { - let a: u32x2 = u32x2::new(0, 1); - let b: i64x2 = i64x2::new(32, 36); - let e: u32x4 = u32x4::new(0, 1, 8, 9); - let r: u32x4 = transmute(vqshrun_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqaddb_u8() { - let a: u8 = 2; - let b: i8 = 2; - let e: u8 = 4; - let r: u8 = vsqaddb_u8(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqaddh_u16() { - let a: u16 = 2; - let b: i16 = 2; - let e: u16 = 4; - let r: u16 = vsqaddh_u16(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqadds_u32() { - let a: u32 = 2; - let b: i32 = 2; - let e: u32 = 4; - let r: u32 = vsqadds_u32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqaddd_u64() { - let a: u64 = 2; - let b: i64 = 2; - let e: u64 = 4; - let r: u64 = vsqaddd_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqrt_f32() { - let a: f32x2 = f32x2::new(4.0, 9.0); - let e: f32x2 = f32x2::new(2.0, 3.0); - let r: f32x2 = transmute(vsqrt_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqrtq_f32() { - let a: f32x4 = f32x4::new(4.0, 9.0, 16.0, 25.0); - let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let r: f32x4 = transmute(vsqrtq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqrt_f64() { - let a: f64 = 4.0; - let e: f64 = 2.0; - let r: f64 = transmute(vsqrt_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsqrtq_f64() { - let a: f64x2 = f64x2::new(4.0, 9.0); - let e: f64x2 = f64x2::new(2.0, 3.0); - let r: f64x2 = transmute(vsqrtq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrte_f64() { - let a: f64 = 1.0; - let e: f64 = 0.998046875; - let r: f64 = transmute(vrsqrte_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrteq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let e: f64x2 = f64x2::new(0.998046875, 0.705078125); - let r: f64x2 = transmute(vrsqrteq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrtes_f32() { - let a: f32 = 1.0; - let e: f32 = 0.998046875; - let r: f32 = vrsqrtes_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrted_f64() { - let a: f64 = 1.0; - let e: f64 = 0.998046875; - let r: f64 = vrsqrted_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrts_f64() { - let a: f64 = 1.0; - let b: f64 = 1.0; - let e: f64 = 1.; - let r: f64 = transmute(vrsqrts_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrtsq_f64() { - let a: f64x2 = f64x2::new(1.0, 2.0); - let b: f64x2 = f64x2::new(1.0, 2.0); - let e: f64x2 = f64x2::new(1., -0.5); - let r: f64x2 = transmute(vrsqrtsq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrtss_f32() { - let a: f32 = 1.0; - let b: f32 = 1.0; - let e: f32 = 1.; - let r: f32 = vrsqrtss_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrtsd_f64() { - let a: f64 = 1.0; - let b: f64 = 1.0; - let e: f64 = 1.; - let r: f64 = vrsqrtsd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpe_f64() { - let a: f64 = 4.0; - let e: f64 = 0.24951171875; - let r: f64 = transmute(vrecpe_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpeq_f64() { - let a: f64x2 = f64x2::new(4.0, 3.0); - let e: f64x2 = f64x2::new(0.24951171875, 0.3330078125); - let r: f64x2 = transmute(vrecpeq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpes_f32() { - let a: f32 = 4.0; - let e: f32 = 0.24951171875; - let r: f32 = vrecpes_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecped_f64() { - let a: f64 = 4.0; - let e: f64 = 0.24951171875; - let r: f64 = vrecped_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecps_f64() { - let a: f64 = 4.0; - let b: f64 = 4.0; - let e: f64 = -14.; - let r: f64 = transmute(vrecps_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpsq_f64() { - let a: f64x2 = f64x2::new(4.0, 3.0); - let b: f64x2 = f64x2::new(4.0, 3.0); - let e: f64x2 = f64x2::new(-14., -7.); - let r: f64x2 = transmute(vrecpsq_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpss_f32() { - let a: f32 = 4.0; - let b: f32 = 4.0; - let e: f32 = -14.; - let r: f32 = vrecpss_f32(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpsd_f64() { - let a: f64 = 4.0; - let b: f64 = 4.0; - let e: f64 = -14.; - let r: f64 = vrecpsd_f64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpxs_f32() { - let a: f32 = 4.0; - let e: f32 = 0.5; - let r: f32 = vrecpxs_f32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpxd_f64() { - let a: f64 = 4.0; - let e: f64 = 0.5; - let r: f64 = vrecpxd_f64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_p64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_p64() { - let a: i64x1 = i64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p64_s64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p64_u64() { - let a: u64x1 = u64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p64_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p64_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_f64() { - let a: f64 = 0.; - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_f64() { - let a: f64 = 0.; - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_s16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_f64() { - let a: f64 = 0.; - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vreinterpret_s32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_f64() { - let a: f64 = 0.; - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vreinterpretq_s32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_s64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_f64() { - let a: f64 = 0.; - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_f64() { - let a: f64 = 0.; - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vreinterpret_u16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_f64() { - let a: f64 = 0.; - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vreinterpret_u32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_f64() { - let a: f64 = 0.; - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vreinterpretq_u32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vreinterpretq_u64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_f64() { - let a: f64 = 0.; - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_f64() { - let a: f64 = 0.; - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_p16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p64_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p64_f64() { - let a: f64 = 0.; - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p64_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_p64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p64_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_p64_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p128_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_f64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_s16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_s32() { - let a: i32x2 = i32x2::new(0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_s64() { - let a: i64x1 = i64x1::new(0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_s32() { - let a: i32x4 = i32x4::new(0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_s64() { - let a: i64x2 = i64x2::new(0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_u16() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_u32() { - let a: u32x2 = u32x2::new(0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_u64() { - let a: u64x1 = u64x1::new(0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_u32() { - let a: u32x4 = u32x4::new(0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_u64() { - let a: u64x2 = u64x2::new(0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_p16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_p64() { - let a: i64x1 = i64x1::new(0); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_p64() { - let a: i64x1 = i64x1::new(0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_p64() { - let a: i64x2 = i64x2::new(0, 0); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_p64() { - let a: i64x2 = i64x2::new(0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_p128() { - let a: p128 = 0; - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f64_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: f64 = 0.; - let r: f64 = transmute(vreinterpret_f64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_f64() { - let a: f64 = 0.; - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f64_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: f64x2 = f64x2::new(0., 0.); - let r: f64x2 = transmute(vreinterpretq_f64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_f64() { - let a: f64x2 = f64x2::new(0., 0.); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshld_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: i64 = 4; - let r: i64 = vrshld_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshld_u64() { - let a: u64 = 1; - let b: i64 = 2; - let e: u64 = 4; - let r: u64 = vrshld_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrd_n_s64() { - let a: i64 = 4; - let e: i64 = 1; - let r: i64 = vrshrd_n_s64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrd_n_u64() { - let a: u64 = 4; - let e: u64 = 1; - let r: u64 = vrshrd_n_u64::<2>(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_s16() { - let a: i8x8 = i8x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let b: i16x8 = i16x8::new(32, 36, 40, 44, 48, 52, 56, 60); - let e: i8x16 = i8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vrshrn_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_s32() { - let a: i16x4 = i16x4::new(0, 1, 8, 9); - let b: i32x4 = i32x4::new(32, 36, 40, 44); - let e: i16x8 = i16x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let r: i16x8 = transmute(vrshrn_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_s64() { - let a: i32x2 = i32x2::new(0, 1); - let b: i64x2 = i64x2::new(32, 36); - let e: i32x4 = i32x4::new(0, 1, 8, 9); - let r: i32x4 = transmute(vrshrn_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_u16() { - let a: u8x8 = u8x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let b: u16x8 = u16x8::new(32, 36, 40, 44, 48, 52, 56, 60); - let e: u8x16 = u8x16::new(0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vrshrn_high_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_u32() { - let a: u16x4 = u16x4::new(0, 1, 8, 9); - let b: u32x4 = u32x4::new(32, 36, 40, 44); - let e: u16x8 = u16x8::new(0, 1, 8, 9, 8, 9, 10, 11); - let r: u16x8 = transmute(vrshrn_high_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_high_n_u64() { - let a: u32x2 = u32x2::new(0, 1); - let b: u64x2 = u64x2::new(32, 36); - let e: u32x4 = u32x4::new(0, 1, 8, 9); - let r: u32x4 = transmute(vrshrn_high_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsrad_n_s64() { - let a: i64 = 1; - let b: i64 = 4; - let e: i64 = 2; - let r: i64 = vrsrad_n_s64::<2>(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsrad_n_u64() { - let a: u64 = 1; - let b: u64 = 4; - let e: u64 = 2; - let r: u64 = vrsrad_n_u64::<2>(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_s16() { - let a: i8x8 = i8x8::new(1, 2, 0, 0, 0, 0, 0, 0); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x16 = i8x16::new(1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vrsubhn_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_s32() { - let a: i16x4 = i16x4::new(1, 2, 0, 0); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let c: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i16x8 = i16x8::new(1, 2, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vrsubhn_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_s64() { - let a: i32x2 = i32x2::new(1, 2); - let b: i64x2 = i64x2::new(1, 2); - let c: i64x2 = i64x2::new(1, 2); - let e: i32x4 = i32x4::new(1, 2, 0, 0); - let r: i32x4 = transmute(vrsubhn_high_s64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_u16() { - let a: u8x8 = u8x8::new(1, 2, 0, 0, 0, 0, 0, 0); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x16 = u8x16::new(1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vrsubhn_high_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_u32() { - let a: u16x4 = u16x4::new(1, 2, 0, 0); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let c: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u16x8 = u16x8::new(1, 2, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vrsubhn_high_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_high_u64() { - let a: u32x2 = u32x2::new(1, 2); - let b: u64x2 = u64x2::new(1, 2); - let c: u64x2 = u64x2::new(1, 2); - let e: u32x4 = u32x4::new(1, 2, 0, 0); - let r: u32x4 = transmute(vrsubhn_high_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_f64() { - let a: f64 = 1.; - let b: f64 = 0.; - let e: f64 = 1.; - let r: f64 = transmute(vset_lane_f64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_f64() { - let a: f64 = 1.; - let b: f64x2 = f64x2::new(0., 2.); - let e: f64x2 = f64x2::new(1., 2.); - let r: f64x2 = transmute(vsetq_lane_f64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshld_s64() { - let a: i64 = 1; - let b: i64 = 2; - let e: i64 = 4; - let r: i64 = vshld_s64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshld_u64() { - let a: u64 = 1; - let b: i64 = 2; - let e: u64 = 4; - let r: u64 = vshld_u64(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_s8() { - let a: i8x16 = i8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i16x8 = transmute(vshll_high_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_s16() { - let a: i16x8 = i16x8::new(0, 0, 1, 2, 1, 2, 3, 4); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vshll_high_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_s32() { - let a: i32x4 = i32x4::new(0, 0, 1, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vshll_high_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_u8() { - let a: u8x16 = u8x16::new(0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u16x8 = transmute(vshll_high_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_u16() { - let a: u16x8 = u16x8::new(0, 0, 1, 2, 1, 2, 3, 4); - let e: u32x4 = u32x4::new(4, 8, 12, 16); - let r: u32x4 = transmute(vshll_high_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshll_high_n_u32() { - let a: u32x4 = u32x4::new(0, 0, 1, 2); - let e: u64x2 = u64x2::new(4, 8); - let r: u64x2 = transmute(vshll_high_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_s16() { - let a: i8x8 = i8x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(20, 24, 28, 32, 52, 56, 60, 64); - let e: i8x16 = i8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); - let r: i8x16 = transmute(vshrn_high_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_s32() { - let a: i16x4 = i16x4::new(1, 2, 5, 6); - let b: i32x4 = i32x4::new(20, 24, 28, 32); - let e: i16x8 = i16x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let r: i16x8 = transmute(vshrn_high_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_s64() { - let a: i32x2 = i32x2::new(1, 2); - let b: i64x2 = i64x2::new(20, 24); - let e: i32x4 = i32x4::new(1, 2, 5, 6); - let r: i32x4 = transmute(vshrn_high_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_u16() { - let a: u8x8 = u8x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(20, 24, 28, 32, 52, 56, 60, 64); - let e: u8x16 = u8x16::new(1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16); - let r: u8x16 = transmute(vshrn_high_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_u32() { - let a: u16x4 = u16x4::new(1, 2, 5, 6); - let b: u32x4 = u32x4::new(20, 24, 28, 32); - let e: u16x8 = u16x8::new(1, 2, 5, 6, 5, 6, 7, 8); - let r: u16x8 = transmute(vshrn_high_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_high_n_u64() { - let a: u32x2 = u32x2::new(1, 2); - let b: u64x2 = u64x2::new(20, 24); - let e: u32x4 = u32x4::new(1, 2, 5, 6); - let r: u32x4 = transmute(vshrn_high_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sm4")] - unsafe fn test_vsm3partw1q_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let c: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(2147549312, 3221323968, 131329, 2684362752); - let r: u32x4 = transmute(vsm3partw1q_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sm4")] - unsafe fn test_vsm3partw2q_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let c: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(128, 256, 384, 1077977696); - let r: u32x4 = transmute(vsm3partw2q_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sm4")] - unsafe fn test_vsm3ss1q_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let c: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(0, 0, 0, 2098176); - let r: u32x4 = transmute(vsm3ss1q_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sm4")] - unsafe fn test_vsm4ekeyq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(1784948604, 136020997, 2940231695, 3789947679); - let r: u32x4 = transmute(vsm4ekeyq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sm4")] - unsafe fn test_vsm4eq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(1093874472, 3616769504, 3878330411, 2765298765); - let r: u32x4 = transmute(vsm4eq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vrax1q_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(3, 4); - let e: u64x2 = u64x2::new(7, 10); - let r: u64x2 = transmute(vrax1q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vsha512hq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(3, 4); - let c: u64x2 = u64x2::new(5, 6); - let e: u64x2 = u64x2::new(11189044327219203, 7177611956453380); - let r: u64x2 = transmute(vsha512hq_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vsha512h2q_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(3, 4); - let c: u64x2 = u64x2::new(5, 6); - let e: u64x2 = u64x2::new(5770237651009406214, 349133864969); - let r: u64x2 = transmute(vsha512h2q_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vsha512su0q_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(3, 4); - let e: u64x2 = u64x2::new(144115188075855874, 9439544818968559619); - let r: u64x2 = transmute(vsha512su0q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,sha3")] - unsafe fn test_vsha512su1q_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(3, 4); - let c: u64x2 = u64x2::new(5, 6); - let e: u64x2 = u64x2::new(105553116266526, 140737488355368); - let r: u64x2 = transmute(vsha512su1q_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32x_f32() { - let a: f32x2 = f32x2::new(-1.5, 2.9); - let e: f32x2 = f32x2::new(-2.0, 3.0); - let r: f32x2 = transmute(vrnd32x_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32xq_f32() { - let a: f32x4 = f32x4::new(-1.5, 2.9, 1.5, -2.5); - let e: f32x4 = f32x4::new(-2.0, 3.0, 2.0, -2.0); - let r: f32x4 = transmute(vrnd32xq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32xq_f64() { - let a: f64x2 = f64x2::new(-1.5, 2.9); - let e: f64x2 = f64x2::new(-2.0, 3.0); - let r: f64x2 = transmute(vrnd32xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(1.5, -2.5); - let e: f64x2 = f64x2::new(2.0, -2.0); - let r: f64x2 = transmute(vrnd32xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(2147483647.499999762, 2147483647.5); - let e: f64x2 = f64x2::new(2147483647.0, -2147483648.0); - let r: f64x2 = transmute(vrnd32xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(-2147483647.499999762, -2147483648.500000477); - let e: f64x2 = f64x2::new(-2147483647.0, -2147483648.0); - let r: f64x2 = transmute(vrnd32xq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32x_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 1.5; - let e: f64 = 2.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2147483647.499999762; - let e: f64 = 2147483647.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2147483647.499999762; - let e: f64 = -2147483647.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2.9; - let e: f64 = 3.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2147483647.5; - let e: f64 = -2147483648.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2147483648.500000477; - let e: f64 = -2147483648.0; - let r: f64 = transmute(vrnd32x_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32z_f32() { - let a: f32x2 = f32x2::new(-1.5, 2.9); - let e: f32x2 = f32x2::new(-1.0, 2.0); - let r: f32x2 = transmute(vrnd32z_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32zq_f32() { - let a: f32x4 = f32x4::new(-1.5, 2.9, 1.5, -2.5); - let e: f32x4 = f32x4::new(-1.0, 2.0, 1.0, -2.0); - let r: f32x4 = transmute(vrnd32zq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32zq_f64() { - let a: f64x2 = f64x2::new(-1.5, 2.9); - let e: f64x2 = f64x2::new(-1.0, 2.0); - let r: f64x2 = transmute(vrnd32zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(1.5, -2.5); - let e: f64x2 = f64x2::new(1.0, -2.0); - let r: f64x2 = transmute(vrnd32zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(2147483647.999999762, 2147483648.0); - let e: f64x2 = f64x2::new(2147483647.0, -2147483648.0); - let r: f64x2 = transmute(vrnd32zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(-2147483647.999999762, -2147483649.0); - let e: f64x2 = f64x2::new(-2147483647.0, -2147483648.0); - let r: f64x2 = transmute(vrnd32zq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd32z_f64() { - let a: f64 = -1.5; - let e: f64 = -1.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 1.5; - let e: f64 = 1.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2147483647.999999762; - let e: f64 = 2147483647.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2147483647.999999762; - let e: f64 = -2147483647.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2.9; - let e: f64 = 2.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2147483648.0; - let e: f64 = -2147483648.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2147483649.0; - let e: f64 = -2147483648.0; - let r: f64 = transmute(vrnd32z_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64x_f32() { - let a: f32x2 = f32x2::new(-1.5, 2.9); - let e: f32x2 = f32x2::new(-2.0, 3.0); - let r: f32x2 = transmute(vrnd64x_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64xq_f32() { - let a: f32x4 = f32x4::new(-1.5, 2.9, 1.5, -2.5); - let e: f32x4 = f32x4::new(-2.0, 3.0, 2.0, -2.0); - let r: f32x4 = transmute(vrnd64xq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64xq_f64() { - let a: f64x2 = f64x2::new(-1.5, 2.9); - let e: f64x2 = f64x2::new(-2.0, 3.0); - let r: f64x2 = transmute(vrnd64xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(1.5, -2.5); - let e: f64x2 = f64x2::new(2.0, -2.0); - let r: f64x2 = transmute(vrnd64xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(9223372036854774784.0, 9223372036854775808.0); - let e: f64x2 = f64x2::new(9223372036854774784.0, -9223372036854775808.0); - let r: f64x2 = transmute(vrnd64xq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(-9223372036854775808.0, -9223372036854777856.0); - let e: f64x2 = f64x2::new(-9223372036854775808.0, -9223372036854775808.0); - let r: f64x2 = transmute(vrnd64xq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64x_f64() { - let a: f64 = -1.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 1.5; - let e: f64 = 2.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 9223372036854774784.0; - let e: f64 = 9223372036854774784.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -9223372036854775808.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2.9; - let e: f64 = 3.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 9223372036854775808.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -9223372036854777856.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64x_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64z_f32() { - let a: f32x2 = f32x2::new(-1.5, 2.9); - let e: f32x2 = f32x2::new(-1.0, 2.0); - let r: f32x2 = transmute(vrnd64z_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64zq_f32() { - let a: f32x4 = f32x4::new(-1.5, 2.9, 1.5, -2.5); - let e: f32x4 = f32x4::new(-1.0, 2.0, 1.0, -2.0); - let r: f32x4 = transmute(vrnd64zq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64zq_f64() { - let a: f64x2 = f64x2::new(-1.5, 2.9); - let e: f64x2 = f64x2::new(-1.0, 2.0); - let r: f64x2 = transmute(vrnd64zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(1.5, -2.5); - let e: f64x2 = f64x2::new(1.0, -2.0); - let r: f64x2 = transmute(vrnd64zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(9223372036854774784.0, 9223372036854775808.0); - let e: f64x2 = f64x2::new(9223372036854774784.0, -9223372036854775808.0); - let r: f64x2 = transmute(vrnd64zq_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64x2 = f64x2::new(-9223372036854775808.0, -9223372036854777856.0); - let e: f64x2 = f64x2::new(-9223372036854775808.0, -9223372036854775808.0); - let r: f64x2 = transmute(vrnd64zq_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,frintts")] - unsafe fn test_vrnd64z_f64() { - let a: f64 = -1.5; - let e: f64 = -1.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 1.5; - let e: f64 = 1.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 9223372036854774784.0; - let e: f64 = 9223372036854774784.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -9223372036854775808.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 2.9; - let e: f64 = 2.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -2.5; - let e: f64 = -2.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = 9223372036854775808.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - - let a: f64 = -9223372036854777856.0; - let e: f64 = -9223372036854775808.0; - let r: f64 = transmute(vrnd64z_f64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_s8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: i8x8 = transmute(vtrn1_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_s8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); - let r: i8x16 = transmute(vtrn1q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_s16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(0, 1, 4, 5); - let r: i16x4 = transmute(vtrn1_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_s16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: i16x8 = transmute(vtrn1q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_s32() { - let a: i32x4 = i32x4::new(0, 2, 4, 6); - let b: i32x4 = i32x4::new(1, 3, 5, 7); - let e: i32x4 = i32x4::new(0, 1, 4, 5); - let r: i32x4 = transmute(vtrn1q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_u8() { - let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u8x8 = u8x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: u8x8 = transmute(vtrn1_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_u8() { - let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: u8x16 = u8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); - let r: u8x16 = transmute(vtrn1q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_u16() { - let a: u16x4 = u16x4::new(0, 2, 4, 6); - let b: u16x4 = u16x4::new(1, 3, 5, 7); - let e: u16x4 = u16x4::new(0, 1, 4, 5); - let r: u16x4 = transmute(vtrn1_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_u16() { - let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u16x8 = u16x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: u16x8 = transmute(vtrn1q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_u32() { - let a: u32x4 = u32x4::new(0, 2, 4, 6); - let b: u32x4 = u32x4::new(1, 3, 5, 7); - let e: u32x4 = u32x4::new(0, 1, 4, 5); - let r: u32x4 = transmute(vtrn1q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_p8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: i8x8 = transmute(vtrn1_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_p8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29); - let r: i8x16 = transmute(vtrn1q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_p16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(0, 1, 4, 5); - let r: i16x4 = transmute(vtrn1_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_p16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(0, 1, 4, 5, 8, 9, 12, 13); - let r: i16x8 = transmute(vtrn1q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vtrn1_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_s64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vtrn1q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vtrn1_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_u64() { - let a: u64x2 = u64x2::new(0, 2); - let b: u64x2 = u64x2::new(1, 3); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vtrn1q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_p64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vtrn1q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_f32() { - let a: f32x4 = f32x4::new(0., 2., 4., 6.); - let b: f32x4 = f32x4::new(1., 3., 5., 7.); - let e: f32x4 = f32x4::new(0., 1., 4., 5.); - let r: f32x4 = transmute(vtrn1q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vtrn1_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn1q_f64() { - let a: f64x2 = f64x2::new(0., 2.); - let b: f64x2 = f64x2::new(1., 3.); - let e: f64x2 = f64x2::new(0., 1.); - let r: f64x2 = transmute(vtrn1q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_s8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: i8x8 = transmute(vtrn2_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_s8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); - let r: i8x16 = transmute(vtrn2q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_s16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(2, 3, 6, 7); - let r: i16x4 = transmute(vtrn2_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_s16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: i16x8 = transmute(vtrn2q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_s32() { - let a: i32x4 = i32x4::new(0, 2, 4, 6); - let b: i32x4 = i32x4::new(1, 3, 5, 7); - let e: i32x4 = i32x4::new(2, 3, 6, 7); - let r: i32x4 = transmute(vtrn2q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_u8() { - let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u8x8 = u8x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: u8x8 = transmute(vtrn2_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_u8() { - let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: u8x16 = u8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); - let r: u8x16 = transmute(vtrn2q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_u16() { - let a: u16x4 = u16x4::new(0, 2, 4, 6); - let b: u16x4 = u16x4::new(1, 3, 5, 7); - let e: u16x4 = u16x4::new(2, 3, 6, 7); - let r: u16x4 = transmute(vtrn2_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_u16() { - let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u16x8 = u16x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: u16x8 = transmute(vtrn2q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_u32() { - let a: u32x4 = u32x4::new(0, 2, 4, 6); - let b: u32x4 = u32x4::new(1, 3, 5, 7); - let e: u32x4 = u32x4::new(2, 3, 6, 7); - let r: u32x4 = transmute(vtrn2q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_p8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: i8x8 = transmute(vtrn2_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_p8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31); - let r: i8x16 = transmute(vtrn2q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_p16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(2, 3, 6, 7); - let r: i16x4 = transmute(vtrn2_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_p16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(2, 3, 6, 7, 10, 11, 14, 15); - let r: i16x8 = transmute(vtrn2q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: i32x2 = i32x2::new(2, 3); - let r: i32x2 = transmute(vtrn2_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_s64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(2, 3); - let r: i64x2 = transmute(vtrn2q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: u32x2 = u32x2::new(2, 3); - let r: u32x2 = transmute(vtrn2_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_u64() { - let a: u64x2 = u64x2::new(0, 2); - let b: u64x2 = u64x2::new(1, 3); - let e: u64x2 = u64x2::new(2, 3); - let r: u64x2 = transmute(vtrn2q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_p64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(2, 3); - let r: i64x2 = transmute(vtrn2q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_f32() { - let a: f32x4 = f32x4::new(0., 2., 4., 6.); - let b: f32x4 = f32x4::new(1., 3., 5., 7.); - let e: f32x4 = f32x4::new(2., 3., 6., 7.); - let r: f32x4 = transmute(vtrn2q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: f32x2 = f32x2::new(2., 3.); - let r: f32x2 = transmute(vtrn2_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn2q_f64() { - let a: f64x2 = f64x2::new(0., 2.); - let b: f64x2 = f64x2::new(1., 3.); - let e: f64x2 = f64x2::new(2., 3.); - let r: f64x2 = transmute(vtrn2q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_s8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vzip1_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_s8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vzip1q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_s16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vzip1_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_s16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vzip1q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vzip1_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_s32() { - let a: i32x4 = i32x4::new(0, 2, 4, 6); - let b: i32x4 = i32x4::new(1, 3, 5, 7); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vzip1q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_s64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vzip1q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_u8() { - let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vzip1_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_u8() { - let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vzip1q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_u16() { - let a: u16x4 = u16x4::new(0, 2, 4, 6); - let b: u16x4 = u16x4::new(1, 3, 5, 7); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vzip1_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_u16() { - let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vzip1q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vzip1_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_u32() { - let a: u32x4 = u32x4::new(0, 2, 4, 6); - let b: u32x4 = u32x4::new(1, 3, 5, 7); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vzip1q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_u64() { - let a: u64x2 = u64x2::new(0, 2); - let b: u64x2 = u64x2::new(1, 3); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vzip1q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_p8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vzip1_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_p8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vzip1q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_p16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vzip1_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_p16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vzip1q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_p64() { - let a: i64x2 = i64x2::new(0, 2); - let b: i64x2 = i64x2::new(1, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vzip1q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vzip1_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_f32() { - let a: f32x4 = f32x4::new(0., 2., 4., 6.); - let b: f32x4 = f32x4::new(1., 3., 5., 7.); - let e: f32x4 = f32x4::new(0., 1., 2., 3.); - let r: f32x4 = transmute(vzip1q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip1q_f64() { - let a: f64x2 = f64x2::new(0., 2.); - let b: f64x2 = f64x2::new(1., 3.); - let e: f64x2 = f64x2::new(0., 1.); - let r: f64x2 = transmute(vzip1q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_s8() { - let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: i8x8 = transmute(vzip2_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_s8() { - let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); - let r: i8x16 = transmute(vzip2q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_s16() { - let a: i16x4 = i16x4::new(0, 16, 16, 18); - let b: i16x4 = i16x4::new(1, 17, 17, 19); - let e: i16x4 = i16x4::new(16, 17, 18, 19); - let r: i16x4 = transmute(vzip2_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_s16() { - let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: i16x8 = transmute(vzip2q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_s32() { - let a: i32x2 = i32x2::new(0, 16); - let b: i32x2 = i32x2::new(1, 17); - let e: i32x2 = i32x2::new(16, 17); - let r: i32x2 = transmute(vzip2_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_s32() { - let a: i32x4 = i32x4::new(0, 16, 16, 18); - let b: i32x4 = i32x4::new(1, 17, 17, 19); - let e: i32x4 = i32x4::new(16, 17, 18, 19); - let r: i32x4 = transmute(vzip2q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_s64() { - let a: i64x2 = i64x2::new(0, 16); - let b: i64x2 = i64x2::new(1, 17); - let e: i64x2 = i64x2::new(16, 17); - let r: i64x2 = transmute(vzip2q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_u8() { - let a: u8x8 = u8x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: u8x8 = u8x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: u8x8 = u8x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: u8x8 = transmute(vzip2_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_u8() { - let a: u8x16 = u8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); - let b: u8x16 = u8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); - let e: u8x16 = u8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); - let r: u8x16 = transmute(vzip2q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_u16() { - let a: u16x4 = u16x4::new(0, 16, 16, 18); - let b: u16x4 = u16x4::new(1, 17, 17, 19); - let e: u16x4 = u16x4::new(16, 17, 18, 19); - let r: u16x4 = transmute(vzip2_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_u16() { - let a: u16x8 = u16x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: u16x8 = u16x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: u16x8 = u16x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: u16x8 = transmute(vzip2q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_u32() { - let a: u32x2 = u32x2::new(0, 16); - let b: u32x2 = u32x2::new(1, 17); - let e: u32x2 = u32x2::new(16, 17); - let r: u32x2 = transmute(vzip2_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_u32() { - let a: u32x4 = u32x4::new(0, 16, 16, 18); - let b: u32x4 = u32x4::new(1, 17, 17, 19); - let e: u32x4 = u32x4::new(16, 17, 18, 19); - let r: u32x4 = transmute(vzip2q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_u64() { - let a: u64x2 = u64x2::new(0, 16); - let b: u64x2 = u64x2::new(1, 17); - let e: u64x2 = u64x2::new(16, 17); - let r: u64x2 = transmute(vzip2q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_p8() { - let a: i8x8 = i8x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: i8x8 = i8x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: i8x8 = i8x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: i8x8 = transmute(vzip2_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_p8() { - let a: i8x16 = i8x16::new(0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31); - let e: i8x16 = i8x16::new(16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31); - let r: i8x16 = transmute(vzip2q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_p16() { - let a: i16x4 = i16x4::new(0, 16, 16, 18); - let b: i16x4 = i16x4::new(1, 17, 17, 19); - let e: i16x4 = i16x4::new(16, 17, 18, 19); - let r: i16x4 = transmute(vzip2_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_p16() { - let a: i16x8 = i16x8::new(0, 16, 16, 18, 16, 18, 20, 22); - let b: i16x8 = i16x8::new(1, 17, 17, 19, 17, 19, 21, 23); - let e: i16x8 = i16x8::new(16, 17, 18, 19, 20, 21, 22, 23); - let r: i16x8 = transmute(vzip2q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_p64() { - let a: i64x2 = i64x2::new(0, 16); - let b: i64x2 = i64x2::new(1, 17); - let e: i64x2 = i64x2::new(16, 17); - let r: i64x2 = transmute(vzip2q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2_f32() { - let a: f32x2 = f32x2::new(0., 8.); - let b: f32x2 = f32x2::new(1., 9.); - let e: f32x2 = f32x2::new(8., 9.); - let r: f32x2 = transmute(vzip2_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_f32() { - let a: f32x4 = f32x4::new(0., 8., 8., 10.); - let b: f32x4 = f32x4::new(1., 9., 9., 11.); - let e: f32x4 = f32x4::new(8., 9., 10., 11.); - let r: f32x4 = transmute(vzip2q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip2q_f64() { - let a: f64x2 = f64x2::new(0., 8.); - let b: f64x2 = f64x2::new(1., 9.); - let e: f64x2 = f64x2::new(8., 9.); - let r: f64x2 = transmute(vzip2q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_s8() { - let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: i8x8 = transmute(vuzp1_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_s8() { - let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); - let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); - let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); - let r: i8x16 = transmute(vuzp1q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_s16() { - let a: i16x4 = i16x4::new(1, 0, 2, 0); - let b: i16x4 = i16x4::new(2, 0, 3, 0); - let e: i16x4 = i16x4::new(1, 2, 2, 3); - let r: i16x4 = transmute(vuzp1_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_s16() { - let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: i16x8 = transmute(vuzp1q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_s32() { - let a: i32x4 = i32x4::new(1, 0, 2, 0); - let b: i32x4 = i32x4::new(2, 0, 3, 0); - let e: i32x4 = i32x4::new(1, 2, 2, 3); - let r: i32x4 = transmute(vuzp1q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_u8() { - let a: u8x8 = u8x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: u8x8 = u8x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: u8x8 = u8x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: u8x8 = transmute(vuzp1_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_u8() { - let a: u8x16 = u8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); - let b: u8x16 = u8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); - let e: u8x16 = u8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); - let r: u8x16 = transmute(vuzp1q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_u16() { - let a: u16x4 = u16x4::new(1, 0, 2, 0); - let b: u16x4 = u16x4::new(2, 0, 3, 0); - let e: u16x4 = u16x4::new(1, 2, 2, 3); - let r: u16x4 = transmute(vuzp1_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_u16() { - let a: u16x8 = u16x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: u16x8 = u16x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: u16x8 = u16x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: u16x8 = transmute(vuzp1q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_u32() { - let a: u32x4 = u32x4::new(1, 0, 2, 0); - let b: u32x4 = u32x4::new(2, 0, 3, 0); - let e: u32x4 = u32x4::new(1, 2, 2, 3); - let r: u32x4 = transmute(vuzp1q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_p8() { - let a: i8x8 = i8x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: i8x8 = i8x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: i8x8 = transmute(vuzp1_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_p8() { - let a: i8x16 = i8x16::new(1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0); - let b: i8x16 = i8x16::new(2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0); - let e: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16); - let r: i8x16 = transmute(vuzp1q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_p16() { - let a: i16x4 = i16x4::new(1, 0, 2, 0); - let b: i16x4 = i16x4::new(2, 0, 3, 0); - let e: i16x4 = i16x4::new(1, 2, 2, 3); - let r: i16x4 = transmute(vuzp1_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_p16() { - let a: i16x8 = i16x8::new(1, 0, 2, 0, 2, 0, 3, 0); - let b: i16x8 = i16x8::new(2, 0, 3, 0, 7, 0, 8, 0); - let e: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 7, 8); - let r: i16x8 = transmute(vuzp1q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_s32() { - let a: i32x2 = i32x2::new(1, 0); - let b: i32x2 = i32x2::new(2, 0); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vuzp1_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_s64() { - let a: i64x2 = i64x2::new(1, 0); - let b: i64x2 = i64x2::new(2, 0); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vuzp1q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_u32() { - let a: u32x2 = u32x2::new(1, 0); - let b: u32x2 = u32x2::new(2, 0); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vuzp1_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_u64() { - let a: u64x2 = u64x2::new(1, 0); - let b: u64x2 = u64x2::new(2, 0); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vuzp1q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_p64() { - let a: i64x2 = i64x2::new(1, 0); - let b: i64x2 = i64x2::new(2, 0); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vuzp1q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_f32() { - let a: f32x4 = f32x4::new(0., 8., 1., 9.); - let b: f32x4 = f32x4::new(1., 10., 3., 11.); - let e: f32x4 = f32x4::new(0., 1., 1., 3.); - let r: f32x4 = transmute(vuzp1q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1_f32() { - let a: f32x2 = f32x2::new(0., 8.); - let b: f32x2 = f32x2::new(1., 10.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vuzp1_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp1q_f64() { - let a: f64x2 = f64x2::new(0., 8.); - let b: f64x2 = f64x2::new(1., 10.); - let e: f64x2 = f64x2::new(0., 1.); - let r: f64x2 = transmute(vuzp1q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_s8() { - let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: i8x8 = transmute(vuzp2_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_s8() { - let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); - let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); - let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); - let r: i8x16 = transmute(vuzp2q_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_s16() { - let a: i16x4 = i16x4::new(0, 17, 0, 18); - let b: i16x4 = i16x4::new(0, 18, 0, 19); - let e: i16x4 = i16x4::new(17, 18, 18, 19); - let r: i16x4 = transmute(vuzp2_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_s16() { - let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: i16x8 = transmute(vuzp2q_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_s32() { - let a: i32x4 = i32x4::new(0, 17, 0, 18); - let b: i32x4 = i32x4::new(0, 18, 0, 19); - let e: i32x4 = i32x4::new(17, 18, 18, 19); - let r: i32x4 = transmute(vuzp2q_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_u8() { - let a: u8x8 = u8x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: u8x8 = u8x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: u8x8 = u8x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: u8x8 = transmute(vuzp2_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_u8() { - let a: u8x16 = u8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); - let b: u8x16 = u8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); - let e: u8x16 = u8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); - let r: u8x16 = transmute(vuzp2q_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_u16() { - let a: u16x4 = u16x4::new(0, 17, 0, 18); - let b: u16x4 = u16x4::new(0, 18, 0, 19); - let e: u16x4 = u16x4::new(17, 18, 18, 19); - let r: u16x4 = transmute(vuzp2_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_u16() { - let a: u16x8 = u16x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: u16x8 = u16x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: u16x8 = u16x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: u16x8 = transmute(vuzp2q_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_u32() { - let a: u32x4 = u32x4::new(0, 17, 0, 18); - let b: u32x4 = u32x4::new(0, 18, 0, 19); - let e: u32x4 = u32x4::new(17, 18, 18, 19); - let r: u32x4 = transmute(vuzp2q_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_p8() { - let a: i8x8 = i8x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: i8x8 = i8x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: i8x8 = i8x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: i8x8 = transmute(vuzp2_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_p8() { - let a: i8x16 = i8x16::new(0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24); - let b: i8x16 = i8x16::new(0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32); - let e: i8x16 = i8x16::new(17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32); - let r: i8x16 = transmute(vuzp2q_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_p16() { - let a: i16x4 = i16x4::new(0, 17, 0, 18); - let b: i16x4 = i16x4::new(0, 18, 0, 19); - let e: i16x4 = i16x4::new(17, 18, 18, 19); - let r: i16x4 = transmute(vuzp2_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_p16() { - let a: i16x8 = i16x8::new(0, 17, 0, 18, 0, 18, 0, 19); - let b: i16x8 = i16x8::new(0, 18, 0, 19, 0, 23, 0, 24); - let e: i16x8 = i16x8::new(17, 18, 18, 19, 18, 19, 23, 24); - let r: i16x8 = transmute(vuzp2q_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_s32() { - let a: i32x2 = i32x2::new(0, 17); - let b: i32x2 = i32x2::new(0, 18); - let e: i32x2 = i32x2::new(17, 18); - let r: i32x2 = transmute(vuzp2_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_s64() { - let a: i64x2 = i64x2::new(0, 17); - let b: i64x2 = i64x2::new(0, 18); - let e: i64x2 = i64x2::new(17, 18); - let r: i64x2 = transmute(vuzp2q_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_u32() { - let a: u32x2 = u32x2::new(0, 17); - let b: u32x2 = u32x2::new(0, 18); - let e: u32x2 = u32x2::new(17, 18); - let r: u32x2 = transmute(vuzp2_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_u64() { - let a: u64x2 = u64x2::new(0, 17); - let b: u64x2 = u64x2::new(0, 18); - let e: u64x2 = u64x2::new(17, 18); - let r: u64x2 = transmute(vuzp2q_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_p64() { - let a: i64x2 = i64x2::new(0, 17); - let b: i64x2 = i64x2::new(0, 18); - let e: i64x2 = i64x2::new(17, 18); - let r: i64x2 = transmute(vuzp2q_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_f32() { - let a: f32x4 = f32x4::new(0., 8., 1., 9.); - let b: f32x4 = f32x4::new(2., 9., 3., 11.); - let e: f32x4 = f32x4::new(8., 9., 9., 11.); - let r: f32x4 = transmute(vuzp2q_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2_f32() { - let a: f32x2 = f32x2::new(0., 8.); - let b: f32x2 = f32x2::new(2., 9.); - let e: f32x2 = f32x2::new(8., 9.); - let r: f32x2 = transmute(vuzp2_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp2q_f64() { - let a: f64x2 = f64x2::new(0., 8.); - let b: f64x2 = f64x2::new(2., 9.); - let e: f64x2 = f64x2::new(8., 9.); - let r: f64x2 = transmute(vuzp2q_f64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_u8() { - let a: u16x8 = u16x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let c: u8x16 = u8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); - let e: u16x8 = u16x8::new(20, 20, 20, 20, 20, 20, 20, 20); - let r: u16x8 = transmute(vabal_high_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_u16() { - let a: u32x4 = u32x4::new(9, 10, 11, 12); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 9, 10, 11, 12); - let c: u16x8 = u16x8::new(10, 10, 10, 10, 20, 0, 2, 4); - let e: u32x4 = u32x4::new(20, 20, 20, 20); - let r: u32x4 = transmute(vabal_high_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_u32() { - let a: u64x2 = u64x2::new(15, 16); - let b: u32x4 = u32x4::new(1, 2, 15, 16); - let c: u32x4 = u32x4::new(10, 10, 10, 12); - let e: u64x2 = u64x2::new(20, 20); - let r: u64x2 = transmute(vabal_high_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_s8() { - let a: i16x8 = i16x8::new(9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let c: i8x16 = i8x16::new(10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12); - let e: i16x8 = i16x8::new(20, 20, 20, 20, 20, 20, 20, 20); - let r: i16x8 = transmute(vabal_high_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_s16() { - let a: i32x4 = i32x4::new(9, 10, 11, 12); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 9, 10, 11, 12); - let c: i16x8 = i16x8::new(10, 10, 10, 10, 20, 0, 2, 4); - let e: i32x4 = i32x4::new(20, 20, 20, 20); - let r: i32x4 = transmute(vabal_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_high_s32() { - let a: i64x2 = i64x2::new(15, 16); - let b: i32x4 = i32x4::new(1, 2, 15, 16); - let c: i32x4 = i32x4::new(10, 10, 10, 12); - let e: i64x2 = i64x2::new(20, 20); - let r: i64x2 = transmute(vabal_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabs_s64() { - let a: i64x1 = i64x1::new(-9223372036854775808); - let e: i64x1 = i64x1::new(0x7F_FF_FF_FF_FF_FF_FF_FF); - let r: i64x1 = transmute(vqabs_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsq_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, -7); - let e: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 7); - let r: i64x2 = transmute(vqabsq_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsb_s8() { - let a: i8 = -7; - let e: i8 = 7; - let r: i8 = vqabsb_s8(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsh_s16() { - let a: i16 = -7; - let e: i16 = 7; - let r: i16 = vqabsh_s16(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabss_s32() { - let a: i32 = -7; - let e: i32 = 7; - let r: i32 = vqabss_s32(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsd_s64() { - let a: i64 = -7; - let e: i64 = 7; - let r: i64 = vqabsd_s64(a); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vslid_n_s64() { - let a: i64 = 333; - let b: i64 = 2042; - let e: i64 = 8169; - let r: i64 = vslid_n_s64::<2>(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vslid_n_u64() { - let a: u64 = 333; - let b: u64 = 2042; - let e: u64 = 8169; - let r: u64 = vslid_n_u64::<2>(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsrid_n_s64() { - let a: i64 = 333; - let b: i64 = 2042; - let e: i64 = 510; - let r: i64 = vsrid_n_s64::<2>(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsrid_n_u64() { - let a: u64 = 333; - let b: u64 = 2042; - let e: u64 = 510; - let r: u64 = vsrid_n_u64::<2>(a, b); - assert_eq!(r, e); - } +#[cfg_attr(all(test, not(target_env = "msvc")), assert_instr(zip2))] +pub unsafe fn vzip2q_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { + simd_shuffle!(a, b, [1, 3]) } diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index b8328887e6..e89067142b 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -1,3080 +1,4329 @@ // This code is automatically generated. DO NOT MODIFY. // -// Instead, modify `crates/stdarch-gen-arm/neon.spec` and run the following command to re-generate this file: +// Instead, modify `crates/stdarch-gen2/spec/` and run the following command to re-generate this file: // // ``` -// OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-arm -- crates/stdarch-gen-arm/neon.spec +// cargo run --bin=stdarch-gen2 -- crates/stdarch-gen2/spec // ``` -use super::*; +#![allow(improper_ctypes)] + #[cfg(test)] use stdarch_test::assert_instr; -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8) +use super::*; + +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + let d: int8x8_t = vabd_s8(b, c); + let e: uint8x8_t = simd_cast(d); + simd_add(a, simd_cast(e)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8) +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + let d: int16x4_t = vabd_s16(b, c); + let e: uint16x4_t = simd_cast(d); + simd_add(a, simd_cast(e)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16) +#[doc = "Signed Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + let d: int32x2_t = vabd_s32(b, c); + let e: uint32x2_t = simd_cast(d); + simd_add(a, simd_cast(e)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + let d: uint8x8_t = vabd_u8(b, c); + simd_add(a, simd_cast(d)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + let d: uint16x4_t = vabd_u16(b, c); + simd_add(a, simd_cast(d)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32) +#[doc = "Unsigned Absolute difference and Accumulate Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + let d: uint32x2_t = vabd_u32(b, c); + simd_add(a, simd_cast(d)) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8) +#[doc = "Absolute difference between the arguments of Floating"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fabd.v2f32" + )] + fn _vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vabd_f32(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8) +#[doc = "Absolute difference between the arguments of Floating"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fabd.v4f32" + )] + fn _vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vabdq_f32(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")] + fn _vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vabd_s8(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")] + fn _vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vabdq_s8(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")] + fn _vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vabd_s16(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")] + fn _vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vabdq_s16(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")] + fn _vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vabd_s32(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sabd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")] + fn _vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vabdq_s32(a, b) } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")] + fn _vabd_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vabd_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise and -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(and))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_and(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")] + fn _vabdq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vabdq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")] + fn _vabd_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vabd_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")] + fn _vabdq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vabdq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")] + fn _vabd_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vabd_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16) +#[doc = "Absolute difference between the arguments"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uabd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")] + fn _vabdq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vabdq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32) +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + let c: uint8x8_t = simd_cast(vabd_s8(a, b)); + simd_cast(c) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32) +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + let c: uint16x4_t = simd_cast(vabd_s16(a, b)); + simd_cast(c) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8) +#[doc = "Signed Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + let c: uint32x2_t = simd_cast(vabd_s32(a, b)); + simd_cast(c) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + simd_cast(vabd_u8(a, b)) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + simd_cast(vabd_u16(a, b)) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16) +#[doc = "Unsigned Absolute difference Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uabdl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + simd_cast(vabd_u32(a, b)) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32) +#[doc = "Floating-point absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { + simd_fabs(a) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32) +#[doc = "Floating-point absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { + simd_fabs(a) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + simd_xor(a, b) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + simd_xor(a, b) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + simd_xor(a, b) } -/// Vector bitwise or (immediate, inclusive) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(orr))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_or(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + simd_xor(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { simd_xor(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { simd_xor(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16) +#[doc = "Bitwise exclusive OR"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { + a ^ b } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_xor(a, b) -} - -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_and(a, b) } -/// Vector bitwise exclusive or (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(eor))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_xor(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_and(a, b) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v8i8")] - fn vabd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vabd_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_and(a, b) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v16i8")] - fn vabdq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vabdq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_and(a, b) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v4i16")] - fn vabd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vabd_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vand_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_and(a, b) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16) +#[doc = "Vector bitwise and"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v8i16")] - fn vabdq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vabdq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vand))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(and) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vandq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_and(a, b) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v2i32")] - fn vabd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.v2i32.v2f32" + )] + fn _vcage_f32(a: float32x2_t, b: float32x2_t) -> int32x2_t; } -vabd_s32_(a, b) + _vcage_f32(a, b).as_unsigned() } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32) +#[doc = "Floating-point absolute compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sabd.v4i32")] - fn vabdq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facge.v4i32.v4f32" + )] + fn _vcageq_f32(a: float32x4_t, b: float32x4_t) -> int32x4_t; } -vabdq_s32_(a, b) + _vcageq_f32(a, b).as_unsigned() } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v8i8")] - fn vabd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32" + )] + fn _vcagt_f32(a: float32x2_t, b: float32x2_t) -> int32x2_t; } -vabd_u8_(a, b) + _vcagt_f32(a, b).as_unsigned() } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8) +#[doc = "Floating-point absolute compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v16i8")] - fn vabdq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32" + )] + fn _vcagtq_f32(a: float32x4_t, b: float32x4_t) -> int32x4_t; } -vabdq_u8_(a, b) + _vcagtq_f32(a, b).as_unsigned() } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v4i16")] - fn vabd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vabd_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + vcage_f32(b, a) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16) +#[doc = "Floating-point absolute compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v8i16")] - fn vabdq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vabdq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + vcageq_f32(b, a) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v2i32")] - fn vabd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } -vabd_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + vcagt_f32(b, a) } -/// Absolute difference between the arguments -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32) +#[doc = "Floating-point absolute compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabdu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uabd.v4i32")] - fn vabdq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } -vabdq_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(facgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + vcagtq_f32(b, a) } -/// Absolute difference between the arguments of Floating -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fabd.v2f32")] - fn vabd_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vabd_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + simd_eq(a, b) } -/// Absolute difference between the arguments of Floating -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32) +#[doc = "Floating-point compare equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabd.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fabd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vabds.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fabd.v4f32")] - fn vabdq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vabdq_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + simd_eq(a, b) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - simd_cast(vabd_u8(a, b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + simd_eq(a, b) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - simd_cast(vabd_u16(a, b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + simd_eq(a, b) } -/// Unsigned Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - simd_cast(vabd_u32(a, b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + simd_eq(a, b) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - let c: uint8x8_t = simd_cast(vabd_s8(a, b)); - simd_cast(c) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + simd_eq(a, b) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - let c: uint16x4_t = simd_cast(vabd_s16(a, b)); - simd_cast(c) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + simd_eq(a, b) } -/// Signed Absolute difference Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabdl.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabdl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabdl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - let c: uint32x2_t = simd_cast(vabd_s32(a, b)); - simd_cast(c) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceq_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceqq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceq_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceqq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceq_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vceqq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceq_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8) +#[doc = "Compare bitwise Equal (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceqq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmeq) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { simd_eq(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceq_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_eq(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + simd_ge(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16) +#[doc = "Floating-point compare greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceqq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_eq(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + simd_ge(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceq_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_eq(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + simd_ge(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceqq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_eq(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + simd_ge(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_p8) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceq_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { - simd_eq(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + simd_ge(a, b) } -/// Compare bitwise Equal (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_p8) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceqq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { - simd_eq(a, b) -} - -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceq_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_eq(a, b) -} - -/// Floating-point compare equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vceq.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmeq))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vceqq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_eq(a, b) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - let c: int8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - let c: int8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - let c: int16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - let c: int16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - let c: int32x2_t = simd_and(a, b); - let d: i32x2 = i32x2::new(0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - let c: int32x4_t = simd_and(a, b); - let d: i32x4 = i32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { - let c: poly8x8_t = simd_and(a, b); - let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) -} - -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { - let c: poly8x16_t = simd_and(a, b); - let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + simd_ge(a, b) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { - let c: poly16x4_t = simd_and(a, b); - let d: i16x4 = i16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + simd_ge(a, b) } -/// Signed compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16) +#[doc = "Compare signed greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { - let c: poly16x8_t = simd_and(a, b); - let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - let c: uint8x8_t = simd_and(a, b); - let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - let c: uint8x16_t = simd_and(a, b); - let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - let c: uint16x4_t = simd_and(a, b); - let d: u16x4 = u16x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - let c: uint16x8_t = simd_and(a, b); - let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - let c: uint32x2_t = simd_and(a, b); - let d: u32x2 = u32x2::new(0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_ge(a, b) } -/// Unsigned compare bitwise Test bits nonzero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32) +#[doc = "Compare unsigned greater than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmtst))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - let c: uint32x4_t = simd_and(a, b); - let d: u32x4 = u32x4::new(0, 0, 0, 0); - simd_ne(c, transmute(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_ge(a, b) } -/// Floating-point absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabs_f32(a: float32x2_t) -> float32x2_t { - simd_fabs(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + simd_gt(a, b) } -/// Floating-point absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32) +#[doc = "Floating-point compare greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vabs))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabsq_f32(a: float32x4_t) -> float32x4_t { - simd_fabs(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { simd_gt(a, b) } -/// Compare signed greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32) +#[doc = "Compare signed greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { simd_gt(a, b) } -/// Compare unsigned greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32) +#[doc = "Compare unsigned greater than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcgtq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { simd_gt(a, b) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_gt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + simd_le(a, b) } -/// Floating-point compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32) +#[doc = "Floating-point compare less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_gt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + simd_le(a, b) } -/// Compare signed less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32) +#[doc = "Compare signed less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmge) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_le(a, b) } -/// Compare unsigned less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32) +#[doc = "Compare unsigned less than or equal"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhi))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_lt(a, b) -} - -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_le(a, b) } -/// Floating-point compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_lt(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v8i8" + )] + fn _vcls_s8(a: int8x8_t) -> int8x8_t; + } + _vcls_s8(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v16i8" + )] + fn _vclsq_s8(a: int8x16_t) -> int8x16_t; + } + _vclsq_s8(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v4i16" + )] + fn _vcls_s16(a: int16x4_t) -> int16x4_t; + } + _vcls_s16(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v8i16" + )] + fn _vclsq_s16(a: int16x8_t) -> int16x8_t; + } + _vclsq_s16(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v2i32" + )] + fn _vcls_s32(a: int32x2_t) -> int32x2_t; + } + _vcls_s32(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.cls.v4i32" + )] + fn _vclsq_s32(a: int32x4_t) -> int32x4_t; + } + _vclsq_s32(a) } -/// Compare signed less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { + vcls_s8(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { + vclsq_s8(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { + vcls_s16(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { + vclsq_s16(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { + vcls_s32(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32) +#[doc = "Count leading sign bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { + vclsq_s32(transmute(a)) } -/// Compare unsigned less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { + simd_lt(a, b) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32) +#[doc = "Floating-point compare less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcle_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { + simd_lt(a, b) } -/// Floating-point compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_le(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32) +#[doc = "Compare signed less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmgt) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + simd_lt(a, b) } -/// Compare signed greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclt_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32) +#[doc = "Compare unsigned less than"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcgt.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmhi) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcltq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_lt(a, b) } -/// Compare unsigned greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cmhs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { + vclz_s16_(a) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcge_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { + vclzq_s16_(a) } -/// Floating-point compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcmge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcgeq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - simd_ge(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { + vclz_s32_(a) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_s8(a: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v8i8")] - fn vcls_s8_(a: int8x8_t) -> int8x8_t; - } -vcls_s8_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { + vclzq_s32_(a) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_s8(a: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v16i8")] - fn vclsq_s8_(a: int8x16_t) -> int8x16_t; - } -vclsq_s8_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { + vclz_s8_(a) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_s16(a: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v4i16")] - fn vcls_s16_(a: int16x4_t) -> int16x4_t; - } -vcls_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { + vclzq_s8_(a) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_s16(a: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v8i16")] - fn vclsq_s16_(a: int16x8_t) -> int16x8_t; - } -vclsq_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { + transmute(vclz_s16_(transmute(a))) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_s32(a: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v2i32")] - fn vcls_s32_(a: int32x2_t) -> int32x2_t; - } -vcls_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { + transmute(vclzq_s16_(transmute(a))) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vcls.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_s32(a: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcls.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.cls.v4i32")] - fn vclsq_s32_(a: int32x4_t) -> int32x4_t; - } -vclsq_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { + transmute(vclz_s32_(transmute(a))) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u8) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_u8(a: uint8x8_t) -> int8x8_t { - vcls_s8(transmute(a)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { + transmute(vclzq_s32_(transmute(a))) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u8) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_u8(a: uint8x16_t) -> int8x16_t { - vclsq_s8(transmute(a)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { + transmute(vclz_s8_(transmute(a))) } -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_u16(a: uint16x4_t) -> int16x4_t { - vcls_s16(transmute(a)) -} - -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_u16(a: uint16x8_t) -> int16x8_t { - vclsq_s16(transmute(a)) -} - -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcls_u32(a: uint32x2_t) -> int32x2_t { - vcls_s32(transmute(a)) -} - -/// Count leading sign bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcls))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(cls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclsq_u32(a: uint32x4_t) -> int32x4_t { - vclsq_s32(transmute(a)) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_s8(a: int8x8_t) -> int8x8_t { - vclz_s8_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclzq_s8(a: int8x16_t) -> int8x16_t { - vclzq_s8_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_s16(a: int16x4_t) -> int16x4_t { - vclz_s16_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclzq_s16(a: int16x8_t) -> int16x8_t { - vclzq_s16_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_s32(a: int32x2_t) -> int32x2_t { - vclz_s32_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclzq_s32(a: int32x4_t) -> int32x4_t { - vclzq_s32_(a) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_u8(a: uint8x8_t) -> uint8x8_t { - transmute(vclz_s8_(transmute(a))) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8) +#[doc = "Count leading zero bits"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(clz) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vclzq_u8(a: uint8x16_t) -> uint8x16_t { transmute(vclzq_s8_(transmute(a))) } -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_u16(a: uint16x4_t) -> uint16x4_t { - transmute(vclz_s16_(transmute(a))) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclzq_u16(a: uint16x8_t) -> uint16x8_t { - transmute(vclzq_s16_(transmute(a))) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclz_u32(a: uint32x2_t) -> uint32x2_t { - transmute(vclz_s32_(transmute(a))) -} - -/// Count leading zero bits -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vclz.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(clz))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vclzq_u32(a: uint32x4_t) -> uint32x4_t { - transmute(vclzq_s32_(transmute(a))) -} - -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcagt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v2i32.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.v2i32.v2f32")] - fn vcagt_f32_(a: float32x2_t, b: float32x2_t) -> uint32x2_t; - } -vcagt_f32_(a, b) -} - -/// Floating-point absolute compare greater than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcagtq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacgt.v4i32.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facgt.v4i32.v4f32")] - fn vcagtq_f32_(a: float32x4_t, b: float32x4_t) -> uint32x4_t; - } -vcagtq_f32_(a, b) -} - -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcage_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v2i32.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.v2i32.v2f32")] - fn vcage_f32_(a: float32x2_t, b: float32x2_t) -> uint32x2_t; - } -vcage_f32_(a, b) -} - -/// Floating-point absolute compare greater than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcageq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vacge.v4i32.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.facge.v4i32.v4f32")] - fn vcageq_f32_(a: float32x4_t, b: float32x4_t) -> uint32x4_t; - } -vcageq_f32_(a, b) -} - -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcalt_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - vcagt_f32(b, a) -} - -/// Floating-point absolute compare less than -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacgt.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facgt))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcaltq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - vcagtq_f32(b, a) -} - -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcale_f32(a: float32x2_t, b: float32x2_t) -> uint32x2_t { - vcage_f32(b, a) -} - -/// Floating-point absolute compare less than or equal -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vacge.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(facge))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcaleq_f32(a: float32x4_t, b: float32x4_t) -> uint32x4_t { - vcageq_f32(b, a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { + transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_s8(a: u64) -> int8x8_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_s16(a: u64) -> int16x4_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_s32(a: u64) -> int32x2_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_s64(a: u64) -> int64x1_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_u8(a: u64) -> uint8x8_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_u16(a: u64) -> uint16x4_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_u32(a: u64) -> uint32x2_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_u64(a: u64) -> uint64x1_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_p8(a: u64) -> poly8x8_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_p16(a: u64) -> poly16x4_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcreate_p64(a: u64) -> poly64x1_t { transmute(a) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcreate_f32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vcreate_f32(a: u64) -> float32x2_t { - transmute(a) -} - -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(scvtf))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(scvtf) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvt_f32_s32(a: int32x2_t) -> float32x2_t { simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(scvtf))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(scvtf) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvtq_f32_s32(a: int32x4_t) -> float32x4_t { simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ucvtf))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ucvtf) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvt_f32_u32(a: uint32x2_t) -> float32x2_t { simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ucvtf))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ucvtf) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { simd_cast(a) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -3083,36 +4332,20 @@ pub unsafe fn vcvtq_f32_u32(a: uint32x4_t) -> float32x4_t { #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32")] - fn vcvt_n_f32_s32_(a: int32x2_t, n: i32) -> float32x2_t; - } -vcvt_n_f32_s32_(a, N) -} - -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32) -#[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(scvtf, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32")] - fn vcvt_n_f32_s32_(a: int32x2_t, n: i32) -> float32x2_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfxs2fp.v2f32.v2i32" + )] + fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t; } -vcvt_n_f32_s32_(a, N) + _vcvt_n_f32_s32(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -3121,74 +4354,86 @@ vcvt_n_f32_s32_(a, N) #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32")] - fn vcvtq_n_f32_s32_(a: int32x4_t, n: i32) -> float32x4_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfxs2fp.v4f32.v4i32" + )] + fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t; } -vcvtq_n_f32_s32_(a, N) + _vcvtq_n_f32_s32(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { +pub unsafe fn vcvt_n_f32_s32(a: int32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32")] - fn vcvtq_n_f32_s32_(a: int32x4_t, n: i32) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.v2f32.v2i32" + )] + fn _vcvt_n_f32_s32(a: int32x2_t, n: i32) -> float32x2_t; } -vcvtq_n_f32_s32_(a, N) + _vcvt_n_f32_s32(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vcvt, N = 2))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(scvtf, N = 2))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_f32_s32(a: int32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32")] - fn vcvt_n_f32_u32_(a: uint32x2_t, n: i32) -> float32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxs2fp.v4f32.v4i32" + )] + fn _vcvtq_n_f32_s32(a: int32x4_t, n: i32) -> float32x4_t; } -vcvt_n_f32_u32_(a, N) + _vcvtq_n_f32_s32(a, N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ucvtf, N = 2))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32")] - fn vcvt_n_f32_u32_(a: uint32x2_t, n: i32) -> float32x2_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfxu2fp.v2f32.v2i32" + )] + fn _vcvt_n_f32_u32(a: int32x2_t, n: i32) -> float32x2_t; } -vcvt_n_f32_u32_(a, N) + _vcvt_n_f32_u32(a.as_signed(), N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -3197,74 +4442,86 @@ vcvt_n_f32_u32_(a, N) #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32")] - fn vcvtq_n_f32_u32_(a: uint32x4_t, n: i32) -> float32x4_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfxu2fp.v4f32.v4i32" + )] + fn _vcvtq_n_f32_u32(a: int32x4_t, n: i32) -> float32x4_t; } -vcvtq_n_f32_u32_(a, N) + _vcvtq_n_f32_u32(a.as_signed(), N) } -/// Fixed-point convert to floating-point -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { +pub unsafe fn vcvt_n_f32_u32(a: uint32x2_t) -> float32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32")] - fn vcvtq_n_f32_u32_(a: uint32x4_t, n: i32) -> float32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.v2f32.v2i32" + )] + fn _vcvt_n_f32_u32(a: int32x2_t, n: i32) -> float32x2_t; } -vcvtq_n_f32_u32_(a, N) + _vcvt_n_f32_u32(a.as_signed(), N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32) +#[doc = "Fixed-point convert to floating-point"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vcvt, N = 2))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ucvtf, N = 2))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_f32_u32(a: uint32x4_t) -> float32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32")] - fn vcvt_n_s32_f32_(a: float32x2_t, n: i32) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfxu2fp.v4f32.v4i32" + )] + fn _vcvtq_n_f32_u32(a: int32x4_t, n: i32) -> float32x4_t; } -vcvt_n_s32_f32_(a, N) + _vcvtq_n_f32_u32(a.as_signed(), N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32")] - fn vcvt_n_s32_f32_(a: float32x2_t, n: i32) -> int32x2_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfp2fxs.v2i32.v2f32" + )] + fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t; } -vcvt_n_s32_f32_(a, N) + _vcvt_n_s32_f32(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -3273,74 +4530,86 @@ vcvt_n_s32_f32_(a, N) #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32")] - fn vcvtq_n_s32_f32_(a: float32x4_t, n: i32) -> int32x4_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfp2fxs.v4i32.v4f32" + )] + fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t; } -vcvtq_n_s32_f32_(a, N) + _vcvtq_n_s32_f32(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { +pub unsafe fn vcvt_n_s32_f32(a: float32x2_t) -> int32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32")] - fn vcvtq_n_s32_f32_(a: float32x4_t, n: i32) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.v2i32.v2f32" + )] + fn _vcvt_n_s32_f32(a: float32x2_t, n: i32) -> int32x2_t; } -vcvtq_n_s32_f32_(a, N) + _vcvt_n_s32_f32(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vcvt, N = 2))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(fcvtzs, N = 2))] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvtq_n_s32_f32(a: float32x4_t) -> int32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32")] - fn vcvt_n_u32_f32_(a: float32x2_t, n: i32) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxs.v4i32.v4f32" + )] + fn _vcvtq_n_s32_f32(a: float32x4_t, n: i32) -> int32x4_t; } -vcvt_n_u32_f32_(a, N) + _vcvtq_n_s32_f32(a, N) } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vcvt, N = 2))] #[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32")] - fn vcvt_n_u32_f32_(a: float32x2_t, n: i32) -> uint32x2_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfp2fxu.v2i32.v2f32" + )] + fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> int32x2_t; } -vcvt_n_u32_f32_(a, N) + _vcvt_n_u32_f32(a, N).as_unsigned() } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] @@ -3349,1087 +4618,2110 @@ vcvt_n_u32_f32_(a, N) #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32")] - fn vcvtq_n_u32_f32_(a: float32x4_t, n: i32) -> uint32x4_t; + #[cfg_attr( + target_arch = "arm", + link_name = "llvm.arm.neon.vcvtfp2fxu.v4i32.v4f32" + )] + fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> int32x4_t; } -vcvtq_n_u32_f32_(a, N) + _vcvtq_n_u32_f32(a, N).as_unsigned() } -/// Floating-point convert to fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32) +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_n_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] +#[target_feature(enable = "neon")] #[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(fcvtzu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vcvt_n_u32_f32(a: float32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.v2i32.v2f32" + )] + fn _vcvt_n_u32_f32(a: float32x2_t, n: i32) -> int32x2_t; + } + _vcvt_n_u32_f32(a, N).as_unsigned() +} + +#[doc = "Floating-point convert to fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_n_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] #[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[cfg_attr(test, assert_instr(fcvtzu, N = 2))] #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtq_n_u32_f32(a: float32x4_t) -> uint32x4_t { static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32")] - fn vcvtq_n_u32_f32_(a: float32x4_t, n: i32) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.vcvtfp2fxu.v4i32.v4f32" + )] + fn _vcvtq_n_u32_f32(a: float32x4_t, n: i32) -> int32x4_t; } -vcvtq_n_u32_f32_(a, N) + _vcvtq_n_u32_f32(a, N).as_unsigned() } -/// Floating-point convert to signed fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32) +#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcvtzs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcvtzs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvt_s32_f32(a: float32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v2i32.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptosi.sat.v2i32.v2f32")] - fn vcvt_s32_f32_(a: float32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptosi.sat.v2i32.v2f32" + )] + fn _vcvt_s32_f32(a: float32x2_t) -> int32x2_t; } -vcvt_s32_f32_(a) + _vcvt_s32_f32(a) } -/// Floating-point convert to signed fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32) +#[doc = "Floating-point convert to signed fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcvtzs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcvtzs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvtq_s32_f32(a: float32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptosi.sat.v4i32.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptosi.sat.v4i32.v4f32")] - fn vcvtq_s32_f32_(a: float32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptosi.sat.v4i32.v4f32" + )] + fn _vcvtq_s32_f32(a: float32x4_t) -> int32x4_t; } -vcvtq_s32_f32_(a) + _vcvtq_s32_f32(a) } -/// Floating-point convert to unsigned fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32) +#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcvtzu))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcvtzu) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvt_u32_f32(a: float32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v2i32.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptoui.sat.v2i32.v2f32")] - fn vcvt_u32_f32_(a: float32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptoui.sat.v2i32.v2f32" + )] + fn _vcvt_u32_f32(a: float32x2_t) -> int32x2_t; } -vcvt_u32_f32_(a) + _vcvt_u32_f32(a).as_unsigned() } -/// Floating-point convert to unsigned fixed-point, rounding toward zero -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32) +#[doc = "Floating-point convert to unsigned fixed-point, rounding toward zero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vcvt))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fcvtzu))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fcvtzu) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vcvtq_u32_f32(a: float32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.fptoui.sat.v4i32.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fptoui.sat.v4i32.v4f32")] - fn vcvtq_u32_f32_(a: float32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.fptoui.sat.v4i32.v4f32" + )] + fn _vcvtq_u32_f32(a: float32x4_t) -> int32x4_t; + } + _vcvtq_u32_f32(a).as_unsigned() +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_s32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdotq_lane_s32( + a: int32x4_t, + b: int8x16_t, + c: int8x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = transmute(c); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_s32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdot_lane_u32( + a: uint32x2_t, + b: uint8x8_t, + c: uint8x8_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: uint32x2_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vdot_u32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (indexed)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdotq_lane_u32( + a: uint32x4_t, + b: uint8x16_t, + c: uint8x8_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: uint32x2_t = transmute(c); + let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vdotq_u32(a, b, transmute(c)) +} + +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8" + )] + fn _vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; + } + _vdot_s32(a, b, c) +} + +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8" + )] + fn _vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; } -vcvtq_u32_f32_(a) + _vdotq_s32(a, b, c) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8) +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v2i32.v8i8" + )] + fn _vdot_u32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; + } + _vdot_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() +} + +#[doc = "Dot product arithmetic (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,dotprod")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(udot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_dotprod", issue = "117224") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.udot.v4i32.v16i8" + )] + fn _vdotq_u32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; + } + _vdotq_u32(a.as_signed(), b.as_signed(), c.as_signed()).as_unsigned() +} + +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(N, 1); + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_s32(a: int32x2_t) -> int32x2_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 1); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(N, 3); +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32]) + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] pub unsafe fn vdupq_lane_s16(a: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_s32(a: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_s8(a: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_u8(a: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_u32(a: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_s8(a: int8x8_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 0) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N == 0); + a } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 0) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N == 0); + a } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_u8(a: uint8x8_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_s32(a: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_u16(a: uint16x4_t) -> uint16x8_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_u32(a: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_u32(a: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 1); +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_p8(a: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_p16(a: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 3); simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_s16(a: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 8))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { - static_assert_uimm_bits!(N, 4); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_u16(a: uint16x8_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_p16(a: poly16x8_t) -> poly16x4_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_p16(a: poly16x8_t) -> poly16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p8) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 4))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_p8(a: poly8x8_t) -> poly8x16_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_s16(a: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(N, 3); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_p16) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.16", N = 4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 4) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_p16(a: poly16x4_t) -> poly16x8_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 3); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_p8(a: poly8x16_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { - static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_s8(a: int8x16_t) -> int8x8_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_u8(a: uint8x16_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { - static_assert!(N == 0); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_p8(a: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_f32(a: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.8", N = 8))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 8) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_laneq_f32(a: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + simd_shuffle!( + a, + a, + [ + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, + N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32 + ] + ) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 2))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_f32(a: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(N, 2); - simd_shuffle!(a, a, [N as u32, N as u32]) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { + static_assert_uimm_bits!(N, 1); + transmute::(simd_extract!(a, N as u32)) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vdup.32", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(dup, N = 1))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdupq_lane_f32(a: float32x2_t) -> float32x4_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { static_assert_uimm_bits!(N, 1); - simd_shuffle!(a, a, [N as u32, N as u32, N as u32, N as u32]) + transmute::(simd_extract!(a, N as u32)) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 0) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_s64(a: int64x1_t) -> int64x1_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_s64(a: int64x1_t) -> int64x2_t { static_assert!(N == 0); - a + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, N = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, N = 0))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 0) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_lane_u64(a: uint64x1_t) -> uint64x1_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_lane_u64(a: uint64x1_t) -> uint64x2_t { static_assert!(N == 0); - a + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_s64(a: int64x2_t) -> int64x1_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_s64(a: int64x2_t) -> int64x2_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Set all vector lanes to the same value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u64) +#[doc = "Set all vector lanes to the same value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(dup, N = 1) +)] #[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdup_laneq_u64(a: uint64x2_t) -> uint64x1_t { +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vdupq_laneq_u64(a: uint64x2_t) -> uint64x2_t { static_assert_uimm_bits!(N, 1); - transmute::(simd_extract!(a, N as u32)) + simd_shuffle!(a, a, [N as u32, N as u32]) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 15))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), - 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), - 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), - 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), - 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), - 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), - 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), - 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), - 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 15))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), - 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), - 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), - 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), - 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), - 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), - 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), - 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), - 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), - _ => unreachable_unchecked(), - } +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_xor(a, b) } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16) +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 3); - match N & 0b111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veor_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_xor(a, b) +} + +#[doc = "Vector bitwise exclusive or (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(veor))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(eor) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn veorq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_xor(a, b) +} + +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), @@ -4438,40 +6730,58 @@ pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), @@ -4486,74 +6796,100 @@ pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 15))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(N, 4); - match N & 0b1111 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), - 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), - 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), - 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), - 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), - 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), - 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), - 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), - 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), - 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), - 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), - 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), - 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 3); + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(N, 2); - match N & 0b11 { - 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), - 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), - 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), - 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 7))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), @@ -4568,78 +6904,132 @@ pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_ } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(N, 3); + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 7))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 7) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(N, 3); + match N & 0b111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), + 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), + 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), + 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), + 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vext_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(N, 1); - match N & 0b1 { - 0 => simd_shuffle!(a, b, [0, 1]), - 1 => simd_shuffle!(a, b, [1, 2]), +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(N, 2); + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), } } -/// Extract vector from pair of vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ext, N = 3))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), @@ -4650,42284 +7040,42844 @@ pub unsafe fn vextq_f32(a: float32x4_t, b: float32x4_t) -> float32 } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 2); + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 2); + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 3) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vext_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(N, 2); + match N & 0b11 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), + 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), + 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), + 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - simd_add(a, simd_mul(b, c)) -} - -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmov, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 1); + match N & 0b1 { + 0 => simd_shuffle!(a, b, [0, 1]), + 1 => simd_shuffle!(a, b, [1, 2]), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 4); + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 4); + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16) +#[doc = "Extract vector from pair of vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vext.8", N = 15))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ext, N = 15) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vextq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(N, 4); + match N & 0b1111 { + 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), + 1 => simd_shuffle!( + a, + b, + [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16] + ), + 2 => simd_shuffle!( + a, + b, + [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17] + ), + 3 => simd_shuffle!( + a, + b, + [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18] + ), + 4 => simd_shuffle!( + a, + b, + [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19] + ), + 5 => simd_shuffle!( + a, + b, + [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20] + ), + 6 => simd_shuffle!( + a, + b, + [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21] + ), + 7 => simd_shuffle!( + a, + b, + [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22] + ), + 8 => simd_shuffle!( + a, + b, + [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23] + ), + 9 => simd_shuffle!( + a, + b, + [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24] + ), + 10 => simd_shuffle!( + a, + b, + [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25] + ), + 11 => simd_shuffle!( + a, + b, + [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26] + ), + 12 => simd_shuffle!( + a, + b, + [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27] + ), + 13 => simd_shuffle!( + a, + b, + [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28] + ), + 14 => simd_shuffle!( + a, + b, + [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29] + ), + 15 => simd_shuffle!( + a, + b, + [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30] + ), + _ => unreachable_unchecked(), + } } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v2f32")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")] + fn _vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; + } + _vfma_f32(b, c, a) } -/// Multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "aarch64", link_name = "llvm.fma.v4f32")] + #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")] + fn _vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; + } + _vfmaq_f32(b, c, a) } -/// Floating-point multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfma_f32(a, b, vdup_n_f32_vfp4(c)) } -/// Floating-point multiply-add to accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32) +#[doc = "Floating-point fused Multiply-Add to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - simd_add(a, simd_mul(b, c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16) +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { - vmla_s16(a, b, vdup_n_s16(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + let b: float32x2_t = simd_neg(b); + vfma_f32(a, b, c) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16) +#[doc = "Floating-point fused multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { - vmlaq_s16(a, b, vdupq_n_s16(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + let b: float32x4_t = simd_neg(b); + vfmaq_f32(a, b, c) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32) +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { - vmla_s32(a, b, vdup_n_s32(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vfms_f32(a, b, vdup_n_f32_vfp4(c)) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32) +#[doc = "Floating-point fused Multiply-subtract to accumulator(vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { - vmlaq_s32(a, b, vdupq_n_s32(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { - vmla_u16(a, b, vdup_n_u16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] + fn _vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vhadd_s8(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { - vmlaq_u16(a, b, vdupq_n_u16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] + fn _vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vhaddq_s8(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { - vmla_u32(a, b, vdup_n_u32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] + fn _vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vhadd_s16(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { - vmlaq_u32(a, b, vdupq_n_u32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] + fn _vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vhaddq_s16(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vmla_f32(a, b, vdup_n_f32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] + fn _vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vhadd_s32(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vmlaq_f32(a, b, vdupq_n_f32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] + fn _vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vhaddq_s32(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - vmla_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] + fn _vhadd_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vhadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - vmla_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] + fn _vhaddq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vhaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - vmlaq_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] + fn _vhadd_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vhadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - vmlaq_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] + fn _vhaddq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vhaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] + fn _vhadd_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vhadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32) +#[doc = "Halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] + fn _vhaddq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vhaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlaq_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] + fn _vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vhsub_s16(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlaq_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] + fn _vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vhsubq_s16(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - vmla_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] + fn _vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vhsub_s32(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - vmla_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] + fn _vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vhsubq_s32(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - vmlaq_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] + fn _vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vhsub_s8(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - vmlaq_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) -} - -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.shsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] + fn _vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vhsubq_s8(a, b) } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] + fn _vhsub_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vhsub_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlaq_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] + fn _vhsubq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vhsubq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mla, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlaq_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] + fn _vhsub_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vhsub_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] + fn _vhsubq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vhsubq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmla_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] + fn _vhsub_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vhsub_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32) +#[doc = "Signed halving subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlaq_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uhsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uhsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] + fn _vhsubq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vhsubq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Vector multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlaq_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlaq_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0f32")] + fn _vld1_f32_x2(a: *const f32) -> float32x2x2_t; + } + _vld1_f32_x2(a) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - simd_add(a, vmull_s8(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0f32")] + fn _vld1_f32_x3(a: *const f32) -> float32x2x3_t; + } + _vld1_f32_x3(a) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - simd_add(a, vmull_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0f32")] + fn _vld1_f32_x4(a: *const f32) -> float32x2x4_t; + } + _vld1_f32_x4(a) } -/// Signed multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - simd_add(a, vmull_s32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0f32")] + fn _vld1q_f32_x2(a: *const f32) -> float32x4x2_t; + } + _vld1q_f32_x2(a) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - simd_add(a, vmull_u8(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0f32")] + fn _vld1q_f32_x3(a: *const f32) -> float32x4x3_t; + } + _vld1q_f32_x3(a) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - simd_add(a, vmull_u16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0f32")] + fn _vld1q_f32_x4(a: *const f32) -> float32x4x4_t; + } + _vld1q_f32_x4(a) } -/// Unsigned multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - simd_add(a, vmull_u32(b, c)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { + transmute(vld1_s64_x2(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vmlal_s16(a, b, vdup_n_s16(c)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { + transmute(vld1_s64_x3(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vmlal_s32(a, b, vdup_n_s32(c)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { + transmute(vld1_s64_x4(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { - vmlal_u16(a, b, vdup_n_u16(c)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { + transmute(vld1q_s64_x2(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { - vmlal_u32(a, b, vdup_n_u32(c)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { + transmute(vld1q_s64_x3(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { + transmute(vld1q_s64_x4(transmute(a))) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlal_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0i8")] + fn _vld1_s8_x2(a: *const i8) -> int8x8x2_t; + } + _vld1_s8_x2(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0i8")] + fn _vld1_s8_x3(a: *const i8) -> int8x8x3_t; + } + _vld1_s8_x3(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0i8")] + fn _vld1_s8_x4(a: *const i8) -> int8x8x4_t; + } + _vld1_s8_x4(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0i8")] + fn _vld1q_s8_x2(a: *const i8) -> int8x16x2_t; + } + _vld1q_s8_x2(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlal_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0i8")] + fn _vld1q_s8_x3(a: *const i8) -> int8x16x3_t; + } + _vld1q_s8_x3(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0i8")] + fn _vld1q_s8_x4(a: *const i8) -> int8x16x4_t; + } + _vld1q_s8_x4(a) } -/// Vector widening multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlal, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlal_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0i16")] + fn _vld1_s16_x2(a: *const i16) -> int16x4x2_t; + } + _vld1_s16_x2(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0i16")] + fn _vld1_s16_x3(a: *const i16) -> int16x4x3_t; + } + _vld1_s16_x3(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0i16")] + fn _vld1_s16_x4(a: *const i16) -> int16x4x4_t; + } + _vld1_s16_x4(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0i16")] + fn _vld1q_s16_x2(a: *const i16) -> int16x8x2_t; + } + _vld1q_s16_x2(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0i16")] + fn _vld1q_s16_x3(a: *const i16) -> int16x8x3_t; + } + _vld1q_s16_x3(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0i16")] + fn _vld1q_s16_x4(a: *const i16) -> int16x8x4_t; + } + _vld1q_s16_x4(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0i32")] + fn _vld1_s32_x2(a: *const i32) -> int32x2x2_t; + } + _vld1_s32_x2(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0i32")] + fn _vld1_s32_x3(a: *const i32) -> int32x2x3_t; + } + _vld1_s32_x3(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0i32")] + fn _vld1_s32_x4(a: *const i32) -> int32x2x4_t; + } + _vld1_s32_x4(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0i32")] + fn _vld1q_s32_x2(a: *const i32) -> int32x4x2_t; + } + _vld1q_s32_x2(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0i32")] + fn _vld1q_s32_x3(a: *const i32) -> int32x4x3_t; + } + _vld1q_s32_x3(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0i32")] + fn _vld1q_s32_x4(a: *const i32) -> int32x4x4_t; + } + _vld1q_s32_x4(a) } -/// Multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0i64")] + fn _vld1_s64_x2(a: *const i64) -> int64x1x2_t; + } + _vld1_s64_x2(a) } -/// Floating-point multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0i64")] + fn _vld1_s64_x3(a: *const i64) -> int64x1x3_t; + } + _vld1_s64_x3(a) } -/// Floating-point multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - simd_sub(a, simd_mul(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0i64")] + fn _vld1_s64_x4(a: *const i64) -> int64x1x4_t; + } + _vld1_s64_x4(a) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { - vmls_s16(a, b, vdup_n_s16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0i64")] + fn _vld1q_s64_x2(a: *const i64) -> int64x2x2_t; + } + _vld1q_s64_x2(a) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { - vmlsq_s16(a, b, vdupq_n_s16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0i64")] + fn _vld1q_s64_x3(a: *const i64) -> int64x2x3_t; + } + _vld1q_s64_x3(a) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { - vmls_s32(a, b, vdup_n_s32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0i64")] + fn _vld1q_s64_x4(a: *const i64) -> int64x2x4_t; + } + _vld1q_s64_x4(a) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { - vmlsq_s32(a, b, vdupq_n_s32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { + transmute(vld1_s8_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { - vmls_u16(a, b, vdup_n_u16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { + transmute(vld1_s8_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { - vmlsq_u16(a, b, vdupq_n_u16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { + transmute(vld1_s8_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { - vmls_u32(a, b, vdup_n_u32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { + transmute(vld1q_s8_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { - vmlsq_u32(a, b, vdupq_n_u32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { + transmute(vld1q_s8_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vmls_f32(a, b, vdup_n_f32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { + transmute(vld1q_s8_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vmlsq_f32(a, b, vdupq_n_f32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { + transmute(vld1_s16_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - vmls_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { + transmute(vld1_s16_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_laneq_s16(a: int16x4_t, b: int16x4_t, c: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - vmls_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { + transmute(vld1_s16_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - vmlsq_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { + transmute(vld1q_s16_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_laneq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - vmlsq_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { + transmute(vld1q_s16_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { + transmute(vld1q_s16_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_laneq_s32(a: int32x2_t, b: int32x2_t, c: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { + transmute(vld1_s32_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlsq_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { + transmute(vld1_s32_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_laneq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsq_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { + transmute(vld1_s32_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_lane_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - vmls_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { + transmute(vld1q_s32_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_laneq_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - vmls_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { + transmute(vld1q_s32_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_lane_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - vmlsq_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { + transmute(vld1q_s32_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_laneq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - vmlsq_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { + transmute(vld1_s64_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_lane_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { + transmute(vld1_s64_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_laneq_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { + transmute(vld1_s64_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_lane_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlsq_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { + transmute(vld1q_s64_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mls, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_laneq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsq_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { + transmute(vld1q_s64_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { + transmute(vld1q_s64_x4(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmls_laneq_f32(a: float32x2_t, b: float32x2_t, c: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { + transmute(vld1_s8_x2(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - vmlsq_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { + transmute(vld1_s8_x3(transmute(a))) } -/// Vector multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsq_laneq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsq_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { + transmute(vld1_s8_x4(transmute(a))) } -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - simd_sub(a, vmull_s8(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { + transmute(vld1q_s8_x2(transmute(a))) } -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - simd_sub(a, vmull_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { + transmute(vld1q_s8_x3(transmute(a))) } -/// Signed multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - simd_sub(a, vmull_s32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { + transmute(vld1q_s8_x4(transmute(a))) } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - simd_sub(a, vmull_u8(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { + transmute(vld1_s16_x2(transmute(a))) } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - simd_sub(a, vmull_u16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { + transmute(vld1_s16_x3(transmute(a))) } -/// Unsigned multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - simd_sub(a, vmull_u32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { + transmute(vld1_s16_x4(transmute(a))) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vmlsl_s16(a, b, vdup_n_s16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { + transmute(vld1q_s16_x2(transmute(a))) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vmlsl_s32(a, b, vdup_n_s32(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { + transmute(vld1q_s16_x3(transmute(a))) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16) +#[doc = "Load multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { - vmlsl_u16(a, b, vdup_n_u16(c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { + transmute(vld1q_s16_x4(transmute(a))) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { - vmlsl_u32(a, b, vdup_n_u32(c)) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0i8")] + fn _vld2_dup_f32(ptr: *const i8, size: i32) -> float32x2x2_t; + } + _vld2_dup_f32(a as *const i8, 4) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0i8")] + fn _vld2q_dup_f32(ptr: *const i8, size: i32) -> float32x4x2_t; + } + _vld2q_dup_f32(a as *const i8, 4) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_laneq_s16(a: int32x4_t, b: int16x4_t, c: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlsl_s16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0i8")] + fn _vld2_dup_s8(ptr: *const i8, size: i32) -> int8x8x2_t; + } + _vld2_dup_s8(a as *const i8, 1) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0i8")] + fn _vld2q_dup_s8(ptr: *const i8, size: i32) -> int8x16x2_t; + } + _vld2q_dup_s8(a as *const i8, 1) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_laneq_s32(a: int64x2_t, b: int32x2_t, c: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0i8")] + fn _vld2_dup_s16(ptr: *const i8, size: i32) -> int16x4x2_t; + } + _vld2_dup_s16(a as *const i8, 2) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_lane_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0i8")] + fn _vld2q_dup_s16(ptr: *const i8, size: i32) -> int16x8x2_t; + } + _vld2q_dup_s16(a as *const i8, 2) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_laneq_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmlsl_u16(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0i8")] + fn _vld2_dup_s32(ptr: *const i8, size: i32) -> int32x2x2_t; + } + _vld2_dup_s32(a as *const i8, 4) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_lane_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0i8")] + fn _vld2q_dup_s32(ptr: *const i8, size: i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as *const i8, 4) } -/// Vector widening multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umlsl, LANE = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmlsl_laneq_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2f32.p0f32" + )] + fn _vld2_dup_f32(ptr: *const f32) -> float32x2x2_t; + } + _vld2_dup_f32(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4f32.p0f32" + )] + fn _vld2q_dup_f32(ptr: *const f32) -> float32x4x2_t; + } + _vld2q_dup_f32(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i8.p0i8" + )] + fn _vld2_dup_s8(ptr: *const i8) -> int8x8x2_t; + } + _vld2_dup_s8(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v16i8.p0i8" + )] + fn _vld2q_dup_s8(ptr: *const i8) -> int8x16x2_t; + } + _vld2q_dup_s8(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i16.p0i16" + )] + fn _vld2_dup_s16(ptr: *const i16) -> int16x4x2_t; + } + _vld2_dup_s16(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v8i16.p0i16" + )] + fn _vld2q_dup_s16(ptr: *const i16) -> int16x8x2_t; + } + _vld2q_dup_s16(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(neg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v2i32.p0i32" + )] + fn _vld2_dup_s32(ptr: *const i32) -> int32x2x2_t; + } + _vld2_dup_s32(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { - simd_neg(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v4i32.p0i32" + )] + fn _vld2q_dup_s32(ptr: *const i32) -> int32x4x2_t; + } + _vld2q_dup_s32(a as _) } -/// Negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { - simd_neg(a) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v8i8")] - fn vqneg_s8_(a: int8x8_t) -> int8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0i8")] + fn _vld2_dup_s64(ptr: *const i8, size: i32) -> int64x1x2_t; } -vqneg_s8_(a) + _vld2_dup_s64(a as *const i8, 8) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2r))] +pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v16i8")] - fn vqnegq_s8_(a: int8x16_t) -> int8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2r.v1i64.p0i64" + )] + fn _vld2_dup_s64(ptr: *const i64) -> int64x1x2_t; } -vqnegq_s8_(a) + _vld2_dup_s64(a as _) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v4i16")] - fn vqneg_s16_(a: int16x4_t) -> int16x4_t; - } -vqneg_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_dup_s64(transmute(a))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v8i16")] - fn vqnegq_s16_(a: int16x8_t) -> int16x8_t; - } -vqnegq_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v2i32")] - fn vqneg_s32_(a: int32x2_t) -> int32x2_t; - } -vqneg_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -/// Signed saturating negate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqneg))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqneg.v4i32")] - fn vqnegq_s32_(a: int32x4_t) -> int32x4_t; - } -vqnegq_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v8i8")] - fn vqsub_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } -vqsub_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v16i8")] - fn vqsubq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } -vqsubq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_dup_s32(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v4i16")] - fn vqsub_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vqsub_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_dup_s32(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v8i16")] - fn vqsubq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vqsubq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_dup_s8(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v2i32")] - fn vqsub_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } -vqsub_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_dup_s8(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v4i32")] - fn vqsubq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } -vqsubq_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_dup_s16(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64) +#[doc = "Load single 2-element structure and replicate to all lanes of two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v1i64")] - fn vqsub_u64_(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t; - } -vqsub_u64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_dup_s16(transmute(a))) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqsub.v2i64")] - fn vqsubq_u64_(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32.p0i8")] + fn _vld2_f32(ptr: *const i8, size: i32) -> float32x2x2_t; } -vqsubq_u64_(a, b) + _vld2_f32(a as *const i8, 4) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v8i8")] - fn vqsub_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32.p0i8")] + fn _vld2q_f32(ptr: *const i8, size: i32) -> float32x4x2_t; } -vqsub_s8_(a, b) + _vld2q_f32(a as *const i8, 4) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v16i8")] - fn vqsubq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8.p0i8")] + fn _vld2_s8(ptr: *const i8, size: i32) -> int8x8x2_t; } -vqsubq_s8_(a, b) + _vld2_s8(a as *const i8, 1) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v4i16")] - fn vqsub_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8.p0i8")] + fn _vld2q_s8(ptr: *const i8, size: i32) -> int8x16x2_t; } -vqsub_s16_(a, b) + _vld2q_s8(a as *const i8, 1) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v8i16")] - fn vqsubq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16.p0i8")] + fn _vld2_s16(ptr: *const i8, size: i32) -> int16x4x2_t; } -vqsubq_s16_(a, b) + _vld2_s16(a as *const i8, 2) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v2i32")] - fn vqsub_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16.p0i8")] + fn _vld2q_s16(ptr: *const i8, size: i32) -> int16x8x2_t; } -vqsub_s32_(a, b) + _vld2q_s16(a as *const i8, 2) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v4i32")] - fn vqsubq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32.p0i8")] + fn _vld2_s32(ptr: *const i8, size: i32) -> int32x2x2_t; } -vqsubq_s32_(a, b) + _vld2_s32(a as *const i8, 4) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v1i64")] - fn vqsub_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32.p0i8")] + fn _vld2q_s32(ptr: *const i8, size: i32) -> int32x4x2_t; } -vqsub_s64_(a, b) + _vld2q_s32(a as *const i8, 4) } -/// Saturating subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqsub.v2i64")] - fn vqsubq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v2f32.p0v2f32" + )] + fn _vld2_f32(ptr: *const float32x2_t) -> float32x2x2_t; } -vqsubq_s64_(a, b) + _vld2_f32(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v8i8")] - fn vhadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v4f32.p0v4f32" + )] + fn _vld2q_f32(ptr: *const float32x4_t) -> float32x4x2_t; } -vhadd_u8_(a, b) + _vld2q_f32(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v16i8")] - fn vhaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v8i8.p0v8i8" + )] + fn _vld2_s8(ptr: *const int8x8_t) -> int8x8x2_t; } -vhaddq_u8_(a, b) + _vld2_s8(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v4i16")] - fn vhadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v16i8.p0v16i8" + )] + fn _vld2q_s8(ptr: *const int8x16_t) -> int8x16x2_t; } -vhadd_u16_(a, b) + _vld2q_s8(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v8i16")] - fn vhaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v4i16.p0v4i16" + )] + fn _vld2_s16(ptr: *const int16x4_t) -> int16x4x2_t; } -vhaddq_u16_(a, b) + _vld2_s16(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v2i32")] - fn vhadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v8i16.p0v8i16" + )] + fn _vld2q_s16(ptr: *const int16x8_t) -> int16x8x2_t; } -vhadd_u32_(a, b) + _vld2q_s16(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhaddu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhadd.v4i32")] - fn vhaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v2i32.p0v2i32" + )] + fn _vld2_s32(ptr: *const int32x2_t) -> int32x2x2_t; } -vhaddq_u32_(a, b) + _vld2_s32(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld2))] +pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v8i8")] - fn vhadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v4i32.p0v4i32" + )] + fn _vld2q_s32(ptr: *const int32x4_t) -> int32x4x2_t; } -vhadd_s8_(a, b) + _vld2q_s32(a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v16i8")] - fn vhaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0i8" + )] + fn _vld2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; } -vhaddq_s8_(a, b) + _vld2_lane_f32(b.0, b.1, LANE as i64, a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v4i16")] - fn vhadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0i8" + )] + fn _vld2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) + -> float32x4x2_t; } -vhadd_s16_(a, b) + _vld2q_lane_f32(b.0, b.1, LANE as i64, a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v8i16")] - fn vhaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0i8" + )] + fn _vld2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; } -vhaddq_s16_(a, b) + _vld2_lane_s8(b.0, b.1, LANE as i64, a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v2i32")] - fn vhadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0i8" + )] + fn _vld2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; } -vhadd_s32_(a, b) + _vld2_lane_s16(b.0, b.1, LANE as i64, a as _) } -/// Halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhadds.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shadd.v4i32")] - fn vhaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0i8" + )] + fn _vld2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; } -vhaddq_s32_(a, b) + _vld2q_lane_s16(b.0, b.1, LANE as i64, a as _) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v8i8")] - fn vrhadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0i8" + )] + fn _vld2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; } -vrhadd_u8_(a, b) + _vld2_lane_s32(b.0, b.1, LANE as i64, a as _) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v16i8")] - fn vrhaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0i8" + )] + fn _vld2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; } -vrhaddq_u8_(a, b) + _vld2q_lane_s32(b.0, b.1, LANE as i64, a as _) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v4i16")] - fn vrhadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0i8")] + fn _vld2_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x2_t; } -vrhadd_u16_(a, b) + _vld2_lane_f32(a as _, b.0, b.1, LANE, 4) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v8i16")] - fn vrhaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0i8")] + fn _vld2q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x2_t; } -vrhaddq_u16_(a, b) + _vld2q_lane_f32(a as _, b.0, b.1, LANE, 4) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v2i32")] - fn vrhadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0i8")] + fn _vld2q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x2_t; } -vrhadd_u32_(a, b) + _vld2q_lane_s16(a as _, b.0, b.1, LANE, 2) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urhadd.v4i32")] - fn vrhaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0i8")] + fn _vld2q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x2_t; } -vrhaddq_u32_(a, b) + _vld2q_lane_s32(a as _, b.0, b.1, LANE, 4) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v8i8")] - fn vrhadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0i8")] + fn _vld2_lane_s8(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) + -> int8x8x2_t; } -vrhadd_s8_(a, b) + _vld2_lane_s8(a as _, b.0, b.1, LANE, 1) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v16i8")] - fn vrhaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0i8")] + fn _vld2_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x2_t; } -vrhaddq_s8_(a, b) + _vld2_lane_s16(a as _, b.0, b.1, LANE, 2) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v4i16")] - fn vrhadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0i8")] + fn _vld2_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x2_t; } -vrhadd_s16_(a, b) + _vld2_lane_s32(a as _, b.0, b.1, LANE, 4) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v8i16")] - fn vrhaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vrhaddq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v2i32")] - fn vrhadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vrhadd_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -/// Rounding halving add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srhadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srhadd.v4i32")] - fn vrhaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vrhaddq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -/// Floating-point round to integral, to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frintn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frintn.v2f32")] - fn vrndn_f32_(a: float32x2_t) -> float32x2_t; - } -vrndn_f32_(a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld2_lane_s32::(transmute(a), transmute(b))) } -/// Floating-point round to integral, to nearest with ties to even -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frintn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frintn.v4f32")] - fn vrndnq_f32_(a: float32x4_t) -> float32x4_t; - } -vrndnq_f32_(a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2q_lane_s32::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v8i8")] - fn vqadd_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } -vqadd_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2_lane_s8::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v16i8")] - fn vqaddq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } -vqaddq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld2_lane_s16::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v4i16")] - fn vqadd_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vqadd_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld2q_lane_s16::(transmute(a), transmute(b))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v8i16")] - fn vqaddq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vqaddq_u16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { + transmute(vld2_s64(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v2i32")] - fn vqadd_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64.p0i8")] + fn _vld2_s64(ptr: *const i8, size: i32) -> int64x1x2_t; } -vqadd_u32_(a, b) + _vld2_s64(a as *const i8, 8) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v4i32")] - fn vqaddq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld2.v1i64.p0v1i64" + )] + fn _vld2_s64(ptr: *const int64x1_t) -> int64x1x2_t; } -vqaddq_u32_(a, b) + _vld2_s64(a as _) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v1i64")] - fn vqadd_u64_(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t; - } -vqadd_u64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { + transmute(vld2_s64(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqadd.v2i64")] - fn vqaddq_u64_(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t; - } -vqaddq_u64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { + transmute(vld2_s8(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v8i8")] - fn vqadd_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vqadd_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v16i8")] - fn vqaddq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vqaddq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { + transmute(vld2_s16(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v4i16")] - fn vqadd_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vqadd_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { + transmute(vld2q_s16(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v8i16")] - fn vqaddq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vqaddq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { + transmute(vld2_s32(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v2i32")] - fn vqadd_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vqadd_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { + transmute(vld2q_s32(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v4i32")] - fn vqaddq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vqaddq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { + transmute(vld2_s8(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v1i64")] - fn vqadd_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } -vqadd_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { + transmute(vld2q_s8(transmute(a))) } -/// Saturating add -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqadd))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqadd.v2i64")] - fn vqaddq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } -vqaddq_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { + transmute(vld2_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x2) +#[doc = "Load multiple 2-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s8_x2(a: *const i8) -> int8x8x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v8i8.p0i8")] - fn vld1_s8_x2_(a: *const i8) -> int8x8x2_t; - } -vld1_s8_x2_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { + transmute(vld2q_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s16_x2(a: *const i16) -> int16x4x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v4i16.p0i16")] - fn vld1_s16_x2_(a: *const i16) -> int16x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2f32.p0f32" + )] + fn _vld3_dup_f32(ptr: *const f32) -> float32x2x3_t; } -vld1_s16_x2_(a) + _vld3_dup_f32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s32_x2(a: *const i32) -> int32x2x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v2i32.p0i32")] - fn vld1_s32_x2_(a: *const i32) -> int32x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4f32.p0f32" + )] + fn _vld3q_dup_f32(ptr: *const f32) -> float32x4x3_t; } -vld1_s32_x2_(a) + _vld3q_dup_f32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s64_x2(a: *const i64) -> int64x1x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v1i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v1i64.p0i64")] - fn vld1_s64_x2_(a: *const i64) -> int64x1x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v8i8.p0i8" + )] + fn _vld3_dup_s8(ptr: *const i8) -> int8x8x3_t; } -vld1_s64_x2_(a) + _vld3_dup_s8(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s8_x2(a: *const i8) -> int8x16x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v16i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v16i8.p0i8")] - fn vld1q_s8_x2_(a: *const i8) -> int8x16x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v16i8.p0i8" + )] + fn _vld3q_dup_s8(ptr: *const i8) -> int8x16x3_t; } -vld1q_s8_x2_(a) + _vld3q_dup_s8(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s16_x2(a: *const i16) -> int16x8x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v8i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v8i16.p0i16")] - fn vld1q_s16_x2_(a: *const i16) -> int16x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4i16.p0i16" + )] + fn _vld3_dup_s16(ptr: *const i16) -> int16x4x3_t; } -vld1q_s16_x2_(a) + _vld3_dup_s16(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s32_x2(a: *const i32) -> int32x4x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v4i32.p0i32")] - fn vld1q_s32_x2_(a: *const i32) -> int32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v8i16.p0i16" + )] + fn _vld3q_dup_s16(ptr: *const i16) -> int16x8x3_t; } -vld1q_s32_x2_(a) + _vld3q_dup_s16(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s64_x2(a: *const i64) -> int64x2x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v2i64.p0i64")] - fn vld1q_s64_x2_(a: *const i64) -> int64x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v2i32.p0i32" + )] + fn _vld3_dup_s32(ptr: *const i32) -> int32x2x3_t; } -vld1q_s64_x2_(a) + _vld3_dup_s32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s8_x3(a: *const i8) -> int8x8x3_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v8i8.p0i8")] - fn vld1_s8_x3_(a: *const i8) -> int8x8x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v4i32.p0i32" + )] + fn _vld3q_dup_s32(ptr: *const i32) -> int32x4x3_t; } -vld1_s8_x3_(a) + _vld3q_dup_s32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s16_x3(a: *const i16) -> int16x4x3_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld3r))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v4i16.p0i16")] - fn vld1_s16_x3_(a: *const i16) -> int16x4x3_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3r.v1i64.p0i64" + )] + fn _vld3_dup_s64(ptr: *const i64) -> int64x1x3_t; } -vld1_s16_x3_(a) + _vld3_dup_s64(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s32_x3(a: *const i32) -> int32x2x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v2i32.p0i32")] - fn vld1_s32_x3_(a: *const i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0i8")] + fn _vld3_dup_f32(ptr: *const i8, size: i32) -> float32x2x3_t; } -vld1_s32_x3_(a) + _vld3_dup_f32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s64_x3(a: *const i64) -> int64x1x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v1i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v1i64.p0i64")] - fn vld1_s64_x3_(a: *const i64) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0i8")] + fn _vld3q_dup_f32(ptr: *const i8, size: i32) -> float32x4x3_t; } -vld1_s64_x3_(a) + _vld3q_dup_f32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s8_x3(a: *const i8) -> int8x16x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v16i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v16i8.p0i8")] - fn vld1q_s8_x3_(a: *const i8) -> int8x16x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0i8")] + fn _vld3_dup_s8(ptr: *const i8, size: i32) -> int8x8x3_t; } -vld1q_s8_x3_(a) + _vld3_dup_s8(a as *const i8, 1) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s16_x3(a: *const i16) -> int16x8x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v8i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v8i16.p0i16")] - fn vld1q_s16_x3_(a: *const i16) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0i8")] + fn _vld3q_dup_s8(ptr: *const i8, size: i32) -> int8x16x3_t; } -vld1q_s16_x3_(a) + _vld3q_dup_s8(a as *const i8, 1) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s32_x3(a: *const i32) -> int32x4x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v4i32.p0i32")] - fn vld1q_s32_x3_(a: *const i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0i8")] + fn _vld3_dup_s16(ptr: *const i8, size: i32) -> int16x4x3_t; } -vld1q_s32_x3_(a) + _vld3_dup_s16(a as *const i8, 2) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x3) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s64_x3(a: *const i64) -> int64x2x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v2i64.p0i64")] - fn vld1q_s64_x3_(a: *const i64) -> int64x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0i8")] + fn _vld3q_dup_s16(ptr: *const i8, size: i32) -> int16x8x3_t; } -vld1q_s64_x3_(a) + _vld3q_dup_s16(a as *const i8, 2) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s8_x4(a: *const i8) -> int8x8x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v8i8.p0i8")] - fn vld1_s8_x4_(a: *const i8) -> int8x8x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0i8")] + fn _vld3_dup_s32(ptr: *const i8, size: i32) -> int32x2x3_t; } -vld1_s8_x4_(a) + _vld3_dup_s32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s16_x4(a: *const i16) -> int16x4x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v4i16.p0i16")] - fn vld1_s16_x4_(a: *const i16) -> int16x4x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0i8")] + fn _vld3q_dup_s32(ptr: *const i8, size: i32) -> int32x4x3_t; } -vld1_s16_x4_(a) + _vld3q_dup_s32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s32_x4(a: *const i32) -> int32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v2i32.p0i32")] - fn vld1_s32_x4_(a: *const i32) -> int32x2x4_t; - } -vld1_s32_x4_(a) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_s64_x4(a: *const i64) -> int64x1x4_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v1i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v1i64.p0i64")] - fn vld1_s64_x4_(a: *const i64) -> int64x1x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0i8")] + fn _vld3_dup_s64(ptr: *const i8, size: i32) -> int64x1x3_t; } -vld1_s64_x4_(a) + _vld3_dup_s64(a as *const i8, 8) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s8_x4(a: *const i8) -> int8x16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v16i8.p0i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v16i8.p0i8")] - fn vld1q_s8_x4_(a: *const i8) -> int8x16x4_t; - } -vld1q_s8_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_dup_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s16_x4(a: *const i16) -> int16x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v8i16.p0i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v8i16.p0i16")] - fn vld1q_s16_x4_(a: *const i16) -> int16x8x4_t; - } -vld1q_s16_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s32_x4(a: *const i32) -> int32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4i32.p0i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v4i32.p0i32")] - fn vld1q_s32_x4_(a: *const i32) -> int32x4x4_t; - } -vld1q_s32_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64_x4) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_s64_x4(a: *const i64) -> int64x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2i64.p0i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v2i64.p0i64")] - fn vld1q_s64_x4_(a: *const i64) -> int64x2x4_t; - } -vld1q_s64_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u8_x2(a: *const u8) -> uint8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u16_x2(a: *const u16) -> uint16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_dup_s32(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u32_x2(a: *const u32) -> uint32x2x2_t { - transmute(vld1_s32_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_dup_s32(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u64_x2(a: *const u64) -> uint64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_dup_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u8_x2(a: *const u8) -> uint8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_dup_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u16_x2(a: *const u16) -> uint16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_dup_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x2) +#[doc = "Load single 3-element structure and replicate to all lanes of three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u32_x2(a: *const u32) -> uint32x4x2_t { - transmute(vld1q_s32_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_dup_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u64_x2(a: *const u64) -> uint64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v2f32.p0v2f32" + )] + fn _vld3_f32(ptr: *const float32x2_t) -> float32x2x3_t; + } + _vld3_f32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u8_x3(a: *const u8) -> uint8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v4f32.p0v4f32" + )] + fn _vld3q_f32(ptr: *const float32x4_t) -> float32x4x3_t; + } + _vld3q_f32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u16_x3(a: *const u16) -> uint16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v8i8.p0v8i8" + )] + fn _vld3_s8(ptr: *const int8x8_t) -> int8x8x3_t; + } + _vld3_s8(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u32_x3(a: *const u32) -> uint32x2x3_t { - transmute(vld1_s32_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v16i8.p0v16i8" + )] + fn _vld3q_s8(ptr: *const int8x16_t) -> int8x16x3_t; + } + _vld3q_s8(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u64_x3(a: *const u64) -> uint64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v4i16.p0v4i16" + )] + fn _vld3_s16(ptr: *const int16x4_t) -> int16x4x3_t; + } + _vld3_s16(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u8_x3(a: *const u8) -> uint8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v8i16.p0v8i16" + )] + fn _vld3q_s16(ptr: *const int16x8_t) -> int16x8x3_t; + } + _vld3q_s16(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u16_x3(a: *const u16) -> uint16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v2i32.p0v2i32" + )] + fn _vld3_s32(ptr: *const int32x2_t) -> int32x2x3_t; + } + _vld3_s32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u32_x3(a: *const u32) -> uint32x4x3_t { - transmute(vld1q_s32_x3(transmute(a))) +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v4i32.p0v4i32" + )] + fn _vld3q_s32(ptr: *const int32x4_t) -> int32x4x3_t; + } + _vld3q_s32(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u64_x3(a: *const u64) -> uint64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0i8")] + fn _vld3_f32(ptr: *const i8, size: i32) -> float32x2x3_t; + } + _vld3_f32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u8_x4(a: *const u8) -> uint8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0i8")] + fn _vld3q_f32(ptr: *const i8, size: i32) -> float32x4x3_t; + } + _vld3q_f32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u16_x4(a: *const u16) -> uint16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0i8")] + fn _vld3_s8(ptr: *const i8, size: i32) -> int8x8x3_t; + } + _vld3_s8(a as *const i8, 1) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u32_x4(a: *const u32) -> uint32x2x4_t { - transmute(vld1_s32_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0i8")] + fn _vld3q_s8(ptr: *const i8, size: i32) -> int8x16x3_t; + } + _vld3q_s8(a as *const i8, 1) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_u64_x4(a: *const u64) -> uint64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0i8")] + fn _vld3_s16(ptr: *const i8, size: i32) -> int16x4x3_t; + } + _vld3_s16(a as *const i8, 2) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u8_x4(a: *const u8) -> uint8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0i8")] + fn _vld3q_s16(ptr: *const i8, size: i32) -> int16x8x3_t; + } + _vld3q_s16(a as *const i8, 2) +} + +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0i8")] + fn _vld3_s32(ptr: *const i8, size: i32) -> int32x2x3_t; + } + _vld3_s32(a as *const i8, 4) +} + +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld3))] +pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0i8")] + fn _vld3q_s32(ptr: *const i8, size: i32) -> int32x4x3_t; + } + _vld3q_s32(a as *const i8, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u16_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u16_x4(a: *const u16) -> uint16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0i8" + )] + fn _vld3_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x3_t; + } + _vld3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u32_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u32_x4(a: *const u32) -> uint32x4x4_t { - transmute(vld1q_s32_x4(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0i8" + )] + fn _vld3q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x3_t; + } + _vld3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) +} + +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0i8")] + fn _vld3_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x3_t; + } + _vld3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64_x4) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_u64_x4(a: *const u64) -> uint64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0i8" + )] + fn _vld3_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x3_t; + } + _vld3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x2) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p8_x2(a: *const p8) -> poly8x8x2_t { - transmute(vld1_s8_x2(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0i8" + )] + fn _vld3_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x3_t; + } + _vld3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x3) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p8_x3(a: *const p8) -> poly8x8x3_t { - transmute(vld1_s8_x3(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0i8" + )] + fn _vld3q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x3_t; + } + _vld3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p8_x4) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p8_x4(a: *const p8) -> poly8x8x4_t { - transmute(vld1_s8_x4(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0i8" + )] + fn _vld3_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x3_t; + } + _vld3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x2) +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p8_x2(a: *const p8) -> poly8x16x2_t { - transmute(vld1q_s8_x2(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0i8" + )] + fn _vld3q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x3_t; + } + _vld3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) +} + +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0i8")] + fn _vld3_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x3_t; + } + _vld3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) +} + +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0i8")] + fn _vld3_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x3_t; + } + _vld3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) +} + +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0i8")] + fn _vld3q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x3_t; + } + _vld3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) +} + +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0i8")] + fn _vld3_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x3_t; + } + _vld3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) +} + +#[doc = "Load multiple 3-element structures to two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0i8")] + fn _vld3q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x3_t; + } + _vld3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p8_x3(a: *const p8) -> poly8x16x3_t { - transmute(vld1q_s8_x3(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p8_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p8_x4(a: *const p8) -> poly8x16x4_t { - transmute(vld1q_s8_x4(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p16_x2(a: *const p16) -> poly16x4x2_t { - transmute(vld1_s16_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p16_x3(a: *const p16) -> poly16x4x3_t { - transmute(vld1_s16_x3(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld3_lane_s32::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p16_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p16_x4(a: *const p16) -> poly16x4x4_t { - transmute(vld1_s16_x4(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3q_lane_s32::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p16_x2(a: *const p16) -> poly16x8x2_t { - transmute(vld1q_s16_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p16_x3(a: *const p16) -> poly16x8x3_t { - transmute(vld1q_s16_x3(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { + static_assert_uimm_bits!(LANE, 2); + transmute(vld3_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p16_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p16_x4(a: *const p16) -> poly16x8x4_t { - transmute(vld1q_s16_x4(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld3q_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p64_x2(a: *const p64) -> poly64x1x2_t { - transmute(vld1_s64_x2(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { + transmute(vld3_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p64_x3(a: *const p64) -> poly64x1x3_t { - transmute(vld1_s64_x3(transmute(a))) +#[target_feature(enable = "neon")] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld3.v1i64.p0v1i64" + )] + fn _vld3_s64(ptr: *const int64x1_t) -> int64x1x3_t; + } + _vld3_s64(a as _) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_p64_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_p64_x4(a: *const p64) -> poly64x1x4_t { - transmute(vld1_s64_x4(transmute(a))) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0i8")] + fn _vld3_s64(ptr: *const i8, size: i32) -> int64x1x3_t; + } + _vld3_s64(a as *const i8, 8) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p64_x2(a: *const p64) -> poly64x2x2_t { - transmute(vld1q_s64_x2(transmute(a))) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { + transmute(vld3_s64(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p64_x3(a: *const p64) -> poly64x2x3_t { - transmute(vld1q_s64_x3(transmute(a))) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { + transmute(vld3_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_p64_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_p64_x4(a: *const p64) -> poly64x2x4_t { - transmute(vld1q_s64_x4(transmute(a))) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { + transmute(vld3q_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_f32_x2(a: *const f32) -> float32x2x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v2f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v2f32.p0f32")] - fn vld1_f32_x2_(a: *const f32) -> float32x2x2_t; - } -vld1_f32_x2_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { + transmute(vld3_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x2) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_f32_x2(a: *const f32) -> float32x4x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x2.v4f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x2.v4f32.p0f32")] - fn vld1q_f32_x2_(a: *const f32) -> float32x4x2_t; - } -vld1q_f32_x2_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { + transmute(vld3q_s16(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_f32_x3(a: *const f32) -> float32x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v2f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v2f32.p0f32")] - fn vld1_f32_x3_(a: *const f32) -> float32x2x3_t; - } -vld1_f32_x3_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { + transmute(vld3_s32(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x3) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_f32_x3(a: *const f32) -> float32x4x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x3.v4f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x3.v4f32.p0f32")] - fn vld1q_f32_x3_(a: *const f32) -> float32x4x3_t; - } -vld1q_f32_x3_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { + transmute(vld3q_s32(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1_f32_x4(a: *const f32) -> float32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v2f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v2f32.p0f32")] - fn vld1_f32_x4_(a: *const f32) -> float32x2x4_t; - } -vld1_f32_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { + transmute(vld3_s8(transmute(a))) } -/// Load multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32_x4) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld1q_f32_x4(a: *const f32) -> float32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld1x4.v4f32.p0f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld1x4.v4f32.p0f32")] - fn vld1q_f32_x4_(a: *const f32) -> float32x4x4_t; - } -vld1q_f32_x4_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { + transmute(vld3q_s8(transmute(a))) +} + +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { + transmute(vld3_s16(transmute(a))) +} + +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { + transmute(vld3q_s16(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8) +#[doc = "Load multiple 3-element structures to three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg_attr(test, assert_instr(vld3, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i8.p0i8")] - fn vld2_s8_(ptr: *const i8, size: i32) -> int8x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0i8")] + fn _vld3q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x3_t; } -vld2_s8_(a as *const i8, 1) + _vld3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_s8(a: *const i8) -> int8x8x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v8i8.p0v8i8")] - fn vld2_s8_(ptr: *const int8x8_t) -> int8x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0i8")] + fn _vld4_dup_f32(ptr: *const i8, size: i32) -> float32x2x4_t; } -vld2_s8_(a as _) + _vld4_dup_f32(a as *const i8, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg_attr(test, assert_instr(vld4))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i16.p0i8")] - fn vld2_s16_(ptr: *const i8, size: i32) -> int16x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0i8")] + fn _vld4q_dup_f32(ptr: *const i8, size: i32) -> float32x4x4_t; } -vld2_s16_(a as *const i8, 2) + _vld4q_dup_f32(a as *const i8, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_s16(a: *const i16) -> int16x4x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v4i16.p0v4i16")] - fn vld2_s16_(ptr: *const int16x4_t) -> int16x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0i8")] + fn _vld4_dup_s8(ptr: *const i8, size: i32) -> int8x8x4_t; } -vld2_s16_(a as _) + _vld4_dup_s8(a as *const i8, 1) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg_attr(test, assert_instr(vld4))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2i32.p0i8")] - fn vld2_s32_(ptr: *const i8, size: i32) -> int32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0i8")] + fn _vld4q_dup_s8(ptr: *const i8, size: i32) -> int8x16x4_t; } -vld2_s32_(a as *const i8, 4) + _vld4q_dup_s8(a as *const i8, 1) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_s32(a: *const i32) -> int32x2x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v2i32.p0v2i32")] - fn vld2_s32_(ptr: *const int32x2_t) -> int32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0i8")] + fn _vld4_dup_s16(ptr: *const i8, size: i32) -> int16x4x4_t; } -vld2_s32_(a as _) + _vld4_dup_s16(a as *const i8, 2) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg_attr(test, assert_instr(vld4))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v16i8.p0i8")] - fn vld2q_s8_(ptr: *const i8, size: i32) -> int8x16x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0i8")] + fn _vld4q_dup_s16(ptr: *const i8, size: i32) -> int16x8x4_t; } -vld2q_s8_(a as *const i8, 1) + _vld4q_dup_s16(a as *const i8, 2) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_s8(a: *const i8) -> int8x16x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vld4))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v16i8.p0v16i8")] - fn vld2q_s8_(ptr: *const int8x16_t) -> int8x16x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0i8")] + fn _vld4_dup_s32(ptr: *const i8, size: i32) -> int32x2x4_t; } -vld2q_s8_(a as _) + _vld4_dup_s32(a as *const i8, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg_attr(test, assert_instr(vld4))] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v8i16.p0i8")] - fn vld2q_s16_(ptr: *const i8, size: i32) -> int16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0i8")] + fn _vld4q_dup_s32(ptr: *const i8, size: i32) -> int32x4x4_t; } -vld2q_s16_(a as *const i8, 2) + _vld4q_dup_s32(a as *const i8, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_s16(a: *const i16) -> int16x8x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v8i16.p0v8i16")] - fn vld2q_s16_(ptr: *const int16x8_t) -> int16x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v2f32.p0f32" + )] + fn _vld4_dup_f32(ptr: *const f32) -> float32x2x4_t; } -vld2q_s16_(a as _) + _vld4_dup_f32(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4i32.p0i8")] - fn vld2q_s32_(ptr: *const i8, size: i32) -> int32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4f32.p0f32" + )] + fn _vld4q_dup_f32(ptr: *const f32) -> float32x4x4_t; } -vld2q_s32_(a as *const i8, 4) + _vld4q_dup_f32(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_s32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_s32(a: *const i32) -> int32x4x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v4i32.p0v4i32")] - fn vld2q_s32_(ptr: *const int32x4_t) -> int32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v8i8.p0i8" + )] + fn _vld4_dup_s8(ptr: *const i8) -> int8x8x4_t; } -vld2q_s32_(a as _) + _vld4_dup_s8(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v1i64.p0i8")] - fn vld2_s64_(ptr: *const i8, size: i32) -> int64x1x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v16i8.p0i8" + )] + fn _vld4q_dup_s8(ptr: *const i8) -> int8x16x4_t; } -vld2_s64_(a as *const i8, 8) + _vld4q_dup_s8(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_s64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_s64(a: *const i64) -> int64x1x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v1i64.p0v1i64")] - fn vld2_s64_(ptr: *const int64x1_t) -> int64x1x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4i16.p0i16" + )] + fn _vld4_dup_s16(ptr: *const i16) -> int16x4x4_t; } -vld2_s64_(a as _) + _vld4_dup_s16(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_s8(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v8i16.p0i16" + )] + fn _vld4q_dup_s16(ptr: *const i16) -> int16x8x4_t; + } + _vld4q_dup_s16(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_s16(transmute(a))) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v2i32.p0i32" + )] + fn _vld4_dup_s32(ptr: *const i32) -> int32x2x4_t; + } + _vld4_dup_s32(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_s32(transmute(a))) -} +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v4i32.p0i32" + )] + fn _vld4q_dup_s32(ptr: *const i32) -> int32x4x4_t; + } + _vld4q_dup_s32(a as _) +} + +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4r))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4r.v1i64.p0i64" + )] + fn _vld4_dup_s64(ptr: *const i64) -> int64x1x4_t; + } + _vld4_dup_s64(a as _) +} + +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) +} + +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(nop))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0i8")] + fn _vld4_dup_s64(ptr: *const i8, size: i32) -> int64x1x4_t; + } + _vld4_dup_s64(a as *const i8, 8) +} -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_dup_s64(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_u32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p8) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_dup_s32(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_p16) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_dup_s32(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_u64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_s64(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_dup_s8(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_p64) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_s64(transmute(a))) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_dup_s8(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v2f32.p0i8")] - fn vld2_f32_(ptr: *const i8, size: i32) -> float32x2x2_t; - } -vld2_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_dup_s16(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_f32) +#[doc = "Load single 4-element structure and replicate to all lanes of four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_f32(a: *const f32) -> float32x2x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v2f32.p0v2f32")] - fn vld2_f32_(ptr: *const float32x2_t) -> float32x2x2_t; - } -vld2_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4r) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_dup_s16(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2.v4f32.p0i8")] - fn vld2q_f32_(ptr: *const i8, size: i32) -> float32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v2f32.p0v2f32" + )] + fn _vld4_f32(ptr: *const float32x2_t) -> float32x2x4_t; } -vld2q_f32_(a as *const i8, 4) + _vld4_f32(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2))] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_f32(a: *const f32) -> float32x4x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2.v4f32.p0v4f32")] - fn vld2q_f32_(ptr: *const float32x4_t) -> float32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v4f32.p0v4f32" + )] + fn _vld4q_f32(ptr: *const float32x4_t) -> float32x4x4_t; } -vld2q_f32_(a as _) + _vld4q_f32(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i8.p0i8")] - fn vld2_dup_s8_(ptr: *const i8, size: i32) -> int8x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v8i8.p0v8i8" + )] + fn _vld4_s8(ptr: *const int8x8_t) -> int8x8x4_t; } -vld2_dup_s8_(a as *const i8, 1) + _vld4_s8(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_s8(a: *const i8) -> int8x8x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v8i8.p0i8")] - fn vld2_dup_s8_(ptr: *const i8) -> int8x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v16i8.p0v16i8" + )] + fn _vld4q_s8(ptr: *const int8x16_t) -> int8x16x4_t; } -vld2_dup_s8_(a as _) + _vld4q_s8(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i16.p0i8")] - fn vld2_dup_s16_(ptr: *const i8, size: i32) -> int16x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v4i16.p0v4i16" + )] + fn _vld4_s16(ptr: *const int16x4_t) -> int16x4x4_t; } -vld2_dup_s16_(a as *const i8, 2) + _vld4_s16(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_s16(a: *const i16) -> int16x4x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v4i16.p0i16")] - fn vld2_dup_s16_(ptr: *const i16) -> int16x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v8i16.p0v8i16" + )] + fn _vld4q_s16(ptr: *const int16x8_t) -> int16x8x4_t; } -vld2_dup_s16_(a as _) + _vld4q_s16(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2i32.p0i8")] - fn vld2_dup_s32_(ptr: *const i8, size: i32) -> int32x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v2i32.p0v2i32" + )] + fn _vld4_s32(ptr: *const int32x2_t) -> int32x2x4_t; } -vld2_dup_s32_(a as *const i8, 4) + _vld4_s32(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_s32(a: *const i32) -> int32x2x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(ld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v2i32.p0i32")] - fn vld2_dup_s32_(ptr: *const i32) -> int32x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v4i32.p0v4i32" + )] + fn _vld4q_s32(ptr: *const int32x4_t) -> int32x4x4_t; } -vld2_dup_s32_(a as _) + _vld4q_s32(a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v16i8.p0i8")] - fn vld2q_dup_s8_(ptr: *const i8, size: i32) -> int8x16x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0i8")] + fn _vld4_f32(ptr: *const i8, size: i32) -> float32x2x4_t; } -vld2q_dup_s8_(a as *const i8, 1) + _vld4_f32(a as *const i8, 4) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_s8(a: *const i8) -> int8x16x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v16i8.p0i8")] - fn vld2q_dup_s8_(ptr: *const i8) -> int8x16x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0i8")] + fn _vld4q_f32(ptr: *const i8, size: i32) -> float32x4x4_t; } -vld2q_dup_s8_(a as _) + _vld4q_f32(a as *const i8, 4) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v8i16.p0i8")] - fn vld2q_dup_s16_(ptr: *const i8, size: i32) -> int16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0i8")] + fn _vld4_s8(ptr: *const i8, size: i32) -> int8x8x4_t; } -vld2q_dup_s16_(a as *const i8, 2) + _vld4_s8(a as *const i8, 1) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_s16(a: *const i16) -> int16x8x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v8i16.p0i16")] - fn vld2q_dup_s16_(ptr: *const i16) -> int16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0i8")] + fn _vld4q_s8(ptr: *const i8, size: i32) -> int8x16x4_t; } -vld2q_dup_s16_(a as _) + _vld4q_s8(a as *const i8, 1) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4i32.p0i8")] - fn vld2q_dup_s32_(ptr: *const i8, size: i32) -> int32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0i8")] + fn _vld4_s16(ptr: *const i8, size: i32) -> int16x4x4_t; } -vld2q_dup_s32_(a as *const i8, 4) + _vld4_s16(a as *const i8, 2) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_s32(a: *const i32) -> int32x4x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v4i32.p0i32")] - fn vld2q_dup_s32_(ptr: *const i32) -> int32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0i8")] + fn _vld4q_s16(ptr: *const i8, size: i32) -> int16x8x4_t; } -vld2q_dup_s32_(a as _) + _vld4q_s16(a as *const i8, 2) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v1i64.p0i8")] - fn vld2_dup_s64_(ptr: *const i8, size: i32) -> int64x1x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0i8")] + fn _vld4_s32(ptr: *const i8, size: i32) -> int32x2x4_t; } -vld2_dup_s64_(a as *const i8, 8) + _vld4_s32(a as *const i8, 4) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_s64) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_s64(a: *const i64) -> int64x1x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v1i64.p0i64")] - fn vld2_dup_s64_(ptr: *const i64) -> int64x1x2_t; - } -vld2_dup_s64_(a as _) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_u8(a: *const u8) -> uint8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_u16(a: *const u16) -> uint16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_u32(a: *const u32) -> uint32x2x2_t { - transmute(vld2_dup_s32(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_dup_u8(a: *const u8) -> uint8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_dup_u16(a: *const u16) -> uint16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_dup_u32(a: *const u32) -> uint32x4x2_t { - transmute(vld2q_dup_s32(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_p8(a: *const p8) -> poly8x8x2_t { - transmute(vld2_dup_s8(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_p16(a: *const p16) -> poly16x4x2_t { - transmute(vld2_dup_s16(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_dup_p8(a: *const p8) -> poly8x16x2_t { - transmute(vld2q_dup_s8(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_p16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_dup_p16(a: *const p16) -> poly16x8x2_t { - transmute(vld2q_dup_s16(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_u64) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_u64(a: *const u64) -> uint64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_dup_p64(a: *const p64) -> poly64x1x2_t { - transmute(vld2_dup_s64(transmute(a))) -} - -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32) -#[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(vld4))] +pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v2f32.p0i8")] - fn vld2_dup_f32_(ptr: *const i8, size: i32) -> float32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0i8")] + fn _vld4q_s32(ptr: *const i8, size: i32) -> int32x4x4_t; } -vld2_dup_f32_(a as *const i8, 4) + _vld4q_s32(a as *const i8, 4) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_dup_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_dup_f32(a: *const f32) -> float32x2x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v2f32.p0f32")] - fn vld2_dup_f32_(ptr: *const f32) -> float32x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0i8" + )] + fn _vld4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *const i8, + ) -> float32x2x4_t; } -vld2_dup_f32_(a as _) + _vld4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2dup.v4f32.p0i8")] - fn vld2q_dup_f32_(ptr: *const i8, size: i32) -> float32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0i8" + )] + fn _vld4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *const i8, + ) -> float32x4x4_t; } -vld2q_dup_f32_(a as *const i8, 4) + _vld4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load single 2-element structure and replicate to all lanes of two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_dup_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2r))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_dup_f32(a: *const f32) -> float32x4x2_t { - #[allow(improper_ctypes)] +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2r.v4f32.p0f32")] - fn vld2q_dup_f32_(ptr: *const f32) -> float32x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0i8" + )] + fn _vld4_lane_s8( + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i64, + ptr: *const i8, + ) -> int8x8x4_t; } -vld2q_dup_f32_(a as _) + _vld4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i8.p0i8")] - fn vld2_lane_s8_(ptr: *const i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32) -> int8x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0i8" + )] + fn _vld4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *const i8, + ) -> int16x4x4_t; } -vld2_lane_s8_(a as _, b.0, b.1, LANE, 1) + _vld4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s8(a: *const i8, b: int8x8x2_t) -> int8x8x2_t { +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v8i8.p0i8")] - fn vld2_lane_s8_(a: int8x8_t, b: int8x8_t, n: i64, ptr: *const i8) -> int8x8x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0i8" + )] + fn _vld4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *const i8, + ) -> int16x8x4_t; } -vld2_lane_s8_(b.0, b.1, LANE as i64, a as _) + _vld4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i16.p0i8")] - fn vld2_lane_s16_(ptr: *const i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32) -> int16x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0i8" + )] + fn _vld4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *const i8, + ) -> int32x2x4_t; } -vld2_lane_s16_(a as _, b.0, b.1, LANE, 2) + _vld4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(ld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s16(a: *const i16, b: int16x4x2_t) -> int16x4x2_t { +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v4i16.p0i8")] - fn vld2_lane_s16_(a: int16x4_t, b: int16x4_t, n: i64, ptr: *const i8) -> int16x4x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0i8" + )] + fn _vld4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, + ptr: *const i8, + ) -> int32x4x4_t; } -vld2_lane_s16_(b.0, b.1, LANE as i64, a as _) + _vld4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { +pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2i32.p0i8")] - fn vld2_lane_s32_(ptr: *const i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32) -> int32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0i8")] + fn _vld4_lane_f32( + ptr: *const i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i32, + size: i32, + ) -> float32x2x4_t; } -vld2_lane_s32_(a as _, b.0, b.1, LANE, 4) + vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_s32(a: *const i32, b: int32x2x2_t) -> int32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v2i32.p0i8")] - fn vld2_lane_s32_(a: int32x2_t, b: int32x2_t, n: i64, ptr: *const i8) -> int32x2x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0i8")] + fn _vld4q_lane_f32( + ptr: *const i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i32, + size: i32, + ) -> float32x4x4_t; } -vld2_lane_s32_(b.0, b.1, LANE as i64, a as _) + vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { +pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v8i16.p0i8")] - fn vld2q_lane_s16_(ptr: *const i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32) -> int16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0i8")] + fn _vld4_lane_s8( + ptr: *const i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i32, + size: i32, + ) -> int8x8x4_t; } -vld2q_lane_s16_(a as _, b.0, b.1, LANE, 2) + vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s16(a: *const i16, b: int16x8x2_t) -> int16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v8i16.p0i8")] - fn vld2q_lane_s16_(a: int16x8_t, b: int16x8_t, n: i64, ptr: *const i8) -> int16x8x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0i8")] + fn _vld4_lane_s16( + ptr: *const i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i32, + size: i32, + ) -> int16x4x4_t; } -vld2q_lane_s16_(b.0, b.1, LANE as i64, a as _) + vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] +#[target_feature(enable = "neon,v7")] #[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0i8")] + fn _vld4q_lane_s16( + ptr: *const i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i32, + size: i32, + ) -> int16x8x4_t; + } + vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) +} + +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4i32.p0i8")] - fn vld2q_lane_s32_(ptr: *const i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32) -> int32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0i8")] + fn _vld4_lane_s32( + ptr: *const i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i32, + size: i32, + ) -> int32x2x4_t; } -vld2q_lane_s32_(a as _, b.0, b.1, LANE, 4) + vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[cfg_attr(test, assert_instr(vld4, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_s32(a: *const i32, b: int32x4x2_t) -> int32x4x2_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v4i32.p0i8")] - fn vld2q_lane_s32_(a: int32x4_t, b: int32x4_t, n: i64, ptr: *const i8) -> int32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0i8")] + fn _vld4q_lane_s32( + ptr: *const i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i32, + size: i32, + ) -> int32x4x4_t; } -vld2q_lane_s32_(b.0, b.1, LANE as i64, a as _) + vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_lane_u8(a: *const u8, b: uint8x8x2_t) -> uint8x8x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_lane_u16(a: *const u16, b: uint16x4x2_t) -> uint16x4x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_u32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_lane_u32(a: *const u32, b: uint32x2x2_t) -> uint32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld2_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { + static_assert_uimm_bits!(LANE, 3); + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_lane_u16(a: *const u16, b: uint16x8x2_t) -> uint16x8x2_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { + static_assert_uimm_bits!(LANE, 1); + transmute(vld4_lane_s32::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_u32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_lane_u32(a: *const u32, b: uint32x4x2_t) -> uint32x4x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { static_assert_uimm_bits!(LANE, 2); - transmute(vld2q_lane_s32::(transmute(a), transmute(b))) + transmute(vld4q_lane_s32::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_lane_p8(a: *const p8, b: poly8x8x2_t) -> poly8x8x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { static_assert_uimm_bits!(LANE, 3); - transmute(vld2_lane_s8::(transmute(a), transmute(b))) + transmute(vld4_lane_s8::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_p16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2_lane_p16(a: *const p16, b: poly16x4x2_t) -> poly16x4x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { static_assert_uimm_bits!(LANE, 2); - transmute(vld2_lane_s16::(transmute(a), transmute(b))) + transmute(vld4_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_p16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld2q_lane_p16(a: *const p16, b: poly16x8x2_t) -> poly16x8x2_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { static_assert_uimm_bits!(LANE, 3); - transmute(vld2q_lane_s16::(transmute(a), transmute(b))) + transmute(vld4q_lane_s16::(transmute(a), transmute(b))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v2f32.p0i8")] - fn vld2_lane_f32_(ptr: *const i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32) -> float32x2x2_t; - } -vld2_lane_f32_(a as _, b.0, b.1, LANE, 4) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { + transmute(vld4_s64(transmute(a))) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2_lane_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2_lane_f32(a: *const f32, b: float32x2x2_t) -> float32x2x2_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v2f32.p0i8")] - fn vld2_lane_f32_(a: float32x2_t, b: float32x2_t, n: i64, ptr: *const i8) -> float32x2x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ld4.v1i64.p0v1i64" + )] + fn _vld4_s64(ptr: *const int64x1_t) -> int64x1x4_t; } -vld2_lane_f32_(b.0, b.1, LANE as i64, a as _) + _vld4_s64(a as _) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(target_arch = "arm")] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld2lane.v4f32.p0i8")] - fn vld2q_lane_f32_(ptr: *const i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32) -> float32x4x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0i8")] + fn _vld4_s64(ptr: *const i8, size: i32) -> int64x1x4_t; } -vld2q_lane_f32_(a as _, b.0, b.1, LANE, 4) + _vld4_s64(a as *const i8, 8) } -/// Load multiple 2-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld2q_lane_f32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld2q_lane_f32(a: *const f32, b: float32x4x2_t) -> float32x4x2_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld2lane.v4f32.p0i8")] - fn vld2q_lane_f32_(a: float32x4_t, b: float32x4_t, n: i64, ptr: *const i8) -> float32x4x2_t; - } -vld2q_lane_f32_(b.0, b.1, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { + transmute(vld4_s64(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i8.p0i8")] - fn vld3_s8_(ptr: *const i8, size: i32) -> int8x8x3_t; - } -vld3_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { + transmute(vld4_s8(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_s8(a: *const i8) -> int8x8x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v8i8.p0v8i8")] - fn vld3_s8_(ptr: *const int8x8_t) -> int8x8x3_t; - } -vld3_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i16.p0i8")] - fn vld3_s16_(ptr: *const i8, size: i32) -> int16x4x3_t; - } -vld3_s16_(a as *const i8, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { + transmute(vld4_s16(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_s16(a: *const i16) -> int16x4x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v4i16.p0v4i16")] - fn vld3_s16_(ptr: *const int16x4_t) -> int16x4x3_t; - } -vld3_s16_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { + transmute(vld4q_s16(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2i32.p0i8")] - fn vld3_s32_(ptr: *const i8, size: i32) -> int32x2x3_t; - } -vld3_s32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { + transmute(vld4_s32(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s32) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_s32(a: *const i32) -> int32x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v2i32.p0v2i32")] - fn vld3_s32_(ptr: *const int32x2_t) -> int32x2x3_t; - } -vld3_s32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { + transmute(vld4q_s32(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v16i8.p0i8")] - fn vld3q_s8_(ptr: *const i8, size: i32) -> int8x16x3_t; - } -vld3q_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { + transmute(vld4_s8(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s8) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_s8(a: *const i8) -> int8x16x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v16i8.p0v16i8")] - fn vld3q_s8_(ptr: *const int8x16_t) -> int8x16x3_t; - } -vld3q_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { + transmute(vld4q_s8(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v8i16.p0i8")] - fn vld3q_s16_(ptr: *const i8, size: i32) -> int16x8x3_t; - } -vld3q_s16_(a as *const i8, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { + transmute(vld4_s16(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s16) +#[doc = "Load multiple 4-element structures to four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_s16(a: *const i16) -> int16x8x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v8i16.p0v8i16")] - fn vld3q_s16_(ptr: *const int16x8_t) -> int16x8x3_t; - } -vld3q_s16_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ld4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { + transmute(vld4q_s16(transmute(a))) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4i32.p0i8")] - fn vld3q_s32_(ptr: *const i8, size: i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v2f32" + )] + fn _vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } -vld3q_s32_(a as *const i8, 4) + _vmax_f32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_s32) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_s32(a: *const i32) -> int32x4x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v4i32.p0v4i32")] - fn vld3q_s32_(ptr: *const int32x4_t) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmax.v4f32" + )] + fn _vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } -vld3q_s32_(a as _) + _vmaxq_f32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v1i64.p0i8")] - fn vld3_s64_(ptr: *const i8, size: i32) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v8i8" + )] + fn _vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vld3_s64_(a as *const i8, 8) + _vmax_s8(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_s64) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_s64(a: *const i64) -> int64x1x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v1i64.p0v1i64")] - fn vld3_s64_(ptr: *const int64x1_t) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v16i8" + )] + fn _vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vld3_s64_(a as _) + _vmaxq_s8(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u8) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_s8(transmute(a))) -} - -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v4i16" + )] + fn _vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vmax_s16(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u32) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v8i16" + )] + fn _vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vmaxq_s16(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u8) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v2i32" + )] + fn _vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vmax_s32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u16) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smax.v4i32" + )] + fn _vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vmaxq_s32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_u32) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v8i8" + )] + fn _vmax_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vmax_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p8) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v16i8" + )] + fn _vmaxq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vmaxq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p16) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v4i16" + )] + fn _vmax_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vmax_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p8) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v8i16" + )] + fn _vmaxq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vmaxq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_p16) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v2i32" + )] + fn _vmax_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vmax_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_u64) +#[doc = "Maximum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_s64(transmute(a))) -} - -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_s64(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umax) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umax.v4i32" + )] + fn _vmaxq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vmaxq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32) +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmaxnm) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v2f32.p0i8")] - fn vld3_f32_(ptr: *const i8, size: i32) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v2f32" + )] + fn _vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } -vld3_f32_(a as *const i8, 4) + _vmaxnm_f32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_f32) +#[doc = "Floating-point Maximum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_f32(a: *const f32) -> float32x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmaxnm) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v2f32.p0v2f32")] - fn vld3_f32_(ptr: *const float32x2_t) -> float32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmaxnm.v4f32" + )] + fn _vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } -vld3_f32_(a as _) + _vmaxnmq_f32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3.v4f32.p0i8")] - fn vld3q_f32_(ptr: *const i8, size: i32) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v2f32" + )] + fn _vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } -vld3q_f32_(a as *const i8, 4) + _vmin_f32(a, b) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_f32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_f32(a: *const f32) -> float32x4x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3.v4f32.p0v4f32")] - fn vld3q_f32_(ptr: *const float32x4_t) -> float32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fmin.v4f32" + )] + fn _vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } -vld3q_f32_(a as _) + _vminq_f32(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i8.p0i8")] - fn vld3_dup_s8_(ptr: *const i8, size: i32) -> int8x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v8i8" + )] + fn _vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vld3_dup_s8_(a as *const i8, 1) + _vmin_s8(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s8) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_s8(a: *const i8) -> int8x8x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v8i8.p0i8")] - fn vld3_dup_s8_(ptr: *const i8) -> int8x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v16i8" + )] + fn _vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vld3_dup_s8_(a as _) + _vminq_s8(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i16.p0i8")] - fn vld3_dup_s16_(ptr: *const i8, size: i32) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v4i16" + )] + fn _vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vld3_dup_s16_(a as *const i8, 2) + _vmin_s16(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s16) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_s16(a: *const i16) -> int16x4x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v4i16.p0i16")] - fn vld3_dup_s16_(ptr: *const i16) -> int16x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v8i16" + )] + fn _vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vld3_dup_s16_(a as _) + _vminq_s16(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2i32.p0i8")] - fn vld3_dup_s32_(ptr: *const i8, size: i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v2i32" + )] + fn _vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vld3_dup_s32_(a as *const i8, 4) + _vmin_s32(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_s32(a: *const i32) -> int32x2x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v2i32.p0i32")] - fn vld3_dup_s32_(ptr: *const i32) -> int32x2x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smin.v4i32" + )] + fn _vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vld3_dup_s32_(a as _) + _vminq_s32(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v16i8.p0i8")] - fn vld3q_dup_s8_(ptr: *const i8, size: i32) -> int8x16x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v8i8" + )] + fn _vmin_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vld3q_dup_s8_(a as *const i8, 1) + _vmin_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s8) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_s8(a: *const i8) -> int8x16x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v16i8.p0i8")] - fn vld3q_dup_s8_(ptr: *const i8) -> int8x16x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v16i8" + )] + fn _vminq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vld3q_dup_s8_(a as _) + _vminq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v8i16.p0i8")] - fn vld3q_dup_s16_(ptr: *const i8, size: i32) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v4i16" + )] + fn _vmin_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vld3q_dup_s16_(a as *const i8, 2) + _vmin_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s16) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_s16(a: *const i16) -> int16x8x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v8i16.p0i16")] - fn vld3q_dup_s16_(ptr: *const i16) -> int16x8x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v8i16" + )] + fn _vminq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vld3q_dup_s16_(a as _) + _vminq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4i32.p0i8")] - fn vld3q_dup_s32_(ptr: *const i8, size: i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v2i32" + )] + fn _vmin_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vld3q_dup_s32_(a as *const i8, 4) + _vmin_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_s32) +#[doc = "Minimum (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_s32(a: *const i32) -> int32x4x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umin) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v4i32.p0i32")] - fn vld3q_dup_s32_(ptr: *const i32) -> int32x4x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umin.v4i32" + )] + fn _vminq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vld3q_dup_s32_(a as _) + _vminq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64) +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fminnm) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v1i64.p0i8")] - fn vld3_dup_s64_(ptr: *const i8, size: i32) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v2f32" + )] + fn _vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; } -vld3_dup_s64_(a as *const i8, 8) + _vminnm_f32(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_s64) +#[doc = "Floating-point Minimum Number (vector)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_s64(a: *const i64) -> int64x1x3_t { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fminnm) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v1i64.p0i64")] - fn vld3_dup_s64_(ptr: *const i64) -> int64x1x3_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.fminnm.v4f32" + )] + fn _vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; } -vld3_dup_s64_(a as _) + _vminnmq_f32(a, b) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u8) +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_u8(a: *const u8) -> uint8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + simd_add(a, simd_mul(b, c)) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u16) +#[doc = "Floating-point multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_u16(a: *const u16) -> uint16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + simd_add(a, simd_mul(b, c)) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_u32(a: *const u32) -> uint32x2x3_t { - transmute(vld3_dup_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_dup_u8(a: *const u8) -> uint8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_dup_u16(a: *const u16) -> uint16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_u32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_dup_u32(a: *const u32) -> uint32x4x3_t { - transmute(vld3q_dup_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_p8(a: *const p8) -> poly8x8x3_t { - transmute(vld3_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_p16(a: *const p16) -> poly16x4x3_t { - transmute(vld3_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_lane_u16( + a: uint16x4_t, + b: uint16x4_t, + c: uint16x4_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_dup_p8(a: *const p8) -> poly8x16x3_t { - transmute(vld3q_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_laneq_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_p16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_dup_p16(a: *const p16) -> poly16x8x3_t { - transmute(vld3q_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_laneq_u16( + a: uint16x4_t, + b: uint16x4_t, + c: uint16x8_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmla_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_u64) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_u64(a: *const u64) -> uint64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) -} - -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_p64) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x4_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_dup_p64(a: *const p64) -> poly64x1x3_t { - transmute(vld3_dup_s64(transmute(a))) -} - -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_lane_u16( + a: uint16x8_t, + b: uint16x8_t, + c: uint16x4_t, +) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlaq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v2f32.p0i8")] - fn vld3_dup_f32_(ptr: *const i8, size: i32) -> float32x2x3_t; - } -vld3_dup_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_laneq_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_laneq_u16( + a: uint16x8_t, + b: uint16x8_t, + c: uint16x8_t, +) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlaq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_dup_f32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_dup_f32(a: *const f32) -> float32x2x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v2f32.p0f32")] - fn vld3_dup_f32_(ptr: *const f32) -> float32x2x3_t; - } -vld3_dup_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_lane_u32( + a: uint32x2_t, + b: uint32x2_t, + c: uint32x2_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3dup.v4f32.p0i8")] - fn vld3q_dup_f32_(ptr: *const i8, size: i32) -> float32x4x3_t; - } -vld3q_dup_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_laneq_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 3-element structure and replicate to all lanes of three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_dup_f32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_dup_f32(a: *const f32) -> float32x4x3_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3r.v4f32.p0f32")] - fn vld3q_dup_f32_(ptr: *const f32) -> float32x4x3_t; - } -vld3q_dup_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_laneq_u32( + a: uint32x2_t, + b: uint32x2_t, + c: uint32x4_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmla_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i8.p0i8")] - fn vld3_lane_s8_(ptr: *const i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32) -> int8x8x3_t; - } -vld3_lane_s8_(a as _, b.0, b.1, b.2, LANE, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x2_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s8(a: *const i8, b: int8x8x3_t) -> int8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v8i8.p0i8")] - fn vld3_lane_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *const i8) -> int8x8x3_t; - } -vld3_lane_s8_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_lane_u32( + a: uint32x4_t, + b: uint32x4_t, + c: uint32x2_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlaq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_laneq_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, +) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i16.p0i8")] - fn vld3_lane_s16_(ptr: *const i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i32, size: i32) -> int16x4x3_t; - } -vld3_lane_s16_(a as _, b.0, b.1, b.2, LANE, 2) + vmlaq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s16(a: *const i16, b: int16x4x3_t) -> int16x4x3_t { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_laneq_u32( + a: uint32x4_t, + b: uint32x4_t, + c: uint32x4_t, +) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v4i16.p0i8")] - fn vld3_lane_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *const i8) -> int16x4x3_t; - } -vld3_lane_s16_(b.0, b.1, b.2, LANE as i64, a as _) + vmlaq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2i32.p0i8")] - fn vld3_lane_s32_(ptr: *const i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i32, size: i32) -> int32x2x3_t; - } -vld3_lane_s32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vmla_f32(a, b, vdup_n_f32(c)) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_s32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_s32(a: *const i32, b: int32x2x3_t) -> int32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v2i32.p0i8")] - fn vld3_lane_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *const i8) -> int32x2x3_t; - } -vld3_lane_s32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vmlaq_f32(a, b, vdupq_n_f32(c)) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v8i16.p0i8")] - fn vld3q_lane_s16_(ptr: *const i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i32, size: i32) -> int16x8x3_t; - } -vld3q_lane_s16_(a as _, b.0, b.1, b.2, LANE, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { + vmla_s16(a, b, vdup_n_s16(c)) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s16(a: *const i16, b: int16x8x3_t) -> int16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v8i16.p0i8")] - fn vld3q_lane_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *const i8) -> int16x8x3_t; - } -vld3q_lane_s16_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { + vmlaq_s16(a, b, vdupq_n_s16(c)) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4i32.p0i8")] - fn vld3q_lane_s32_(ptr: *const i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i32, size: i32) -> int32x4x3_t; - } -vld3q_lane_s32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { + vmla_u16(a, b, vdup_n_u16(c)) } -/// Load multiple 3-element structures to two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_s32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_s32(a: *const i32, b: int32x4x3_t) -> int32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v4i32.p0i8")] - fn vld3q_lane_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *const i8) -> int32x4x3_t; - } -vld3q_lane_s32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { + vmlaq_u16(a, b, vdupq_n_u16(c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u8) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_lane_u8(a: *const u8, b: uint8x8x3_t) -> uint8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { + vmla_s32(a, b, vdup_n_s32(c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_lane_u16(a: *const u16, b: uint16x4x3_t) -> uint16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { + vmlaq_s32(a, b, vdupq_n_s32(c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_u32) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_lane_u32(a: *const u32, b: uint32x2x3_t) -> uint32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld3_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { + vmla_u32(a, b, vdup_n_u32(c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u16) +#[doc = "Vector multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_lane_u16(a: *const u16, b: uint16x8x3_t) -> uint16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { + vmlaq_u32(a, b, vdupq_n_u32(c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_u32) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_lane_u32(a: *const u32, b: uint32x4x3_t) -> uint32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3q_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p8) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_lane_p8(a: *const p8, b: poly8x8x3_t) -> poly8x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3_lane_s8::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_p16) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3_lane_p16(a: *const p16, b: poly16x4x3_t) -> poly16x4x3_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld3_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_p16) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld3q_lane_p16(a: *const p16, b: poly16x8x3_t) -> poly16x8x3_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld3q_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v2f32.p0i8")] - fn vld3_lane_f32_(ptr: *const i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i32, size: i32) -> float32x2x3_t; - } -vld3_lane_f32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3_lane_f32) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3_lane_f32(a: *const f32, b: float32x2x3_t) -> float32x2x3_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v2f32.p0i8")] - fn vld3_lane_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *const i8) -> float32x2x3_t; - } -vld3_lane_f32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld3lane.v4f32.p0i8")] - fn vld3q_lane_f32_(ptr: *const i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i32, size: i32) -> float32x4x3_t; - } -vld3q_lane_f32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 3-element structures to three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld3q_lane_f32) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld3q_lane_f32(a: *const f32, b: float32x4x3_t) -> float32x4x3_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld3lane.v4f32.p0i8")] - fn vld3q_lane_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *const i8) -> float32x4x3_t; - } -vld3q_lane_f32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i8.p0i8")] - fn vld4_s8_(ptr: *const i8, size: i32) -> int8x8x4_t; - } -vld4_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s8) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_s8(a: *const i8) -> int8x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v8i8.p0v8i8")] - fn vld4_s8_(ptr: *const int8x8_t) -> int8x8x4_t; - } -vld4_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i16.p0i8")] - fn vld4_s16_(ptr: *const i8, size: i32) -> int16x4x4_t; - } -vld4_s16_(a as *const i8, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmla_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s16) +#[doc = "Multiply-add to accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_s16(a: *const i16) -> int16x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v4i16.p0v4i16")] - fn vld4_s16_(ptr: *const int16x4_t) -> int16x4x4_t; - } -vld4_s16_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmla.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mla) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlaq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + simd_add(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2i32.p0i8")] - fn vld4_s32_(ptr: *const i8, size: i32) -> int32x2x4_t; - } -vld4_s32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_lane_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s32) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_s32(a: *const i32) -> int32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v2i32.p0v2i32")] - fn vld4_s32_(ptr: *const int32x2_t) -> int32x2x4_t; - } -vld4_s32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_laneq_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v16i8.p0i8")] - fn vld4q_s8_(ptr: *const i8, size: i32) -> int8x16x4_t; - } -vld4q_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_lane_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s8) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_s8(a: *const i8) -> int8x16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v16i8.p0v16i8")] - fn vld4q_s8_(ptr: *const int8x16_t) -> int8x16x4_t; - } -vld4q_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_laneq_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v8i16.p0i8")] - fn vld4q_s16_(ptr: *const i8, size: i32) -> int16x8x4_t; - } -vld4q_s16_(a as *const i8, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_lane_u16( + a: uint32x4_t, + b: uint16x4_t, + c: uint16x4_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s16) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_s16(a: *const i16) -> int16x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v8i16.p0v8i16")] - fn vld4q_s16_(ptr: *const int16x8_t) -> int16x8x4_t; - } -vld4q_s16_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_laneq_u16( + a: uint32x4_t, + b: uint16x4_t, + c: uint16x8_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmlal_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4i32.p0i8")] - fn vld4q_s32_(ptr: *const i8, size: i32) -> int32x4x4_t; - } -vld4q_s32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_lane_u32( + a: uint64x2_t, + b: uint32x2_t, + c: uint32x2_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_s32) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_s32(a: *const i32) -> int32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v4i32.p0v4i32")] - fn vld4q_s32_(ptr: *const int32x4_t) -> int32x4x4_t; - } -vld4q_s32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_laneq_u32( + a: uint64x2_t, + b: uint32x2_t, + c: uint32x4_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlal_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v1i64.p0i8")] - fn vld4_s64_(ptr: *const i8, size: i32) -> int64x1x4_t; - } -vld4_s64_(a as *const i8, 8) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vmlal_s16(a, b, vdup_n_s16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_s64) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_s64(a: *const i64) -> int64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v1i64.p0v1i64")] - fn vld4_s64_(ptr: *const int64x1_t) -> int64x1x4_t; - } -vld4_s64_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vmlal_s32(a, b, vdup_n_s32(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u8) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { + vmlal_u16(a, b, vdup_n_u16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u16) +#[doc = "Vector widening multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { + vmlal_u32(a, b, vdup_n_u32(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u32) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + simd_add(a, vmull_s8(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u8) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + simd_add(a, vmull_s16(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u16) +#[doc = "Signed multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + simd_add(a, vmull_s32(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_u32) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + simd_add(a, vmull_u8(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p8) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + simd_add(a, vmull_u16(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p16) +#[doc = "Unsigned multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlal.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + simd_add(a, vmull_u32(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p8) +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_p16) +#[doc = "Floating-point multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_u64) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_s64(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_p64) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_s64(transmute(a))) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_laneq_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x4_t, +) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_f32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v2f32.p0i8")] - fn vld4_f32_(ptr: *const i8, size: i32) -> float32x2x4_t; - } -vld4_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x2_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_f32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_f32(a: *const f32) -> float32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v2f32.p0v2f32")] - fn vld4_f32_(ptr: *const float32x2_t) -> float32x2x4_t; - } -vld4_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_laneq_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, +) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_f32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4.v4f32.p0i8")] - fn vld4q_f32_(ptr: *const i8, size: i32) -> float32x4x4_t; - } -vld4q_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmls_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_f32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_f32(a: *const f32) -> float32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4.v4f32.p0v4f32")] - fn vld4q_f32_(ptr: *const float32x4_t) -> float32x4x4_t; - } -vld4q_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_lane_u16( + a: uint16x4_t, + b: uint16x4_t, + c: uint16x4_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + vmls_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i8.p0i8")] - fn vld4_dup_s8_(ptr: *const i8, size: i32) -> int8x8x4_t; - } -vld4_dup_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_laneq_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmls_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s8(a: *const i8) -> int8x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v8i8.p0i8")] - fn vld4_dup_s8_(ptr: *const i8) -> int8x8x4_t; - } -vld4_dup_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_laneq_u16( + a: uint16x4_t, + b: uint16x4_t, + c: uint16x8_t, +) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 3); + vmls_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i16.p0i8")] - fn vld4_dup_s16_(ptr: *const i8, size: i32) -> int16x4x4_t; - } -vld4_dup_s16_(a as *const i8, 2) -} - -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s16) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x4_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s16(a: *const i16) -> int16x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v4i16.p0i16")] - fn vld4_dup_s16_(ptr: *const i16) -> int16x4x4_t; - } -vld4_dup_s16_(a as _) -} - -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_lane_u16( + a: uint16x8_t, + b: uint16x8_t, + c: uint16x4_t, +) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2i32.p0i8")] - fn vld4_dup_s32_(ptr: *const i8, size: i32) -> int32x2x4_t; - } -vld4_dup_s32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_laneq_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, +) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlsq_s16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_laneq_u16( + a: uint16x8_t, + b: uint16x8_t, + c: uint16x8_t, +) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + vmlsq_u16( + a, + b, + simd_shuffle!( + c, + c, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s32(a: *const i32) -> int32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v2i32.p0i32")] - fn vld4_dup_s32_(ptr: *const i32) -> int32x2x4_t; - } -vld4_dup_s32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_lane_u32( + a: uint32x2_t, + b: uint32x2_t, + c: uint32x2_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v16i8.p0i8")] - fn vld4q_dup_s8_(ptr: *const i8, size: i32) -> int8x16x4_t; - } -vld4q_dup_s8_(a as *const i8, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_laneq_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s8(a: *const i8) -> int8x16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v16i8.p0i8")] - fn vld4q_dup_s8_(ptr: *const i8) -> int8x16x4_t; - } -vld4q_dup_s8_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_laneq_u32( + a: uint32x2_t, + b: uint32x2_t, + c: uint32x4_t, +) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 2); + vmls_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v8i16.p0i8")] - fn vld4q_dup_s16_(ptr: *const i8, size: i32) -> int16x8x4_t; - } -vld4q_dup_s16_(a as *const i8, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x2_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s16(a: *const i16) -> int16x8x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v8i16.p0i16")] - fn vld4q_dup_s16_(ptr: *const i16) -> int16x8x4_t; - } -vld4q_dup_s16_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_lane_u32( + a: uint32x4_t, + b: uint32x4_t, + c: uint32x2_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + vmlsq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4i32.p0i8")] - fn vld4q_dup_s32_(ptr: *const i8, size: i32) -> int32x4x4_t; - } -vld4q_dup_s32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_laneq_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_s32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_s32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_s32(a: *const i32) -> int32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v4i32.p0i32")] - fn vld4q_dup_s32_(ptr: *const i32) -> int32x4x4_t; - } -vld4q_dup_s32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_laneq_u32( + a: uint32x4_t, + b: uint32x4_t, + c: uint32x4_t, +) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsq_u32( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v1i64.p0i8")] - fn vld4_dup_s64_(ptr: *const i8, size: i32) -> int64x1x4_t; - } -vld4_dup_s64_(a as *const i8, 8) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { + vmls_f32(a, b, vdup_n_f32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_s64) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_s64(a: *const i64) -> int64x1x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v1i64.p0i64")] - fn vld4_dup_s64_(ptr: *const i64) -> int64x1x4_t; - } -vld4_dup_s64_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { + vmlsq_f32(a, b, vdupq_n_f32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_u8(a: *const u8) -> uint8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_n_s16(a: int16x4_t, b: int16x4_t, c: i16) -> int16x4_t { + vmls_s16(a, b, vdup_n_s16(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_u16(a: *const u16) -> uint16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_n_s16(a: int16x8_t, b: int16x8_t, c: i16) -> int16x8_t { + vmlsq_s16(a, b, vdupq_n_s16(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_u32(a: *const u32) -> uint32x2x4_t { - transmute(vld4_dup_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_n_u16(a: uint16x4_t, b: uint16x4_t, c: u16) -> uint16x4_t { + vmls_u16(a, b, vdup_n_u16(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_dup_u8(a: *const u8) -> uint8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_n_u16(a: uint16x8_t, b: uint16x8_t, c: u16) -> uint16x8_t { + vmlsq_u16(a, b, vdupq_n_u16(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_dup_u16(a: *const u16) -> uint16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_n_s32(a: int32x2_t, b: int32x2_t, c: i32) -> int32x2_t { + vmls_s32(a, b, vdup_n_s32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_u32) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_dup_u32(a: *const u32) -> uint32x4x4_t { - transmute(vld4q_dup_s32(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_n_s32(a: int32x4_t, b: int32x4_t, c: i32) -> int32x4_t { + vmlsq_s32(a, b, vdupq_n_s32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p8) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_p8(a: *const p8) -> poly8x8x4_t { - transmute(vld4_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_n_u32(a: uint32x2_t, b: uint32x2_t, c: u32) -> uint32x2_t { + vmls_u32(a, b, vdup_n_u32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p16) +#[doc = "Vector multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_p16(a: *const p16) -> poly16x4x4_t { - transmute(vld4_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_n_u32(a: uint32x4_t, b: uint32x4_t, c: u32) -> uint32x4_t { + vmlsq_u32(a, b, vdupq_n_u32(c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p8) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_dup_p8(a: *const p8) -> poly8x16x4_t { - transmute(vld4q_dup_s8(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t) -> int8x8_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_p16) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_dup_p16(a: *const p16) -> poly16x8x4_t { - transmute(vld4q_dup_s16(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t) -> int8x16_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_u64) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_u64(a: *const u64) -> uint64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t) -> int16x4_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_p64) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4r))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_dup_p64(a: *const p64) -> poly64x1x4_t { - transmute(vld4_dup_s64(transmute(a))) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t) -> int16x8_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v2f32.p0i8")] - fn vld4_dup_f32_(ptr: *const i8, size: i32) -> float32x2x4_t; - } -vld4_dup_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t) -> int32x2_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_dup_f32) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_dup_f32(a: *const f32) -> float32x2x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v2f32.p0f32")] - fn vld4_dup_f32_(ptr: *const f32) -> float32x2x4_t; - } -vld4_dup_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t) -> int32x4_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4dup.v4f32.p0i8")] - fn vld4q_dup_f32_(ptr: *const i8, size: i32) -> float32x4x4_t; - } -vld4q_dup_f32_(a as *const i8, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_u8(a: uint8x8_t, b: uint8x8_t, c: uint8x8_t) -> uint8x8_t { + simd_sub(a, simd_mul(b, c)) } -/// Load single 4-element structure and replicate to all lanes of four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_dup_f32) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4r))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_dup_f32(a: *const f32) -> float32x4x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4r.v4f32.p0f32")] - fn vld4q_dup_f32_(ptr: *const f32) -> float32x4x4_t; - } -vld4q_dup_f32_(a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_u8(a: uint8x16_t, b: uint8x16_t, c: uint8x16_t) -> uint8x16_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i8.p0i8")] - fn vld4_lane_s8_(ptr: *const i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i32, size: i32) -> int8x8x4_t; - } -vld4_lane_s8_(a as _, b.0, b.1, b.2, b.3, LANE, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_u16(a: uint16x4_t, b: uint16x4_t, c: uint16x4_t) -> uint16x4_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s8) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v8i8.p0i8")] - fn vld4_lane_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *const i8) -> int8x8x4_t; - } -vld4_lane_s8_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_u16(a: uint16x8_t, b: uint16x8_t, c: uint16x8_t) -> uint16x8_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i16.p0i8")] - fn vld4_lane_s16_(ptr: *const i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, n: i32, size: i32) -> int16x4x4_t; - } -vld4_lane_s16_(a as _, b.0, b.1, b.2, b.3, LANE, 2) -} - -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s16) -#[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> int16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v4i16.p0i8")] - fn vld4_lane_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, n: i64, ptr: *const i8) -> int16x4x4_t; - } -vld4_lane_s16_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmls_u32(a: uint32x2_t, b: uint32x2_t, c: uint32x2_t) -> uint32x2_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32) +#[doc = "Multiply-subtract from accumulator"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2i32.p0i8")] - fn vld4_lane_s32_(ptr: *const i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, n: i32, size: i32) -> int32x2x4_t; - } -vld4_lane_s32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmls.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mls) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsq_u32(a: uint32x4_t, b: uint32x4_t, c: uint32x4_t) -> uint32x4_t { + simd_sub(a, simd_mul(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_s32) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> int32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v2i32.p0i8")] - fn vld4_lane_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, n: i64, ptr: *const i8) -> int32x2x4_t; - } -vld4_lane_s32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_lane_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_laneq_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x8_t, +) -> int32x4_t { static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v8i16.p0i8")] - fn vld4q_lane_s16_(ptr: *const i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, n: i32, size: i32) -> int16x8x4_t; - } -vld4q_lane_s16_(a as _, b.0, b.1, b.2, b.3, LANE, 2) + vmlsl_s16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s16) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> int16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v8i16.p0i8")] - fn vld4q_lane_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, n: i64, ptr: *const i8) -> int16x8x4_t; - } -vld4q_lane_s16_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_lane_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_laneq_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x4_t, +) -> int64x2_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4i32.p0i8")] - fn vld4q_lane_s32_(ptr: *const i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, n: i32, size: i32) -> int32x4x4_t; - } -vld4q_lane_s32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) + vmlsl_s32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_s32) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> int32x4x4_t { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_lane_u16( + a: uint32x4_t, + b: uint16x4_t, + c: uint16x4_t, +) -> uint32x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v4i32.p0i8")] - fn vld4q_lane_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, n: i64, ptr: *const i8) -> int32x4x4_t; - } -vld4q_lane_s32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + vmlsl_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u8) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_lane_u8(a: *const u8, b: uint8x8x4_t) -> uint8x8x4_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_laneq_u16( + a: uint32x4_t, + b: uint16x4_t, + c: uint16x8_t, +) -> uint32x4_t { static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) + vmlsl_u16( + a, + b, + simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u16) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_lane_u16(a: *const u16, b: uint16x4x4_t) -> uint16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_lane_u32( + a: uint64x2_t, + b: uint32x2_t, + c: uint32x2_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_u32) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_lane_u32(a: *const u32, b: uint32x2x4_t) -> uint32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - transmute(vld4_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32", LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl, LANE = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_laneq_u32( + a: uint64x2_t, + b: uint32x2_t, + c: uint32x4_t, +) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmlsl_u32(a, b, simd_shuffle!(c, c, [LANE as u32, LANE as u32])) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u16) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_lane_u16(a: *const u16, b: uint16x8x4_t) -> uint16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vmlsl_s16(a, b, vdup_n_s16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_u32) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_lane_u32(a: *const u32, b: uint32x4x4_t) -> uint32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4q_lane_s32::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vmlsl_s32(a, b, vdup_n_s32(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p8) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_lane_p8(a: *const p8, b: poly8x8x4_t) -> poly8x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4_lane_s8::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_n_u16(a: uint32x4_t, b: uint16x4_t, c: u16) -> uint32x4_t { + vmlsl_u16(a, b, vdup_n_u16(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_p16) +#[doc = "Vector widening multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4_lane_p16(a: *const p16, b: poly16x4x4_t) -> poly16x4x4_t { - static_assert_uimm_bits!(LANE, 2); - transmute(vld4_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_n_u32(a: uint64x2_t, b: uint32x2_t, c: u32) -> uint64x2_t { + vmlsl_u32(a, b, vdup_n_u32(c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_p16) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vld4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vld4q_lane_p16(a: *const p16, b: poly16x8x4_t) -> poly16x8x4_t { - static_assert_uimm_bits!(LANE, 3); - transmute(vld4q_lane_s16::(transmute(a), transmute(b))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { + simd_sub(a, vmull_s8(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v2f32.p0i8")] - fn vld4_lane_f32_(ptr: *const i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, n: i32, size: i32) -> float32x2x4_t; - } -vld4_lane_f32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + simd_sub(a, vmull_s16(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4_lane_f32) +#[doc = "Signed multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> float32x2x4_t { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v2f32.p0i8")] - fn vld4_lane_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, n: i64, ptr: *const i8) -> float32x2x4_t; - } -vld4_lane_f32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + simd_sub(a, vmull_s32(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vld4lane.v4f32.p0i8")] - fn vld4q_lane_f32_(ptr: *const i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, n: i32, size: i32) -> float32x4x4_t; - } -vld4q_lane_f32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { + simd_sub(a, vmull_u8(b, c)) } -/// Load multiple 4-element structures to four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld4q_lane_f32) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(ld4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) -> float32x4x4_t { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ld4lane.v4f32.p0i8")] - fn vld4q_lane_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, n: i64, ptr: *const i8) -> float32x4x4_t; - } -vld4q_lane_f32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { + simd_sub(a, vmull_u16(b, c)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8) +#[doc = "Unsigned multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { - static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmlsl.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmlsl_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { + simd_sub(a, vmull_u32(b, c)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { - static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { - static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { - static_assert!(LANE == 0); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { - static_assert_uimm_bits!(LANE, 4); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { - static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32) +#[doc = "Floating-point multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) +} + +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { - static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { - static_assert!(LANE == 0); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 1); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { - static_assert_uimm_bits!(LANE, 4); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); -} - -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32) + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { - static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_mul( + a, + simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ), + ) +} + +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); + simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { - static_assert_uimm_bits!(LANE, 4); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_mul( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { - static_assert_uimm_bits!(LANE, 3); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { + simd_mul(a, vdup_n_f32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { - static_assert!(LANE == 0); - *a = simd_extract!(b, LANE as u32); +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { + simd_mul(a, vdupq_n_f32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { - static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + simd_mul(a, vdup_n_s16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { - static_assert_uimm_bits!(LANE, 1); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + simd_mul(a, vdupq_n_s16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { - static_assert_uimm_bits!(LANE, 2); - *a = simd_extract!(b, LANE as u32); +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + simd_mul(a, vdup_n_s32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i8.v8i8")] - fn vst1_s8_x2_(ptr: *mut i8, a: int8x8_t, b: int8x8_t); - } -vst1_s8_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + simd_mul(a, vdupq_n_s32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v8i8.p0i8")] - fn vst1_s8_x2_(a: int8x8_t, b: int8x8_t, ptr: *mut i8); - } -vst1_s8_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { + simd_mul(a, vdup_n_u16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i16.v4i16")] - fn vst1_s16_x2_(ptr: *mut i16, a: int16x4_t, b: int16x4_t); - } -vst1_s16_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { + simd_mul(a, vdupq_n_u16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v4i16.p0i16")] - fn vst1_s16_x2_(a: int16x4_t, b: int16x4_t, ptr: *mut i16); - } -vst1_s16_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { + simd_mul(a, vdup_n_u32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2) +#[doc = "Vector multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i32.v2i32")] - fn vst1_s32_x2_(ptr: *mut i32, a: int32x2_t, b: int32x2_t); - } -vst1_s32_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { + simd_mul(a, vdupq_n_u32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2) +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(pmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v2i32.p0i32")] - fn vst1_s32_x2_(a: int32x2_t, b: int32x2_t, ptr: *mut i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmul.v8i8" + )] + fn _vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t; } -vst1_s32_x2_(b.0, b.1, a) + _vmul_p8(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2) +#[doc = "Polynomial multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(pmul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i64.v1i64")] - fn vst1_s64_x2_(ptr: *mut i64, a: int64x1_t, b: int64x1_t); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmul.v16i8" + )] + fn _vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t; } -vst1_s64_x2_(a, b.0, b.1) + _vmulq_p8(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v1i64.p0i64")] - fn vst1_s64_x2_(a: int64x1_t, b: int64x1_t, ptr: *mut i64); - } -vst1_s64_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i8.v16i8")] - fn vst1q_s8_x2_(ptr: *mut i8, a: int8x16_t, b: int8x16_t); - } -vst1q_s8_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v16i8.p0i8")] - fn vst1q_s8_x2_(a: int8x16_t, b: int8x16_t, ptr: *mut i8); - } -vst1q_s8_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i16.v8i16")] - fn vst1q_s16_x2_(ptr: *mut i16, a: int16x8_t, b: int16x8_t); - } -vst1q_s16_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v8i16.p0i16")] - fn vst1q_s16_x2_(a: int16x8_t, b: int16x8_t, ptr: *mut i16); - } -vst1q_s16_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i32.v4i32")] - fn vst1q_s32_x2_(ptr: *mut i32, a: int32x4_t, b: int32x4_t); - } -vst1q_s32_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v4i32.p0i32")] - fn vst1q_s32_x2_(a: int32x4_t, b: int32x4_t, ptr: *mut i32); - } -vst1q_s32_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i64.v2i64")] - fn vst1q_s64_x2_(ptr: *mut i64, a: int64x2_t, b: int64x2_t); - } -vst1q_s64_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v2i64.p0i64")] - fn vst1q_s64_x2_(a: int64x2_t, b: int64x2_t, ptr: *mut i64); - } -vst1q_s64_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v8i8")] - fn vst1_s8_x3_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t); - } -vst1_s8_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v8i8.p0i8")] - fn vst1_s8_x3_(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); - } -vst1_s8_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3) +#[doc = "Multiply"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v4i16")] - fn vst1_s16_x3_(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t); - } -vst1_s16_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(mul) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_mul(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v4i16.p0i16")] - fn vst1_s16_x3_(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16); - } -vst1_s16_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_s16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v2i32")] - fn vst1_s32_x3_(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t); - } -vst1_s32_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_s16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v2i32.p0i32")] - fn vst1_s32_x3_(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32); - } -vst1_s32_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v1i64")] - fn vst1_s64_x3_(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t); - } -vst1_s64_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v1i64.p0i64")] - fn vst1_s64_x3_(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64); - } -vst1_s64_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + vmull_u16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v16i8")] - fn vst1q_s8_x3_(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t); - } -vst1q_s8_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 3); + vmull_u16( + a, + simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]), + ) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v16i8.p0i8")] - fn vst1q_s8_x3_(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); - } -vst1q_s8_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3) +#[doc = "Vector long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v8i16")] - fn vst1q_s16_x3_(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t); - } -vst1q_s16_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 2); + vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3) +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v8i16.p0i16")] - fn vst1q_s16_x3_(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16); - } -vst1q_s16_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { + vmull_s16(a, vdup_n_s16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3) +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v4i32")] - fn vst1q_s32_x3_(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t); - } -vst1q_s32_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { + vmull_s32(a, vdup_n_s32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3) +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v4i32.p0i32")] - fn vst1q_s32_x3_(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32); - } -vst1q_s32_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { + vmull_u16(a, vdup_n_u16(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3) +#[doc = "Vector long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v2i64")] - fn vst1q_s64_x3_(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t); - } -vst1q_s64_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { + vmull_u32(a, vdup_n_u32(b)) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3) +#[doc = "Polynomial multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(pmull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v2i64.p0i64")] - fn vst1q_s64_x3_(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.pmull.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i8")] + fn _vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t; } -vst1q_s64_x3_(b.0, b.1, b.2, a) + _vmull_p8(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v8i8")] - fn vst1_s8_x4_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smull.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")] + fn _vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } -vst1_s8_x4_(a, b.0, b.1, b.2, b.3) + _vmull_s16(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v8i8.p0i8")] - fn vst1_s8_x4_(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smull.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")] + fn _vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; } -vst1_s8_x4_(b.0, b.1, b.2, b.3, a) + _vmull_s32(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4) +#[doc = "Signed multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(smull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v4i16")] - fn vst1_s16_x4_(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.smull.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")] + fn _vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t; } -vst1_s16_x4_(a, b.0, b.1, b.2, b.3) + _vmull_s8(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v4i16.p0i16")] - fn vst1_s16_x4_(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umull.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")] + fn _vmull_u8(a: int8x8_t, b: int8x8_t) -> int16x8_t; } -vst1_s16_x4_(b.0, b.1, b.2, b.3, a) + _vmull_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v2i32")] - fn vst1_s32_x4_(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umull.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")] + fn _vmull_u16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } -vst1_s32_x4_(a, b.0, b.1, b.2, b.3) + _vmull_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4) +#[doc = "Unsigned multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(umull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v2i32.p0i32")] - fn vst1_s32_x4_(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.umull.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")] + fn _vmull_u32(a: int32x2_t, b: int32x2_t) -> int64x2_t; } -vst1_s32_x4_(b.0, b.1, b.2, b.3, a) + _vmull_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v1i64")] - fn vst1_s64_x4_(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t); - } -vst1_s64_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vneg_f32(a: float32x2_t) -> float32x2_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v1i64.p0i64")] - fn vst1_s64_x4_(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64); - } -vst1_s64_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vnegq_f32(a: float32x4_t) -> float32x4_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v16i8")] - fn vst1q_s8_x4_(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t); - } -vst1q_s8_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vneg_s8(a: int8x8_t) -> int8x8_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v16i8.p0i8")] - fn vst1q_s8_x4_(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); - } -vst1q_s8_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vnegq_s8(a: int8x16_t) -> int8x16_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v8i16")] - fn vst1q_s16_x4_(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t); - } -vst1q_s16_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vneg_s16(a: int16x4_t) -> int16x4_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v8i16.p0i16")] - fn vst1q_s16_x4_(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16); - } -vst1q_s16_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vnegq_s16(a: int16x8_t) -> int16x8_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v4i32")] - fn vst1q_s32_x4_(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t); - } -vst1q_s32_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vneg_s32(a: int32x2_t) -> int32x2_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4) +#[doc = "Negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v4i32.p0i32")] - fn vst1q_s32_x4_(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32); - } -vst1q_s32_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vneg.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(neg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vnegq_s32(a: int32x4_t) -> int32x4_t { + simd_neg(a) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v2i64")] - fn vst1q_s64_x4_(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t); - } -vst1q_s64_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_or(a, b) } -/// Store multiple single-element structures from one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v2i64.p0i64")] - fn vst1q_s64_x4_(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64); - } -vst1q_s64_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { - vst1_s8_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { - vst1_s16_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { - vst1_s32_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { - vst1_s64_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { - vst1q_s8_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { - vst1q_s16_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { - vst1q_s32_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { - vst1q_s64_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { - vst1_s8_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { - vst1_s16_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { - vst1_s32_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { - vst1_s64_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { - vst1q_s8_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorr_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3) +#[doc = "Vector bitwise or (immediate, inclusive)"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { - vst1q_s16_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(orr) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vorrq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_or(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3) +#[doc = "Floating-point add pairwise"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { - vst1q_s32_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(faddp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.faddp.v2f32" + )] + fn _vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vpadd_f32(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { - vst1q_s64_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")] + fn _vqabs_s8(a: int8x8_t) -> int8x8_t; + } + _vqabs_s8(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { - vst1_s8_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")] + fn _vqabsq_s8(a: int8x16_t) -> int8x16_t; + } + _vqabsq_s8(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { - vst1_s16_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")] + fn _vqabs_s16(a: int16x4_t) -> int16x4_t; + } + _vqabs_s16(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { - vst1_s32_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")] + fn _vqabsq_s16(a: int16x8_t) -> int16x8_t; + } + _vqabsq_s16(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { - vst1_s64_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")] + fn _vqabs_s32(a: int32x2_t) -> int32x2_t; + } + _vqabs_s32(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4) +#[doc = "Signed saturating Absolute value"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { - vst1q_s8_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqabs) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqabs.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")] + fn _vqabsq_s32(a: int32x4_t) -> int32x4_t; + } + _vqabsq_s32(a) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { - vst1q_s16_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i8")] + fn _vqadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vqadd_s8(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { - vst1q_s32_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v16i8")] + fn _vqaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vqaddq_s8(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { - vst1q_s64_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i16")] + fn _vqadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vqadd_s16(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { - vst1_s8_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v8i16")] + fn _vqaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vqaddq_s16(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { - vst1_s8_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i32")] + fn _vqadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vqadd_s32(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { - vst1_s8_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v4i32")] + fn _vqaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vqaddq_s32(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { - vst1q_s8_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v1i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v1i64")] + fn _vqadd_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vqadd_s64(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { - vst1q_s8_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.s64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqadd.v2i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.sadd.sat.v2i64")] + fn _vqaddq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vqaddq_s64(a, b) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { - vst1q_s8_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i8")] + fn _vqadd_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vqadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { - vst1_s16_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v16i8")] + fn _vqaddq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vqaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { - vst1_s16_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i16")] + fn _vqadd_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vqadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { - vst1_s16_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v8i16")] + fn _vqaddq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vqaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { - vst1q_s16_x2(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i32")] + fn _vqadd_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vqadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { - vst1q_s16_x3(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v4i32")] + fn _vqaddq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vqaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) { - vst1q_s16_x4(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqadd_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v1i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v1i64")] + fn _vqadd_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vqadd_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2) +#[doc = "Saturating add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { - vst1_s64_x2(transmute(a), transmute(b)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqadd.u64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqaddq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqadd.v2i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.uadd.sat.v2i64")] + fn _vqaddq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vqaddq_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { - vst1_s64_x3(transmute(a), transmute(b)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal, N = 2) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_lane_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqaddq_s32(a, vqdmull_lane_s16::(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { - vst1_s64_x4(transmute(a), transmute(b)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal, N = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_lane_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqaddq_s64(a, vqdmull_lane_s32::(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { - vst1q_s64_x2(transmute(a), transmute(b)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vqaddq_s32(a, vqdmull_n_s16(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3) +#[doc = "Vector widening saturating doubling multiply accumulate with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { - vst1q_s64_x3(transmute(a), transmute(b)) -} +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vqaddq_s64(a, vqdmull_n_s32(b, c)) +} -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st1))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { - vst1q_s64_x4(transmute(a), transmute(b)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + vqaddq_s32(a, vqdmull_s16(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2) +#[doc = "Signed saturating doubling multiply-add long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f32.v2f32")] - fn vst1_f32_x2_(ptr: *mut f32, a: float32x2_t, b: float32x2_t); - } -vst1_f32_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlal) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + vqaddq_s64(a, vqdmull_s32(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v2f32.p0f32")] - fn vst1_f32_x2_(a: float32x2_t, b: float32x2_t, ptr: *mut f32); - } -vst1_f32_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl, N = 2) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_lane_s16( + a: int32x4_t, + b: int16x4_t, + c: int16x4_t, +) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + vqsubq_s32(a, vqdmull_lane_s16::(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f32.v4f32")] - fn vst1q_f32_x2_(ptr: *mut f32, a: float32x4_t, b: float32x4_t); - } -vst1q_f32_x2_(a, b.0, b.1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl, N = 1) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_lane_s32( + a: int64x2_t, + b: int32x2_t, + c: int32x2_t, +) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + vqsubq_s64(a, vqdmull_lane_s32::(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x2.v4f32.p0f32")] - fn vst1q_f32_x2_(a: float32x4_t, b: float32x4_t, ptr: *mut f32); - } -vst1q_f32_x2_(b.0, b.1, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { + vqsubq_s32(a, vqdmull_n_s16(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3) +#[doc = "Vector widening saturating doubling multiply subtract with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f32.v2f32")] - fn vst1_f32_x3_(ptr: *mut f32, a: float32x2_t, b: float32x2_t, c: float32x2_t); - } -vst1_f32_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { + vqsubq_s64(a, vqdmull_n_s32(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v2f32.p0f32")] - fn vst1_f32_x3_(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32); - } -vst1_f32_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { + vqsubq_s32(a, vqdmull_s16(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3) +#[doc = "Signed saturating doubling multiply-subtract long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f32.v4f32")] - fn vst1q_f32_x3_(ptr: *mut f32, a: float32x4_t, b: float32x4_t, c: float32x4_t); - } -vst1q_f32_x3_(a, b.0, b.1, b.2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmlsl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { + vqsubq_s64(a, vqdmull_s32(b, c)) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x3.v4f32.p0f32")] - fn vst1q_f32_x3_(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32); - } -vst1q_f32_x3_(b.0, b.1, b.2, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 3); + vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v2f32")] - fn vst1_f32_x4_(ptr: *mut f32, a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t); - } -vst1_f32_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v2f32.p0f32")] - fn vst1_f32_x4_(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut f32); - } -vst1_f32_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4) +#[doc = "Vector saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst1))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v4f32")] - fn vst1q_f32_x4_(ptr: *mut f32, a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t); - } -vst1q_f32_x4_(a, b.0, b.1, b.2, b.3) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) } -/// Store multiple single-element structures to one, two, three, or four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4) +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st1))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st1x4.v4f32.p0f32")] - fn vst1q_f32_x4_(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut f32); - } -vst1q_f32_x4_(b.0, b.1, b.2, b.3, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + let b: int16x4_t = vdup_n_s16(b); + vqdmulh_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8) +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8i8")] - fn vst2_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32); - } -vst2_s8_(a as _, b.0, b.1, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + let b: int16x8_t = vdupq_n_s16(b); + vqdmulhq_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8) +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v8i8.p0i8")] - fn vst2_s8_(a: int8x8_t, b: int8x8_t, ptr: *mut i8); - } -vst2_s8_(b.0, b.1, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + let b: int32x2_t = vdup_n_s32(b); + vqdmulh_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16) +#[doc = "Vector saturating doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4i16")] - fn vst2_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32); - } -vst2_s16_(a as _, b.0, b.1, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + let b: int32x4_t = vdupq_n_s32(b); + vqdmulhq_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v4i16.p0i8")] - fn vst2_s16_(a: int16x4_t, b: int16x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v4i16" + )] + fn _vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vst2_s16_(b.0, b.1, a as _) + _vqdmulh_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v2i32")] - fn vst2_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v8i16" + )] + fn _vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vst2_s32_(a as _, b.0, b.1, 4) + _vqdmulhq_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v2i32.p0i8")] - fn vst2_s32_(a: int32x2_t, b: int32x2_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v2i32" + )] + fn _vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vst2_s32_(b.0, b.1, a as _) + _vqdmulh_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8) +#[doc = "Signed saturating doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v16i8")] - fn vst2q_s8_(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmulh.v4i32" + )] + fn _vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vst2q_s8_(a as _, b.0, b.1, 1) + _vqdmulhq_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8) +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v16i8.p0i8")] - fn vst2q_s8_(a: int8x16_t, b: int8x16_t, ptr: *mut i8); - } -vst2q_s8_(b.0, b.1, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 2); + let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); + vqdmull_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16) +#[doc = "Vector saturating doubling long multiply by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8i16")] - fn vst2q_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32); - } -vst2q_s16_(a as _, b.0, b.1, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull, N = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 1); + let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); + vqdmull_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16) +#[doc = "Vector saturating doubling long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v8i16.p0i8")] - fn vst2q_s16_(a: int16x8_t, b: int16x8_t, ptr: *mut i8); - } -vst2q_s16_(b.0, b.1, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { + vqdmull_s16(a, vdup_n_s16(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32) +#[doc = "Vector saturating doubling long multiply with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4i32")] - fn vst2q_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32); - } -vst2q_s32_(a as _, b.0, b.1, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { + vqdmull_s32(a, vdup_n_s32(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v4i32.p0i8")] - fn vst2q_s32_(a: int32x4_t, b: int32x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmull.v4i32" + )] + fn _vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t; } -vst2q_s32_(b.0, b.1, a as _) + _vqdmull_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64) +#[doc = "Signed saturating doubling multiply long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqdmull) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v1i64")] - fn vst2_s64_(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqdmull.v2i64" + )] + fn _vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t; } -vst2_s64_(a as _, b.0, b.1, 8) + _vqdmull_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v1i64.p0i8")] - fn vst2_s64_(a: int64x1_t, b: int64x1_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v8i8" + )] + fn _vqmovn_s16(a: int16x8_t) -> int8x8_t; } -vst2_s64_(b.0, b.1, a as _) + _vqmovn_s16(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { - vst2_s8(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v4i16" + )] + fn _vqmovn_s32(a: int32x4_t) -> int16x4_t; + } + _vqmovn_s32(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16) +#[doc = "Signed saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { - vst2_s16(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtn.v2i32" + )] + fn _vqmovn_s64(a: int64x2_t) -> int32x2_t; + } + _vqmovn_s64(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32) +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { - vst2_s32(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v8i8" + )] + fn _vqmovn_u16(a: int16x8_t) -> int8x8_t; + } + _vqmovn_u16(a.as_signed()).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8) +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { - vst2q_s8(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v4i16" + )] + fn _vqmovn_u32(a: int32x4_t) -> int16x4_t; + } + _vqmovn_u32(a.as_signed()).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16) +#[doc = "Unsigned saturating extract narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { - vst2q_s16(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqxtn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqxtn.v2i32" + )] + fn _vqmovn_u64(a: int64x2_t) -> int32x2_t; + } + _vqmovn_u64(a.as_signed()).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { - vst2q_s32(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtun) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v8i8" + )] + fn _vqmovun_s16(a: int16x8_t) -> int8x8_t; + } + _vqmovun_s16(a).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { - vst2_s8(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtun) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v4i16" + )] + fn _vqmovun_s32(a: int32x4_t) -> int16x4_t; + } + _vqmovun_s32(a).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16) +#[doc = "Signed saturating extract unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { - vst2_s16(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqxtun) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqxtun.v2i32" + )] + fn _vqmovun_s64(a: int64x2_t) -> int32x2_t; + } + _vqmovun_s64(a).as_unsigned() } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { - vst2q_s8(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqneg_s8(a: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i8")] + fn _vqneg_s8(a: int8x8_t) -> int8x8_t; + } + _vqneg_s8(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { - vst2q_s16(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqnegq_s8(a: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v16i8")] + fn _vqnegq_s8(a: int8x16_t) -> int8x16_t; + } + _vqnegq_s8(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { - vst2_s64(transmute(a), transmute(b)) -} - -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { - vst2_s64(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqneg_s16(a: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i16")] + fn _vqneg_s16(a: int16x4_t) -> int16x4_t; + } + _vqneg_s16(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqnegq_s16(a: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v2f32")] - fn vst2_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v8i16")] + fn _vqnegq_s16(a: int16x8_t) -> int16x8_t; } -vst2_f32_(a as _, b.0, b.1, 4) + _vqnegq_s16(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqneg_s32(a: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v2f32.p0i8")] - fn vst2_f32_(a: float32x2_t, b: float32x2_t, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v2i32")] + fn _vqneg_s32(a: int32x2_t) -> int32x2_t; } -vst2_f32_(b.0, b.1, a as _) + _vqneg_s32(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32) +#[doc = "Signed saturating negate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqneg.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqneg) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqnegq_s32(a: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4f32")] - fn vst2q_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqneg.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqneg.v4i32")] + fn _vqnegq_s32(a: int32x4_t) -> int32x4_t; } -vst2q_f32_(a as _, b.0, b.1, 4) + _vqnegq_s32(a) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2.v4f32.p0i8")] - fn vst2q_f32_(a: float32x4_t, b: float32x4_t, ptr: *mut i8); - } -vst2q_f32_(b.0, b.1, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulh_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i8")] - fn vst2_lane_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32); - } -vst2_lane_s8_(a as _, b.0, b.1, LANE, 1) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); + vqrdmulh_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v8i8.p0i8")] - fn vst2_lane_s8_(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8); - } -vst2_lane_s8_(b.0, b.1, LANE as i64, a as _) + let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulh_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i16")] - fn vst2_lane_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32); - } -vst2_lane_s16_(a as _, b.0, b.1, LANE, 2) + let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); + vqrdmulh_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v4i16.p0i8")] - fn vst2_lane_s16_(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8); - } -vst2_lane_s16_(b.0, b.1, LANE as i64, a as _) + let b: int16x8_t = simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmulhq_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2i32")] - fn vst2_lane_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32); - } -vst2_lane_s32_(a as _, b.0, b.1, LANE, 4) -} - -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32) -#[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v2i32.p0i8")] - fn vst2_lane_s32_(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8); - } -vst2_lane_s32_(b.0, b.1, LANE as i64, a as _) -} - -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16) -#[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i16")] - fn vst2q_lane_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32); - } -vst2q_lane_s16_(a as _, b.0, b.1, LANE, 2) + let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulhq_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v8i16.p0i8")] - fn vst2q_lane_s16_(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8); - } -vst2q_lane_s16_(b.0, b.1, LANE as i64, a as _) -} - -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32) -#[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i32")] - fn vst2q_lane_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32); - } -vst2q_lane_s32_(a as _, b.0, b.1, LANE, 4) + let b: int16x8_t = simd_shuffle!( + b, + b, + [ + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32, + LANE as u32 + ] + ); + vqrdmulhq_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32) +#[doc = "Vector rounding saturating doubling multiply high by scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh, LANE = 1) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v4i32.p0i8")] - fn vst2q_lane_s32_(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8); - } -vst2q_lane_s32_(b.0, b.1, LANE as i64, a as _) + let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vqrdmulhq_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8) +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - vst2_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { + vqrdmulh_s16(a, vdup_n_s16(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16) +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - vst2_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { + vqrdmulhq_s16(a, vdupq_n_s16(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32) +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - vst2_lane_s32::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { + vqrdmulh_s32(a, vdup_n_s32(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16) +#[doc = "Vector saturating rounding doubling multiply high with scalar"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - vst2q_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { + vqrdmulhq_s32(a, vdupq_n_s32(b)) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - vst2q_lane_s32::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v4i16" + )] + fn _vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vqrdmulh_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - vst2_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v8i16" + )] + fn _vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vqrdmulhq_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - vst2_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v2i32" + )] + fn _vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vqrdmulh_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16) +#[doc = "Signed saturating rounding doubling multiply returning high half"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { - static_assert_uimm_bits!(LANE, 3); - vst2q_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrdmulh) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrdmulh.v4i32" + )] + fn _vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vqrdmulhq_s32(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2f32")] - fn vst2_lane_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v8i8" + )] + fn _vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vst2_lane_f32_(a as _, b.0, b.1, LANE, 4) + _vqrshl_s8(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v2f32.p0i8")] - fn vst2_lane_f32_(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v16i8" + )] + fn _vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vst2_lane_f32_(b.0, b.1, LANE as i64, a as _) + _vqrshlq_s8(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f32")] - fn vst2q_lane_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v4i16" + )] + fn _vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vst2q_lane_f32_(a as _, b.0, b.1, LANE, 4) + _vqrshl_s16(a, b) } -/// Store multiple 2-element structures from two registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st2, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st2lane.v4f32.p0i8")] - fn vst2q_lane_f32_(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v8i16" + )] + fn _vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vst2q_lane_f32_(b.0, b.1, LANE as i64, a as _) + _vqrshlq_s16(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i8")] - fn vst3_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v2i32" + )] + fn _vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vst3_s8_(a as _, b.0, b.1, b.2, 1) + _vqrshl_s32(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v8i8.p0i8")] - fn vst3_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v4i32" + )] + fn _vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vst3_s8_(b.0, b.1, b.2, a as _) + _vqrshlq_s32(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i16")] - fn vst3_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v1i64" + )] + fn _vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vst3_s16_(a as _, b.0, b.1, b.2, 2) + _vqrshl_s64(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16) +#[doc = "Signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v4i16.p0i8")] - fn vst3_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshl.v2i64" + )] + fn _vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vst3_s16_(b.0, b.1, b.2, a as _) + _vqrshlq_s64(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2i32")] - fn vst3_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v8i8" + )] + fn _vqrshl_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vst3_s32_(a as _, b.0, b.1, b.2, 4) + _vqrshl_u8(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v2i32.p0i8")] - fn vst3_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v16i8" + )] + fn _vqrshlq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vst3_s32_(b.0, b.1, b.2, a as _) + _vqrshlq_u8(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v16i8")] - fn vst3q_s8_(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v4i16" + )] + fn _vqrshl_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vst3q_s8_(a as _, b.0, b.1, b.2, 1) + _vqrshl_u16(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v16i8.p0i8")] - fn vst3q_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v8i16" + )] + fn _vqrshlq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vst3q_s8_(b.0, b.1, b.2, a as _) + _vqrshlq_u16(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i16")] - fn vst3q_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v2i32" + )] + fn _vqrshl_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vst3q_s16_(a as _, b.0, b.1, b.2, 2) + _vqrshl_u32(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v8i16.p0i8")] - fn vst3q_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v4i32" + )] + fn _vqrshlq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vst3q_s16_(b.0, b.1, b.2, a as _) + _vqrshlq_u32(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i32")] - fn vst3q_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v1i64" + )] + fn _vqrshl_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vst3q_s32_(a as _, b.0, b.1, b.2, 4) + _vqrshl_u64(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32) +#[doc = "Unsigned signed saturating rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqrshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v4i32.p0i8")] - fn vst3q_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshl.v2i64" + )] + fn _vqrshlq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vst3q_s32_(b.0, b.1, b.2, a as _) + _vqrshlq_u64(a.as_signed(), b).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v1i64")] - fn vst3_s64_(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")] + fn _vqrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } -vst3_s64_(a as _, b.0, b.1, b.2, 8) + _vqrshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v1i64.p0i8")] - fn vst3_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")] + fn _vqrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } -vst3_s64_(b.0, b.1, b.2, a as _) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { - vst3_s8(transmute(a), transmute(b)) + _vqrshrn_n_s32( + a, + const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { - vst3_s16(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] + fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + _vqrshrn_n_s64(a, const { int16x8_t([-N as i64, -N as i64]) }) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { - vst3_s32(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v8i8" + )] + fn _vqrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; + } + _vqrshrn_n_s16(a, N) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { - vst3q_s8(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v4i16" + )] + fn _vqrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; + } + _vqrshrn_n_s32(a, N) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16) +#[doc = "Signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { - vst3q_s16(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrn.v2i32" + )] + fn _vqrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; + } + _vqrshrn_n_s64(a, N) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { - vst3q_s32(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] + fn _vqrshrn_n_u16(a: int16x8_t, n: int16x8_t) -> int8x8_t; + } + _vqrshrnq_n_u16( + a.as_signed(), + const { + uint16x8_t([ + -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, + -N as u16, + ]) + }, + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { - vst3_s8(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] + fn _vqrshrn_n_u32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + _vqrshrnq_n_u32( + a.as_signed(), + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + ) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { - vst3_s16(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] + fn _vqrshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + _vqrshrnq_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) }) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { - vst3q_s8(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v8i8" + )] + fn _vqrshrn_n_u16(a: int16x8_t, n: i32) -> int8x8_t; + } + _vqrshrn_n_u16(a.as_signed(), N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { - vst3q_s16(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v4i16" + )] + fn _vqrshrn_n_u32(a: int32x4_t, n: i32) -> int16x4_t; + } + _vqrshrn_n_u32(a.as_signed(), N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64) +#[doc = "Unsigned signed saturating rounded shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { - vst3_s64(transmute(a), transmute(b)) -} - -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { - vst3_s64(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqrshrn.v2i32" + )] + fn _vqrshrn_n_u64(a: int64x2_t, n: i32) -> int32x2_t; + } + _vqrshrn_n_u64(a.as_signed(), N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!( + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + } + ); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2f32")] - fn vst3_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] + fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } -vst3_f32_(a as _, b.0, b.1, b.2, 4) + _vqrshrun_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v2f32.p0i8")] - fn vst3_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] + fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } -vst3_f32_(b.0, b.1, b.2, a as _) + _vqrshrun_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) + .as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3))] +#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(const { int64x2_t([-N as i64, -N as i64]) }); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f32")] - fn vst3q_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] + fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } -vst3q_f32_(a as _, b.0, b.1, b.2, 4) + _vqrshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3.v4f32.p0i8")] - fn vst3q_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v8i8" + )] + fn _vqrshrun_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } -vst3q_f32_(b.0, b.1, b.2, a as _) + _vqrshrun_n_s16(a, N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")] - fn vst3_lane_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v4i16" + )] + fn _vqrshrun_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } -vst3_lane_s8_(a as _, b.0, b.1, b.2, LANE, 1) + _vqrshrun_n_s32(a, N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8) +#[doc = "Signed saturating rounded shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v8i8.p0i8")] - fn vst3_lane_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqrshrun.v2i32" + )] + fn _vqrshrun_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } -vst3_lane_s8_(b.0, b.1, b.2, LANE as i64, a as _) + _vqrshrun_n_s64(a, N).as_unsigned() } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i16")] - fn vst3_lane_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i32, size: i32); - } -vst3_lane_s16_(a as _, b.0, b.1, b.2, LANE, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + vqshl_s8(a, vdup_n_s8(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v4i16.p0i8")] - fn vst3_lane_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8); - } -vst3_lane_s16_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + vqshlq_s8(a, vdupq_n_s8(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2i32")] - fn vst3_lane_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i32, size: i32); - } -vst3_lane_s32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 4); + vqshl_s16(a, vdup_n_s16(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v2i32.p0i8")] - fn vst3_lane_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8); - } -vst3_lane_s32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 4); + vqshlq_s16(a, vdupq_n_s16(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i16")] - fn vst3q_lane_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i32, size: i32); - } -vst3q_lane_s16_(a as _, b.0, b.1, b.2, LANE, 2) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 5); + vqshl_s32(a, vdup_n_s32(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v8i16.p0i8")] - fn vst3q_lane_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8); - } -vst3q_lane_s16_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 5); + vqshlq_s32(a, vdupq_n_s32(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i32")] - fn vst3q_lane_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i32, size: i32); - } -vst3q_lane_s32_(a as _, b.0, b.1, b.2, LANE, 4) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { + static_assert_uimm_bits!(N, 6); + vqshl_s64(a, vdup_n_s64(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v4i32.p0i8")] - fn vst3q_lane_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8); - } -vst3q_lane_s32_(b.0, b.1, b.2, LANE as i64, a as _) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 6); + vqshlq_s64(a, vdupq_n_s64(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - vst3_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + vqshl_u8(a, vdup_n_s8(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - vst3_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + vqshlq_u8(a, vdupq_n_s8(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - vst3_lane_s32::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + vqshl_u16(a, vdup_n_s16(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - vst3q_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + vqshlq_u16(a, vdupq_n_s16(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - vst3q_lane_s32::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + vqshl_u32(a, vdup_n_s32(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - vst3_lane_s8::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + vqshlq_u32(a, vdupq_n_s32(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - vst3_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + vqshl_u64(a, vdup_n_s64(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { - static_assert_uimm_bits!(LANE, 3); - vst3q_lane_s16::(transmute(a), transmute(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + vqshlq_u64(a, vdupq_n_s64(N as _)) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2f32")] - fn vst3_lane_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v8i8" + )] + fn _vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vst3_lane_f32_(a as _, b.0, b.1, b.2, LANE, 4) + _vqshl_s8(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v2f32.p0i8")] - fn vst3_lane_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v16i8" + )] + fn _vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vst3_lane_f32_(b.0, b.1, b.2, LANE as i64, a as _) + _vqshlq_s8(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f32")] - fn vst3q_lane_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v4i16" + )] + fn _vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vst3q_lane_f32_(a as _, b.0, b.1, b.2, LANE, 4) + _vqshl_s16(a, b) } -/// Store multiple 3-element structures from three registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st3, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st3lane.v4f32.p0i8")] - fn vst3q_lane_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v8i16" + )] + fn _vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vst3q_lane_f32_(b.0, b.1, b.2, LANE as i64, a as _) + _vqshlq_s16(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i8")] - fn vst4_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v2i32" + )] + fn _vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vst4_s8_(a as _, b.0, b.1, b.2, b.3, 1) + _vqshl_s32(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v8i8.p0i8")] - fn vst4_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v4i32" + )] + fn _vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vst4_s8_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_s32(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i16")] - fn vst4_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v1i64" + )] + fn _vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vst4_s16_(a as _, b.0, b.1, b.2, b.3, 2) + _vqshl_s64(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16) +#[doc = "Signed saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v4i16.p0i8")] - fn vst4_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshl.v2i64" + )] + fn _vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vst4_s16_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_s64(a, b) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2i32")] - fn vst4_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v8i8" + )] + fn _vqshl_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vst4_s32_(a as _, b.0, b.1, b.2, b.3, 4) + _vqshl_u8(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v2i32.p0i8")] - fn vst4_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v16i8" + )] + fn _vqshlq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vst4_s32_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_u8(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v16i8")] - fn vst4q_s8_(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v4i16" + )] + fn _vqshl_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vst4q_s8_(a as _, b.0, b.1, b.2, b.3, 1) + _vqshl_u16(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v16i8.p0i8")] - fn vst4q_s8_(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v8i16" + )] + fn _vqshlq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vst4q_s8_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_u16(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i16")] - fn vst4q_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v2i32" + )] + fn _vqshl_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vst4q_s16_(a as _, b.0, b.1, b.2, b.3, 2) + _vqshl_u32(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v8i16.p0i8")] - fn vst4q_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v4i32" + )] + fn _vqshlq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vst4q_s16_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_u32(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i32")] - fn vst4q_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v1i64" + )] + fn _vqshl_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vst4q_s32_(a as _, b.0, b.1, b.2, b.3, 4) + _vqshl_u64(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32) +#[doc = "Unsigned saturating shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v4i32.p0i8")] - fn vst4q_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshl.v2i64" + )] + fn _vqshlq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vst4q_s32_(b.0, b.1, b.2, b.3, a as _) + _vqshlq_u64(a.as_signed(), b).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(nop))] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v1i64")] - fn vst4_s64_(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] + fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> int8x8_t; } -vst4_s64_(a as _, b.0, b.1, b.2, b.3, 8) + _vqshlu_n_s8( + a, + const { + int8x8_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(nop))] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v1i64.p0i8")] - fn vst4_s64_(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] + fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> int8x16_t; } -vst4_s64_(b.0, b.1, b.2, b.3, a as _) + _vqshluq_n_s8( + a, + const { + int8x16_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] + fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> int16x4_t; + } + _vqshlu_n_s16( + a, + const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] + fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> int16x8_t; + } + _vqshluq_n_s16( + a, + const { + int16x8_t([ + N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { - vst4_s32(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] + fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> int32x2_t; + } + _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] + fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> int32x4_t; + } + _vqshluq_n_s32( + a, + const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")] + fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> int64x1_t; + } + _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { - vst4q_s32(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] + fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> int64x2_t; + } + _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { - vst4_s8(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v8i8" + )] + fn _vqshlu_n_s8(a: int8x8_t, n: int8x8_t) -> int8x8_t; + } + _vqshlu_n_s8( + a, + const { + int8x8_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { - vst4_s16(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { - vst4q_s8(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v16i8" + )] + fn _vqshluq_n_s8(a: int8x16_t, n: int8x16_t) -> int8x16_t; + } + _vqshluq_n_s8( + a, + const { + int8x16_t([ + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { - vst4q_s16(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v4i16" + )] + fn _vqshlu_n_s16(a: int16x4_t, n: int16x4_t) -> int16x4_t; + } + _vqshlu_n_s16( + a, + const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { - vst4_s64(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v8i16" + )] + fn _vqshluq_n_s16(a: int16x8_t, n: int16x8_t) -> int16x8_t; + } + _vqshluq_n_s16( + a, + const { + int16x8_t([ + N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2f32")] - fn vst4_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v2i32" + )] + fn _vqshlu_n_s32(a: int32x2_t, n: int32x2_t) -> int32x2_t; } -vst4_f32_(a as _, b.0, b.1, b.2, b.3, 4) + _vqshlu_n_s32(a, const { int32x2_t([N as i32, N as i32]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v2f32.p0i8")] - fn vst4_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v4i32" + )] + fn _vqshluq_n_s32(a: int32x4_t, n: int32x4_t) -> int32x4_t; } -vst4_f32_(b.0, b.1, b.2, b.3, a as _) + _vqshluq_n_s32( + a, + const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4))] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f32")] - fn vst4q_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v1i64" + )] + fn _vqshlu_n_s64(a: int64x1_t, n: int64x1_t) -> int64x1_t; } -vst4q_f32_(a as _, b.0, b.1, b.2, b.3, 4) + _vqshlu_n_s64(a, const { int64x1_t([N as i64]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32) +#[doc = "Signed saturating shift left unsigned"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4))] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshlu, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { - #[allow(improper_ctypes)] +pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4.v4f32.p0i8")] - fn vst4q_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshlu.v2i64" + )] + fn _vqshluq_n_s64(a: int64x2_t, n: int64x2_t) -> int64x2_t; } -vst4q_f32_(b.0, b.1, b.2, b.3, a as _) + _vqshluq_n_s64(a, const { int64x2_t([N as i64, N as i64]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i8")] - fn vst4_lane_s8_(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")] + fn _vqshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } -vst4_lane_s8_(a as _, b.0, b.1, b.2, b.3, LANE, 1) + _vqshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v8i8.p0i8")] - fn vst4_lane_s8_(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")] + fn _vqshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } -vst4_lane_s8_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrn_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i16")] - fn vst4_lane_s16_(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")] + fn _vqshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } -vst4_lane_s16_(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vqshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v4i16.p0i8")] - fn vst4_lane_s16_(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v8i8" + )] + fn _vqshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } -vst4_lane_s16_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrn_n_s16(a, N) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2i32")] - fn vst4_lane_s32_(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, n: i32, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v4i16" + )] + fn _vqshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } -vst4_lane_s32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vqshrn_n_s32(a, N) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32) +#[doc = "Signed saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v2i32.p0i8")] - fn vst4_lane_s32_(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrn.v2i32" + )] + fn _vqshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } -vst4_lane_s32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrn_n_s64(a, N) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i16")] - fn vst4q_lane_s16_(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] + fn _vqshrn_n_u16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } -vst4q_lane_s16_(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vqshrn_n_u16( + a.as_signed(), + const { + uint16x8_t([ + -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, + -N as u16, + ]) + }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v8i16.p0i8")] - fn vst4q_lane_s16_(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, n: i64, ptr: *mut i8); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] + fn _vqshrn_n_u32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } -vst4q_lane_s16_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrn_n_u32( + a.as_signed(), + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + ) + .as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i32")] - fn vst4q_lane_s32_(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] + fn _vqshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } -vst4q_lane_s32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vqshrn_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) }).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v4i32.p0i8")] - fn vst4q_lane_s32_(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v8i8" + )] + fn _vqshrn_n_u16(a: int16x8_t, n: i32) -> int8x8_t; } -vst4q_lane_s32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrn_n_u16(a.as_signed(), N).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v4i16" + )] + fn _vqshrn_n_u32(a: int32x4_t, n: i32) -> int16x4_t; + } + _vqshrn_n_u32(a.as_signed(), N).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16) +#[doc = "Unsigned saturating shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(uqshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqshrn.v2i32" + )] + fn _vqshrn_n_u64(a: int64x2_t, n: i32) -> int32x2_t; + } + _vqshrn_n_u64(a.as_signed(), N).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - vst4_lane_s32::(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] + fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; + } + _vqshrun_n_u8( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4q_lane_s32::(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4_lane_s8::(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - vst4_lane_s16::(transmute(a), transmute(b)) -} - -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { - static_assert_uimm_bits!(LANE, 3); - vst4q_lane_s16::(transmute(a), transmute(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] + fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + _vqshrun_n_u16( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2f32")] - fn vst4_lane_f32_(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, n: i32, size: i32); + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] + fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } -vst4_lane_f32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vqshrun_n_u32(a, const { int64x2_t([-N as i64, -N as i64]) }) } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { - static_assert_uimm_bits!(LANE, 1); - #[allow(improper_ctypes)] +pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v2f32.p0i8")] - fn vst4_lane_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v8i8" + )] + fn _vqshrun_n_s16(a: int16x8_t, n: i32) -> int8x8_t; } -vst4_lane_f32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrun_n_s16(a, N).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vst4, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f32")] - fn vst4q_lane_f32_(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, n: i32, size: i32); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v4i16" + )] + fn _vqshrun_n_s32(a: int32x4_t, n: i32) -> int16x4_t; } -vst4q_lane_f32_(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vqshrun_n_s32(a, N).as_unsigned() } -/// Store multiple 4-element structures from four registers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32) +#[doc = "Signed saturating shift right unsigned narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(st4, LANE = 0))] -#[rustc_legacy_const_generics(2)] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { - static_assert_uimm_bits!(LANE, 2); - #[allow(improper_ctypes)] +pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.st4lane.v4f32.p0i8")] - fn vst4q_lane_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, n: i64, ptr: *mut i8); + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqshrun.v2i32" + )] + fn _vqshrun_n_s64(a: int64x2_t, n: i32) -> int32x2_t; } -vst4q_lane_f32_(b.0, b.1, b.2, b.3, LANE as i64, a as _) + _vqshrun_n_s64(a, N).as_unsigned() } -/// Dot product vector form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usdot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8")] - fn vusdot_s32_(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.8i8")] + fn _vqsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vusdot_s32_(a, b, c) + _vqsub_s8(a, b) } -/// Dot product vector form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usdot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8")] - fn vusdotq_s32_(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.16i8")] + fn _vqsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vusdotq_s32_(a, b, c) -} - -/// Dot product index form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32) -#[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vusdot_lane_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, b, transmute(c)) -} - -/// Dot product index form with unsigned and signed integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32) -#[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vusdotq_lane_s32(a: int32x4_t, b: uint8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, b, transmute(c)) -} - -/// Dot product index form with signed and unsigned integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32) -#[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sudot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsudot_lane_s32(a: int32x2_t, b: int8x8_t, c: uint8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vusdot_s32(a, transmute(c), b) + _vqsubq_s8(a, b) } -/// Dot product index form with signed and unsigned integers -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,i8mm")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sudot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsudotq_lane_s32(a: int32x4_t, b: int8x16_t, c: uint8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vusdotq_s32(a, transmute(c), b) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.4i16")] + fn _vqsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vqsub_s16(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.8i16")] + fn _vqsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vqsubq_s16(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.2i32")] + fn _vqsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vqsub_s32(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.4i32")] + fn _vqsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vqsubq_s32(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v1i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.1i64")] + fn _vqsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vqsub_s64(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.s64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sqsub.v2i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.ssub.sat.2i64")] + fn _vqsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vqsubq_s64(a, b) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.8i8")] + fn _vqsub_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vqsub_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.16i8")] + fn _vqsubq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vqsubq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.4i16")] + fn _vqsub_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vqsub_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.8i16")] + fn _vqsubq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vqsubq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.2i32")] + fn _vqsub_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vqsub_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.4i32")] + fn _vqsubq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vqsubq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v1i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.1i64")] + fn _vqsub_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vqsub_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Polynomial multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8) +#[doc = "Saturating subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(pmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqsub.u64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uqsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vqsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.pmul.v8i8")] - fn vmul_p8_(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.uqsub.v2i64" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.usub.sat.2i64")] + fn _vqsubq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vmul_p8_(a, b) + _vqsubq_u64(a.as_signed(), b.as_signed()).as_unsigned() } -/// Polynomial multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(pmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frecpe) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulp.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.pmul.v16i8")] - fn vmulq_p8_(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v2f32" + )] + fn _vrecpe_f32(a: float32x2_t) -> float32x2_t; } -vmulq_p8_(a, b) + _vrecpe_f32(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32) +#[doc = "Reciprocal estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frecpe) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecpe.v4f32" + )] + fn _vrecpeq_f32(a: float32x4_t) -> float32x4_t; + } + _vrecpeq_f32(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32) +#[doc = "Unsigned reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmul.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_mul(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urecpe) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urecpe.v2i32" + )] + fn _vrecpe_u32(a: int32x2_t) -> int32x2_t; + } + _vrecpe_u32(a.as_signed()).as_unsigned() } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16) +#[doc = "Unsigned reciprocal estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - simd_mul(a, vdup_n_s16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urecpe) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urecpe.v4i32" + )] + fn _vrecpeq_u32(a: int32x4_t) -> int32x4_t; + } + _vrecpeq_u32(a.as_signed()).as_unsigned() } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - simd_mul(a, vdupq_n_s16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frecps) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v2f32" + )] + fn _vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vrecps_f32(a, b) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32) +#[doc = "Floating-point reciprocal step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - simd_mul(a, vdup_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frecps) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frecps.v4f32" + )] + fn _vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vrecpsq_f32(a, b) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - simd_mul(a, vdupq_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_n_u16(a: uint16x4_t, b: u16) -> uint16x4_t { - simd_mul(a, vdup_n_u16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_n_u16(a: uint16x8_t, b: u16) -> uint16x8_t { - simd_mul(a, vdupq_n_u16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_n_u32(a: uint32x2_t, b: u32) -> uint32x2_t { - simd_mul(a, vdup_n_u32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_n_u32(a: uint32x4_t, b: u32) -> uint32x4_t { - simd_mul(a, vdupq_n_u32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_n_f32(a: float32x2_t, b: f32) -> float32x2_t { - simd_mul(a, vdup_n_f32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { + transmute(a) } -/// Vector multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_n_f32(a: float32x4_t, b: f32) -> float32x4_t { - simd_mul(a, vdupq_n_f32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint16x4_t { - static_assert_uimm_bits!(LANE, 3); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_lane_u16(a: uint16x8_t, b: uint16x4_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_laneq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_lane_u32(a: uint32x4_t, b: uint32x2_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { + transmute(a) } -/// Multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(mul, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_laneq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { + transmute(a) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_lane_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { + transmute(a) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmul_laneq_f32(a: float32x2_t, b: float32x4_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { + transmute(a) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_lane_f32(a: float32x4_t, b: float32x2_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 1); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { + transmute(a) } -/// Floating-point multiply -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmul, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmul, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmulq_laneq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_mul(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { + transmute(a) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smull.v8i8")] - fn vmull_s8_(a: int8x8_t, b: int8x8_t) -> int16x8_t; - } -vmull_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { + transmute(a) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smull.v4i16")] - fn vmull_s16_(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } -vmull_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { + transmute(a) } -/// Signed multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmulls.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smull.v2i32")] - fn vmull_s32_(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } -vmull_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { + transmute(a) } -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umull.v8i8")] - fn vmull_u8_(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t; - } -vmull_u8_(a, b) -} - -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { + transmute(a) +} + +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umull.v4i16")] - fn vmull_u16_(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t; - } -vmull_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { + transmute(a) } -/// Unsigned multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umull.v2i32")] - fn vmull_u32_(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t; - } -vmull_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { + transmute(a) } -/// Polynomial multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vmull.p8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(pmull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_p8(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmullp.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.pmull.v8i8")] - fn vmull_p8_(a: poly8x8_t, b: poly8x8_t) -> poly16x8_t; - } -vmull_p8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { + transmute(a) } -/// Vector long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { - vmull_s16(a, vdup_n_s16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { + transmute(a) } -/// Vector long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { - vmull_s32(a, vdup_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { + transmute(a) } -/// Vector long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_n_u16(a: uint16x4_t, b: u16) -> uint32x4_t { - vmull_u16(a, vdup_n_u16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { + transmute(a) } -/// Vector long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_n_u32(a: uint32x2_t, b: u32) -> uint64x2_t { - vmull_u32(a, vdup_n_u32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmull_s16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_laneq_s16(a: int16x4_t, b: int16x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmull_s16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_laneq_s32(a: int32x2_t, b: int32x4_t) -> int64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmull_s32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_lane_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 2); - vmull_u16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_laneq_u16(a: uint16x4_t, b: uint16x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 3); - vmull_u16(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_lane_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { + transmute(a) } -/// Vector long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmull, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umull, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmull_laneq_u32(a: uint32x2_t, b: uint32x4_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 2); - vmull_u32(a, simd_shuffle!(b, b, [LANE as u32, LANE as u32])) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { + transmute(a) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfma_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.v2f32")] - fn vfma_f32_(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t; - } -vfma_f32_(b, c, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { + transmute(a) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfmaq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.fma.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.fma.v4f32")] - fn vfmaq_f32_(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t; - } -vfmaq_f32_(b, c, a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { + transmute(a) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfma_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfma_f32(a, b, vdup_n_f32_vfp4(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { + transmute(a) } -/// Floating-point fused Multiply-Add to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfma))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmla))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfmaq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmaq_f32(a, b, vdupq_n_f32_vfp4(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { + transmute(a) } -/// Floating-point fused multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfms_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t) -> float32x2_t { - let b: float32x2_t = simd_neg(b); - vfma_f32(a, b, c) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { + transmute(a) } -/// Floating-point fused multiply-subtract from accumulator -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfmsq_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t) -> float32x4_t { - let b: float32x4_t = simd_neg(b); - vfmaq_f32(a, b, c) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { + transmute(a) } -/// Floating-point fused Multiply-subtract to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfms_n_f32(a: float32x2_t, b: float32x2_t, c: f32) -> float32x2_t { - vfms_f32(a, b, vdup_n_f32_vfp4(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { + transmute(a) } -/// Floating-point fused Multiply-subtract to accumulator(vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "vfp4"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vfms))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmls))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vfmsq_n_f32(a: float32x4_t, b: float32x4_t, c: f32) -> float32x4_t { - vfmsq_f32(a, b, vdupq_n_f32_vfp4(c)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { + transmute(a) } -/// Subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - simd_sub(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vadd_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vadd_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vaddq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vaddq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_p64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vadd_p64(a: poly64x1_t, b: poly64x1_t) -> poly64x1_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vaddq_p64(a: poly64x2_t, b: poly64x2_t) -> poly64x2_t { - simd_xor(a, b) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { + transmute(a) } -/// Bitwise exclusive OR -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_p128) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vaddq_p128(a: p128, b: p128) -> p128 { - a ^ b +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - let c: i32x4 = i32x4::new(16, 16, 16, 16); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - let c: i64x2 = i64x2::new(32, 32); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - let c: u32x4 = u32x4::new(16, 16, 16, 16); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - let c: u64x2 = u64x2::new(32, 32); - simd_cast(simd_shr(simd_sub(a, b), transmute(c))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { - let d: int8x8_t = vsubhn_s16(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { - let d: int16x4_t = vsubhn_s32(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { - let d: int32x2_t = vsubhn_s64(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { - let d: uint8x8_t = vsubhn_u16(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { - let d: uint16x4_t = vsubhn_u32(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { + transmute(a) } -/// Subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(subhn2))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { - let d: uint32x2_t = vsubhn_u64(b, c); - simd_shuffle!(a, d, [0, 1, 2, 3]) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v8i8")] - fn vhsub_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } -vhsub_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v16i8")] - fn vhsubq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } -vhsubq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v4i16")] - fn vhsub_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vhsub_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v8i16")] - fn vhsubq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vhsubq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v2i32")] - fn vhsub_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } -vhsub_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uhsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uhsub.v4i32")] - fn vhsubq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } -vhsubq_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v8i8")] - fn vhsub_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vhsub_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v16i8")] - fn vhsubq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vhsubq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v4i16")] - fn vhsub_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vhsub_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v8i16")] - fn vhsubq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vhsubq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v2i32")] - fn vhsub_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vhsub_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { + transmute(a) } -/// Signed halving subtract -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vhsub.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shsub))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vhsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vhsubs.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.shsub.v4i32")] - fn vhsubq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vhsubq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { + transmute(a) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { + transmute(a) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { + transmute(a) } -/// Signed Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { + transmute(a) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { + transmute(a) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { + transmute(a) } -/// Unsigned Subtract Wide -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubw))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { - simd_sub(a, simd_cast(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { + transmute(a) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { - let c: int16x8_t = simd_cast(a); - let d: int16x8_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { + transmute(a) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - let c: int32x4_t = simd_cast(a); - let d: int32x4_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { + transmute(a) } -/// Signed Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - let c: int64x2_t = simd_cast(a); - let d: int64x2_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { + transmute(a) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { - let c: uint16x8_t = simd_cast(a); - let d: uint16x8_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { + transmute(a) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { - let c: uint32x4_t = simd_cast(a); - let d: uint32x4_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { + transmute(a) } -/// Unsigned Subtract Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usubl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { - let c: uint64x2_t = simd_cast(a); - let d: uint64x2_t = simd_cast(b); - simd_sub(c, d) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { + transmute(a) } -/// Dot product arithmetic (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sdot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v2i32.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sdot.v2i32.v8i8")] - fn vdot_s32_(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; - } -vdot_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { + transmute(a) } -/// Dot product arithmetic (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sdot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.sdot.v4i32.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sdot.v4i32.v16i8")] - fn vdotq_s32_(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; - } -vdotq_s32_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { + transmute(a) } -/// Dot product arithmetic (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(udot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdot_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v2i32.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.udot.v2i32.v8i8")] - fn vdot_u32_(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t; - } -vdot_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { + transmute(a) } -/// Dot product arithmetic (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(udot))] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdotq_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.udot.v4i32.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.udot.v4i32.v16i8")] - fn vdotq_u32_(a: uint32x4_t, b: uint8x16_t, c: uint8x16_t) -> uint32x4_t; - } -vdotq_u32_(a, b, c) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { + transmute(a) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdot_lane_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_s32(a, b, transmute(c)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { + transmute(a) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsdot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sdot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdotq_lane_s32(a: int32x4_t, b: int8x16_t, c: int8x8_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: int32x2_t = transmute(c); - let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_s32(a, b, transmute(c)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { + transmute(a) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdot_lane_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdot_lane_u32(a: uint32x2_t, b: uint8x8_t, c: uint8x8_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); - vdot_u32(a, b, transmute(c)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { + transmute(a) } -/// Dot product arithmetic (indexed) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdotq_lane_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,dotprod")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vudot, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(udot, LANE = 0))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_dotprod", issue = "117224"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vdotq_lane_u32(a: uint32x4_t, b: uint8x16_t, c: uint8x8_t) -> uint32x4_t { - static_assert_uimm_bits!(LANE, 1); - let c: uint32x2_t = transmute(c); - let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vdotq_u32(a, b, transmute(c)) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v8i8")] - fn vmax_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vmax_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v16i8")] - fn vmaxq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vmaxq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v4i16")] - fn vmax_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vmax_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v8i16")] - fn vmaxq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vmaxq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v2i32")] - fn vmax_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vmax_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smax.v4i32")] - fn vmaxq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vmaxq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v8i8")] - fn vmax_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } -vmax_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v16i8")] - fn vmaxq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } -vmaxq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v4i16")] - fn vmax_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vmax_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v8i16")] - fn vmaxq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vmaxq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v2i32")] - fn vmax_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } -vmax_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umax.v4i32")] - fn vmaxq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } -vmaxq_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmax_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmax.v2f32")] - fn vmax_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vmax_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { + transmute(a) } -/// Maximum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmax))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmax))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxs.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmax.v4f32")] - fn vmaxq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vmaxq_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { + transmute(a) } -/// Floating-point Maximum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmaxnm))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnm.v2f32")] - fn vmaxnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vmaxnm_f32_(a, b) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { + transmute(a) } -/// Floating-point Maximum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmaxnm))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmaxnm))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmaxnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmaxnm.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmaxnm.v4f32")] - fn vmaxnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vmaxnmq_f32_(a, b) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v8i8")] - fn vmin_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vmin_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v16i8")] - fn vminq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vminq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v4i16")] - fn vmin_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vmin_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v8i16")] - fn vminq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vminq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v2i32")] - fn vmin_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vmin_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(smin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.smin.v4i32")] - fn vminq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vminq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v8i8")] - fn vmin_u8_(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t; - } -vmin_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v16i8")] - fn vminq_u8_(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t; - } -vminq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v4i16")] - fn vmin_u16_(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t; - } -vmin_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v8i16")] - fn vminq_u16_(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t; - } -vminq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v2i32")] - fn vmin_u32_(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t; - } -vmin_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(umin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.umin.v4i32")] - fn vminq_u32_(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t; - } -vminq_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vmin_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmin.v2f32")] - fn vmin_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vmin_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { + transmute(a) } -/// Minimum (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vmin))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fmin))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vmins.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fmin.v4f32")] - fn vminq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vminq_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { + transmute(a) } -/// Floating-point Minimum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fminnm))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminnm_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnm.v2f32")] - fn vminnm_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vminnm_f32_(a, b) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { + transmute(a) } -/// Floating-point Minimum Number (vector) -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vminnm))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(fminnm))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vminnmq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vminnm.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.fminnm.v4f32")] - fn vminnmq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vminnmq_f32_(a, b) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { + transmute(a) } -/// Floating-point add pairwise -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vpadd))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(faddp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vpadd_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vpadd.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.faddp.v2f32")] - fn vpadd_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vpadd_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { + transmute(a) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmull.v4i32")] - fn vqdmull_s16_(a: int16x4_t, b: int16x4_t) -> int32x4_t; - } -vqdmull_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { + transmute(a) } -/// Signed saturating doubling multiply long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmull.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmull.v2i64")] - fn vqdmull_s32_(a: int32x2_t, b: int32x2_t) -> int64x2_t; - } -vqdmull_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { + transmute(a) } -/// Vector saturating doubling long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_n_s16(a: int16x4_t, b: i16) -> int32x4_t { - vqdmull_s16(a, vdup_n_s16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { + transmute(a) } -/// Vector saturating doubling long multiply with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_n_s32(a: int32x2_t, b: i32) -> int64x2_t { - vqdmull_s32(a, vdup_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { + transmute(a) } -/// Vector saturating doubling long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_lane_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - let b: int16x4_t = simd_shuffle!(b, b, [N as u32, N as u32, N as u32, N as u32]); - vqdmull_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { + transmute(a) } -/// Vector saturating doubling long multiply by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmull_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmull, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmull, N = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmull_lane_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - let b: int32x2_t = simd_shuffle!(b, b, [N as u32, N as u32]); - vqdmull_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { + transmute(a) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - vqaddq_s32(a, vqdmull_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { + transmute(a) } -/// Signed saturating doubling multiply-add long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - vqaddq_s64(a, vqdmull_s32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { + transmute(a) } -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vqaddq_s32(a, vqdmull_n_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { + transmute(a) } -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vqaddq_s64(a, vqdmull_n_s32(b, c)) -} +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { + transmute(a) +} -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal, N = 2))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqaddq_s32(a, vqdmull_lane_s16::(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { + transmute(a) } -/// Vector widening saturating doubling multiply accumulate with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlal_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlal, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlal, N = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlal_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqaddq_s64(a, vqdmull_lane_s32::(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { + transmute(a) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - vqsubq_s32(a, vqdmull_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { + transmute(a) } -/// Signed saturating doubling multiply-subtract long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - vqsubq_s64(a, vqdmull_s32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { + transmute(a) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_n_s16(a: int32x4_t, b: int16x4_t, c: i16) -> int32x4_t { - vqsubq_s32(a, vqdmull_n_s16(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { + transmute(a) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_n_s32(a: int64x2_t, b: int32x2_t, c: i32) -> int64x2_t { - vqsubq_s64(a, vqdmull_n_s32(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { + transmute(a) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl, N = 2))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_lane_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 2); - vqsubq_s32(a, vqdmull_lane_s16::(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { + transmute(a) } -/// Vector widening saturating doubling multiply subtract with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmlsl_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmlsl, N = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmlsl, N = 1))] -#[rustc_legacy_const_generics(3)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmlsl_lane_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 1); - vqsubq_s64(a, vqdmull_lane_s32::(b, c)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { + transmute(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmulh.v4i16")] - fn vqdmulh_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vqdmulh_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { + transmute(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmulh.v8i16")] - fn vqdmulhq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vqdmulhq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { + transmute(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmulh.v2i32")] - fn vqdmulh_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vqdmulh_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { + transmute(a) } -/// Signed saturating doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqdmulh.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqdmulh.v4i32")] - fn vqdmulhq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vqdmulhq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { + transmute(a) } -/// Vector saturating doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - let b: int16x4_t = vdup_n_s16(b); - vqdmulh_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { + transmute(a) } -/// Vector saturating doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - let b: int32x2_t = vdup_n_s32(b); - vqdmulh_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { + transmute(a) } -/// Vector saturating doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - let b: int16x8_t = vdupq_n_s16(b); - vqdmulhq_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { + transmute(a) } -/// Vector saturating doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - let b: int32x4_t = vdupq_n_s32(b); - vqdmulhq_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { + transmute(a) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - vqdmulhq_s16(a, vdupq_n_s16(simd_extract!(b, LANE as u32))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { + transmute(a) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - vqdmulh_s16(a, vdup_n_s16(simd_extract!(b, LANE as u32))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { + transmute(a) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulhq_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - vqdmulhq_s32(a, vdupq_n_s32(simd_extract!(b, LANE as u32))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { + transmute(a) } -/// Vector saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqdmulh_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqdmulh, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqdmulh, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - vqdmulh_s32(a, vdup_n_s32(simd_extract!(b, LANE as u32))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { + transmute(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_s16(a: int16x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtn.v8i8")] - fn vqmovn_s16_(a: int16x8_t) -> int8x8_t; - } -vqmovn_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { + transmute(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_s32(a: int32x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtn.v4i16")] - fn vqmovn_s32_(a: int32x4_t) -> int16x4_t; - } -vqmovn_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { + transmute(a) } -/// Signed saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_s64(a: int64x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovns.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtn.v2i32")] - fn vqmovn_s64_(a: int64x2_t) -> int32x2_t; - } -vqmovn_s64_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { + transmute(a) } -/// Unsigned saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_u16(a: uint16x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqxtn.v8i8")] - fn vqmovn_u16_(a: uint16x8_t) -> uint8x8_t; - } -vqmovn_u16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { + transmute(a) } -/// Unsigned saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_u32(a: uint32x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqxtn.v4i16")] - fn vqmovn_u32_(a: uint32x4_t) -> uint16x4_t; - } -vqmovn_u32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { + transmute(a) } -/// Unsigned saturating extract narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovn_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqxtn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovn_u64(a: uint64x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqxtn.v2i32")] - fn vqmovn_u64_(a: uint64x2_t) -> uint32x2_t; - } -vqmovn_u64_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtun))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovun_s16(a: int16x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtun.v8i8")] - fn vqmovun_s16_(a: int16x8_t) -> uint8x8_t; - } -vqmovun_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtun))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovun_s32(a: int32x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtun.v4i16")] - fn vqmovun_s32_(a: int32x4_t) -> uint16x4_t; - } -vqmovun_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { + transmute(a) } -/// Signed saturating extract unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqmovun_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqmovun))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqxtun))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqmovun_s64(a: int64x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqmovnsu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqxtun.v2i32")] - fn vqmovun_s64_(a: int64x2_t) -> uint32x2_t; - } -vqmovun_s64_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmulh.v4i16")] - fn vqrdmulh_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vqrdmulh_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmulh.v8i16")] - fn vqrdmulhq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vqrdmulhq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmulh.v2i32")] - fn vqrdmulh_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vqrdmulh_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { + transmute(a) } -/// Signed saturating rounding doubling multiply returning high half -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrdmulh.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrdmulh.v4i32")] - fn vqrdmulhq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vqrdmulhq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { + transmute(a) } -/// Vector saturating rounding doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_n_s16(a: int16x4_t, b: i16) -> int16x4_t { - vqrdmulh_s16(a, vdup_n_s16(b)) -} +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { + transmute(a) +} -/// Vector saturating rounding doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_n_s16(a: int16x8_t, b: i16) -> int16x8_t { - vqrdmulhq_s16(a, vdupq_n_s16(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { + transmute(a) } -/// Vector saturating rounding doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_n_s32(a: int32x2_t, b: i32) -> int32x2_t { - vqrdmulh_s32(a, vdup_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { + transmute(a) } -/// Vector saturating rounding doubling multiply high with scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_n_s32(a: int32x4_t, b: i32) -> int32x4_t { - vqrdmulhq_s32(a, vdupq_n_s32(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_lane_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_laneq_s16(a: int16x4_t, b: int16x8_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 3); - let b: int16x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulh_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_lane_s16(a: int16x8_t, b: int16x4_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 2); - let b: int16x8_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_laneq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - let b: int16x8_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s16(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_lane_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 1); - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulh_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulh_laneq_s32(a: int32x2_t, b: int32x4_t) -> int32x2_t { - static_assert_uimm_bits!(LANE, 2); - let b: int32x2_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32]); - vqrdmulh_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_lane_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_lane_s32(a: int32x4_t, b: int32x2_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 1); - let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { + transmute(a) } -/// Vector rounding saturating doubling multiply high by scalar -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrdmulhq_laneq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrdmulh, LANE = 1))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrdmulh, LANE = 1))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrdmulhq_laneq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - let b: int32x4_t = simd_shuffle!(b, b, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); - vqrdmulhq_s32(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v8i8")] - fn vqrshl_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vqrshl_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v16i8")] - fn vqrshlq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vqrshlq_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v4i16")] - fn vqrshl_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vqrshl_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v8i16")] - fn vqrshlq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vqrshlq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v2i32")] - fn vqrshl_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vqrshl_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v4i32")] - fn vqrshlq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vqrshlq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v1i64")] - fn vqrshl_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } -vqrshl_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { + transmute(a) } -/// Signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshifts.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshl.v2i64")] - fn vqrshlq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } -vqrshlq_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v8i8")] - fn vqrshl_u8_(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } -vqrshl_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v16i8")] - fn vqrshlq_u8_(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } -vqrshlq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v4i16")] - fn vqrshl_u16_(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } -vqrshl_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v8i16")] - fn vqrshlq_u16_(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } -vqrshlq_u16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v2i32")] - fn vqrshl_u32_(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } -vqrshl_u32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v4i32")] - fn vqrshlq_u32_(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } -vqrshlq_u32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v1i64")] - fn vqrshl_u64_(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } -vqrshl_u64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { + transmute(a) } -/// Unsigned signed saturating rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqrshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftu.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshl.v2i64")] - fn vqrshlq_u64_(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } -vqrshlq_u64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v8i8")] - fn vqrshrn_n_s16_(a: int16x8_t, n: int16x8_t) -> int8x8_t; - } -vqrshrn_n_s16_(a, const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrn.v8i8")] - fn vqrshrn_n_s16_(a: int16x8_t, n: i32) -> int8x8_t; - } -vqrshrn_n_s16_(a, N) -} - -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32) -#[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v4i16")] - fn vqrshrn_n_s32_(a: int32x4_t, n: int32x4_t) -> int16x4_t; - } -vqrshrn_n_s32_(a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrn.v4i16")] - fn vqrshrn_n_s32_(a: int32x4_t, n: i32) -> int16x4_t; - } -vqrshrn_n_s32_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] - fn vqrshrn_n_s64_(a: int64x2_t, n: int64x2_t) -> int32x2_t; - } -vqrshrn_n_s64_(a, const { int64x2_t([-N as i64, -N as i64]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { + transmute(a) } -/// Signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrn.v2i32")] - fn vqrshrn_n_s64_(a: int64x2_t, n: i32) -> int32x2_t; - } -vqrshrn_n_s64_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] - fn vqrshrn_n_u16_(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; - } -vqrshrn_n_u16_(a, const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshrn.v8i8")] - fn vqrshrn_n_u16_(a: uint16x8_t, n: i32) -> uint8x8_t; - } -vqrshrn_n_u16_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] - fn vqrshrn_n_u32_(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; - } -vqrshrn_n_u32_(a, const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshrn.v4i16")] - fn vqrshrn_n_u32_(a: uint32x4_t, n: i32) -> uint16x4_t; - } -vqrshrn_n_u32_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] - fn vqrshrn_n_u64_(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; - } -vqrshrn_n_u64_(a, const { uint64x2_t([-N as u64, -N as u64]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { + transmute(a) } -/// Unsigned signed saturating rounded shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqrshrn.v2i32")] - fn vqrshrn_n_u64_(a: uint64x2_t, n: i32) -> uint32x2_t; - } -vqrshrn_n_u64_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] - fn vqrshrun_n_s16_(a: int16x8_t, n: int16x8_t) -> uint8x8_t; - } -vqrshrun_n_s16_(a, const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrun.v8i8")] - fn vqrshrun_n_s16_(a: int16x8_t, n: i32) -> uint8x8_t; - } -vqrshrun_n_s16_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] - fn vqrshrun_n_s32_(a: int32x4_t, n: int32x4_t) -> uint16x4_t; - } -vqrshrun_n_s32_(a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrun.v4i16")] - fn vqrshrun_n_s32_(a: int32x4_t, n: i32) -> uint16x4_t; - } -vqrshrun_n_s32_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] - fn vqrshrun_n_s64_(a: int64x2_t, n: int64x2_t) -> uint32x2_t; - } -vqrshrun_n_s64_(a, const { int64x2_t([-N as i64, -N as i64]) }) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { + transmute(a) } -/// Signed saturating rounded shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqrshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqrshrun.v2i32")] - fn vqrshrun_n_s64_(a: int64x2_t, n: i32) -> uint32x2_t; - } -vqrshrun_n_s64_(a, N) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v8i8")] - fn vqshl_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vqshl_s8_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v16i8")] - fn vqshlq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; - } -vqshlq_s8_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v4i16")] - fn vqshl_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; - } -vqshl_s16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v8i16")] - fn vqshlq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vqshlq_s16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v2i32")] - fn vqshl_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vqshl_s32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v4i32")] - fn vqshlq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vqshlq_s32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v1i64")] - fn vqshl_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } -vqshl_s64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshifts.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshl.v2i64")] - fn vqshlq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } -vqshlq_s64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v8i8")] - fn vqshl_u8_(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } -vqshl_u8_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v16i8")] - fn vqshlq_u8_(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } -vqshlq_u8_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v4i16")] - fn vqshl_u16_(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } -vqshl_u16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v8i16")] - fn vqshlq_u16_(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } -vqshlq_u16_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v2i32")] - fn vqshl_u32_(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } -vqshl_u32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v4i32")] - fn vqshlq_u32_(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; - } -vqshlq_u32_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v1i64")] - fn vqshl_u64_(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; - } -vqshl_u64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftu.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshl.v2i64")] - fn vqshlq_u64_(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; - } -vqshlq_u64_(a, b) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - vqshl_s8(a, vdup_n_s8(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - vqshlq_s8(a, vdupq_n_s8(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 4); - vqshl_s16(a, vdup_n_s16(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 4); - vqshlq_s16(a, vdupq_n_s16(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 5); - vqshl_s32(a, vdup_n_s32(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 5); - vqshlq_s32(a, vdupq_n_s32(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_s64(a: int64x1_t) -> int64x1_t { - static_assert_uimm_bits!(N, 6); - vqshl_s64(a, vdup_n_s64(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { + transmute(a) } -/// Signed saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 6); - vqshlq_s64(a, vdupq_n_s64(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - vqshl_u8(a, vdup_n_s8(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - vqshlq_u8(a, vdupq_n_s8(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - vqshl_u16(a, vdup_n_s16(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - vqshlq_u16(a, vdupq_n_s16(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - vqshl_u32(a, vdup_n_s32(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - vqshlq_u32(a, vdupq_n_s32(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshl_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - vqshl_u64(a, vdup_n_s64(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { + transmute(a) } -/// Unsigned saturating shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64) +#[doc = "Vector reinterpret cast operation"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vqshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uqshl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqshlq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - vqshlq_u64(a, vdupq_n_s64(N as _)) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { + transmute(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i8")] - fn vqshlu_n_s8_(a: int8x8_t, n: int8x8_t) -> uint8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i8")] + fn _vrhadd_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vqshlu_n_s8_(a, const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }) + _vrhadd_s8(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s8(a: int8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v8i8")] - fn vqshlu_n_s8_(a: int8x8_t, n: int8x8_t) -> uint8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v16i8")] + fn _vrhaddq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vqshlu_n_s8_(a, const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }) + _vrhaddq_s8(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i16")] - fn vqshlu_n_s16_(a: int16x4_t, n: int16x4_t) -> uint16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i16")] + fn _vrhadd_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vqshlu_n_s16_(a, const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }) + _vrhadd_s16(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s16(a: int16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v4i16")] - fn vqshlu_n_s16_(a: int16x4_t, n: int16x4_t) -> uint16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v8i16")] + fn _vrhaddq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vqshlu_n_s16_(a, const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }) + _vrhaddq_s16(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i32")] - fn vqshlu_n_s32_(a: int32x2_t, n: int32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v2i32")] + fn _vrhadd_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vqshlu_n_s32_(a, const { int32x2_t([N as i32, N as i32]) }) + _vrhadd_s32(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s32(a: int32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.s32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v2i32")] - fn vqshlu_n_s32_(a: int32x2_t, n: int32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhadds.v4i32")] + fn _vrhaddq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vqshlu_n_s32_(a, const { int32x2_t([N as i32, N as i32]) }) + _vrhaddq_s32(a, b) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v1i64")] - fn vqshlu_n_s64_(a: int64x1_t, n: int64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i8")] + fn _vrhadd_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vqshlu_n_s64_(a, const { int64x1_t([N as i64]) }) + _vrhadd_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshlu_n_s64(a: int64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v1i64")] - fn vqshlu_n_s64_(a: int64x1_t, n: int64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v16i8")] + fn _vrhaddq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vqshlu_n_s64_(a, const { int64x1_t([N as i64]) }) + _vrhaddq_u8(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v16i8")] - fn vqshluq_n_s8_(a: int8x16_t, n: int8x16_t) -> uint8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v4i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i16")] + fn _vrhadd_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vqshluq_n_s8_(a, const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }) + _vrhadd_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s8(a: int8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v16i8")] - fn vqshluq_n_s8_(a: int8x16_t, n: int8x16_t) -> uint8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v8i16" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v8i16")] + fn _vrhaddq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vqshluq_n_s8_(a, const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }) + _vrhaddq_u16(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhadd_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v8i16")] - fn vqshluq_n_s16_(a: int16x8_t, n: int16x8_t) -> uint16x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v2i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v2i32")] + fn _vrhadd_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vqshluq_n_s16_(a, const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }) + _vrhadd_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16) +#[doc = "Rounding halving add"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s16(a: int16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vrhadd.u32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urhadd) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrhaddq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v8i16")] - fn vqshluq_n_s16_(a: int16x8_t, n: int16x8_t) -> uint16x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urhadd.v4i32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrhaddu.v4i32")] + fn _vrhaddq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vqshluq_n_s16_(a, const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }) + _vrhaddq_u32(a.as_signed(), b.as_signed()).as_unsigned() } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32) +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v4i32")] - fn vqshluq_n_s32_(a: int32x4_t, n: int32x4_t) -> uint32x4_t; - } -vqshluq_n_s32_(a, const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }) -} - -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32) -#[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s32(a: int32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frintn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrndn_f32(a: float32x2_t) -> float32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v4i32")] - fn vqshluq_n_s32_(a: int32x4_t, n: int32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frintn.v2f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v2f32")] + fn _vrndn_f32(a: float32x2_t) -> float32x2_t; } -vqshluq_n_s32_(a, const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }) + _vrndn_f32(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64) +#[doc = "Floating-point round to integral, to nearest with ties to even"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "fp-armv8,v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrintn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frintn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrndnq_f32(a: float32x4_t) -> float32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftsu.v2i64")] - fn vqshluq_n_s64_(a: int64x2_t, n: int64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frintn.v4f32" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrintn.v4f32")] + fn _vrndnq_f32(a: float32x4_t) -> float32x4_t; } -vqshluq_n_s64_(a, const { int64x2_t([N as i64, N as i64]) }) + _vrndnq_f32(a) } -/// Signed saturating shift left unsigned -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshlu, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshluq_n_s64(a: int64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshlu.v2i64")] - fn vqshluq_n_s64_(a: int64x2_t, n: int64x2_t) -> uint64x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v8i8" + )] + fn _vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vqshluq_n_s64_(a, const { int64x2_t([N as i64, N as i64]) }) + _vrshl_s8(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v8i8")] - fn vqshrn_n_s16_(a: int16x8_t, n: int16x8_t) -> int8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v16i8" + )] + fn _vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vqshrn_n_s16_(a, const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }) + _vrshlq_s8(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrn.v8i8")] - fn vqshrn_n_s16_(a: int16x8_t, n: i32) -> int8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v4i16" + )] + fn _vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vqshrn_n_s16_(a, N) + _vrshl_s16(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v4i16")] - fn vqshrn_n_s32_(a: int32x4_t, n: int32x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v8i16" + )] + fn _vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vqshrn_n_s32_(a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }) + _vrshlq_s16(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrn.v4i16")] - fn vqshrn_n_s32_(a: int32x4_t, n: i32) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v2i32" + )] + fn _vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vqshrn_n_s32_(a, N) + _vrshl_s32(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftns.v2i32")] - fn vqshrn_n_s64_(a: int64x2_t, n: int64x2_t) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v4i32" + )] + fn _vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vqshrn_n_s64_(a, const { int64x2_t([-N as i64, -N as i64]) }) + _vrshlq_s32(a, b) } -/// Signed saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrn.v2i32")] - fn vqshrn_n_s64_(a: int64x2_t, n: i32) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v1i64" + )] + fn _vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vqshrn_n_s64_(a, N) + _vrshl_s64(a, b) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16) +#[doc = "Signed rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v8i8")] - fn vqshrn_n_u16_(a: uint16x8_t, n: uint16x8_t) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.srshl.v2i64" + )] + fn _vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vqshrn_n_u16_(a, const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }) + _vrshlq_s64(a, b) } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshrn.v8i8")] - fn vqshrn_n_u16_(a: uint16x8_t, n: i32) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v8i8" + )] + fn _vrshl_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; } -vqshrn_n_u16_(a, N) + _vrshl_u8(a.as_signed(), b).as_unsigned() } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v4i16")] - fn vqshrn_n_u32_(a: uint32x4_t, n: uint32x4_t) -> uint16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v16i8" + )] + fn _vrshlq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; } -vqshrn_n_u32_(a, const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }) + _vrshlq_u8(a.as_signed(), b).as_unsigned() } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshrn.v4i16")] - fn vqshrn_n_u32_(a: uint32x4_t, n: i32) -> uint16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v4i16" + )] + fn _vrshl_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; } -vqshrn_n_u32_(a, N) + _vrshl_u16(a.as_signed(), b).as_unsigned() } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] - fn vqshrn_n_u64_(a: uint64x2_t, n: uint64x2_t) -> uint32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v8i16" + )] + fn _vrshlq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; } -vqshrn_n_u64_(a, const { uint64x2_t([-N as u64, -N as u64]) }) + _vrshlq_u16(a.as_signed(), b).as_unsigned() } -/// Unsigned saturating shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(uqshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.uqshrn.v2i32")] - fn vqshrn_n_u64_(a: uint64x2_t, n: i32) -> uint32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v2i32" + )] + fn _vrshl_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; } -vqshrn_n_u64_(a, N) + _vrshl_u32(a.as_signed(), b).as_unsigned() } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] - fn vqshrun_n_s16_(a: int16x8_t, n: int16x8_t) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v4i32" + )] + fn _vrshlq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; } -vqshrun_n_s16_(a, const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }) + _vrshlq_u32(a.as_signed(), b).as_unsigned() } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrun.v8i8")] - fn vqshrun_n_s16_(a: int16x8_t, n: i32) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v1i64" + )] + fn _vrshl_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; } -vqshrun_n_s16_(a, N) + _vrshl_u64(a.as_signed(), b).as_unsigned() } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32) +#[doc = "Unsigned rounding shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] - fn vqshrun_n_s32_(a: int32x4_t, n: int32x4_t) -> uint16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.urshl.v2i64" + )] + fn _vrshlq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; } -vqshrun_n_s32_(a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }) + _vrshlq_u64(a.as_signed(), b).as_unsigned() } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrun.v4i16")] - fn vqshrun_n_s32_(a: int32x4_t, n: i32) -> uint16x4_t; - } -vqshrun_n_s32_(a, N) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + vrshl_s8(a, vdup_n_s8(-N as _)) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vqshrun, N = 2))] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] - fn vqshrun_n_s64_(a: int64x2_t, n: int64x2_t) -> uint32x2_t; - } -vqshrun_n_s64_(a, const { int64x2_t([-N as i64, -N as i64]) }) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + vrshlq_s8(a, vdupq_n_s8(-N as _)) } -/// Signed saturating shift right unsigned narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(sqshrun, N = 2))] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] #[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqshrun.v2i32")] - fn vqshrun_n_s64_(a: int64x2_t, n: i32) -> uint32x2_t; - } -vqshrun_n_s64_(a, N) +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + vrshl_s16(a, vdup_n_s16(-N as _)) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frsqrte))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.v2f32")] - fn vrsqrte_f32_(a: float32x2_t) -> float32x2_t; - } -vrsqrte_f32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + vrshlq_s16(a, vdupq_n_s16(-N as _)) } -/// Reciprocal square-root estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frsqrte))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrte.v4f32")] - fn vrsqrteq_f32_(a: float32x4_t) -> float32x4_t; - } -vrsqrteq_f32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + vrshl_s32(a, vdup_n_s32(-N as _)) } -/// Unsigned reciprocal square root estimate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursqrte))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ursqrte.v2i32")] - fn vrsqrte_u32_(a: uint32x2_t) -> uint32x2_t; - } -vrsqrte_u32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + vrshlq_s32(a, vdupq_n_s32(-N as _)) } -/// Unsigned reciprocal square root estimate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursqrte))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ursqrte.v4i32")] - fn vrsqrteq_u32_(a: uint32x4_t) -> uint32x4_t; - } -vrsqrteq_u32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + vrshl_s64(a, vdup_n_s64(-N as _)) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32) +#[doc = "Signed rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frsqrts))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.v2f32")] - fn vrsqrts_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vrsqrts_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + vrshlq_s64(a, vdupq_n_s64(-N as _)) } -/// Floating-point reciprocal square root step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frsqrts))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frsqrts.v4f32")] - fn vrsqrtsq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vrsqrtsq_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + vrshl_u8(a, vdup_n_s8(-N as _)) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frecpe))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecpe_f32(a: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.v2f32")] - fn vrecpe_f32_(a: float32x2_t) -> float32x2_t; - } -vrecpe_f32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + vrshlq_u8(a, vdupq_n_s8(-N as _)) } -/// Reciprocal estimate. -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frecpe))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecpeq_f32(a: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecpe.v4f32")] - fn vrecpeq_f32_(a: float32x4_t) -> float32x4_t; - } -vrecpeq_f32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + vrshl_u16(a, vdup_n_s16(-N as _)) } -/// Unsigned reciprocal estimate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urecpe))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecpe_u32(a: uint32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urecpe.v2i32")] - fn vrecpe_u32_(a: uint32x2_t) -> uint32x2_t; - } -vrecpe_u32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + vrshlq_u16(a, vdupq_n_s16(-N as _)) } -/// Unsigned reciprocal estimate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecpe))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urecpe))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecpeq_u32(a: uint32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecpe.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urecpe.v4i32")] - fn vrecpeq_u32_(a: uint32x4_t) -> uint32x4_t; - } -vrecpeq_u32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + vrshl_u32(a, vdup_n_s32(-N as _)) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frecps))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecps_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v2f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.v2f32")] - fn vrecps_f32_(a: float32x2_t, b: float32x2_t) -> float32x2_t; - } -vrecps_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + vrshlq_u32(a, vdupq_n_s32(-N as _)) } -/// Floating-point reciprocal step -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrecps))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(frecps))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrecpsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrecps.v4f32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.frecps.v4f32")] - fn vrecpsq_f32_(a: float32x4_t, b: float32x4_t) -> float32x4_t; - } -vrecpsq_f32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + vrshl_u64(a, vdup_n_s64(-N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u8) +#[doc = "Unsigned rounding shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_u8(a: uint8x8_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(urshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + vrshlq_u64(a, vdupq_n_s64(-N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p8) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_p8(a: poly8x8_t) -> int8x8_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")] + fn _vrshrn_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; + } + _vrshrn_n_s16( + a, + const { + int16x8_t([ + -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, + -N as i16, + ]) + }, + ) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p16) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_p16(a: poly16x4_t) -> int16x4_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")] + fn _vrshrn_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; + } + _vrshrn_n_s32( + a, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + ) +} + +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vrshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")] + fn _vrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; + } + _vrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u16) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_u16(a: uint16x4_t) -> int16x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v8i8" + )] + fn _vrshrn_n_s16(a: int16x8_t, n: i32) -> int8x8_t; + } + _vrshrn_n_s16(a, N) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u32) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_u32(a: uint32x2_t) -> int32x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v4i16" + )] + fn _vrshrn_n_s32(a: int32x4_t, n: i32) -> int16x4_t; + } + _vrshrn_n_s32(a, N) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u64) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_u64(a: uint64x1_t) -> int64x1_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(rshrn, N = 2))] +#[rustc_legacy_const_generics(1)] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rshrn.v2i32" + )] + fn _vrshrn_n_s64(a: int64x2_t, n: i32) -> int32x2_t; + } + _vrshrn_n_s64(a, N) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u8) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_u8(a: uint8x16_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rshrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + transmute(vrshrn_n_s16::(transmute(a))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p8) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_p8(a: poly8x16_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rshrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + transmute(vrshrn_n_s32::(transmute(a))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p16) +#[doc = "Rounding shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_p16(a: poly16x8_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rshrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + transmute(vrshrn_n_s64::(transmute(a))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u16) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_u16(a: uint16x8_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frsqrte) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrte_f32(a: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v2f32" + )] + fn _vrsqrte_f32(a: float32x2_t) -> float32x2_t; + } + _vrsqrte_f32(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u32) +#[doc = "Reciprocal square-root estimate."] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_u32(a: uint32x4_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frsqrte) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrteq_f32(a: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrte.v4f32" + )] + fn _vrsqrteq_f32(a: float32x4_t) -> float32x4_t; + } + _vrsqrteq_f32(a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u64) +#[doc = "Unsigned reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_u64(a: uint64x2_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursqrte) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrte_u32(a: uint32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ursqrte.v2i32" + )] + fn _vrsqrte_u32(a: int32x2_t) -> int32x2_t; + } + _vrsqrte_u32(a.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p8) +#[doc = "Unsigned reciprocal square root estimate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_p8(a: poly8x8_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrte))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursqrte) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrteq_u32(a: uint32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrte.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ursqrte.v4i32" + )] + fn _vrsqrteq_u32(a: int32x4_t) -> int32x4_t; + } + _vrsqrteq_u32(a.as_signed()).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s8) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_s8(a: int8x8_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frsqrts) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v2f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v2f32" + )] + fn _vrsqrts_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t; + } + _vrsqrts_f32(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p16) +#[doc = "Floating-point reciprocal square root step"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_p16(a: poly16x4_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsqrts))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(frsqrts) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsqrts.v4f32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.frsqrts.v4f32" + )] + fn _vrsqrtsq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t; + } + _vrsqrtsq_f32(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s16) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_s16(a: int16x4_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vrshr_n_s8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s32) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_s32(a: int32x2_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vrshrq_n_s8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s64) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_s64(a: int64x1_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vrshr_n_s16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p8) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_p8(a: poly8x16_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vrshrq_n_s16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s8) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_s8(a: int8x16_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vrshr_n_s32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p16) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_p16(a: poly16x8_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vrshrq_n_s32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s16) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_s16(a: int16x8_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vrshr_n_s64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s32) +#[doc = "Signed rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_s32(a: int32x4_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(srsra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vrshrq_n_s64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s64) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_s64(a: int64x2_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vrshr_n_u8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s8) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_s8(a: int8x8_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vrshrq_n_u8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u8) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_u8(a: uint8x8_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vrshr_n_u16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s16) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_s16(a: int16x4_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vrshrq_n_u16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u16) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_u16(a: uint16x4_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vrshr_n_u32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s8) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_s8(a: int8x16_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vrshrq_n_u32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u8) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_u8(a: uint8x16_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vrshr_n_u64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s16) +#[doc = "Unsigned rounding shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_s16(a: int16x8_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ursra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vrshrq_n_u64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u16) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_u16(a: uint16x8_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v8i8" + )] + fn _vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t; + } + _vrsubhn_s16(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s16) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_s16(a: int16x4_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v4i16" + )] + fn _vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t; + } + _vrsubhn_s32(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u16) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_u16(a: uint16x4_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.rsubhn.v2i32" + )] + fn _vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t; + } + _vrsubhn_s64(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p16) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_p16(a: poly16x4_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + transmute(vrsubhn_s16(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s32) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_s32(a: int32x2_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + transmute(vrsubhn_s32(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u32) +#[doc = "Rounding subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_u32(a: uint32x2_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(rsubhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + transmute(vrsubhn_s64(transmute(a), transmute(b))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_s64(a: int64x1_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_u64(a: uint64x1_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_s16(a: int16x8_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_u16(a: uint16x8_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_p16(a: poly16x8_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_s32(a: int32x4_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_u32(a: uint32x4_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_s64(a: int64x2_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_u64(a: uint64x2_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_p16(a: poly16x4_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_s16(a: int16x4_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_u16(a: uint16x4_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_s32(a: int32x2_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_u32(a: uint32x2_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_s64(a: int64x1_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_u64(a: uint64x1_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_p16(a: poly16x8_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_s16(a: int16x8_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { + static_assert_uimm_bits!(LANE, 4); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_u16(a: uint16x8_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { + static_assert_uimm_bits!(LANE, 2); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_s32(a: int32x4_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { + static_assert_uimm_bits!(LANE, 3); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u32) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_u32(a: uint32x4_t) -> uint16x8_t { - transmute(a) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { + static_assert!(LANE == 0); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_s64(a: int64x2_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { + static_assert!(LANE == 0); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u64) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_u64(a: uint64x2_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { + static_assert!(LANE == 0); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p16) +#[doc = "Insert vector element from another vector element"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_p16(a: poly16x4_t) -> poly8x8_t { - transmute(a) +#[target_feature(enable = "neon,aes")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { + static_assert_uimm_bits!(LANE, 1); + simd_insert!(b, LANE as u32, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s16) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_s16(a: int16x4_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_s8(a: int8x8_t) -> int8x8_t { + static_assert_uimm_bits!(N, 3); + simd_shl(a, vdup_n_s8(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u16) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_u16(a: uint16x4_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert_uimm_bits!(N, 3); + simd_shl(a, vdupq_n_s8(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s32) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_s32(a: int32x2_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_s16(a: int16x4_t) -> int16x4_t { + static_assert_uimm_bits!(N, 4); + simd_shl(a, vdup_n_s16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u32) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_u32(a: uint32x2_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert_uimm_bits!(N, 4); + simd_shl(a, vdupq_n_s16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p16) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_p16(a: poly16x8_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_s32(a: int32x2_t) -> int32x2_t { + static_assert_uimm_bits!(N, 5); + simd_shl(a, vdup_n_s32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s16) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_s16(a: int16x8_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert_uimm_bits!(N, 5); + simd_shl(a, vdupq_n_s32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u16) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_u16(a: uint16x8_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_s64(a: int64x1_t) -> int64x1_t { + static_assert_uimm_bits!(N, 6); + simd_shl(a, vdup_n_s64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s32) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_s32(a: int32x4_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert_uimm_bits!(N, 6); + simd_shl(a, vdupq_n_s64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u32) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_u32(a: uint32x4_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert_uimm_bits!(N, 3); + simd_shl(a, vdup_n_u8(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p64) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_p64(a: poly64x1_t) -> int32x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert_uimm_bits!(N, 3); + simd_shl(a, vdupq_n_u8(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p64) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_p64(a: poly64x1_t) -> uint32x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert_uimm_bits!(N, 4); + simd_shl(a, vdup_n_u16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p64) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_p64(a: poly64x2_t) -> int32x4_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert_uimm_bits!(N, 4); + simd_shl(a, vdupq_n_u16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p64) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_p64(a: poly64x2_t) -> uint32x4_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert_uimm_bits!(N, 5); + simd_shl(a, vdup_n_u32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p128) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_p128(a: p128) -> int64x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert_uimm_bits!(N, 5); + simd_shl(a, vdupq_n_u32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p128) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_p128(a: p128) -> uint64x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert_uimm_bits!(N, 6); + simd_shl(a, vdup_n_u64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p128) +#[doc = "Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_p128(a: p128) -> poly64x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shl, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert_uimm_bits!(N, 6); + simd_shl(a, vdupq_n_u64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p8) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_p8(a: poly8x8_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v8i8" + )] + fn _vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vshl_s8(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s8) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_s8(a: int8x8_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v16i8" + )] + fn _vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vshlq_s8(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u8) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_u8(a: uint8x8_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v4i16" + )] + fn _vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vshl_s16(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p16) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_p16(a: poly16x4_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v8i16" + )] + fn _vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vshlq_s16(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s16) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_s16(a: int16x4_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v2i32" + )] + fn _vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vshl_s32(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u16) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_u16(a: uint16x4_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v4i32" + )] + fn _vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vshlq_s32(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s32) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_s32(a: int32x2_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v1i64" + )] + fn _vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vshl_s64(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u32) +#[doc = "Signed Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_u32(a: uint32x2_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.sshl.v2i64" + )] + fn _vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vshlq_s64(a, b) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p8) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_p8(a: poly8x16_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v8i8" + )] + fn _vshl_u8(a: int8x8_t, b: int8x8_t) -> int8x8_t; + } + _vshl_u8(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s8) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_s8(a: int8x16_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v16i8" + )] + fn _vshlq_u8(a: int8x16_t, b: int8x16_t) -> int8x16_t; + } + _vshlq_u8(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u8) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_u8(a: uint8x16_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v4i16" + )] + fn _vshl_u16(a: int16x4_t, b: int16x4_t) -> int16x4_t; + } + _vshl_u16(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p16) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_p16(a: poly16x8_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v8i16" + )] + fn _vshlq_u16(a: int16x8_t, b: int16x8_t) -> int16x8_t; + } + _vshlq_u16(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s16) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_s16(a: int16x8_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v2i32" + )] + fn _vshl_u32(a: int32x2_t, b: int32x2_t) -> int32x2_t; + } + _vshl_u32(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u16) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_u16(a: uint16x8_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v4i32" + )] + fn _vshlq_u32(a: int32x4_t, b: int32x4_t) -> int32x4_t; + } + _vshlq_u32(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s32) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_s32(a: int32x4_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v1i64" + )] + fn _vshl_u64(a: int64x1_t, b: int64x1_t) -> int64x1_t; + } + _vshl_u64(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u32) +#[doc = "Unsigned Shift left"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_u32(a: uint32x4_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")] + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.ushl.v2i64" + )] + fn _vshlq_u64(a: int64x2_t, b: int64x2_t) -> int64x2_t; + } + _vshlq_u64(a.as_signed(), b).as_unsigned() } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p8) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_p8(a: poly8x8_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_s16(a: int16x4_t) -> int32x4_t { + static_assert!(N >= 0 && N <= 16); + simd_shl(simd_cast(a), vdupq_n_s32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s8) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_s8(a: int8x8_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_s32(a: int32x2_t) -> int64x2_t { + static_assert!(N >= 0 && N <= 32); + simd_shl(simd_cast(a), vdupq_n_s64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u8) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_u8(a: uint8x8_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_s8(a: int8x8_t) -> int16x8_t { + static_assert!(N >= 0 && N <= 8); + simd_shl(simd_cast(a), vdupq_n_s16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p16) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_p16(a: poly16x4_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { + static_assert!(N >= 0 && N <= 16); + simd_shl(simd_cast(a), vdupq_n_u32(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s16) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_s16(a: int16x4_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { + static_assert!(N >= 0 && N <= 32); + simd_shl(simd_cast(a), vdupq_n_u64(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u16) +#[doc = "Signed shift left long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_u16(a: uint16x4_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushll, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { + static_assert!(N >= 0 && N <= 8); + simd_shl(simd_cast(a), vdupq_n_u16(N as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s32) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_s32(a: int32x2_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_s8(a: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { 7 } else { N }; + simd_shr(a, vdup_n_s8(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u32) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_u32(a: uint32x2_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { 7 } else { N }; + simd_shr(a, vdupq_n_s8(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_p8(a: poly8x16_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_s16(a: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { 15 } else { N }; + simd_shr(a, vdup_n_s16(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_s8(a: int8x16_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { 15 } else { N }; + simd_shr(a, vdupq_n_s16(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_u8(a: uint8x16_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_s32(a: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { 31 } else { N }; + simd_shr(a, vdup_n_s32(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p16) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_p16(a: poly16x8_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { 31 } else { N }; + simd_shr(a, vdupq_n_s32(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s16) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_s16(a: int16x8_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_s64(a: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { 63 } else { N }; + simd_shr(a, vdup_n_s64(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u16) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_u16(a: uint16x8_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sshr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { 63 } else { N }; + simd_shr(a, vdupq_n_s64(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s32) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_s32(a: int32x4_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { + return vdup_n_u8(0); + } else { + N + }; + simd_shr(a, vdup_n_u8(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u32) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_u32(a: uint32x4_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + let n: i32 = if N == 8 { + return vdupq_n_u8(0); + } else { + N + }; + simd_shr(a, vdupq_n_u8(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_p8(a: poly8x8_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { + return vdup_n_u16(0); + } else { + N + }; + simd_shr(a, vdup_n_u16(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_s8(a: int8x8_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + let n: i32 = if N == 16 { + return vdupq_n_u16(0); + } else { + N + }; + simd_shr(a, vdupq_n_u16(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_u8(a: uint8x8_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { + return vdup_n_u32(0); + } else { + N + }; + simd_shr(a, vdup_n_u32(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_p8(a: poly8x16_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + let n: i32 = if N == 32 { + return vdupq_n_u32(0); + } else { + N + }; + simd_shr(a, vdupq_n_u32(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_s8(a: int8x16_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { + return vdup_n_u64(0); + } else { + N + }; + simd_shr(a, vdup_n_u64(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u8) +#[doc = "Shift right"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_u8(a: uint8x16_t) -> poly16x8_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s32) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_s32(a: int32x2_t) -> poly64x1_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u32) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_u32(a: uint32x2_t) -> poly64x1_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s32) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_s32(a: int32x4_t) -> poly64x2_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u32) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_u32(a: uint32x4_t) -> poly64x2_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_s64(a: int64x2_t) -> p128 { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ushr, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + let n: i32 = if N == 64 { + return vdupq_n_u64(0); + } else { + N + }; + simd_shr(a, vdupq_n_u64(n as _)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_u64(a: uint64x2_t) -> p128 { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_cast(simd_shr(a, vdupq_n_s16(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_p64(a: poly64x2_t) -> p128 { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_cast(simd_shr(a, vdupq_n_s32(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s32) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_s32(a: int32x2_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_cast(simd_shr(a, vdupq_n_s64(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u32) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_u32(a: uint32x2_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_cast(simd_shr(a, vdupq_n_u16(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_s64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_s64(a: int64x1_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_cast(simd_shr(a, vdupq_n_u32(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_u64) +#[doc = "Shift right narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_u64(a: uint64x1_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(shrn, N = 2) +)] +#[rustc_legacy_const_generics(1)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_cast(simd_shr(a, vdupq_n_u64(N as _))) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s32) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_s32(a: int32x4_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vshr_n_s8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u32) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_u32(a: uint32x4_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vshrq_n_s8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_s64) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_s64(a: int64x2_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vshr_n_s16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_u64) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_u64(a: uint64x2_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vshrq_n_s16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s32) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_s32(a: int32x2_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vshr_n_s32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u32) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_u32(a: uint32x2_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vshrq_n_s32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_s64) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_s64(a: int64x1_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vshr_n_s64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_u64) +#[doc = "Signed shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_u64(a: uint64x1_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vshrq_n_s64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s32) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_s32(a: int32x4_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vshr_n_u8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u32) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_u32(a: uint32x4_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + static_assert!(N >= 1 && N <= 8); + simd_add(a, vshrq_n_u8::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_s64) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_s64(a: int64x2_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vshr_n_u16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_u64) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_u64(a: uint64x2_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + static_assert!(N >= 1 && N <= 16); + simd_add(a, vshrq_n_u16::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s32) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_s32(a: int32x2_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vshr_n_u32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u32) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_u32(a: uint32x2_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + static_assert!(N >= 1 && N <= 32); + simd_add(a, vshrq_n_u32::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_s64) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_s64(a: int64x1_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vshr_n_u64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_u64) +#[doc = "Unsigned shift right and accumulate"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_u64(a: uint64x1_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usra, N = 2) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + static_assert!(N >= 1 && N <= 64); + simd_add(a, vshrq_n_u64::(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_s32(a: int32x4_t) -> poly8x16_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst1))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f32.v2f32")] + fn _vst1_f32_x2(ptr: *mut f32, a: float32x2_t, b: float32x2_t); + } + _vst1_f32_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_u32(a: uint32x4_t) -> poly8x16_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst1))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0f32.v4f32")] + fn _vst1q_f32_x2(ptr: *mut f32, a: float32x4_t, b: float32x4_t); + } + _vst1q_f32_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_s64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_s64(a: int64x2_t) -> poly16x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1_f32_x2(a: *mut f32, b: float32x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v2f32.p0f32" + )] + fn _vst1_f32_x2(a: float32x2_t, b: float32x2_t, ptr: *mut f32); + } + _vst1_f32_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_u64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_u64(a: uint64x2_t) -> poly16x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1q_f32_x2(a: *mut f32, b: float32x4x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v4f32.p0f32" + )] + fn _vst1q_f32_x2(a: float32x4_t, b: float32x4_t, ptr: *mut f32); + } + _vst1q_f32_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_p64(a: poly64x1_t) -> int16x4_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst1))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f32.v2f32")] + fn _vst1_f32_x3(ptr: *mut f32, a: float32x2_t, b: float32x2_t, c: float32x2_t); + } + _vst1_f32_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_p64(a: poly64x1_t) -> uint16x4_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst1))] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0f32.v4f32")] + fn _vst1q_f32_x3(ptr: *mut f32, a: float32x4_t, b: float32x4_t, c: float32x4_t); + } + _vst1q_f32_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_p64(a: poly64x1_t) -> poly16x4_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1_f32_x3(a: *mut f32, b: float32x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v2f32.p0f32" + )] + fn _vst1_f32_x3(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut f32); + } + _vst1_f32_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_p64(a: poly64x2_t) -> int16x8_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1q_f32_x3(a: *mut f32, b: float32x4x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v4f32.p0f32" + )] + fn _vst1q_f32_x3(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut f32); + } + _vst1q_f32_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_p64(a: poly64x2_t) -> uint16x8_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v2f32")] + fn _vst1_f32_x4( + ptr: *mut f32, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + ); + } + _vst1_f32_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_p64(a: poly64x2_t) -> poly16x8_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0f32.v4f32")] + fn _vst1q_f32_x4( + ptr: *mut f32, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + ); + } + _vst1q_f32_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p128) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_p128(a: p128) -> int32x4_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1_f32_x4(a: *mut f32, b: float32x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v2f32.p0f32" + )] + fn _vst1_f32_x4( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + ptr: *mut f32, + ); + } + _vst1_f32_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p128) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_p128(a: p128) -> uint32x4_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[cfg_attr(test, assert_instr(st1))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst1q_f32_x4(a: *mut f32, b: float32x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v4f32.p0f32" + )] + fn _vst1q_f32_x4( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + ptr: *mut f32, + ); + } + _vst1q_f32_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_p8(a: poly8x8_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_f32(a: *mut f32, b: float32x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_s8(a: int8x8_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_f32(a: *mut f32, b: float32x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_u8(a: uint8x8_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_s8(a: *mut i8, b: int8x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_p16(a: poly16x4_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_s8(a: *mut i8, b: int8x16_t) { + static_assert_uimm_bits!(LANE, 4); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_s16(a: int16x4_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_s16(a: *mut i16, b: int16x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_u16(a: uint16x4_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_s16(a: *mut i16, b: int16x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_p8(a: poly8x16_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_s32(a: *mut i32, b: int32x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_s8(a: int8x16_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_s32(a: *mut i32, b: int32x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_u8(a: uint8x16_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_s64(a: *mut i64, b: int64x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_p16(a: poly16x8_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_u8(a: *mut u8, b: uint8x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_s16(a: int16x8_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_u8(a: *mut u8, b: uint8x16_t) { + static_assert_uimm_bits!(LANE, 4); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_u16(a: uint16x8_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_u16(a: *mut u16, b: uint16x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_p8(a: poly8x8_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_u16(a: *mut u16, b: uint16x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_s8(a: int8x8_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_u32(a: *mut u32, b: uint32x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_u8(a: uint8x8_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_u32(a: *mut u32, b: uint32x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_p16(a: poly16x4_t) -> uint64x1_t { - transmute(a) -} - -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_s16(a: int16x4_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_u64(a: *mut u64, b: uint64x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_u16(a: uint16x4_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_p8(a: *mut p8, b: poly8x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_p8(a: poly8x16_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_p8(a: *mut p8, b: poly8x16_t) { + static_assert_uimm_bits!(LANE, 4); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_s8(a: int8x16_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_p16(a: *mut p16, b: poly16x4_t) { + static_assert_uimm_bits!(LANE, 2); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_u8(a: uint8x16_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_p16(a: *mut p16, b: poly16x8_t) { + static_assert_uimm_bits!(LANE, 3); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_p16(a: poly16x8_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_p64(a: *mut p64, b: poly64x1_t) { + static_assert!(LANE == 0); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_s16(a: int16x8_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_s64(a: *mut i64, b: int64x1_t) { + static_assert!(LANE == 0); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_u16(a: uint16x8_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_lane_u64(a: *mut u64, b: uint64x1_t) { + static_assert!(LANE == 0); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_p16(a: poly16x4_t) -> poly64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p64_x2(a: *mut p64, b: poly64x1x2_t) { + vst1_s64_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_s16(a: int16x4_t) -> poly64x1_t { - transmute(a) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p64_x3(a: *mut p64, b: poly64x1x3_t) { + vst1_s64_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_u16(a: uint16x4_t) -> poly64x1_t { - transmute(a) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p64_x4(a: *mut p64, b: poly64x1x4_t) { + vst1_s64_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_p16(a: poly16x8_t) -> poly64x2_t { - transmute(a) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p64_x2(a: *mut p64, b: poly64x2x2_t) { + vst1q_s64_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_s16(a: int16x8_t) -> poly64x2_t { - transmute(a) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p64_x3(a: *mut p64, b: poly64x2x3_t) { + vst1q_s64_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon,aes")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_u16(a: uint16x8_t) -> poly64x2_t { - transmute(a) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p64_x4(a: *mut p64, b: poly64x2x4_t) { + vst1q_s64_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s32) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_s32(a: int32x4_t) -> p128 { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v8i8.p0i8" + )] + fn _vst1_s8_x2(a: int8x8_t, b: int8x8_t, ptr: *mut i8); + } + _vst1_s8_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u32) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_u32(a: uint32x4_t) -> p128 { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v16i8.p0i8" + )] + fn _vst1q_s8_x2(a: int8x16_t, b: int8x16_t, ptr: *mut i8); + } + _vst1q_s8_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_s64(a: int64x1_t) -> int8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v4i16.p0i16" + )] + fn _vst1_s16_x2(a: int16x4_t, b: int16x4_t, ptr: *mut i16); + } + _vst1_s16_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_u64(a: uint64x1_t) -> int8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v8i16.p0i16" + )] + fn _vst1q_s16_x2(a: int16x8_t, b: int16x8_t, ptr: *mut i16); + } + _vst1q_s16_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_s64(a: int64x1_t) -> uint8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v2i32.p0i32" + )] + fn _vst1_s32_x2(a: int32x2_t, b: int32x2_t, ptr: *mut i32); + } + _vst1_s32_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_u64(a: uint64x1_t) -> uint8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v4i32.p0i32" + )] + fn _vst1q_s32_x2(a: int32x4_t, b: int32x4_t, ptr: *mut i32); + } + _vst1q_s32_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_s64(a: int64x1_t) -> poly8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v1i64.p0i64" + )] + fn _vst1_s64_x2(a: int64x1_t, b: int64x1_t, ptr: *mut i64); + } + _vst1_s64_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_u64(a: uint64x1_t) -> poly8x8_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x2.v2i64.p0i64" + )] + fn _vst1q_s64_x2(a: int64x2_t, b: int64x2_t, ptr: *mut i64); + } + _vst1q_s64_x2(b.0, b.1, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_s64(a: int64x2_t) -> int8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s8_x2(a: *mut i8, b: int8x8x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i8.v8i8")] + fn _vst1_s8_x2(ptr: *mut i8, a: int8x8_t, b: int8x8_t); + } + _vst1_s8_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_u64(a: uint64x2_t) -> int8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s8_x2(a: *mut i8, b: int8x16x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i8.v16i8")] + fn _vst1q_s8_x2(ptr: *mut i8, a: int8x16_t, b: int8x16_t); + } + _vst1q_s8_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_s64(a: int64x2_t) -> uint8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s16_x2(a: *mut i16, b: int16x4x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i16.v4i16")] + fn _vst1_s16_x2(ptr: *mut i16, a: int16x4_t, b: int16x4_t); + } + _vst1_s16_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_u64(a: uint64x2_t) -> uint8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s16_x2(a: *mut i16, b: int16x8x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i16.v8i16")] + fn _vst1q_s16_x2(ptr: *mut i16, a: int16x8_t, b: int16x8_t); + } + _vst1q_s16_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_s64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_s64(a: int64x2_t) -> poly8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s32_x2(a: *mut i32, b: int32x2x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i32.v2i32")] + fn _vst1_s32_x2(ptr: *mut i32, a: int32x2_t, b: int32x2_t); + } + _vst1_s32_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_u64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_u64(a: uint64x2_t) -> poly8x16_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s32_x2(a: *mut i32, b: int32x4x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i32.v4i32")] + fn _vst1q_s32_x2(ptr: *mut i32, a: int32x4_t, b: int32x4_t); + } + _vst1q_s32_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_p64(a: poly64x1_t) -> int8x8_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s64_x2(a: *mut i64, b: int64x1x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i64.v1i64")] + fn _vst1_s64_x2(ptr: *mut i64, a: int64x1_t, b: int64x1_t); + } + _vst1_s64_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_p64(a: poly64x1_t) -> uint8x8_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s64_x2(a: *mut i64, b: int64x2x2_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x2.p0i64.v2i64")] + fn _vst1q_s64_x2(ptr: *mut i64, a: int64x2_t, b: int64x2_t); + } + _vst1q_s64_x2(a, b.0, b.1) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_p64(a: poly64x1_t) -> poly8x8_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v8i8.p0i8" + )] + fn _vst1_s8_x3(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); + } + _vst1_s8_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_p64(a: poly64x2_t) -> int8x16_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v16i8.p0i8" + )] + fn _vst1q_s8_x3(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); + } + _vst1q_s8_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_p64(a: poly64x2_t) -> uint8x16_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v4i16.p0i16" + )] + fn _vst1_s16_x3(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i16); + } + _vst1_s16_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p64) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_p64(a: poly64x2_t) -> poly8x16_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v8i16.p0i16" + )] + fn _vst1q_s16_x3(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i16); + } + _vst1q_s16_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_p128) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_p128(a: p128) -> int16x8_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v2i32.p0i32" + )] + fn _vst1_s32_x3(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i32); + } + _vst1_s32_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_p128) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_p128(a: p128) -> uint16x8_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v4i32.p0i32" + )] + fn _vst1q_s32_x3(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i32); + } + _vst1q_s32_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_p128) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_p128(a: p128) -> poly16x8_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v1i64.p0i64" + )] + fn _vst1_s64_x3(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i64); + } + _vst1_s64_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_p8(a: poly8x8_t) -> int64x1_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x3.v2i64.p0i64" + )] + fn _vst1q_s64_x3(a: int64x2_t, b: int64x2_t, c: int64x2_t, ptr: *mut i64); + } + _vst1q_s64_x3(b.0, b.1, b.2, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_s8(a: int8x8_t) -> int64x1_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s8_x3(a: *mut i8, b: int8x8x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v8i8")] + fn _vst1_s8_x3(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t); + } + _vst1_s8_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_u8(a: uint8x8_t) -> int64x1_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s8_x3(a: *mut i8, b: int8x16x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i8.v16i8")] + fn _vst1q_s8_x3(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t); + } + _vst1q_s8_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_p8(a: poly8x8_t) -> uint64x1_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s16_x3(a: *mut i16, b: int16x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v4i16")] + fn _vst1_s16_x3(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t); + } + _vst1_s16_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_s8(a: int8x8_t) -> uint64x1_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s16_x3(a: *mut i16, b: int16x8x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i16.v8i16")] + fn _vst1q_s16_x3(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t); + } + _vst1q_s16_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_u8(a: uint8x8_t) -> uint64x1_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s32_x3(a: *mut i32, b: int32x2x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v2i32")] + fn _vst1_s32_x3(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t); + } + _vst1_s32_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_p8(a: poly8x16_t) -> int64x2_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s32_x3(a: *mut i32, b: int32x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i32.v4i32")] + fn _vst1q_s32_x3(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t); + } + _vst1q_s32_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_s8(a: int8x16_t) -> int64x2_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s64_x3(a: *mut i64, b: int64x1x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v1i64")] + fn _vst1_s64_x3(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t); + } + _vst1_s64_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_u8(a: uint8x16_t) -> int64x2_t { - transmute(a) +#[target_feature(enable = "neon,v7")] +#[cfg(target_arch = "arm")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s64_x3(a: *mut i64, b: int64x2x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x3.p0i64.v2i64")] + fn _vst1q_s64_x3(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t); + } + _vst1q_s64_x3(a, b.0, b.1, b.2) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_p8(a: poly8x16_t) -> uint64x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v8i8.p0i8" + )] + fn _vst1_s8_x4(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); + } + _vst1_s8_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_s8(a: int8x16_t) -> uint64x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v16i8.p0i8" + )] + fn _vst1q_s8_x4(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); + } + _vst1q_s8_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_u8(a: uint8x16_t) -> uint64x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v4i16.p0i16" + )] + fn _vst1_s16_x4(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i16); + } + _vst1_s16_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_p8(a: poly8x8_t) -> poly64x1_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v8i16.p0i16" + )] + fn _vst1q_s16_x4(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i16); + } + _vst1q_s16_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_s8(a: int8x8_t) -> poly64x1_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v2i32.p0i32" + )] + fn _vst1_s32_x4(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i32); + } + _vst1_s32_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p64_u8(a: uint8x8_t) -> poly64x1_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v4i32.p0i32" + )] + fn _vst1q_s32_x4(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i32); + } + _vst1q_s32_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_p8(a: poly8x16_t) -> poly64x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v1i64.p0i64" + )] + fn _vst1_s64_x4(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i64); + } + _vst1_s64_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_s8(a: int8x16_t) -> poly64x2_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st1))] +pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st1x4.v2i64.p0i64" + )] + fn _vst1q_s64_x4(a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t, ptr: *mut i64); + } + _vst1q_s64_x4(b.0, b.1, b.2, b.3, a) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p64_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p64_u8(a: uint8x16_t) -> poly64x2_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s8_x4(a: *mut i8, b: int8x8x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v8i8")] + fn _vst1_s8_x4(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t); + } + _vst1_s8_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_s16(a: int16x8_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s8_x4(a: *mut i8, b: int8x16x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i8.v16i8")] + fn _vst1q_s8_x4(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t); + } + _vst1q_s8_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_u16(a: uint16x8_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s16_x4(a: *mut i16, b: int16x4x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v4i16")] + fn _vst1_s16_x4(ptr: *mut i16, a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t); + } + _vst1_s16_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_p16(a: poly16x8_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s16_x4(a: *mut i16, b: int16x8x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i16.v8i16")] + fn _vst1q_s16_x4(ptr: *mut i16, a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t); + } + _vst1q_s16_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_s8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_s8(a: int8x16_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s32_x4(a: *mut i32, b: int32x2x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v2i32")] + fn _vst1_s32_x4(ptr: *mut i32, a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t); + } + _vst1_s32_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_u8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_u8(a: uint8x16_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s32_x4(a: *mut i32, b: int32x4x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i32.v4i32")] + fn _vst1q_s32_x4(ptr: *mut i32, a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t); + } + _vst1q_s32_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_p8) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_p8(a: poly8x16_t) -> p128 { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1_s64_x4(a: *mut i64, b: int64x1x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v1i64")] + fn _vst1_s64_x4(ptr: *mut i64, a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t); + } + _vst1_s64_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_p128) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_p128(a: p128) -> int8x16_t { - transmute(a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst1))] +pub unsafe fn vst1q_s64_x4(a: *mut i64, b: int64x2x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst1x4.p0i64.v2i64")] + fn _vst1q_s64_x4(ptr: *mut i64, a: int64x2_t, b: int64x2_t, c: int64x2_t, d: int64x2_t); + } + _vst1q_s64_x4(a, b.0, b.1, b.2, b.3) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_p128) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_p128(a: p128) -> uint8x16_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u8_x2(a: *mut u8, b: uint8x8x2_t) { + vst1_s8_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_p128) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_p128(a: p128) -> poly8x16_t { - transmute(a) +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u8_x3(a: *mut u8, b: uint8x8x3_t) { + vst1_s8_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s8_f32(a: float32x2_t) -> int8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u8_x4(a: *mut u8, b: uint8x8x4_t) { + vst1_s8_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s16_f32(a: float32x2_t) -> int16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u8_x2(a: *mut u8, b: uint8x16x2_t) { + vst1q_s8_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s32_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s32_f32(a: float32x2_t) -> int32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u8_x3(a: *mut u8, b: uint8x16x3_t) { + vst1q_s8_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_s64_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_s64_f32(a: float32x2_t) -> int64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u8_x4(a: *mut u8, b: uint8x16x4_t) { + vst1q_s8_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s8_f32(a: float32x4_t) -> int8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u16_x2(a: *mut u16, b: uint16x4x2_t) { + vst1_s16_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s16_f32(a: float32x4_t) -> int16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u16_x3(a: *mut u16, b: uint16x4x3_t) { + vst1_s16_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s32_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s32_f32(a: float32x4_t) -> int32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u16_x4(a: *mut u16, b: uint16x4x4_t) { + vst1_s16_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_s64_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_s64_f32(a: float32x4_t) -> int64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u16_x2(a: *mut u16, b: uint16x8x2_t) { + vst1q_s16_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u8_f32(a: float32x2_t) -> uint8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u16_x3(a: *mut u16, b: uint16x8x3_t) { + vst1q_s16_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u16_f32(a: float32x2_t) -> uint16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u16_x4(a: *mut u16, b: uint16x8x4_t) { + vst1q_s16_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u32_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u32_f32(a: float32x2_t) -> uint32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u32_x2(a: *mut u32, b: uint32x2x2_t) { + vst1_s32_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_u64_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_u64_f32(a: float32x2_t) -> uint64x1_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u32_x3(a: *mut u32, b: uint32x2x3_t) { + vst1_s32_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u8_f32(a: float32x4_t) -> uint8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u32_x4(a: *mut u32, b: uint32x2x4_t) { + vst1_s32_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u16_f32(a: float32x4_t) -> uint16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u32_x2(a: *mut u32, b: uint32x4x2_t) { + vst1q_s32_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u32_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u32_f32(a: float32x4_t) -> uint32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u32_x3(a: *mut u32, b: uint32x4x3_t) { + vst1q_s32_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_u64_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_u64_f32(a: float32x4_t) -> uint64x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u32_x4(a: *mut u32, b: uint32x4x4_t) { + vst1q_s32_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p8_f32(a: float32x2_t) -> poly8x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u64_x2(a: *mut u64, b: uint64x1x2_t) { + vst1_s64_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_p16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_p16_f32(a: float32x2_t) -> poly16x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u64_x3(a: *mut u64, b: uint64x1x3_t) { + vst1_s64_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p8_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p8_f32(a: float32x4_t) -> poly8x16_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_u64_x4(a: *mut u64, b: uint64x1x4_t) { + vst1_s64_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p16_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p16_f32(a: float32x4_t) -> poly16x8_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u64_x2(a: *mut u64, b: uint64x2x2_t) { + vst1q_s64_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_p128_f32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_p128_f32(a: float32x4_t) -> p128 { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u64_x3(a: *mut u64, b: uint64x2x3_t) { + vst1q_s64_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s8) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_s8(a: int8x8_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_u64_x4(a: *mut u64, b: uint64x2x4_t) { + vst1q_s64_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_s16(a: int16x4_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p8_x2(a: *mut p8, b: poly8x8x2_t) { + vst1_s8_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_s32(a: int32x2_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p8_x3(a: *mut p8, b: poly8x8x3_t) { + vst1_s8_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_s64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_s64(a: int64x1_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p8_x4(a: *mut p8, b: poly8x8x4_t) { + vst1_s8_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s8) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_s8(a: int8x16_t) -> float32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p8_x2(a: *mut p8, b: poly8x16x2_t) { + vst1q_s8_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_s16(a: int16x8_t) -> float32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p8_x3(a: *mut p8, b: poly8x16x3_t) { + vst1q_s8_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p8_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_s32(a: int32x4_t) -> float32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p8_x4(a: *mut p8, b: poly8x16x4_t) { + vst1q_s8_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_s64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_s64(a: int64x2_t) -> float32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p16_x2(a: *mut p16, b: poly16x4x2_t) { + vst1_s16_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u8) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_u8(a: uint8x8_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p16_x3(a: *mut p16, b: poly16x4x3_t) { + vst1_s16_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u16) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_p16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_u16(a: uint16x4_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1_p16_x4(a: *mut p16, b: poly16x4x4_t) { + vst1_s16_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u32) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x2)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_u32(a: uint32x2_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p16_x2(a: *mut p16, b: poly16x8x2_t) { + vst1q_s16_x2(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_u64) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x3)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_u64(a: uint64x1_t) -> float32x2_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p16_x3(a: *mut p16, b: poly16x8x3_t) { + vst1q_s16_x3(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u8) +#[doc = "Store multiple single-element structures to one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_p16_x4)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_u8(a: uint8x16_t) -> float32x4_t { - transmute(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst1))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st1) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_p16_x4(a: *mut p16, b: poly16x8x4_t) { + vst1q_s16_x4(transmute(a), transmute(b)) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u16) +#[doc = "Store multiple single-element structures from one, two, three, or four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_u16(a: uint16x8_t) -> float32x4_t { - transmute(a) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst1q_lane_p64(a: *mut p64, b: poly64x2_t) { + static_assert_uimm_bits!(LANE, 1); + *a = simd_extract!(b, LANE as u32); } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_u32(a: uint32x4_t) -> float32x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v2f32.p0i8" + )] + fn _vst2_f32(a: float32x2_t, b: float32x2_t, ptr: *mut i8); + } + _vst2_f32(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_u64(a: uint64x2_t) -> float32x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v4f32.p0i8" + )] + fn _vst2q_f32(a: float32x4_t, b: float32x4_t, ptr: *mut i8); + } + _vst2q_f32(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_p8(a: poly8x8_t) -> float32x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v8i8.p0i8" + )] + fn _vst2_s8(a: int8x8_t, b: int8x8_t, ptr: *mut i8); + } + _vst2_s8(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpret_f32_p16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpret_f32_p16(a: poly16x4_t) -> float32x2_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v16i8.p0i8" + )] + fn _vst2q_s8(a: int8x16_t, b: int8x16_t, ptr: *mut i8); + } + _vst2q_s8(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_p8(a: poly8x16_t) -> float32x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v4i16.p0i8" + )] + fn _vst2_s16(a: int16x4_t, b: int16x4_t, ptr: *mut i8); + } + _vst2_s16(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_p16(a: poly16x8_t) -> float32x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v8i16.p0i8" + )] + fn _vst2q_s16(a: int16x8_t, b: int16x8_t, ptr: *mut i8); + } + _vst2q_s16(b.0, b.1, a as _) } -/// Vector reinterpret cast operation -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vreinterpretq_f32_p128) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vreinterpretq_f32_p128(a: p128) -> float32x4_t { - transmute(a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v2i32.p0i8" + )] + fn _vst2_s32(a: int32x2_t, b: int32x2_t, ptr: *mut i8); + } + _vst2_s32(b.0, b.1, a as _) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st2))] +pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v8i8")] - fn vrshl_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v4i32.p0i8" + )] + fn _vst2q_s32(a: int32x4_t, b: int32x4_t, ptr: *mut i8); } -vrshl_s8_(a, b) + _vst2q_s32(b.0, b.1, a as _) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2_f32(a: *mut f32, b: float32x2x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v16i8")] - fn vrshlq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v2f32")] + fn _vst2_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, size: i32); } -vrshlq_s8_(a, b) + _vst2_f32(a as _, b.0, b.1, 4) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2q_f32(a: *mut f32, b: float32x4x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v4i16")] - fn vrshl_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4f32")] + fn _vst2q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, size: i32); } -vrshl_s16_(a, b) + _vst2q_f32(a as _, b.0, b.1, 4) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2_s8(a: *mut i8, b: int8x8x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v8i16")] - fn vrshlq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8i8")] + fn _vst2_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, size: i32); } -vrshlq_s16_(a, b) + _vst2_s8(a as _, b.0, b.1, 1) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2q_s8(a: *mut i8, b: int8x16x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v2i32")] - fn vrshl_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v16i8")] + fn _vst2q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, size: i32); } -vrshl_s32_(a, b) + _vst2q_s8(a as _, b.0, b.1, 1) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2_s16(a: *mut i16, b: int16x4x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v4i32")] - fn vrshlq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4i16")] + fn _vst2_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, size: i32); } -vrshlq_s32_(a, b) + _vst2_s16(a as _, b.0, b.1, 2) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2q_s16(a: *mut i16, b: int16x8x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v1i64")] - fn vrshl_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v8i16")] + fn _vst2q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, size: i32); } -vrshl_s64_(a, b) + _vst2q_s16(a as _, b.0, b.1, 2) } -/// Signed rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2_s32(a: *mut i32, b: int32x2x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshifts.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.srshl.v2i64")] - fn vrshlq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v2i32")] + fn _vst2_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, size: i32); } -vrshlq_s64_(a, b) + _vst2_s32(a as _, b.0, b.1, 4) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst2))] +pub unsafe fn vst2q_s32(a: *mut i32, b: int32x4x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v8i8")] - fn vrshl_u8_(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v4i32")] + fn _vst2q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, size: i32); } -vrshl_u8_(a, b) + _vst2q_s32(a as _, b.0, b.1, 4) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v16i8")] - fn vrshlq_u8_(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v2f32.p0i8" + )] + fn _vst2_lane_f32(a: float32x2_t, b: float32x2_t, n: i64, ptr: *mut i8); } -vrshlq_u8_(a, b) + _vst2_lane_f32(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v4i16")] - fn vrshl_u16_(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v4f32.p0i8" + )] + fn _vst2q_lane_f32(a: float32x4_t, b: float32x4_t, n: i64, ptr: *mut i8); } -vrshl_u16_(a, b) + _vst2q_lane_f32(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v8i16")] - fn vrshlq_u16_(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v8i8.p0i8" + )] + fn _vst2_lane_s8(a: int8x8_t, b: int8x8_t, n: i64, ptr: *mut i8); } -vrshlq_u16_(a, b) + _vst2_lane_s8(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v2i32")] - fn vrshl_u32_(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v4i16.p0i8" + )] + fn _vst2_lane_s16(a: int16x4_t, b: int16x4_t, n: i64, ptr: *mut i8); } -vrshl_u32_(a, b) + _vst2_lane_s16(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { + static_assert_uimm_bits!(LANE, 3); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v4i32")] - fn vrshlq_u32_(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v8i16.p0i8" + )] + fn _vst2q_lane_s16(a: int16x8_t, b: int16x8_t, n: i64, ptr: *mut i8); } -vrshlq_u32_(a, b) + _vst2q_lane_s16(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { + static_assert_uimm_bits!(LANE, 1); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v1i64")] - fn vrshl_u64_(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v2i32.p0i8" + )] + fn _vst2_lane_s32(a: int32x2_t, b: int32x2_t, n: i64, ptr: *mut i8); } -vrshl_u64_(a, b) + _vst2_lane_s32(b.0, b.1, LANE as i64, a as _) } -/// Unsigned rounding shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st2, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { + static_assert_uimm_bits!(LANE, 2); extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftu.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.urshl.v2i64")] - fn vrshlq_u64_(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2lane.v4i32.p0i8" + )] + fn _vst2q_lane_s32(a: int32x4_t, b: int32x4_t, n: i64, ptr: *mut i8); } -vrshlq_u64_(a, b) + _vst2q_lane_s32(b.0, b.1, LANE as i64, a as _) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_s8(a: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - vrshl_s8(a, vdup_n_s8(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2f32")] + fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32); + } + _vst2_f32(a as _, b.0, b.1, LANE, 4) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - vrshlq_s8(a, vdupq_n_s8(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f32")] + fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32); + } + _vst2q_f32(a as _, b.0, b.1, LANE, 4) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_s16(a: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - vrshl_s16(a, vdup_n_s16(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i8")] + fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32); + } + _vst2_s8(a as _, b.0, b.1, LANE, 1) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - vrshlq_s16(a, vdupq_n_s16(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i16")] + fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32); + } + _vst2_s16(a as _, b.0, b.1, LANE, 2) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_s32(a: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - vrshl_s32(a, vdup_n_s32(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i16")] + fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32); + } + _vst2q_s16(a as _, b.0, b.1, LANE, 2) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - vrshlq_s32(a, vdupq_n_s32(-N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2i32")] + fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32); + } + _vst2_s32(a as _, b.0, b.1, LANE, 4) +} + +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst2, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i32")] + fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32); + } + _vst2q_s32(a as _, b.0, b.1, LANE, 4) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - vrshl_s64(a, vdup_n_s64(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_lane_u8(a: *mut u8, b: uint8x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + vst2_lane_s8::(transmute(a), transmute(b)) } -/// Signed rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - vrshlq_s64(a, vdupq_n_s64(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_lane_u16(a: *mut u16, b: uint16x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + vst2_lane_s16::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - vrshl_u8(a, vdup_n_s8(-N as _)) -} - -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - vrshlq_u8(a, vdupq_n_s8(-N as _)) -} - -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16) -#[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - vrshl_u16(a, vdup_n_s16(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_lane_u16(a: *mut u16, b: uint16x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + vst2q_lane_s16::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - vrshlq_u16(a, vdupq_n_s16(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_lane_u32(a: *mut u32, b: uint32x2x2_t) { + static_assert_uimm_bits!(LANE, 1); + vst2_lane_s32::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - vrshl_u32(a, vdup_n_s32(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_lane_u32(a: *mut u32, b: uint32x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + vst2q_lane_s32::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - vrshlq_u32(a, vdupq_n_s32(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_lane_p8(a: *mut p8, b: poly8x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + vst2_lane_s8::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshr_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - vrshl_u64(a, vdup_n_s64(-N as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_lane_p16(a: *mut p16, b: poly16x4x2_t) { + static_assert_uimm_bits!(LANE, 2); + vst2_lane_s16::(transmute(a), transmute(b)) } -/// Unsigned rounding shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshr, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(urshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - vrshlq_u64(a, vdupq_n_s64(-N as _)) -} - -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16) -#[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v8i8")] - fn vrshrn_n_s16_(a: int16x8_t, n: int16x8_t) -> int8x8_t; - } -vrshrn_n_s16_(a, const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_lane_p16(a: *mut p16, b: poly16x8x2_t) { + static_assert_uimm_bits!(LANE, 3); + vst2q_lane_s16::(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rshrn.v8i8")] - fn vrshrn_n_s16_(a: int16x8_t, n: i32) -> int8x8_t; - } -vrshrn_n_s16_(a, N) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_p64(a: *mut p64, b: poly64x1x2_t) { + vst2_s64(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[cfg(target_arch = "arm")] #[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v4i16")] - fn vrshrn_n_s32_(a: int32x4_t, n: int32x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2.p0i8.v1i64")] + fn _vst2_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, size: i32); } -vrshrn_n_s32_(a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }) + _vst2_s64(a as _, b.0, b.1, 8) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[cfg(not(target_arch = "arm"))] #[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rshrn.v4i16")] - fn vrshrn_n_s32_(a: int32x4_t, n: i32) -> int16x4_t; - } -vrshrn_n_s32_(a, N) -} - -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64) -#[inline] -#[cfg(target_arch = "arm")] -#[target_feature(enable = "neon,v7")] -#[cfg_attr(test, assert_instr(vrshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] -pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrshiftn.v2i32")] - fn vrshrn_n_s64_(a: int64x2_t, n: int64x2_t) -> int32x2_t; - } -vrshrn_n_s64_(a, const { int64x2_t([-N as i64, -N as i64]) }) -} - -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64) -#[inline] #[cfg(not(target_arch = "arm"))] -#[target_feature(enable = "neon")] -#[cfg_attr(test, assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] -pub unsafe fn vrshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - #[allow(improper_ctypes)] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst2_s64(a: *mut i64, b: int64x1x2_t) { extern "unadjusted" { - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rshrn.v2i32")] - fn vrshrn_n_s64_(a: int64x2_t, n: i32) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st2.v1i64.p0i8" + )] + fn _vst2_s64(a: int64x1_t, b: int64x1_t, ptr: *mut i8); } -vrshrn_n_s64_(a, N) + _vst2_s64(b.0, b.1, a as _) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - transmute(vrshrn_n_s16::(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_u64(a: *mut u64, b: uint64x1x2_t) { + vst2_s64(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - transmute(vrshrn_n_s32::(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_u8(a: *mut u8, b: uint8x8x2_t) { + vst2_s8(transmute(a), transmute(b)) } -/// Rounding shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrshrn, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rshrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - transmute(vrshrn_n_s64::(transmute(a))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_u8(a: *mut u8, b: uint8x16x2_t) { + vst2q_s8(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshr_n_s8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_u16(a: *mut u16, b: uint16x4x2_t) { + vst2_s16(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshrq_n_s8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_u16(a: *mut u16, b: uint16x8x2_t) { + vst2q_s16(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshr_n_s16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_u32(a: *mut u32, b: uint32x2x2_t) { + vst2_s32(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshrq_n_s16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_u32(a: *mut u32, b: uint32x4x2_t) { + vst2q_s32(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshr_n_s32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_p8(a: *mut p8, b: poly8x8x2_t) { + vst2_s8(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshrq_n_s32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_p8(a: *mut p8, b: poly8x16x2_t) { + vst2q_s8(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshr_n_s64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2_p16(a: *mut p16, b: poly16x4x2_t) { + vst2_s16(transmute(a), transmute(b)) } -/// Signed rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64) +#[doc = "Store multiple 2-element structures from two registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst2q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(srsra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshrq_n_s64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst2))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst2q_p16(a: *mut p16, b: poly16x8x2_t) { + vst2q_s16(transmute(a), transmute(b)) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshr_n_u8::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2f32")] + fn _vst3_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, c: float32x2_t, size: i32); + } + _vst3_f32(a as _, b.0, b.1, b.2, 4) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vrshrq_n_u8::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4f32")] + fn _vst3q_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, c: float32x4_t, size: i32); + } + _vst3q_f32(a as _, b.0, b.1, b.2, 4) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshr_n_u16::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i8")] + fn _vst3_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, size: i32); + } + _vst3_s8(a as _, b.0, b.1, b.2, 1) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vrshrq_n_u16::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v16i8")] + fn _vst3q_s8(ptr: *mut i8, a: int8x16_t, b: int8x16_t, c: int8x16_t, size: i32); + } + _vst3q_s8(a as _, b.0, b.1, b.2, 1) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshr_n_u32::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i16")] + fn _vst3_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, c: int16x4_t, size: i32); + } + _vst3_s16(a as _, b.0, b.1, b.2, 2) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vrshrq_n_u32::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v8i16")] + fn _vst3q_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, c: int16x8_t, size: i32); + } + _vst3q_s16(a as _, b.0, b.1, b.2, 2) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshr_n_u64::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v2i32")] + fn _vst3_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, c: int32x2_t, size: i32); + } + _vst3_s32(a as _, b.0, b.1, b.2, 4) } -/// Unsigned rounding shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ursra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vrshrq_n_u64::(b)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst3))] +pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v4i32")] + fn _vst3q_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, c: int32x4_t, size: i32); + } + _vst3q_s32(a as _, b.0, b.1, b.2, 4) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3_f32(a: *mut f32, b: float32x2x3_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rsubhn.v8i8")] - fn vrsubhn_s16_(a: int16x8_t, b: int16x8_t) -> int8x8_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v2f32.p0i8" + )] + fn _vst3_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, ptr: *mut i8); } -vrsubhn_s16_(a, b) + _vst3_f32(b.0, b.1, b.2, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_f32(a: *mut f32, b: float32x4x3_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rsubhn.v4i16")] - fn vrsubhn_s32_(a: int32x4_t, b: int32x4_t) -> int16x4_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v4f32.p0i8" + )] + fn _vst3q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, ptr: *mut i8); } -vrsubhn_s32_(a, b) + _vst3q_f32(b.0, b.1, b.2, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3_s8(a: *mut i8, b: int8x8x3_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vrsubhn.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.rsubhn.v2i32")] - fn vrsubhn_s64_(a: int64x2_t, b: int64x2_t) -> int32x2_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v8i8.p0i8" + )] + fn _vst3_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, ptr: *mut i8); } -vrsubhn_s64_(a, b) + _vst3_s8(b.0, b.1, b.2, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { - transmute(vrsubhn_s16(transmute(a), transmute(b))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_s8(a: *mut i8, b: int8x16x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v16i8.p0i8" + )] + fn _vst3q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, ptr: *mut i8); + } + _vst3q_s8(b.0, b.1, b.2, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { - transmute(vrsubhn_s32(transmute(a), transmute(b))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3_s16(a: *mut i16, b: int16x4x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v4i16.p0i8" + )] + fn _vst3_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, ptr: *mut i8); + } + _vst3_s16(b.0, b.1, b.2, a as _) } -/// Rounding subtract returning high narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vrsubhn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(rsubhn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vrsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { - transmute(vrsubhn_s64(transmute(a), transmute(b))) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_s16(a: *mut i16, b: int16x8x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v8i16.p0i8" + )] + fn _vst3q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, ptr: *mut i8); + } + _vst3q_s16(b.0, b.1, b.2, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_s8(a: i8, b: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3_s32(a: *mut i32, b: int32x2x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v2i32.p0i8" + )] + fn _vst3_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, ptr: *mut i8); + } + _vst3_s32(b.0, b.1, b.2, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_s16(a: i16, b: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st3))] +pub unsafe fn vst3q_s32(a: *mut i32, b: int32x4x3_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v4i32.p0i8" + )] + fn _vst3q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, ptr: *mut i8); + } + _vst3q_s32(b.0, b.1, b.2, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_s32(a: i32, b: int32x2_t) -> int32x2_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2f32")] + fn _vst3_lane_f32( + ptr: *mut i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + n: i32, + size: i32, + ); + } + _vst3_f32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_s64(a: i64, b: int64x1_t) -> int64x1_t { - static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4f32")] + fn _vst3q_lane_f32( + ptr: *mut i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + n: i32, + size: i32, + ); + } + _vst3q_f32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_u8(a: u8, b: uint8x8_t) -> uint8x8_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")] + fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32); + } + _vst3_s8(a as _, b.0, b.1, b.2, LANE, 1) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_u16(a: u16, b: uint16x4_t) -> uint16x4_t { +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i16")] + fn _vst3_lane_s16( + ptr: *mut i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + n: i32, + size: i32, + ); + } + _vst3_s16(a as _, b.0, b.1, b.2, LANE, 2) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_u32(a: u32, b: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i16")] + fn _vst3q_lane_s16( + ptr: *mut i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + n: i32, + size: i32, + ); + } + _vst3q_s16(a as _, b.0, b.1, b.2, LANE, 2) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_u64(a: u64, b: uint64x1_t) -> uint64x1_t { - static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v2i32")] + fn _vst3_lane_s32( + ptr: *mut i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + n: i32, + size: i32, + ); + } + _vst3_s32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_p8(a: p8, b: poly8x8_t) -> poly8x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst3, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v4i32")] + fn _vst3q_lane_s32( + ptr: *mut i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + n: i32, + size: i32, + ); + } + _vst3q_s32(a as _, b.0, b.1, b.2, LANE, 4) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_p16(a: p16, b: poly16x4_t) -> poly16x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v2f32.p0i8" + )] + fn _vst3_lane_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, n: i64, ptr: *mut i8); + } + _vst3_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_p64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[target_feature(enable = "neon")] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_p64(a: p64, b: poly64x1_t) -> poly64x1_t { - static_assert!(LANE == 0); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v4f32.p0i8" + )] + fn _vst3q_lane_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_f32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_s8(a: i8, b: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v8i8.p0i8" + )] + fn _vst3_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i64, ptr: *mut i8); + } + _vst3_lane_s8(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_s16(a: i16, b: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v4i16.p0i8" + )] + fn _vst3_lane_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, n: i64, ptr: *mut i8); + } + _vst3_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_s32(a: i32, b: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v8i16.p0i8" + )] + fn _vst3q_lane_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_s16(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_s64(a: i64, b: int64x2_t) -> int64x2_t { +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v2i32.p0i8" + )] + fn _vst3_lane_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, n: i64, ptr: *mut i8); + } + _vst3_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] +#[cfg(not(target_arch = "arm"))] #[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_u8(a: u8, b: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(test, assert_instr(st3, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3lane.v4i32.p0i8" + )] + fn _vst3q_lane_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, n: i64, ptr: *mut i8); + } + _vst3q_lane_s32(b.0, b.1, b.2, LANE as i64, a as _) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_u16(a: u16, b: uint16x8_t) -> uint16x8_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_lane_u8(a: *mut u8, b: uint8x8x3_t) { static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) + vst3_lane_s8::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_u32(a: u32, b: uint32x4_t) -> uint32x4_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_lane_u16(a: *mut u16, b: uint16x4x3_t) { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + vst3_lane_s16::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_u64(a: u64, b: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_lane_u16(a: *mut u16, b: uint16x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + vst3q_lane_s16::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_p8(a: p8, b: poly8x16_t) -> poly8x16_t { - static_assert_uimm_bits!(LANE, 4); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_lane_u32(a: *mut u32, b: uint32x2x3_t) { + static_assert_uimm_bits!(LANE, 1); + vst3_lane_s32::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_p16(a: p16, b: poly16x8_t) -> poly16x8_t { - static_assert_uimm_bits!(LANE, 3); - simd_insert!(b, LANE as u32, a) -} - -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_p64) -#[inline] -#[target_feature(enable = "neon,aes")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_p64(a: p64, b: poly64x2_t) -> poly64x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_lane_u32(a: *mut u32, b: uint32x4x3_t) { + static_assert_uimm_bits!(LANE, 2); + vst3q_lane_s32::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vset_lane_f32(a: f32, b: float32x2_t) -> float32x2_t { - static_assert_uimm_bits!(LANE, 1); - simd_insert!(b, LANE as u32, a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_lane_p8(a: *mut p8, b: poly8x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + vst3_lane_s8::(transmute(a), transmute(b)) } -/// Insert vector element from another vector element -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop, LANE = 0))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(nop, LANE = 0))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsetq_lane_f32(a: f32, b: float32x4_t) -> float32x4_t { +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_lane_p16(a: *mut p16, b: poly16x4x3_t) { static_assert_uimm_bits!(LANE, 2); - simd_insert!(b, LANE as u32, a) + vst3_lane_s16::(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v8i8")] - fn vshl_s8_(a: int8x8_t, b: int8x8_t) -> int8x8_t; - } -vshl_s8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_lane_p16(a: *mut p16, b: poly16x8x3_t) { + static_assert_uimm_bits!(LANE, 3); + vst3q_lane_s16::(transmute(a), transmute(b)) +} + +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_p64(a: *mut p64, b: poly64x1x3_t) { + vst3_s64(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v16i8")] - fn vshlq_s8_(a: int8x16_t, b: int8x16_t) -> int8x16_t; + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st3.v1i64.p0i8" + )] + fn _vst3_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, ptr: *mut i8); } -vshlq_s8_(a, b) + _vst3_s64(b.0, b.1, b.2, a as _) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst3_s64(a: *mut i64, b: int64x1x3_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v4i16")] - fn vshl_s16_(a: int16x4_t, b: int16x4_t) -> int16x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3.p0i8.v1i64")] + fn _vst3_s64(ptr: *mut i8, a: int64x1_t, b: int64x1_t, c: int64x1_t, size: i32); } -vshl_s16_(a, b) + _vst3_s64(a as _, b.0, b.1, b.2, 8) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v8i16")] - fn vshlq_s16_(a: int16x8_t, b: int16x8_t) -> int16x8_t; - } -vshlq_s16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_u64(a: *mut u64, b: uint64x1x3_t) { + vst3_s64(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v2i32")] - fn vshl_s32_(a: int32x2_t, b: int32x2_t) -> int32x2_t; - } -vshl_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_u8(a: *mut u8, b: uint8x8x3_t) { + vst3_s8(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v4i32")] - fn vshlq_s32_(a: int32x4_t, b: int32x4_t) -> int32x4_t; - } -vshlq_s32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_u8(a: *mut u8, b: uint8x16x3_t) { + vst3q_s8(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v1i64")] - fn vshl_s64_(a: int64x1_t, b: int64x1_t) -> int64x1_t; - } -vshl_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_u16(a: *mut u16, b: uint16x4x3_t) { + vst3_s16(transmute(a), transmute(b)) } -/// Signed Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshifts.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sshl.v2i64")] - fn vshlq_s64_(a: int64x2_t, b: int64x2_t) -> int64x2_t; - } -vshlq_s64_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_u16(a: *mut u16, b: uint16x8x3_t) { + vst3q_s16(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_u8(a: uint8x8_t, b: int8x8_t) -> uint8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v8i8")] - fn vshl_u8_(a: uint8x8_t, b: int8x8_t) -> uint8x8_t; - } -vshl_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_u32(a: *mut u32, b: uint32x2x3_t) { + vst3_s32(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_u8(a: uint8x16_t, b: int8x16_t) -> uint8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v16i8")] - fn vshlq_u8_(a: uint8x16_t, b: int8x16_t) -> uint8x16_t; - } -vshlq_u8_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_u32(a: *mut u32, b: uint32x4x3_t) { + vst3q_s32(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_u16(a: uint16x4_t, b: int16x4_t) -> uint16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v4i16")] - fn vshl_u16_(a: uint16x4_t, b: int16x4_t) -> uint16x4_t; - } -vshl_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_p8(a: *mut p8, b: poly8x8x3_t) { + vst3_s8(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_u16(a: uint16x8_t, b: int16x8_t) -> uint16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v8i16")] - fn vshlq_u16_(a: uint16x8_t, b: int16x8_t) -> uint16x8_t; - } -vshlq_u16_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_p8(a: *mut p8, b: poly8x16x3_t) { + vst3q_s8(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_u32(a: uint32x2_t, b: int32x2_t) -> uint32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v2i32")] - fn vshl_u32_(a: uint32x2_t, b: int32x2_t) -> uint32x2_t; - } -vshl_u32_(a, b) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3_p16(a: *mut p16, b: poly16x4x3_t) { + vst3_s16(transmute(a), transmute(b)) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32) +#[doc = "Store multiple 3-element structures from three registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst3q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_u32(a: uint32x4_t, b: int32x4_t) -> uint32x4_t { - #[allow(improper_ctypes)] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst3))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st3) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst3q_p16(a: *mut p16, b: poly16x8x3_t) { + vst3q_s16(transmute(a), transmute(b)) +} + +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v4i32")] - fn vshlq_u32_(a: uint32x4_t, b: int32x4_t) -> uint32x4_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2f32")] + fn _vst4_f32( + ptr: *mut i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + size: i32, + ); } -vshlq_u32_(a, b) + _vst4_f32(a as _, b.0, b.1, b.2, b.3, 4) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_u64(a: uint64x1_t, b: int64x1_t) -> uint64x1_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v1i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v1i64")] - fn vshl_u64_(a: uint64x1_t, b: int64x1_t) -> uint64x1_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4f32")] + fn _vst4q_f32( + ptr: *mut i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + size: i32, + ); } -vshl_u64_(a, b) + _vst4q_f32(a as _, b.0, b.1, b.2, b.3, 4) } -/// Unsigned Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushl))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_u64(a: uint64x2_t, b: int64x2_t) -> uint64x2_t { - #[allow(improper_ctypes)] +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vshiftu.v2i64")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.ushl.v2i64")] - fn vshlq_u64_(a: uint64x2_t, b: int64x2_t) -> uint64x2_t; + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i8")] + fn _vst4_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, size: i32); } -vshlq_u64_(a, b) + _vst4_s8(a as _, b.0, b.1, b.2, b.3, 1) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_s8(a: int8x8_t) -> int8x8_t { - static_assert_uimm_bits!(N, 3); - simd_shl(a, vdup_n_s8(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v16i8")] + fn _vst4q_s8( + ptr: *mut i8, + a: int8x16_t, + b: int8x16_t, + c: int8x16_t, + d: int8x16_t, + size: i32, + ); + } + _vst4q_s8(a as _, b.0, b.1, b.2, b.3, 1) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert_uimm_bits!(N, 3); - simd_shl(a, vdupq_n_s8(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i16")] + fn _vst4_s16( + ptr: *mut i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + size: i32, + ); + } + _vst4_s16(a as _, b.0, b.1, b.2, b.3, 2) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_s16(a: int16x4_t) -> int16x4_t { - static_assert_uimm_bits!(N, 4); - simd_shl(a, vdup_n_s16(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v8i16")] + fn _vst4q_s16( + ptr: *mut i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + size: i32, + ); + } + _vst4q_s16(a as _, b.0, b.1, b.2, b.3, 2) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert_uimm_bits!(N, 4); - simd_shl(a, vdupq_n_s16(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v2i32")] + fn _vst4_s32( + ptr: *mut i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + size: i32, + ); + } + _vst4_s32(a as _, b.0, b.1, b.2, b.3, 4) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_s32(a: int32x2_t) -> int32x2_t { - static_assert_uimm_bits!(N, 5); - simd_shl(a, vdup_n_s32(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(vst4))] +pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v4i32")] + fn _vst4q_s32( + ptr: *mut i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + size: i32, + ); + } + _vst4q_s32(a as _, b.0, b.1, b.2, b.3, 4) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert_uimm_bits!(N, 5); - simd_shl(a, vdupq_n_s32(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_f32(a: *mut f32, b: float32x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v2f32.p0i8" + )] + fn _vst4_f32(a: float32x2_t, b: float32x2_t, c: float32x2_t, d: float32x2_t, ptr: *mut i8); + } + _vst4_f32(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert_uimm_bits!(N, 3); - simd_shl(a, vdup_n_u8(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_f32(a: *mut f32, b: float32x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v4f32.p0i8" + )] + fn _vst4q_f32(a: float32x4_t, b: float32x4_t, c: float32x4_t, d: float32x4_t, ptr: *mut i8); + } + _vst4q_f32(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert_uimm_bits!(N, 3); - simd_shl(a, vdupq_n_u8(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s8(a: *mut i8, b: int8x8x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v8i8.p0i8" + )] + fn _vst4_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, ptr: *mut i8); + } + _vst4_s8(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert_uimm_bits!(N, 4); - simd_shl(a, vdup_n_u16(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s8(a: *mut i8, b: int8x16x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v16i8.p0i8" + )] + fn _vst4q_s8(a: int8x16_t, b: int8x16_t, c: int8x16_t, d: int8x16_t, ptr: *mut i8); + } + _vst4q_s8(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert_uimm_bits!(N, 4); - simd_shl(a, vdupq_n_u16(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s16(a: *mut i16, b: int16x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v4i16.p0i8" + )] + fn _vst4_s16(a: int16x4_t, b: int16x4_t, c: int16x4_t, d: int16x4_t, ptr: *mut i8); + } + _vst4_s16(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert_uimm_bits!(N, 5); - simd_shl(a, vdup_n_u32(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s16(a: *mut i16, b: int16x8x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v8i16.p0i8" + )] + fn _vst4q_s16(a: int16x8_t, b: int16x8_t, c: int16x8_t, d: int16x8_t, ptr: *mut i8); + } + _vst4q_s16(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert_uimm_bits!(N, 5); - simd_shl(a, vdupq_n_u32(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4_s32(a: *mut i32, b: int32x2x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v2i32.p0i8" + )] + fn _vst4_s32(a: int32x2_t, b: int32x2_t, c: int32x2_t, d: int32x2_t, ptr: *mut i8); + } + _vst4_s32(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_s64(a: int64x1_t) -> int64x1_t { - static_assert_uimm_bits!(N, 6); - simd_shl(a, vdup_n_s64(N as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(st4))] +pub unsafe fn vst4q_s32(a: *mut i32, b: int32x4x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v4i32.p0i8" + )] + fn _vst4q_s32(a: int32x4_t, b: int32x4_t, c: int32x4_t, d: int32x4_t, ptr: *mut i8); + } + _vst4q_s32(b.0, b.1, b.2, b.3, a as _) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert_uimm_bits!(N, 6); - simd_shl(a, vdupq_n_s64(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2f32")] + fn _vst4_lane_f32( + ptr: *mut i8, + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i32, + size: i32, + ); + } + _vst4_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshl_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert_uimm_bits!(N, 6); - simd_shl(a, vdup_n_u64(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4f32")] + fn _vst4q_lane_f32( + ptr: *mut i8, + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i32, + size: i32, + ); + } + _vst4q_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Shift left -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vshl, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shl, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshlq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert_uimm_bits!(N, 6); - simd_shl(a, vdupq_n_u64(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i8")] + fn _vst4_lane_s8( + ptr: *mut i8, + a: int8x8_t, + b: int8x8_t, + c: int8x8_t, + d: int8x8_t, + n: i32, + size: i32, + ); + } + _vst4_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_s8(a: int8x8_t) -> int16x8_t { - static_assert!(N >= 0 && N <= 8); - simd_shl(simd_cast(a), vdupq_n_s16(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i16")] + fn _vst4_lane_s16( + ptr: *mut i8, + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i32, + size: i32, + ); + } + _vst4_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_s16(a: int16x4_t) -> int32x4_t { - static_assert!(N >= 0 && N <= 16); - simd_shl(simd_cast(a), vdupq_n_s32(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v8i16")] + fn _vst4q_lane_s16( + ptr: *mut i8, + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i32, + size: i32, + ); + } + _vst4q_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.s32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_s32(a: int32x2_t) -> int64x2_t { - static_assert!(N >= 0 && N <= 32); - simd_shl(simd_cast(a), vdupq_n_s64(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v2i32")] + fn _vst4_lane_s32( + ptr: *mut i8, + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i32, + size: i32, + ); + } + _vst4_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_u8(a: uint8x8_t) -> uint16x8_t { - static_assert!(N >= 0 && N <= 8); - simd_shl(simd_cast(a), vdupq_n_u16(N as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[cfg_attr(test, assert_instr(vst4, LANE = 0))] +#[rustc_legacy_const_generics(2)] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4lane.p0i8.v4i32")] + fn _vst4q_lane_s32( + ptr: *mut i8, + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i32, + size: i32, + ); + } + _vst4q_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_u16(a: uint16x4_t) -> uint32x4_t { - static_assert!(N >= 0 && N <= 16); - simd_shl(simd_cast(a), vdupq_n_u32(N as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2f32.p0i8" + )] + fn _vst4_lane_f32( + a: float32x2_t, + b: float32x2_t, + c: float32x2_t, + d: float32x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Signed shift left long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshll.u32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushll, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshll_n_u32(a: uint32x2_t) -> uint64x2_t { - static_assert!(N >= 0 && N <= 32); - simd_shl(simd_cast(a), vdupq_n_u64(N as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4f32.p0i8" + )] + fn _vst4q_lane_f32( + a: float32x4_t, + b: float32x4_t, + c: float32x4_t, + d: float32x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_f32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_s8(a: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { 7 } else { N }; - simd_shr(a, vdup_n_s8(n as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v8i8.p0i8" + )] + fn _vst4_lane_s8(a: int8x8_t, b: int8x8_t, c: int8x8_t, d: int8x8_t, n: i64, ptr: *mut i8); + } + _vst4_lane_s8(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_s8(a: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { 7 } else { N }; - simd_shr(a, vdupq_n_s8(n as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4i16.p0i8" + )] + fn _vst4_lane_s16( + a: int16x4_t, + b: int16x4_t, + c: int16x4_t, + d: int16x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_s16(a: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { 15 } else { N }; - simd_shr(a, vdup_n_s16(n as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v8i16.p0i8" + )] + fn _vst4q_lane_s16( + a: int16x8_t, + b: int16x8_t, + c: int16x8_t, + d: int16x8_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s16(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_s16(a: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { 15 } else { N }; - simd_shr(a, vdupq_n_s16(n as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v2i32.p0i8" + )] + fn _vst4_lane_s32( + a: int32x2_t, + b: int32x2_t, + c: int32x2_t, + d: int32x2_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_s32(a: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { 31 } else { N }; - simd_shr(a, vdup_n_s32(n as _)) +#[cfg(not(target_arch = "arm"))] +#[rustc_legacy_const_generics(2)] +#[cfg_attr(test, assert_instr(st4, LANE = 0))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4lane.v4i32.p0i8" + )] + fn _vst4q_lane_s32( + a: int32x4_t, + b: int32x4_t, + c: int32x4_t, + d: int32x4_t, + n: i64, + ptr: *mut i8, + ); + } + _vst4q_lane_s32(b.0, b.1, b.2, b.3, LANE as i64, a as _) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_s32(a: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { 31 } else { N }; - simd_shr(a, vdupq_n_s32(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u8(a: *mut u8, b: uint8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4_lane_s8::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_s64(a: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { 63 } else { N }; - simd_shr(a, vdup_n_s64(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u16(a: *mut u16, b: uint16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4_lane_s16::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.s64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sshr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_s64(a: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { 63 } else { N }; - simd_shr(a, vdupq_n_s64(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u16(a: *mut u16, b: uint16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4q_lane_s16::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_u8(a: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { return vdup_n_u8(0); } else { N }; - simd_shr(a, vdup_n_u8(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_u32(a: *mut u32, b: uint32x2x4_t) { + static_assert_uimm_bits!(LANE, 1); + vst4_lane_s32::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u8", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_u8(a: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - let n: i32 = if N == 8 { return vdupq_n_u8(0); } else { N }; - simd_shr(a, vdupq_n_u8(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_u32(a: *mut u32, b: uint32x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4q_lane_s32::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_u16(a: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { return vdup_n_u16(0); } else { N }; - simd_shr(a, vdup_n_u16(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p8(a: *mut p8, b: poly8x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4_lane_s8::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_u16(a: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - let n: i32 = if N == 16 { return vdupq_n_u16(0); } else { N }; - simd_shr(a, vdupq_n_u16(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_lane_p16(a: *mut p16, b: poly16x4x4_t) { + static_assert_uimm_bits!(LANE, 2); + vst4_lane_s16::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_lane_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_u32(a: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { return vdup_n_u32(0); } else { N }; - simd_shr(a, vdup_n_u32(n as _)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4, LANE = 0) +)] +#[rustc_legacy_const_generics(2)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_lane_p16(a: *mut p16, b: poly16x8x4_t) { + static_assert_uimm_bits!(LANE, 3); + vst4q_lane_s16::(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_u32(a: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - let n: i32 = if N == 32 { return vdupq_n_u32(0); } else { N }; - simd_shr(a, vdupq_n_u32(n as _)) +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[target_feature(enable = "neon,aes")] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p64(a: *mut p64, b: poly64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshr_n_u64(a: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { return vdup_n_u64(0); } else { N }; - simd_shr(a, vdup_n_u64(n as _)) +#[cfg(target_arch = "arm")] +#[target_feature(enable = "neon,v7")] +#[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + extern "unadjusted" { + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst4.p0i8.v1i64")] + fn _vst4_s64( + ptr: *mut i8, + a: int64x1_t, + b: int64x1_t, + c: int64x1_t, + d: int64x1_t, + size: i32, + ); + } + _vst4_s64(a as _, b.0, b.1, b.2, b.3, 8) } -/// Shift right -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshr.u64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ushr, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrq_n_u64(a: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - let n: i32 = if N == 64 { return vdupq_n_u64(0); } else { N }; - simd_shr(a, vdupq_n_u64(n as _)) +#[cfg(not(target_arch = "arm"))] +#[stable(feature = "neon_intrinsics", since = "1.59.0")] +#[cfg_attr(test, assert_instr(nop))] +pub unsafe fn vst4_s64(a: *mut i64, b: int64x1x4_t) { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.st4.v1i64.p0i8" + )] + fn _vst4_s64(a: int64x1_t, b: int64x1_t, c: int64x1_t, d: int64x1_t, ptr: *mut i8); + } + _vst4_s64(b.0, b.1, b.2, b.3, a as _) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_s16(a: int16x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_cast(simd_shr(a, vdupq_n_s16(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(nop))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(nop) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u64(a: *mut u64, b: uint64x1x4_t) { + vst4_s64(transmute(a), transmute(b)) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_s32(a: int32x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_cast(simd_shr(a, vdupq_n_s32(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u8(a: *mut u8, b: uint8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_s64(a: int64x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_cast(simd_shr(a, vdupq_n_s64(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u8(a: *mut u8, b: uint8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i16", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_u16(a: uint16x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_cast(simd_shr(a, vdupq_n_u16(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u16(a: *mut u16, b: uint16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i32", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_u32(a: uint32x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_cast(simd_shr(a, vdupq_n_u32(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u16(a: *mut u16, b: uint16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) } -/// Shift right narrow -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vshrn.i64", N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(shrn, N = 2))] -#[rustc_legacy_const_generics(1)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vshrn_n_u64(a: uint64x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_cast(simd_shr(a, vdupq_n_u64(N as _))) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_u32(a: *mut u32, b: uint32x2x4_t) { + vst4_s32(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vshr_n_s8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_u32(a: *mut u32, b: uint32x4x4_t) { + vst4q_s32(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vshrq_n_s8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p8(a: *mut p8, b: poly8x8x4_t) { + vst4_s8(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vshr_n_s16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p8(a: *mut p8, b: poly8x16x4_t) { + vst4q_s8(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vshrq_n_s16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4_p16(a: *mut p16, b: poly16x4x4_t) { + vst4_s16(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32) +#[doc = "Store multiple 4-element structures from four registers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst4q_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vshr_n_s32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vst4))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(st4) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vst4q_p16(a: *mut p16, b: poly16x8x4_t) { + vst4q_s16(transmute(a), transmute(b)) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vshrq_n_s32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_f32(a: float32x2_t, b: float32x2_t) -> float32x2_t { + simd_sub(a, b) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vshr_n_s64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.f32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(fsub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_f32(a: float32x4_t, b: float32x4_t) -> float32x4_t { + simd_sub(a, b) } -/// Signed shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(ssra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vshrq_n_s64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_s16(a: int16x4_t, b: int16x4_t) -> int16x4_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vshr_n_u8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_s16(a: int16x8_t, b: int16x8_t) -> int16x8_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { - static_assert!(N >= 1 && N <= 8); - simd_add(a, vshrq_n_u8::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vshr_n_u16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i16"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { - static_assert!(N >= 1 && N <= 16); - simd_add(a, vshrq_n_u16::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_s32(a: int32x2_t, b: int32x2_t) -> int32x2_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vshr_n_u32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_s32(a: int32x4_t, b: int32x4_t) -> int32x4_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { - static_assert!(N >= 1 && N <= 32); - simd_add(a, vshrq_n_u32::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsra_n_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vshr_n_u64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i32"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + simd_sub(a, b) } -/// Unsigned shift right and accumulate -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsra, N = 2))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(usra, N = 2))] -#[rustc_legacy_const_generics(2)] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vsraq_n_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { - static_assert!(N >= 1 && N <= 64); - simd_add(a, vshrq_n_u64::(b)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_s64(a: int64x1_t, b: int64x1_t) -> int64x1_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_s64(a: int64x2_t, b: int64x2_t) -> int64x2_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_u64(a: uint64x1_t, b: uint64x1_t) -> uint64x1_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a1: int8x16_t = simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]); - let b1: int8x16_t = simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i64"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_u64(a: uint64x2_t, b: uint64x2_t) -> uint64x2_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_s8(a: int8x8_t, b: int8x8_t) -> int8x8_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_s8(a: int8x16_t, b: int8x16_t) -> int8x16_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsub_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16) +#[doc = "Subtract"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vsub.i8"))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sub) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + simd_sub(a, b) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a1: uint8x16_t = simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]); - let b1: uint8x16_t = simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_s16(a: int8x8_t, b: int16x8_t, c: int16x8_t) -> int8x16_t { + let d: int8x8_t = vsubhn_s16(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_s32(a: int16x4_t, b: int32x4_t, c: int32x4_t) -> int16x8_t { + let d: int16x4_t = vsubhn_s32(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_s64(a: int32x2_t, b: int64x2_t, c: int64x2_t) -> int32x4_t { + let d: int32x2_t = vsubhn_s64(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_u16(a: uint8x8_t, b: uint16x8_t, c: uint16x8_t) -> uint8x16_t { + let d: uint8x8_t = vsubhn_u16(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_u32(a: uint16x4_t, b: uint32x4_t, c: uint32x4_t) -> uint16x8_t { + let d: uint16x4_t = vsubhn_u32(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3, 4, 5, 6, 7]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a1: poly8x16_t = simd_shuffle!(a, b, [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]); - let b1: poly8x16_t = simd_shuffle!(a, b, [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn2) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_high_u64(a: uint32x2_t, b: uint64x2_t, c: uint64x2_t) -> uint32x4_t { + let d: uint32x2_t = vsubhn_u64(b, c); + simd_shuffle!(a, d, [0, 1, 2, 3]) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); - let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_s16(a: int16x8_t, b: int16x8_t) -> int8x8_t { + let c: i16x8 = i16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_s32(a: int32x4_t, b: int32x4_t) -> int16x4_t { + let c: i32x4 = i32x4::new(16, 16, 16, 16); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_s64(a: int64x2_t, b: int64x2_t) -> int32x2_t { + let c: i64x2 = i64x2::new(32, 32); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_u16(a: uint16x8_t, b: uint16x8_t) -> uint8x8_t { + let c: u16x8 = u16x8::new(8, 8, 8, 8, 8, 8, 8, 8); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Transpose elements -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(trn))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); - let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); - transmute((a1, b1)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_u32(a: uint32x4_t, b: uint32x4_t) -> uint16x4_t { + let c: u32x4 = u32x4::new(16, 16, 16, 16); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8) +#[doc = "Subtract returning high narrow"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubhn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(subhn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubhn_u64(a: uint64x2_t, b: uint64x2_t) -> uint32x2_t { + let c: u64x2 = u64x2::new(32, 32); + simd_cast(simd_shr(simd_sub(a, b), transmute(c))) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_s8(a: int8x8_t, b: int8x8_t) -> int16x8_t { + let c: int16x8_t = simd_cast(a); + let d: int16x8_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_s16(a: int16x4_t, b: int16x4_t) -> int32x4_t { + let c: int32x4_t = simd_cast(a); + let d: int32x4_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16) +#[doc = "Signed Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_s32(a: int32x2_t, b: int32x2_t) -> int64x2_t { + let c: int64x2_t = simd_cast(a); + let d: int64x2_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_u8(a: uint8x8_t, b: uint8x8_t) -> uint16x8_t { + let c: uint16x8_t = simd_cast(a); + let d: uint16x8_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_u16(a: uint16x4_t, b: uint16x4_t) -> uint32x4_t { + let c: uint32x4_t = simd_cast(a); + let d: uint32x4_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32) +#[doc = "Unsigned Subtract Long"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubl))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubl) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubl_u32(a: uint32x2_t, b: uint32x2_t) -> uint64x2_t { + let c: uint64x2_t = simd_cast(a); + let d: uint64x2_t = simd_cast(b); + simd_sub(c, d) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_s8(a: int16x8_t, b: int8x8_t) -> int16x8_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a0: int8x16_t = simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]); - let b0: int8x16_t = simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_s16(a: int32x4_t, b: int16x4_t) -> int32x4_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16) +#[doc = "Signed Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(ssubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_s32(a: int64x2_t, b: int32x2_t) -> int64x2_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_u8(a: uint16x8_t, b: uint8x8_t) -> uint16x8_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a0: uint8x16_t = simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]); - let b0: uint8x16_t = simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_u16(a: uint32x4_t, b: uint16x4_t) -> uint32x4_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16) +#[doc = "Unsigned Subtract Wide"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsubw))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usubw) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsubw_u32(a: uint64x2_t, b: uint32x2_t) -> uint64x2_t { + simd_sub(a, simd_cast(b)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32) +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudot_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsudot_lane_s32( + a: int32x2_t, + b: int8x8_t, + c: uint8x8_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: uint32x2_t = transmute(c); + let c: uint32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, transmute(c), b) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8) +#[doc = "Dot product index form with signed and unsigned integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsudotq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] -#[target_feature(enable = "neon")] -#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a0: poly8x16_t = simd_shuffle!(a, b, [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]); - let b0: poly8x16_t = simd_shuffle!(a, b, [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]); - transmute((a0, b0)) +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vsudot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(sudot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vsudotq_lane_s32( + a: int32x4_t, + b: int8x16_t, + c: uint8x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: uint32x2_t = transmute(c); + let c: uint32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, transmute(c), b) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); - let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + let a1: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + let a1: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) } -/// Zip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); - let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + let a1: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b1: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { - let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + let a1: float32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: float32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { - let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + let a1: int8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { - let a0: int8x16_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]); - let b0: int8x16_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + let a1: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: int8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { - let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + let a1: int16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { - let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + let a1: int16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: int16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { - let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + let a1: int32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: int32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { - let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + let a1: uint8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { - let a0: uint8x16_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]); - let b0: uint8x16_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + let a1: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: uint8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { - let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + let a1: uint16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { - let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + let a1: uint16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: uint16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { - let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + let a1: uint32x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: uint32x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { - let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + let a1: poly8x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly8x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { - let a0: poly8x16_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]); - let b0: poly8x16_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + let a1: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30] + ); + let b1: poly8x16_t = simd_shuffle!( + a, + b, + [1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31] + ); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { - let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); - let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrn_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + let a1: poly16x4_t = simd_shuffle!(a, b, [0, 4, 2, 6]); + let b1: poly16x4_t = simd_shuffle!(a, b, [1, 5, 3, 7]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32) +#[doc = "Transpose elements"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrnq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] #[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { - let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(trn) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtrnq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + let a1: poly16x8_t = simd_shuffle!(a, b, [0, 8, 2, 10, 4, 12, 6, 14]); + let b1: poly16x8_t = simd_shuffle!(a, b, [1, 9, 3, 11, 5, 13, 7, 15]); + transmute((a1, b1)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { - let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_s8(a: int8x8_t, b: int8x8_t) -> uint8x8_t { + let c: int8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(zip))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { - let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); - let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_s8(a: int8x16_t, b: int8x16_t) -> uint8x16_t { + let c: int8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Unzip vectors -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uzp))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { - let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); - let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); - transmute((a0, b0)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_s16(a: int16x4_t, b: int16x4_t) -> uint16x4_t { + let c: int16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_u8(a: uint16x8_t, b: uint8x8_t, c: uint8x8_t) -> uint16x8_t { - let d: uint8x8_t = vabd_u8(b, c); - simd_add(a, simd_cast(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_s16(a: int16x8_t, b: int16x8_t) -> uint16x8_t { + let c: int16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_u16(a: uint32x4_t, b: uint16x4_t, c: uint16x4_t) -> uint32x4_t { - let d: uint16x4_t = vabd_u16(b, c); - simd_add(a, simd_cast(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_s32(a: int32x2_t, b: int32x2_t) -> uint32x2_t { + let c: int32x2_t = simd_and(a, b); + let d: i32x2 = i32x2::new(0, 0); + simd_ne(c, transmute(d)) } -/// Unsigned Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.u32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(uabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_u32(a: uint64x2_t, b: uint32x2_t, c: uint32x2_t) -> uint64x2_t { - let d: uint32x2_t = vabd_u32(b, c); - simd_add(a, simd_cast(d)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_s32(a: int32x4_t, b: int32x4_t) -> uint32x4_t { + let c: int32x4_t = simd_and(a, b); + let d: i32x4 = i32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_s8(a: int16x8_t, b: int8x8_t, c: int8x8_t) -> int16x8_t { - let d: int8x8_t = vabd_s8(b, c); - let e: uint8x8_t = simd_cast(d); - simd_add(a, simd_cast(e)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_p8(a: poly8x8_t, b: poly8x8_t) -> uint8x8_t { + let c: poly8x8_t = simd_and(a, b); + let d: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_s16(a: int32x4_t, b: int16x4_t, c: int16x4_t) -> int32x4_t { - let d: int16x4_t = vabd_s16(b, c); - let e: uint16x4_t = simd_cast(d); - simd_add(a, simd_cast(e)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_p8(a: poly8x16_t, b: poly8x16_t) -> uint8x16_t { + let c: poly8x16_t = simd_and(a, b); + let d: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed Absolute difference and Accumulate Long -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vabal.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sabal))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vabal_s32(a: int64x2_t, b: int32x2_t, c: int32x2_t) -> int64x2_t { - let d: int32x2_t = vabd_s32(b, c); - let e: uint32x2_t = simd_cast(d); - simd_add(a, simd_cast(e)) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_p16(a: poly16x4_t, b: poly16x4_t) -> uint16x4_t { + let c: poly16x4_t = simd_and(a, b); + let d: i16x4 = i16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8) +#[doc = "Signed compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabs_s8(a: int8x8_t) -> int8x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v8i8")] - fn vqabs_s8_(a: int8x8_t) -> int8x8_t; - } -vqabs_s8_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_p16(a: poly16x8_t, b: poly16x8_t) -> uint16x8_t { + let c: poly16x8_t = simd_and(a, b); + let d: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s8"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabsq_s8(a: int8x16_t) -> int8x16_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v16i8")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v16i8")] - fn vqabsq_s8_(a: int8x16_t) -> int8x16_t; - } -vqabsq_s8_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8_t { + let c: uint8x8_t = simd_and(a, b); + let d: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabs_s16(a: int16x4_t) -> int16x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v4i16")] - fn vqabs_s16_(a: int16x4_t) -> int16x4_t; - } -vqabs_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16_t { + let c: uint8x16_t = simd_and(a, b); + let d: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s16"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabsq_s16(a: int16x8_t) -> int16x8_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v8i16")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v8i16")] - fn vqabsq_s16_(a: int16x8_t) -> int16x8_t; - } -vqabsq_s16_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4_t { + let c: uint16x4_t = simd_and(a, b); + let d: u16x4 = u16x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabs_s32(a: int32x2_t) -> int32x2_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v2i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v2i32")] - fn vqabs_s32_(a: int32x2_t) -> int32x2_t; - } -vqabs_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8_t { + let c: uint16x8_t = simd_and(a, b); + let d: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); + simd_ne(c, transmute(d)) } -/// Signed saturating Absolute value -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32) +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] #[inline] #[target_feature(enable = "neon")] #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] -#[cfg_attr(all(test, target_arch = "arm"), assert_instr("vqabs.s32"))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr(sqabs))] -#[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] -#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] -pub unsafe fn vqabsq_s32(a: int32x4_t) -> int32x4_t { - #[allow(improper_ctypes)] - extern "unadjusted" { - #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqabs.v4i32")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "llvm.aarch64.neon.sqabs.v4i32")] - fn vqabsq_s32_(a: int32x4_t) -> int32x4_t; - } -vqabsq_s32_(a) +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtst_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2_t { + let c: uint32x2_t = simd_and(a, b); + let d: u32x2 = u32x2::new(0, 0); + simd_ne(c, transmute(d)) } -#[cfg(test)] -#[allow(overflowing_literals)] -mod test { - use super::*; - use crate::core_arch::simd::*; - use std::mem::transmute; - use stdarch_test::simd_test; - - #[simd_test(enable = "neon")] - unsafe fn test_vand_s8() { - let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i8x8 = transmute(vand_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: i8x8 = transmute(vand_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_s8() { - let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let b: i8x16 = i8x16::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let r: i8x16 = transmute(vandq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: i8x16 = transmute(vandq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_s16() { - let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let b: i16x4 = i16x4::new(0x0F, 0x0F, 0x0F, 0x0F); - let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let r: i16x4 = transmute(vand_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00); - let e: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00); - let r: i16x4 = transmute(vand_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_s16() { - let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i16x8 = transmute(vandq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: i16x8 = transmute(vandq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_s32() { - let a: i32x2 = i32x2::new(0x00, 0x01); - let b: i32x2 = i32x2::new(0x0F, 0x0F); - let e: i32x2 = i32x2::new(0x00, 0x01); - let r: i32x2 = transmute(vand_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i32x2 = i32x2::new(0x00, 0x01); - let b: i32x2 = i32x2::new(0x00, 0x00); - let e: i32x2 = i32x2::new(0x00, 0x00); - let r: i32x2 = transmute(vand_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_s32() { - let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(0x0F, 0x0F, 0x0F, 0x0F); - let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let r: i32x4 = transmute(vandq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let e: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let r: i32x4 = transmute(vandq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_u8() { - let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u8x8 = transmute(vand_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: u8x8 = transmute(vand_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_u8() { - let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let b: u8x16 = u8x16::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let r: u8x16 = transmute(vandq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00); - let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: u8x16 = transmute(vandq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_u16() { - let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let b: u16x4 = u16x4::new(0x0F, 0x0F, 0x0F, 0x0F); - let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let r: u16x4 = transmute(vand_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00); - let e: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00); - let r: u16x4 = transmute(vand_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_u16() { - let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F); - let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u16x8 = transmute(vandq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let r: u16x8 = transmute(vandq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_u32() { - let a: u32x2 = u32x2::new(0x00, 0x01); - let b: u32x2 = u32x2::new(0x0F, 0x0F); - let e: u32x2 = u32x2::new(0x00, 0x01); - let r: u32x2 = transmute(vand_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u32x2 = u32x2::new(0x00, 0x01); - let b: u32x2 = u32x2::new(0x00, 0x00); - let e: u32x2 = u32x2::new(0x00, 0x00); - let r: u32x2 = transmute(vand_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_u32() { - let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0x0F, 0x0F, 0x0F, 0x0F); - let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let r: u32x4 = transmute(vandq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let e: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let r: u32x4 = transmute(vandq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_s64() { - let a: i64x1 = i64x1::new(0x00); - let b: i64x1 = i64x1::new(0x0F); - let e: i64x1 = i64x1::new(0x00); - let r: i64x1 = transmute(vand_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x1 = i64x1::new(0x00); - let b: i64x1 = i64x1::new(0x00); - let e: i64x1 = i64x1::new(0x00); - let r: i64x1 = transmute(vand_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_s64() { - let a: i64x2 = i64x2::new(0x00, 0x01); - let b: i64x2 = i64x2::new(0x0F, 0x0F); - let e: i64x2 = i64x2::new(0x00, 0x01); - let r: i64x2 = transmute(vandq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i64x2 = i64x2::new(0x00, 0x01); - let b: i64x2 = i64x2::new(0x00, 0x00); - let e: i64x2 = i64x2::new(0x00, 0x00); - let r: i64x2 = transmute(vandq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vand_u64() { - let a: u64x1 = u64x1::new(0x00); - let b: u64x1 = u64x1::new(0x0F); - let e: u64x1 = u64x1::new(0x00); - let r: u64x1 = transmute(vand_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u64x1 = u64x1::new(0x00); - let b: u64x1 = u64x1::new(0x00); - let e: u64x1 = u64x1::new(0x00); - let r: u64x1 = transmute(vand_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vandq_u64() { - let a: u64x2 = u64x2::new(0x00, 0x01); - let b: u64x2 = u64x2::new(0x0F, 0x0F); - let e: u64x2 = u64x2::new(0x00, 0x01); - let r: u64x2 = transmute(vandq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u64x2 = u64x2::new(0x00, 0x01); - let b: u64x2 = u64x2::new(0x00, 0x00); - let e: u64x2 = u64x2::new(0x00, 0x00); - let r: u64x2 = transmute(vandq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_s8() { - let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i8x8 = transmute(vorr_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_s8() { - let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: i8x16 = transmute(vorrq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_s16() { - let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00); - let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let r: i16x4 = transmute(vorr_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_s16() { - let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i16x8 = transmute(vorrq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_s32() { - let a: i32x2 = i32x2::new(0x00, 0x01); - let b: i32x2 = i32x2::new(0x00, 0x00); - let e: i32x2 = i32x2::new(0x00, 0x01); - let r: i32x2 = transmute(vorr_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_s32() { - let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let r: i32x4 = transmute(vorrq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_u8() { - let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u8x8 = transmute(vorr_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_u8() { - let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: u8x16 = transmute(vorrq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_u16() { - let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00); - let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let r: u16x4 = transmute(vorr_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_u16() { - let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u16x8 = transmute(vorrq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_u32() { - let a: u32x2 = u32x2::new(0x00, 0x01); - let b: u32x2 = u32x2::new(0x00, 0x00); - let e: u32x2 = u32x2::new(0x00, 0x01); - let r: u32x2 = transmute(vorr_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_u32() { - let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let r: u32x4 = transmute(vorrq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_s64() { - let a: i64x1 = i64x1::new(0x00); - let b: i64x1 = i64x1::new(0x00); - let e: i64x1 = i64x1::new(0x00); - let r: i64x1 = transmute(vorr_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_s64() { - let a: i64x2 = i64x2::new(0x00, 0x01); - let b: i64x2 = i64x2::new(0x00, 0x00); - let e: i64x2 = i64x2::new(0x00, 0x01); - let r: i64x2 = transmute(vorrq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorr_u64() { - let a: u64x1 = u64x1::new(0x00); - let b: u64x1 = u64x1::new(0x00); - let e: u64x1 = u64x1::new(0x00); - let r: u64x1 = transmute(vorr_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vorrq_u64() { - let a: u64x2 = u64x2::new(0x00, 0x01); - let b: u64x2 = u64x2::new(0x00, 0x00); - let e: u64x2 = u64x2::new(0x00, 0x01); - let r: u64x2 = transmute(vorrq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_s8() { - let a: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x8 = i8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i8x8 = transmute(veor_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_s8() { - let a: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: i8x16 = i8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x16 = i8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: i8x16 = transmute(veorq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_s16() { - let a: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let b: i16x4 = i16x4::new(0x00, 0x00, 0x00, 0x00); - let e: i16x4 = i16x4::new(0x00, 0x01, 0x02, 0x03); - let r: i16x4 = transmute(veor_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_s16() { - let a: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: i16x8 = transmute(veorq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_s32() { - let a: i32x2 = i32x2::new(0x00, 0x01); - let b: i32x2 = i32x2::new(0x00, 0x00); - let e: i32x2 = i32x2::new(0x00, 0x01); - let r: i32x2 = transmute(veor_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_s32() { - let a: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(0x00, 0x00, 0x00, 0x00); - let e: i32x4 = i32x4::new(0x00, 0x01, 0x02, 0x03); - let r: i32x4 = transmute(veorq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_u8() { - let a: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x8 = u8x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u8x8 = transmute(veor_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_u8() { - let a: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let b: u8x16 = u8x16::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u8x16 = u8x16::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F); - let r: u8x16 = transmute(veorq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_u16() { - let a: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let b: u16x4 = u16x4::new(0x00, 0x00, 0x00, 0x00); - let e: u16x4 = u16x4::new(0x00, 0x01, 0x02, 0x03); - let r: u16x4 = transmute(veor_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_u16() { - let a: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: u16x8 = u16x8::new(0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let r: u16x8 = transmute(veorq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_u32() { - let a: u32x2 = u32x2::new(0x00, 0x01); - let b: u32x2 = u32x2::new(0x00, 0x00); - let e: u32x2 = u32x2::new(0x00, 0x01); - let r: u32x2 = transmute(veor_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_u32() { - let a: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0x00, 0x00, 0x00, 0x00); - let e: u32x4 = u32x4::new(0x00, 0x01, 0x02, 0x03); - let r: u32x4 = transmute(veorq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_s64() { - let a: i64x1 = i64x1::new(0x00); - let b: i64x1 = i64x1::new(0x00); - let e: i64x1 = i64x1::new(0x00); - let r: i64x1 = transmute(veor_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_s64() { - let a: i64x2 = i64x2::new(0x00, 0x01); - let b: i64x2 = i64x2::new(0x00, 0x00); - let e: i64x2 = i64x2::new(0x00, 0x01); - let r: i64x2 = transmute(veorq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veor_u64() { - let a: u64x1 = u64x1::new(0x00); - let b: u64x1 = u64x1::new(0x00); - let e: u64x1 = u64x1::new(0x00); - let r: u64x1 = transmute(veor_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_veorq_u64() { - let a: u64x2 = u64x2::new(0x00, 0x01); - let b: u64x2 = u64x2::new(0x00, 0x00); - let e: u64x2 = u64x2::new(0x00, 0x01); - let r: u64x2 = transmute(veorq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i8x8 = i8x8::new(15, 13, 11, 9, 7, 5, 3, 1); - let r: i8x8 = transmute(vabd_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: i8x16 = i8x16::new(15, 13, 11, 9, 7, 5, 3, 1, 1, 3, 5, 7, 9, 11, 13, 15); - let r: i8x16 = transmute(vabdq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(16, 15, 14, 13); - let e: i16x4 = i16x4::new(15, 13, 11, 9); - let r: i16x4 = transmute(vabd_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i16x8 = i16x8::new(15, 13, 11, 9, 7, 5, 3, 1); - let r: i16x8 = transmute(vabdq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(16, 15); - let e: i32x2 = i32x2::new(15, 13); - let r: i32x2 = transmute(vabd_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(16, 15, 14, 13); - let e: i32x4 = i32x4::new(15, 13, 11, 9); - let r: i32x4 = transmute(vabdq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u8x8 = u8x8::new(15, 13, 11, 9, 7, 5, 3, 1); - let r: u8x8 = transmute(vabd_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: u8x16 = u8x16::new(15, 13, 11, 9, 7, 5, 3, 1, 1, 3, 5, 7, 9, 11, 13, 15); - let r: u8x16 = transmute(vabdq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(16, 15, 14, 13); - let e: u16x4 = u16x4::new(15, 13, 11, 9); - let r: u16x4 = transmute(vabd_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u16x8 = u16x8::new(15, 13, 11, 9, 7, 5, 3, 1); - let r: u16x8 = transmute(vabdq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(16, 15); - let e: u32x2 = u32x2::new(15, 13); - let r: u32x2 = transmute(vabd_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(16, 15, 14, 13); - let e: u32x4 = u32x4::new(15, 13, 11, 9); - let r: u32x4 = transmute(vabdq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabd_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(9.0, 3.0); - let e: f32x2 = f32x2::new(8.0, 1.0); - let r: f32x2 = transmute(vabd_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 5.0, -4.0); - let b: f32x4 = f32x4::new(9.0, 3.0, 2.0, 8.0); - let e: f32x4 = f32x4::new(8.0, 1.0, 3.0, 12.0); - let r: f32x4 = transmute(vabdq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 4, 3, 2, 1); - let b: u8x8 = u8x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: u16x8 = u16x8::new(9, 8, 7, 6, 6, 7, 8, 9); - let r: u16x8 = transmute(vabdl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(10, 10, 10, 10); - let e: u32x4 = u32x4::new(9, 8, 7, 6); - let r: u32x4 = transmute(vabdl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(10, 10); - let e: u64x2 = u64x2::new(9, 8); - let r: u64x2 = transmute(vabdl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 4, 3, 2, 1); - let b: i8x8 = i8x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: i16x8 = i16x8::new(9, 8, 7, 6, 6, 7, 8, 9); - let r: i16x8 = transmute(vabdl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_s16() { - let a: i16x4 = i16x4::new(1, 2, 11, 12); - let b: i16x4 = i16x4::new(10, 10, 10, 10); - let e: i32x4 = i32x4::new(9, 8, 1, 2); - let r: i32x4 = transmute(vabdl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabdl_s32() { - let a: i32x2 = i32x2::new(1, 11); - let b: i32x2 = i32x2::new(10, 10); - let e: i64x2 = i64x2::new(9, 1); - let r: i64x2 = transmute(vabdl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_u8() { - let a: u8x8 = u8x8::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vceq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u8x8 = u8x8::new(0, 0, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u8x8 = u8x8::new(0, 0xFF, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08); - let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x8 = transmute(vceq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_u8() { - let a: u8x16 = u8x16::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0xFF); - let b: u8x16 = u8x16::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0xFF); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vceqq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u8x16 = u8x16::new(0, 0, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, 0xFF); - let b: u8x16 = u8x16::new(0, 0xFF, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, 0); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x16 = transmute(vceqq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_u16() { - let a: u16x4 = u16x4::new(0, 0x01, 0x02, 0x03); - let b: u16x4 = u16x4::new(0, 0x01, 0x02, 0x03); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vceq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u16x4 = u16x4::new(0, 0, 0x02, 0x03); - let b: u16x4 = u16x4::new(0, 0xFF_FF, 0x02, 0x04); - let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0); - let r: u16x4 = transmute(vceq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_u16() { - let a: u16x8 = u16x8::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vceqq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u16x8 = u16x8::new(0, 0, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: u16x8 = u16x8::new(0, 0xFF_FF, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08); - let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0); - let r: u16x8 = transmute(vceqq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_u32() { - let a: u32x2 = u32x2::new(0, 0x01); - let b: u32x2 = u32x2::new(0, 0x01); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vceq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u32x2 = u32x2::new(0, 0); - let b: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vceq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_u32() { - let a: u32x4 = u32x4::new(0, 0x01, 0x02, 0x03); - let b: u32x4 = u32x4::new(0, 0x01, 0x02, 0x03); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vceqq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: u32x4 = u32x4::new(0, 0, 0x02, 0x03); - let b: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0x02, 0x04); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vceqq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_s8() { - let a: i8x8 = i8x8::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vceq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x8 = i8x8::new(-128, -128, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(-128, 0x7F, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08); - let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x8 = transmute(vceq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_s8() { - let a: i8x16 = i8x16::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vceqq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x16 = i8x16::new(-128, -128, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x7F, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, -128); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x16 = transmute(vceqq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_s16() { - let a: i16x4 = i16x4::new(-32768, 0x01, 0x02, 0x03); - let b: i16x4 = i16x4::new(-32768, 0x01, 0x02, 0x03); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vceq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i16x4 = i16x4::new(-32768, -32768, 0x02, 0x03); - let b: i16x4 = i16x4::new(-32768, 0x7F_FF, 0x02, 0x04); - let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0); - let r: u16x4 = transmute(vceq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_s16() { - let a: i16x8 = i16x8::new(-32768, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(-32768, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vceqq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i16x8 = i16x8::new(-32768, -32768, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i16x8 = i16x8::new(-32768, 0x7F_FF, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08); - let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0); - let r: u16x8 = transmute(vceqq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_s32() { - let a: i32x2 = i32x2::new(-2147483648, 0x01); - let b: i32x2 = i32x2::new(-2147483648, 0x01); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vceq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i32x2 = i32x2::new(-2147483648, -2147483648); - let b: i32x2 = i32x2::new(-2147483648, 0x7F_FF_FF_FF); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vceq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_s32() { - let a: i32x4 = i32x4::new(-2147483648, 0x01, 0x02, 0x03); - let b: i32x4 = i32x4::new(-2147483648, 0x01, 0x02, 0x03); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vceqq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i32x4 = i32x4::new(-2147483648, -2147483648, 0x02, 0x03); - let b: i32x4 = i32x4::new(-2147483648, 0x7F_FF_FF_FF, 0x02, 0x04); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vceqq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_p8() { - let a: i8x8 = i8x8::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vceq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x8 = i8x8::new(-128, -128, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07); - let b: i8x8 = i8x8::new(-128, 0x7F, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08); - let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x8 = transmute(vceq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_p8() { - let a: i8x16 = i8x16::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vceqq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - - let a: i8x16 = i8x16::new(-128, -128, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x7F, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, -128); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x16 = transmute(vceqq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceq_f32() { - let a: f32x2 = f32x2::new(1.2, 3.4); - let b: f32x2 = f32x2::new(1.2, 3.4); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vceq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vceqq_f32() { - let a: f32x4 = f32x4::new(1.2, 3.4, 5.6, 7.8); - let b: f32x4 = f32x4::new(1.2, 3.4, 5.6, 7.8); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vceqq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_s8() { - let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vtst_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_s8() { - let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vtstq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_s16() { - let a: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); - let b: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); - let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vtst_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_s16() { - let a: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vtstq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_s32() { - let a: i32x2 = i32x2::new(-2147483648, 0x00); - let b: i32x2 = i32x2::new(-2147483648, 0x00); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vtst_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_s32() { - let a: i32x4 = i32x4::new(-2147483648, 0x00, 0x01, 0x02); - let b: i32x4 = i32x4::new(-2147483648, 0x00, 0x01, 0x02); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vtstq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_p8() { - let a: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: i8x8 = i8x8::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vtst_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_p8() { - let a: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let b: i8x16 = i8x16::new(-128, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x7F); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vtstq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_p16() { - let a: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); - let b: i16x4 = i16x4::new(-32768, 0x00, 0x01, 0x02); - let e: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vtst_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_p16() { - let a: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: i16x8 = i16x8::new(-32768, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vtstq_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_u8() { - let a: u8x8 = u8x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: u8x8 = u8x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u8x8 = u8x8::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vtst_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_u8() { - let a: u8x16 = u8x16::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0xFF); - let b: u8x16 = u8x16::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0xFF); - let e: u8x16 = u8x16::new(0, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vtstq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_u16() { - let a: u16x4 = u16x4::new(0, 0x00, 0x01, 0x02); - let b: u16x4 = u16x4::new(0, 0x00, 0x01, 0x02); - let e: u16x4 = u16x4::new(0, 0, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vtst_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_u16() { - let a: u16x8 = u16x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let b: u16x8 = u16x8::new(0, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06); - let e: u16x8 = u16x8::new(0, 0, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vtstq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtst_u32() { - let a: u32x2 = u32x2::new(0, 0x00); - let b: u32x2 = u32x2::new(0, 0x00); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vtst_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtstq_u32() { - let a: u32x4 = u32x4::new(0, 0x00, 0x01, 0x02); - let b: u32x4 = u32x4::new(0, 0x00, 0x01, 0x02); - let e: u32x4 = u32x4::new(0, 0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vtstq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabs_f32() { - let a: f32x2 = f32x2::new(-0.1, -2.2); - let e: f32x2 = f32x2::new(0.1, 2.2); - let r: f32x2 = transmute(vabs_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabsq_f32() { - let a: f32x4 = f32x4::new(-0.1, -2.2, -3.3, -6.6); - let e: f32x4 = f32x4::new(0.1, 2.2, 3.3, 6.6); - let r: f32x4 = transmute(vabsq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcgt_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgtq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcgt_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgtq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcgt_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgtq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcgt_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgtq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcgt_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgtq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(0, 1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcgt_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgtq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgt_f32() { - let a: f32x2 = f32x2::new(1.2, 2.3); - let b: f32x2 = f32x2::new(0.1, 1.2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcgt_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgtq_f32() { - let a: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5); - let b: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgtq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vclt_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcltq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vclt_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcltq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(1, 2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vclt_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcltq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vclt_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcltq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vclt_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcltq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vclt_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcltq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclt_f32() { - let a: f32x2 = f32x2::new(0.1, 1.2); - let b: f32x2 = f32x2::new(1.2, 2.3); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vclt_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcltq_f32() { - let a: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4); - let b: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcltq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcle_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcleq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcle_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcleq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(1, 2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcle_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcleq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcle_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcleq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcle_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcleq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcle_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcleq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcle_f32() { - let a: f32x2 = f32x2::new(0.1, 1.2); - let b: f32x2 = f32x2::new(1.2, 2.3); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcle_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcleq_f32() { - let a: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4); - let b: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcleq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcge_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgeq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcge_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgeq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcge_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgeq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vcge_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x16 = transmute(vcgeq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vcge_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x8 = transmute(vcgeq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(0, 1); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcge_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgeq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcge_f32() { - let a: f32x2 = f32x2::new(1.2, 2.3); - let b: f32x2 = f32x2::new(0.1, 1.2); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcge_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcgeq_f32() { - let a: f32x4 = f32x4::new(1.2, 2.3, 3.4, 4.5); - let b: f32x4 = f32x4::new(0.1, 1.2, 2.3, 3.4); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcgeq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x8 = i8x8::new(0, 7, 7, 7, 7, 7, 7, 7); - let r: i8x8 = transmute(vcls_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7F); - let e: i8x16 = i8x16::new(0, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 0); - let r: i8x16 = transmute(vclsq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x00); - let e: i16x4 = i16x4::new(0, 15, 15, 15); - let r: i16x4 = transmute(vcls_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(0, 15, 15, 15, 15, 15, 15, 15); - let r: i16x8 = transmute(vclsq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: i32x2 = i32x2::new(0, 31); - let r: i32x2 = transmute(vcls_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x00); - let e: i32x4 = i32x4::new(0, 31, 31, 31); - let r: i32x4 = transmute(vclsq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_u8() { - let a: u8x8 = u8x8::new(0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i8x8 = i8x8::new(7, 7, 7, 7, 7, 7, 7, 7); - let r: i8x8 = transmute(vcls_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_u8() { - let a: u8x16 = u8x16::new(0, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF); - let e: i8x16 = i8x16::new(7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7); - let r: i8x16 = transmute(vclsq_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_u16() { - let a: u16x4 = u16x4::new(0, 0xFF_FF, 0x00, 0x00); - let e: i16x4 = i16x4::new(15, 15, 15, 15); - let r: i16x4 = transmute(vcls_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_u16() { - let a: u16x8 = u16x8::new(0, 0xFF_FF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00); - let e: i16x8 = i16x8::new(15, 15, 15, 15, 15, 15, 15, 15); - let r: i16x8 = transmute(vclsq_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcls_u32() { - let a: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let e: i32x2 = i32x2::new(31, 31); - let r: i32x2 = transmute(vcls_u32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unsigned compare bitwise Test bits nonzero"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtst))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(cmtst) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vtstq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4_t { + let c: uint32x4_t = simd_and(a, b); + let d: u32x4 = u32x4::new(0, 0, 0, 0); + simd_ne(c, transmute(d)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclsq_u32() { - let a: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0x00, 0x00); - let e: i32x4 = i32x4::new(31, 31, 31, 31); - let r: i32x4 = transmute(vclsq_u32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vusdot_lane_s32( + a: int32x2_t, + b: uint8x8_t, + c: int8x8_t, +) -> int32x2_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = transmute(c); + let c: int32x2_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32]); + vusdot_s32(a, b, transmute(c)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclz_s8() { - let a: i8x8 = i8x8::new(-128, -1, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01); - let e: i8x8 = i8x8::new(0, 0, 8, 7, 7, 7, 7, 7); - let r: i8x8 = transmute(vclz_s8(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Dot product index form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_lane_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot, LANE = 0))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot, LANE = 0) +)] +#[rustc_legacy_const_generics(3)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vusdotq_lane_s32( + a: int32x4_t, + b: uint8x16_t, + c: int8x8_t, +) -> int32x4_t { + static_assert_uimm_bits!(LANE, 1); + let c: int32x2_t = transmute(c); + let c: int32x4_t = simd_shuffle!(c, c, [LANE as u32, LANE as u32, LANE as u32, LANE as u32]); + vusdotq_s32(a, b, transmute(c)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_s8() { - let a: i8x16 = i8x16::new(-128, -1, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x7F); - let e: i8x16 = i8x16::new(0, 0, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 1); - let r: i8x16 = transmute(vclzq_s8(transmute(a))); - assert_eq!(r, e); +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdot_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vusdot_s32(a: int32x2_t, b: uint8x8_t, c: int8x8_t) -> int32x2_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v2i32.v8i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v2i32.v8i8")] + fn _vusdot_s32(a: int32x2_t, b: int8x8_t, c: int8x8_t) -> int32x2_t; } + _vusdot_s32(a, b.as_signed(), c) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclz_s16() { - let a: i16x4 = i16x4::new(-32768, -1, 0x00, 0x01); - let e: i16x4 = i16x4::new(0, 0, 16, 15); - let r: i16x4 = transmute(vclz_s16(transmute(a))); - assert_eq!(r, e); +#[doc = "Dot product vector form with unsigned and signed integers"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vusdotq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon,i8mm")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vusdot))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(usdot) +)] +#[cfg_attr( + not(target_arch = "arm"), + unstable(feature = "stdarch_neon_i8mm", issue = "117223") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vusdotq_s32(a: int32x4_t, b: uint8x16_t, c: int8x16_t) -> int32x4_t { + extern "unadjusted" { + #[cfg_attr( + any(target_arch = "aarch64", target_arch = "arm64ec"), + link_name = "llvm.aarch64.neon.usdot.v4i32.v16i8" + )] + #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.usdot.v4i32.v16i8")] + fn _vusdotq_s32(a: int32x4_t, b: int8x16_t, c: int8x16_t) -> int32x4_t; } + _vusdotq_s32(a, b.as_signed(), c) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_s16() { - let a: i16x8 = i16x8::new(-32768, -1, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01); - let e: i16x8 = i16x8::new(0, 0, 16, 15, 15, 15, 15, 15); - let r: i16x8 = transmute(vclzq_s16(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vclz_s32() { - let a: i32x2 = i32x2::new(-2147483648, -1); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vclz_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_s32() { - let a: i32x4 = i32x4::new(-2147483648, -1, 0x00, 0x01); - let e: i32x4 = i32x4::new(0, 0, 32, 31); - let r: i32x4 = transmute(vclzq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclz_u8() { - let a: u8x8 = u8x8::new(0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01); - let e: u8x8 = u8x8::new(8, 8, 7, 7, 7, 7, 7, 7); - let r: u8x8 = transmute(vclz_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_u8() { - let a: u8x16 = u8x16::new(0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF); - let e: u8x16 = u8x16::new(8, 8, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 0); - let r: u8x16 = transmute(vclzq_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclz_u16() { - let a: u16x4 = u16x4::new(0, 0x00, 0x01, 0x01); - let e: u16x4 = u16x4::new(16, 16, 15, 15); - let r: u16x4 = transmute(vclz_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_u16() { - let a: u16x8 = u16x8::new(0, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01); - let e: u16x8 = u16x8::new(16, 16, 15, 15, 15, 15, 15, 15); - let r: u16x8 = transmute(vclzq_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclz_u32() { - let a: u32x2 = u32x2::new(0, 0x00); - let e: u32x2 = u32x2::new(32, 32); - let r: u32x2 = transmute(vclz_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vclzq_u32() { - let a: u32x4 = u32x4::new(0, 0x00, 0x01, 0x01); - let e: u32x4 = u32x4::new(32, 32, 31, 31); - let r: u32x4 = transmute(vclzq_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagt_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let b: f32x2 = f32x2::new(-1.1, 0.0); - let e: u32x2 = u32x2::new(!0, 0); - let r: u32x2 = transmute(vcagt_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcagtq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let b: f32x4 = f32x4::new(-1.1, 0.0, 1.1, 2.4); - let e: u32x4 = u32x4::new(!0, 0, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vcagtq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcage_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let b: f32x2 = f32x2::new(-1.1, 0.0); - let e: u32x2 = u32x2::new(!0, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcage_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcageq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let b: f32x4 = f32x4::new(-1.1, 0.0, 1.1, 2.4); - let e: u32x4 = u32x4::new(!0, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vcageq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcalt_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let b: f32x2 = f32x2::new(-1.1, 0.0); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vcalt_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaltq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let b: f32x4 = f32x4::new(-1.1, 0.0, 1.1, 2.4); - let e: u32x4 = u32x4::new(0, 0, 0, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcaltq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcale_f32() { - let a: f32x2 = f32x2::new(-1.2, 0.0); - let b: f32x2 = f32x2::new(-1.1, 0.0); - let e: u32x2 = u32x2::new(0, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vcale_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcaleq_f32() { - let a: f32x4 = f32x4::new(-1.2, 0.0, 1.2, 2.3); - let b: f32x4 = f32x4::new(-1.1, 0.0, 1.1, 2.4); - let e: u32x4 = u32x4::new(0, 0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF); - let r: u32x4 = transmute(vcaleq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_s8() { - let a: u64 = 1; - let e: i8x8 = i8x8::new(1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vcreate_s8(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_s16() { - let a: u64 = 1; - let e: i16x4 = i16x4::new(1, 0, 0, 0); - let r: i16x4 = transmute(vcreate_s16(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_s32() { - let a: u64 = 1; - let e: i32x2 = i32x2::new(1, 0); - let r: i32x2 = transmute(vcreate_s32(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_s64() { - let a: u64 = 1; - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vcreate_s64(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_u8() { - let a: u64 = 1; - let e: u8x8 = u8x8::new(1, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vcreate_u8(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_u16() { - let a: u64 = 1; - let e: u16x4 = u16x4::new(1, 0, 0, 0); - let r: u16x4 = transmute(vcreate_u16(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_u32() { - let a: u64 = 1; - let e: u32x2 = u32x2::new(1, 0); - let r: u32x2 = transmute(vcreate_u32(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_u64() { - let a: u64 = 1; - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vcreate_u64(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_p8() { - let a: u64 = 1; - let e: i8x8 = i8x8::new(1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vcreate_p8(a)); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_p16() { - let a: u64 = 1; - let e: i16x4 = i16x4::new(1, 0, 0, 0); - let r: i16x4 = transmute(vcreate_p16(a)); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon,aes")] - unsafe fn test_vcreate_p64() { - let a: u64 = 1; - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vcreate_p64(a)); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + let a0: float32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: float32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcreate_f32() { - let a: u64 = 0; - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vcreate_f32(a)); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + let a0: int8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f32_s32() { - let a: i32x2 = i32x2::new(1, 2); - let e: f32x2 = f32x2::new(1., 2.); - let r: f32x2 = transmute(vcvt_f32_s32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_f32_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let e: f32x4 = f32x4::new(1., 2., 3., 4.); - let r: f32x4 = transmute(vcvtq_f32_s32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + let a0: int16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_f32_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: f32x2 = f32x2::new(1., 2.); - let r: f32x2 = transmute(vcvt_f32_u32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + let a0: int16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: int16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_f32_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: f32x4 = f32x4::new(1., 2., 3., 4.); - let r: f32x4 = transmute(vcvtq_f32_u32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + let a0: int32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: int32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_f32_s32() { - let a: i32x2 = i32x2::new(1, 2); - let e: f32x2 = f32x2::new(0.25, 0.5); - let r: f32x2 = transmute(vcvt_n_f32_s32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_f32_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let e: f32x4 = f32x4::new(0.25, 0.5, 0.75, 1.); - let r: f32x4 = transmute(vcvtq_n_f32_s32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_f32_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: f32x2 = f32x2::new(0.25, 0.5); - let r: f32x2 = transmute(vcvt_n_f32_u32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_f32_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: f32x4 = f32x4::new(0.25, 0.5, 0.75, 1.); - let r: f32x4 = transmute(vcvtq_n_f32_u32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: uint16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_s32_f32() { - let a: f32x2 = f32x2::new(0.25, 0.5); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vcvt_n_s32_f32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: uint32x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_s32_f32() { - let a: f32x4 = f32x4::new(0.25, 0.5, 0.75, 1.); - let e: i32x4 = i32x4::new(1, 2, 3, 4); - let r: i32x4 = transmute(vcvtq_n_s32_f32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_n_u32_f32() { - let a: f32x2 = f32x2::new(0.25, 0.5); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vcvt_n_u32_f32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_n_u32_f32() { - let a: f32x4 = f32x4::new(0.25, 0.5, 0.75, 1.); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vcvtq_n_u32_f32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_s32_f32() { - let a: f32x2 = f32x2::new(-1.1, 2.1); - let e: i32x2 = i32x2::new(-1, 2); - let r: i32x2 = transmute(vcvt_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_s32_f32() { - let a: f32x4 = f32x4::new(-1.1, 2.1, -2.9, 3.9); - let e: i32x4 = i32x4::new(-1, 2, -2, 3); - let r: i32x4 = transmute(vcvtq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvt_u32_f32() { - let a: f32x2 = f32x2::new(1.1, 2.1); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vcvt_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vcvtq_u32_f32() { - let a: f32x4 = f32x4::new(1.1, 2.1, 2.9, 3.9); - let e: u32x4 = u32x4::new(1, 2, 2, 3); - let r: u32x4 = transmute(vcvtq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x8 = transmute(vdup_lane_s8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x16 = transmute(vdupq_laneq_s8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vdup_lane_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vdupq_laneq_s16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_s32() { - let a: i32x2 = i32x2::new(1, 1); - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vdup_lane_s32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 4); - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vdupq_laneq_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x8 = transmute(vdup_laneq_s8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vdup_laneq_s16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 4); - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vdup_laneq_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x16 = transmute(vdupq_lane_s8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vdupq_lane_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_s32() { - let a: i32x2 = i32x2::new(1, 1); - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vdupq_lane_s32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: u8x8 = transmute(vdup_lane_u8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: u8x16 = transmute(vdupq_laneq_u8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 4); - let e: u16x4 = u16x4::new(1, 1, 1, 1); - let r: u16x4 = transmute(vdup_lane_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: u16x8 = transmute(vdupq_laneq_u16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_u32() { - let a: u32x2 = u32x2::new(1, 1); - let e: u32x2 = u32x2::new(1, 1); - let r: u32x2 = transmute(vdup_lane_u32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 4); - let e: u32x4 = u32x4::new(1, 1, 1, 1); - let r: u32x4 = transmute(vdupq_laneq_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: u8x8 = transmute(vdup_laneq_u8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u16x4 = u16x4::new(1, 1, 1, 1); - let r: u16x4 = transmute(vdup_laneq_u16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 4); - let e: u32x2 = u32x2::new(1, 1); - let r: u32x2 = transmute(vdup_laneq_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: u8x16 = transmute(vdupq_lane_u8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 4); - let e: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: u16x8 = transmute(vdupq_lane_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_u32() { - let a: u32x2 = u32x2::new(1, 1); - let e: u32x4 = u32x4::new(1, 1, 1, 1); - let r: u32x4 = transmute(vdupq_lane_u32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_p8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x8 = transmute(vdup_lane_p8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_p8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x16 = transmute(vdupq_laneq_p8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_p16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vdup_lane_p16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_p16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vdupq_laneq_p16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_p8() { - let a: i8x16 = i8x16::new(1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16); - let e: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x8 = transmute(vdup_laneq_p8::<8>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_p16() { - let a: i16x8 = i16x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vdup_laneq_p16::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_p8() { - let a: i8x8 = i8x8::new(1, 1, 1, 4, 1, 6, 7, 8); - let e: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let r: i8x16 = transmute(vdupq_lane_p8::<4>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_p16() { - let a: i16x4 = i16x4::new(1, 1, 1, 4); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vdupq_lane_p16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_s64() { - let a: i64x2 = i64x2::new(1, 1); - let e: i64x2 = i64x2::new(1, 1); - let r: i64x2 = transmute(vdupq_laneq_s64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_s64() { - let a: i64x1 = i64x1::new(1); - let e: i64x2 = i64x2::new(1, 1); - let r: i64x2 = transmute(vdupq_lane_s64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_u64() { - let a: u64x2 = u64x2::new(1, 1); - let e: u64x2 = u64x2::new(1, 1); - let r: u64x2 = transmute(vdupq_laneq_u64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_u64() { - let a: u64x1 = u64x1::new(1); - let e: u64x2 = u64x2::new(1, 1); - let r: u64x2 = transmute(vdupq_lane_u64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let e: f32x2 = f32x2::new(1., 1.); - let r: f32x2 = transmute(vdup_lane_f32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_laneq_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 4.); - let e: f32x4 = f32x4::new(1., 1., 1., 1.); - let r: f32x4 = transmute(vdupq_laneq_f32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 4.); - let e: f32x2 = f32x2::new(1., 1.); - let r: f32x2 = transmute(vdup_laneq_f32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdupq_lane_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let e: f32x4 = f32x4::new(1., 1., 1., 1.); - let r: f32x4 = transmute(vdupq_lane_f32::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_s64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vdup_lane_s64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_lane_u64() { - let a: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vdup_lane_u64::<0>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vdup_laneq_s64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vdup_laneq_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vdup_laneq_u64::<1>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: i8x8 = transmute(vext_s8::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let r: i8x16 = transmute(vextq_s8::<15>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(1, 2, 2, 2); - let r: i16x4 = transmute(vext_s16::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vextq_s16::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vext_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(1, 2, 2, 2); - let r: i32x4 = transmute(vextq_s32::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x8 = u8x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: u8x8 = transmute(vext_u8::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x16 = u8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let r: u8x16 = transmute(vextq_u8::<15>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 1); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let e: u16x4 = u16x4::new(1, 2, 2, 2); - let r: u16x4 = transmute(vext_u16::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: u16x8 = transmute(vextq_u16::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_u32() { - let a: u32x2 = u32x2::new(1, 1); - let b: u32x2 = u32x2::new(2, 2); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vext_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 1); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let e: u32x4 = u32x4::new(1, 2, 2, 2); - let r: u32x4 = transmute(vextq_u32::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_p8() { - let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: i8x8 = transmute(vext_p8::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_p8() { - let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let r: i8x16 = transmute(vextq_p8::<15>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_p16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(1, 2, 2, 2); - let r: i16x4 = transmute(vext_p16::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_p16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(1, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vextq_p16::<7>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_s64() { - let a: i64x2 = i64x2::new(1, 1); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vextq_s64::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_u64() { - let a: u64x2 = u64x2::new(1, 1); - let b: u64x2 = u64x2::new(2, 2); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vextq_u64::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vext_f32() { - let a: f32x2 = f32x2::new(1., 1.); - let b: f32x2 = f32x2::new(2., 2.); - let e: f32x2 = f32x2::new(1., 2.); - let r: f32x2 = transmute(vext_f32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vextq_f32() { - let a: f32x4 = f32x4::new(1., 1., 1., 1.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let e: f32x4 = f32x4::new(1., 2., 2., 2.); - let r: f32x4 = transmute(vextq_f32::<3>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x8 = i8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i8x8 = i8x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i8x8 = transmute(vmla_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x16 = i8x16::new(3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3); - let e: i8x16 = i8x16::new(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21); - let r: i8x16 = transmute(vmlaq_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(3, 3, 3, 3); - let e: i16x4 = i16x4::new(6, 7, 8, 9); - let r: i16x4 = transmute(vmla_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vmlaq_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(3, 3); - let e: i32x2 = i32x2::new(6, 7); - let r: i32x2 = transmute(vmla_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(3, 3, 3, 3); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlaq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x8 = u8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u8x8 = u8x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u8x8 = transmute(vmla_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x16 = u8x16::new(3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3); - let e: u8x16 = u8x16::new(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21); - let r: u8x16 = transmute(vmlaq_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(3, 3, 3, 3); - let e: u16x4 = u16x4::new(6, 7, 8, 9); - let r: u16x4 = transmute(vmla_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vmlaq_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(3, 3); - let e: u32x2 = u32x2::new(6, 7); - let r: u32x2 = transmute(vmla_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(3, 3, 3, 3); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlaq_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_f32() { - let a: f32x2 = f32x2::new(0., 1.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x2 = f32x2::new(3., 3.); - let e: f32x2 = f32x2::new(6., 7.); - let r: f32x2 = transmute(vmla_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_f32() { - let a: f32x4 = f32x4::new(0., 1., 2., 3.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x4 = f32x4::new(3., 3., 3., 3.); - let e: f32x4 = f32x4::new(6., 7., 8., 9.); - let r: f32x4 = transmute(vmlaq_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_n_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16 = 3; - let e: i16x4 = i16x4::new(6, 7, 8, 9); - let r: i16x4 = transmute(vmla_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_n_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16 = 3; - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vmlaq_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_n_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32 = 3; - let e: i32x2 = i32x2::new(6, 7); - let r: i32x2 = transmute(vmla_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_n_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32 = 3; - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlaq_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_n_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16 = 3; - let e: u16x4 = u16x4::new(6, 7, 8, 9); - let r: u16x4 = transmute(vmla_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_n_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16 = 3; - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vmlaq_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_n_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32 = 3; - let e: u32x2 = u32x2::new(6, 7); - let r: u32x2 = transmute(vmla_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_n_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32 = 3; - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlaq_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_n_f32() { - let a: f32x2 = f32x2::new(0., 1.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32 = 3.; - let e: f32x2 = f32x2::new(6., 7.); - let r: f32x2 = transmute(vmla_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_n_f32() { - let a: f32x4 = f32x4::new(0., 1., 2., 3.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32 = 3.; - let e: f32x4 = f32x4::new(6., 7., 8., 9.); - let r: f32x4 = transmute(vmlaq_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_lane_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i16x4 = i16x4::new(6, 7, 8, 9); - let r: i16x4 = transmute(vmla_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_laneq_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(6, 7, 8, 9); - let r: i16x4 = transmute(vmla_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_lane_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vmlaq_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_laneq_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vmlaq_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_lane_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i32x2 = i32x2::new(6, 7); - let r: i32x2 = transmute(vmla_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_laneq_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i32x2 = i32x2::new(6, 7); - let r: i32x2 = transmute(vmla_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_lane_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlaq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_laneq_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlaq_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_lane_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u16x4 = u16x4::new(6, 7, 8, 9); - let r: u16x4 = transmute(vmla_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_laneq_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u16x4 = u16x4::new(6, 7, 8, 9); - let r: u16x4 = transmute(vmla_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_lane_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vmlaq_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_laneq_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vmlaq_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_lane_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u32x2 = u32x2::new(6, 7); - let r: u32x2 = transmute(vmla_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_laneq_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u32x2 = u32x2::new(6, 7); - let r: u32x2 = transmute(vmla_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_lane_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlaq_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_laneq_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlaq_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_lane_f32() { - let a: f32x2 = f32x2::new(0., 1.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x2 = f32x2::new(0., 3.); - let e: f32x2 = f32x2::new(6., 7.); - let r: f32x2 = transmute(vmla_lane_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmla_laneq_f32() { - let a: f32x2 = f32x2::new(0., 1.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x4 = f32x4::new(0., 3., 0., 0.); - let e: f32x2 = f32x2::new(6., 7.); - let r: f32x2 = transmute(vmla_laneq_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_lane_f32() { - let a: f32x4 = f32x4::new(0., 1., 2., 3.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x2 = f32x2::new(0., 3.); - let e: f32x4 = f32x4::new(6., 7., 8., 9.); - let r: f32x4 = transmute(vmlaq_lane_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlaq_laneq_f32() { - let a: f32x4 = f32x4::new(0., 1., 2., 3.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x4 = f32x4::new(0., 3., 0., 0.); - let e: f32x4 = f32x4::new(6., 7., 8., 9.); - let r: f32x4 = transmute(vmlaq_laneq_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_s8() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x8 = i8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: i16x8 = transmute(vmlal_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_s16() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(3, 3, 3, 3); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlal_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_s32() { - let a: i64x2 = i64x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(3, 3); - let e: i64x2 = i64x2::new(6, 7); - let r: i64x2 = transmute(vmlal_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_u8() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x8 = u8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let r: u16x8 = transmute(vmlal_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_u16() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(3, 3, 3, 3); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlal_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_u32() { - let a: u64x2 = u64x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(3, 3); - let e: u64x2 = u64x2::new(6, 7); - let r: u64x2 = transmute(vmlal_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_n_s16() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16 = 3; - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlal_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_n_s32() { - let a: i64x2 = i64x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32 = 3; - let e: i64x2 = i64x2::new(6, 7); - let r: i64x2 = transmute(vmlal_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_n_u16() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16 = 3; - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlal_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_n_u32() { - let a: u64x2 = u64x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32 = 3; - let e: u64x2 = u64x2::new(6, 7); - let r: u64x2 = transmute(vmlal_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_lane_s16() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlal_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_laneq_s16() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(6, 7, 8, 9); - let r: i32x4 = transmute(vmlal_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_lane_s32() { - let a: i64x2 = i64x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i64x2 = i64x2::new(6, 7); - let r: i64x2 = transmute(vmlal_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_laneq_s32() { - let a: i64x2 = i64x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i64x2 = i64x2::new(6, 7); - let r: i64x2 = transmute(vmlal_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_lane_u16() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlal_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_laneq_u16() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(6, 7, 8, 9); - let r: u32x4 = transmute(vmlal_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_lane_u32() { - let a: u64x2 = u64x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u64x2 = u64x2::new(6, 7); - let r: u64x2 = transmute(vmlal_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlal_laneq_u32() { - let a: u64x2 = u64x2::new(0, 1); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u64x2 = u64x2::new(6, 7); - let r: u64x2 = transmute(vmlal_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_s8() { - let a: i8x8 = i8x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x8 = i8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vmls_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_s8() { - let a: i8x16 = i8x16::new(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x16 = i8x16::new(3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vmlsq_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_s16() { - let a: i16x4 = i16x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(3, 3, 3, 3); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vmls_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_s16() { - let a: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vmlsq_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_s32() { - let a: i32x2 = i32x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(3, 3); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vmls_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_s32() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(3, 3, 3, 3); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_u8() { - let a: u8x8 = u8x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x8 = u8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vmls_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_u8() { - let a: u8x16 = u8x16::new(6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21); - let b: u8x16 = u8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x16 = u8x16::new(3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vmlsq_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_u16() { - let a: u16x4 = u16x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(3, 3, 3, 3); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vmls_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_u16() { - let a: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vmlsq_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_u32() { - let a: u32x2 = u32x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(3, 3); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vmls_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_u32() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(3, 3, 3, 3); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsq_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_f32() { - let a: f32x2 = f32x2::new(6., 7.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x2 = f32x2::new(3., 3.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vmls_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_f32() { - let a: f32x4 = f32x4::new(6., 7., 8., 9.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x4 = f32x4::new(3., 3., 3., 3.); - let e: f32x4 = f32x4::new(0., 1., 2., 3.); - let r: f32x4 = transmute(vmlsq_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_n_s16() { - let a: i16x4 = i16x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16 = 3; - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vmls_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_n_s16() { - let a: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16 = 3; - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vmlsq_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_n_s32() { - let a: i32x2 = i32x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32 = 3; - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vmls_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_n_s32() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32 = 3; - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsq_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_n_u16() { - let a: u16x4 = u16x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16 = 3; - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vmls_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_n_u16() { - let a: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16 = 3; - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vmlsq_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_n_u32() { - let a: u32x2 = u32x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32 = 3; - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vmls_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_n_u32() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32 = 3; - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsq_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_n_f32() { - let a: f32x2 = f32x2::new(6., 7.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32 = 3.; - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vmls_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_n_f32() { - let a: f32x4 = f32x4::new(6., 7., 8., 9.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32 = 3.; - let e: f32x4 = f32x4::new(0., 1., 2., 3.); - let r: f32x4 = transmute(vmlsq_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_lane_s16() { - let a: i16x4 = i16x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vmls_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_laneq_s16() { - let a: i16x4 = i16x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vmls_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_lane_s16() { - let a: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vmlsq_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_laneq_s16() { - let a: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vmlsq_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_lane_s32() { - let a: i32x2 = i32x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vmls_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_laneq_s32() { - let a: i32x2 = i32x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vmls_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_lane_s32() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_laneq_s32() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsq_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_lane_u16() { - let a: u16x4 = u16x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vmls_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_laneq_u16() { - let a: u16x4 = u16x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vmls_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_lane_u16() { - let a: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vmlsq_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_laneq_u16() { - let a: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u16x8 = u16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vmlsq_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_lane_u32() { - let a: u32x2 = u32x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vmls_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_laneq_u32() { - let a: u32x2 = u32x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vmls_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_lane_u32() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsq_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_laneq_u32() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u32x4 = u32x4::new(2, 2, 2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsq_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_lane_f32() { - let a: f32x2 = f32x2::new(6., 7.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x2 = f32x2::new(0., 3.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vmls_lane_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmls_laneq_f32() { - let a: f32x2 = f32x2::new(6., 7.); - let b: f32x2 = f32x2::new(2., 2.); - let c: f32x4 = f32x4::new(0., 3., 0., 0.); - let e: f32x2 = f32x2::new(0., 1.); - let r: f32x2 = transmute(vmls_laneq_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_lane_f32() { - let a: f32x4 = f32x4::new(6., 7., 8., 9.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x2 = f32x2::new(0., 3.); - let e: f32x4 = f32x4::new(0., 1., 2., 3.); - let r: f32x4 = transmute(vmlsq_lane_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsq_laneq_f32() { - let a: f32x4 = f32x4::new(6., 7., 8., 9.); - let b: f32x4 = f32x4::new(2., 2., 2., 2.); - let c: f32x4 = f32x4::new(0., 3., 0., 0.); - let e: f32x4 = f32x4::new(0., 1., 2., 3.); - let r: f32x4 = transmute(vmlsq_laneq_f32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_s8() { - let a: i16x8 = i16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: i8x8 = i8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vmlsl_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_s16() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(3, 3, 3, 3); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsl_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_s32() { - let a: i64x2 = i64x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(3, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vmlsl_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_u8() { - let a: u16x8 = u16x8::new(6, 7, 8, 9, 10, 11, 12, 13); - let b: u8x8 = u8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let c: u8x8 = u8x8::new(3, 3, 3, 3, 3, 3, 3, 3); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vmlsl_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_u16() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(3, 3, 3, 3); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsl_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_u32() { - let a: u64x2 = u64x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(3, 3); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vmlsl_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_n_s16() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16 = 3; - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsl_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_n_s32() { - let a: i64x2 = i64x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32 = 3; - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vmlsl_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_n_u16() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16 = 3; - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsl_n_u16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_n_u32() { - let a: u64x2 = u64x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32 = 3; - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vmlsl_n_u32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_lane_s16() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x4 = i16x4::new(0, 3, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsl_lane_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_laneq_s16() { - let a: i32x4 = i32x4::new(6, 7, 8, 9); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let c: i16x8 = i16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vmlsl_laneq_s16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_lane_s32() { - let a: i64x2 = i64x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x2 = i32x2::new(0, 3); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vmlsl_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_laneq_s32() { - let a: i64x2 = i64x2::new(6, 7); - let b: i32x2 = i32x2::new(2, 2); - let c: i32x4 = i32x4::new(0, 3, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vmlsl_laneq_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_lane_u16() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x4 = u16x4::new(0, 3, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsl_lane_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_laneq_u16() { - let a: u32x4 = u32x4::new(6, 7, 8, 9); - let b: u16x4 = u16x4::new(2, 2, 2, 2); - let c: u16x8 = u16x8::new(0, 3, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vmlsl_laneq_u16::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_lane_u32() { - let a: u64x2 = u64x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x2 = u32x2::new(0, 3); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vmlsl_lane_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmlsl_laneq_u32() { - let a: u64x2 = u64x2::new(6, 7); - let b: u32x2 = u32x2::new(2, 2); - let c: u32x4 = u32x4::new(0, 3, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vmlsl_laneq_u32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_s8() { - let a: i8x8 = i8x8::new(0, 1, -1, 2, -2, 3, -3, 4); - let e: i8x8 = i8x8::new(0, -1, 1, -2, 2, -3, 3, -4); - let r: i8x8 = transmute(vneg_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_s8() { - let a: i8x16 = i8x16::new(0, 1, -1, 2, -2, 3, -3, 4, -4, 5, -5, 6, -6, 7, -7, 8); - let e: i8x16 = i8x16::new(0, -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, -8); - let r: i8x16 = transmute(vnegq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_s16() { - let a: i16x4 = i16x4::new(0, 1, -1, 2); - let e: i16x4 = i16x4::new(0, -1, 1, -2); - let r: i16x4 = transmute(vneg_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_s16() { - let a: i16x8 = i16x8::new(0, 1, -1, 2, -2, 3, -3, 4); - let e: i16x8 = i16x8::new(0, -1, 1, -2, 2, -3, 3, -4); - let r: i16x8 = transmute(vnegq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i32x2 = i32x2::new(0, -1); - let r: i32x2 = transmute(vneg_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_s32() { - let a: i32x4 = i32x4::new(0, 1, -1, 2); - let e: i32x4 = i32x4::new(0, -1, 1, -2); - let r: i32x4 = transmute(vnegq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vneg_f32() { - let a: f32x2 = f32x2::new(0., 1.); - let e: f32x2 = f32x2::new(0., -1.); - let r: f32x2 = transmute(vneg_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vnegq_f32() { - let a: f32x4 = f32x4::new(0., 1., -1., 2.); - let e: f32x4 = f32x4::new(0., -1., 1., -2.); - let r: f32x4 = transmute(vnegq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqneg_s8() { - let a: i8x8 = i8x8::new(-128, 0, 1, -1, 2, -2, 3, -3); - let e: i8x8 = i8x8::new(0x7F, 0, -1, 1, -2, 2, -3, 3); - let r: i8x8 = transmute(vqneg_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegq_s8() { - let a: i8x16 = i8x16::new(-128, 0, 1, -1, 2, -2, 3, -3, 4, -4, 5, -5, 6, -6, 7, -7); - let e: i8x16 = i8x16::new(0x7F, 0, -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7); - let r: i8x16 = transmute(vqnegq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqneg_s16() { - let a: i16x4 = i16x4::new(-32768, 0, 1, -1); - let e: i16x4 = i16x4::new(0x7F_FF, 0, -1, 1); - let r: i16x4 = transmute(vqneg_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegq_s16() { - let a: i16x8 = i16x8::new(-32768, 0, 1, -1, 2, -2, 3, -3); - let e: i16x8 = i16x8::new(0x7F_FF, 0, -1, 1, -2, 2, -3, 3); - let r: i16x8 = transmute(vqnegq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqneg_s32() { - let a: i32x2 = i32x2::new(-2147483648, 0); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0); - let r: i32x2 = transmute(vqneg_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqnegq_s32() { - let a: i32x4 = i32x4::new(-2147483648, 0, 1, -1); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0, -1, 1); - let r: i32x4 = transmute(vqnegq_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_u8() { - let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(41, 40, 39, 38, 37, 36, 35, 34); - let r: u8x8 = transmute(vqsub_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_u8() { - let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26); - let r: u8x16 = transmute(vqsubq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_u16() { - let a: u16x4 = u16x4::new(42, 42, 42, 42); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(41, 40, 39, 38); - let r: u16x4 = transmute(vqsub_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_u16() { - let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(41, 40, 39, 38, 37, 36, 35, 34); - let r: u16x8 = transmute(vqsubq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_u32() { - let a: u32x2 = u32x2::new(42, 42); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(41, 40); - let r: u32x2 = transmute(vqsub_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_u32() { - let a: u32x4 = u32x4::new(42, 42, 42, 42); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(41, 40, 39, 38); - let r: u32x4 = transmute(vqsubq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_u64() { - let a: u64x1 = u64x1::new(42); - let b: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(41); - let r: u64x1 = transmute(vqsub_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_u64() { - let a: u64x2 = u64x2::new(42, 42); - let b: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(41, 40); - let r: u64x2 = transmute(vqsubq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_s8() { - let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(41, 40, 39, 38, 37, 36, 35, 34); - let r: i8x8 = transmute(vqsub_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_s8() { - let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26); - let r: i8x16 = transmute(vqsubq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_s16() { - let a: i16x4 = i16x4::new(42, 42, 42, 42); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(41, 40, 39, 38); - let r: i16x4 = transmute(vqsub_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_s16() { - let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(41, 40, 39, 38, 37, 36, 35, 34); - let r: i16x8 = transmute(vqsubq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_s32() { - let a: i32x2 = i32x2::new(42, 42); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(41, 40); - let r: i32x2 = transmute(vqsub_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_s32() { - let a: i32x4 = i32x4::new(42, 42, 42, 42); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(41, 40, 39, 38); - let r: i32x4 = transmute(vqsubq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsub_s64() { - let a: i64x1 = i64x1::new(42); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(41); - let r: i64x1 = transmute(vqsub_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqsubq_s64() { - let a: i64x2 = i64x2::new(42, 42); - let b: i64x2 = i64x2::new(1, 2); - let e: i64x2 = i64x2::new(41, 40); - let r: i64x2 = transmute(vqsubq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_u8() { - let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(21, 22, 22, 23, 23, 24, 24, 25); - let r: u8x8 = transmute(vhadd_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_u8() { - let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29); - let r: u8x16 = transmute(vhaddq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_u16() { - let a: u16x4 = u16x4::new(42, 42, 42, 42); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(21, 22, 22, 23); - let r: u16x4 = transmute(vhadd_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_u16() { - let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(21, 22, 22, 23, 23, 24, 24, 25); - let r: u16x8 = transmute(vhaddq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_u32() { - let a: u32x2 = u32x2::new(42, 42); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(21, 22); - let r: u32x2 = transmute(vhadd_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_u32() { - let a: u32x4 = u32x4::new(42, 42, 42, 42); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(21, 22, 22, 23); - let r: u32x4 = transmute(vhaddq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_s8() { - let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(21, 22, 22, 23, 23, 24, 24, 25); - let r: i8x8 = transmute(vhadd_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_s8() { - let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29); - let r: i8x16 = transmute(vhaddq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_s16() { - let a: i16x4 = i16x4::new(42, 42, 42, 42); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(21, 22, 22, 23); - let r: i16x4 = transmute(vhadd_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_s16() { - let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(21, 22, 22, 23, 23, 24, 24, 25); - let r: i16x8 = transmute(vhaddq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhadd_s32() { - let a: i32x2 = i32x2::new(42, 42); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(21, 22); - let r: i32x2 = transmute(vhadd_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhaddq_s32() { - let a: i32x4 = i32x4::new(42, 42, 42, 42); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(21, 22, 22, 23); - let r: i32x4 = transmute(vhaddq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_u8() { - let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(22, 22, 23, 23, 24, 24, 25, 25); - let r: u8x8 = transmute(vrhadd_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_u8() { - let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29); - let r: u8x16 = transmute(vrhaddq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_u16() { - let a: u16x4 = u16x4::new(42, 42, 42, 42); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(22, 22, 23, 23); - let r: u16x4 = transmute(vrhadd_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_u16() { - let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(22, 22, 23, 23, 24, 24, 25, 25); - let r: u16x8 = transmute(vrhaddq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_u32() { - let a: u32x2 = u32x2::new(42, 42); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(22, 22); - let r: u32x2 = transmute(vrhadd_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_u32() { - let a: u32x4 = u32x4::new(42, 42, 42, 42); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(22, 22, 23, 23); - let r: u32x4 = transmute(vrhaddq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_s8() { - let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(22, 22, 23, 23, 24, 24, 25, 25); - let r: i8x8 = transmute(vrhadd_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_s8() { - let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29); - let r: i8x16 = transmute(vrhaddq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_s16() { - let a: i16x4 = i16x4::new(42, 42, 42, 42); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(22, 22, 23, 23); - let r: i16x4 = transmute(vrhadd_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_s16() { - let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(22, 22, 23, 23, 24, 24, 25, 25); - let r: i16x8 = transmute(vrhaddq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhadd_s32() { - let a: i32x2 = i32x2::new(42, 42); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(22, 22); - let r: i32x2 = transmute(vrhadd_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrhaddq_s32() { - let a: i32x4 = i32x4::new(42, 42, 42, 42); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(22, 22, 23, 23); - let r: i32x4 = transmute(vrhaddq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vrndn_f32() { - let a: f32x2 = f32x2::new(-1.5, 0.5); - let e: f32x2 = f32x2::new(-2.0, 0.0); - let r: f32x2 = transmute(vrndn_f32(transmute(a))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vrndnq_f32() { - let a: f32x4 = f32x4::new(-1.5, 0.5, 1.5, 2.5); - let e: f32x4 = f32x4::new(-2.0, 0.0, 2.0, 2.0); - let r: f32x4 = transmute(vrndnq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_u8() { - let a: u8x8 = u8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(43, 44, 45, 46, 47, 48, 49, 50); - let r: u8x8 = transmute(vqadd_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_u8() { - let a: u8x16 = u8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58); - let r: u8x16 = transmute(vqaddq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_u16() { - let a: u16x4 = u16x4::new(42, 42, 42, 42); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(43, 44, 45, 46); - let r: u16x4 = transmute(vqadd_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_u16() { - let a: u16x8 = u16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(43, 44, 45, 46, 47, 48, 49, 50); - let r: u16x8 = transmute(vqaddq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_u32() { - let a: u32x2 = u32x2::new(42, 42); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(43, 44); - let r: u32x2 = transmute(vqadd_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_u32() { - let a: u32x4 = u32x4::new(42, 42, 42, 42); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(43, 44, 45, 46); - let r: u32x4 = transmute(vqaddq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_u64() { - let a: u64x1 = u64x1::new(42); - let b: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(43); - let r: u64x1 = transmute(vqadd_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_u64() { - let a: u64x2 = u64x2::new(42, 42); - let b: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(43, 44); - let r: u64x2 = transmute(vqaddq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_s8() { - let a: i8x8 = i8x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(43, 44, 45, 46, 47, 48, 49, 50); - let r: i8x8 = transmute(vqadd_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_s8() { - let a: i8x16 = i8x16::new(42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58); - let r: i8x16 = transmute(vqaddq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_s16() { - let a: i16x4 = i16x4::new(42, 42, 42, 42); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(43, 44, 45, 46); - let r: i16x4 = transmute(vqadd_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_s16() { - let a: i16x8 = i16x8::new(42, 42, 42, 42, 42, 42, 42, 42); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(43, 44, 45, 46, 47, 48, 49, 50); - let r: i16x8 = transmute(vqaddq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_s32() { - let a: i32x2 = i32x2::new(42, 42); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(43, 44); - let r: i32x2 = transmute(vqadd_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_s32() { - let a: i32x4 = i32x4::new(42, 42, 42, 42); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(43, 44, 45, 46); - let r: i32x4 = transmute(vqaddq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqadd_s64() { - let a: i64x1 = i64x1::new(42); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(43); - let r: i64x1 = transmute(vqadd_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqaddq_s64() { - let a: i64x2 = i64x2::new(42, 42); - let b: i64x2 = i64x2::new(1, 2); - let e: i64x2 = i64x2::new(43, 44); - let r: i64x2 = transmute(vqaddq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s8_x2() { - let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i8x8; 2] = transmute(vld1_s8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s16_x2() { - let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8)]; - let r: [i16x4; 2] = transmute(vld1_s16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s32_x2() { - let a: [i32; 5] = [0, 1, 2, 3, 4]; - let e: [i32x2; 2] = [i32x2::new(1, 2), i32x2::new(3, 4)]; - let r: [i32x2; 2] = transmute(vld1_s32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s64_x2() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld1_s64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s8_x2() { - let a: [i8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x16; 2] = transmute(vld1q_s8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s16_x2() { - let a: [i16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i16x8; 2] = transmute(vld1q_s16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s32_x2() { - let a: [i32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i32x4; 2] = [i32x4::new(1, 2, 3, 4), i32x4::new(5, 6, 7, 8)]; - let r: [i32x4; 2] = transmute(vld1q_s32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s64_x2() { - let a: [i64; 5] = [0, 1, 2, 3, 4]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(3, 4)]; - let r: [i64x2; 2] = transmute(vld1q_s64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s8_x3() { - let a: [i8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16), i8x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [i8x8; 3] = transmute(vld1_s8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s16_x3() { - let a: [i16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8), i16x4::new(9, 10, 11, 12)]; - let r: [i16x4; 3] = transmute(vld1_s16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s32_x3() { - let a: [i32; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [i32x2; 3] = [i32x2::new(1, 2), i32x2::new(3, 4), i32x2::new(5, 6)]; - let r: [i32x2; 3] = transmute(vld1_s32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s64_x3() { - let a: [i64; 4] = [0, 1, 2, 3]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(3)]; - let r: [i64x1; 3] = transmute(vld1_s64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s8_x3() { - let a: [i8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i8x16; 3] = transmute(vld1q_s8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s16_x3() { - let a: [i16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16), i16x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [i16x8; 3] = transmute(vld1q_s16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s32_x3() { - let a: [i32; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [i32x4; 3] = [i32x4::new(1, 2, 3, 4), i32x4::new(5, 6, 7, 8), i32x4::new(9, 10, 11, 12)]; - let r: [i32x4; 3] = transmute(vld1q_s32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s64_x3() { - let a: [i64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(3, 4), i64x2::new(5, 6)]; - let r: [i64x2; 3] = transmute(vld1q_s64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s8_x4() { - let a: [i8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16), i8x8::new(17, 18, 19, 20, 21, 22, 23, 24), i8x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x8; 4] = transmute(vld1_s8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s16_x4() { - let a: [i16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8), i16x4::new(9, 10, 11, 12), i16x4::new(13, 14, 15, 16)]; - let r: [i16x4; 4] = transmute(vld1_s16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s32_x4() { - let a: [i32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i32x2; 4] = [i32x2::new(1, 2), i32x2::new(3, 4), i32x2::new(5, 6), i32x2::new(7, 8)]; - let r: [i32x2; 4] = transmute(vld1_s32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_s64_x4() { - let a: [i64; 5] = [0, 1, 2, 3, 4]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(3), i64x1::new(4)]; - let r: [i64x1; 4] = transmute(vld1_s64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s8_x4() { - let a: [i8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x16; 4] = transmute(vld1q_s8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s16_x4() { - let a: [i16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16), i16x8::new(17, 18, 19, 20, 21, 22, 23, 24), i16x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i16x8; 4] = transmute(vld1q_s16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s32_x4() { - let a: [i32; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i32x4; 4] = [i32x4::new(1, 2, 3, 4), i32x4::new(5, 6, 7, 8), i32x4::new(9, 10, 11, 12), i32x4::new(13, 14, 15, 16)]; - let r: [i32x4; 4] = transmute(vld1q_s32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_s64_x4() { - let a: [i64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(3, 4), i64x2::new(5, 6), i64x2::new(7, 8)]; - let r: [i64x2; 4] = transmute(vld1q_s64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u8_x2() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8x8; 2] = [u8x8::new(1, 2, 3, 4, 5, 6, 7, 8), u8x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [u8x8; 2] = transmute(vld1_u8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u16_x2() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u16x4; 2] = [u16x4::new(1, 2, 3, 4), u16x4::new(5, 6, 7, 8)]; - let r: [u16x4; 2] = transmute(vld1_u16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u32_x2() { - let a: [u32; 5] = [0, 1, 2, 3, 4]; - let e: [u32x2; 2] = [u32x2::new(1, 2), u32x2::new(3, 4)]; - let r: [u32x2; 2] = transmute(vld1_u32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u64_x2() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64x1; 2] = [u64x1::new(1), u64x1::new(2)]; - let r: [u64x1; 2] = transmute(vld1_u64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u8_x2() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8x16; 2] = [u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), u8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [u8x16; 2] = transmute(vld1q_u8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u16_x2() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16x8; 2] = [u16x8::new(1, 2, 3, 4, 5, 6, 7, 8), u16x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [u16x8; 2] = transmute(vld1q_u16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u32_x2() { - let a: [u32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u32x4; 2] = [u32x4::new(1, 2, 3, 4), u32x4::new(5, 6, 7, 8)]; - let r: [u32x4; 2] = transmute(vld1q_u32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u64_x2() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64x2; 2] = [u64x2::new(1, 2), u64x2::new(3, 4)]; - let r: [u64x2; 2] = transmute(vld1q_u64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u8_x3() { - let a: [u8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u8x8; 3] = [u8x8::new(1, 2, 3, 4, 5, 6, 7, 8), u8x8::new(9, 10, 11, 12, 13, 14, 15, 16), u8x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [u8x8; 3] = transmute(vld1_u8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u16_x3() { - let a: [u16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [u16x4; 3] = [u16x4::new(1, 2, 3, 4), u16x4::new(5, 6, 7, 8), u16x4::new(9, 10, 11, 12)]; - let r: [u16x4; 3] = transmute(vld1_u16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u32_x3() { - let a: [u32; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [u32x2; 3] = [u32x2::new(1, 2), u32x2::new(3, 4), u32x2::new(5, 6)]; - let r: [u32x2; 3] = transmute(vld1_u32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u64_x3() { - let a: [u64; 4] = [0, 1, 2, 3]; - let e: [u64x1; 3] = [u64x1::new(1), u64x1::new(2), u64x1::new(3)]; - let r: [u64x1; 3] = transmute(vld1_u64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u8_x3() { - let a: [u8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8x16; 3] = [u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), u8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [u8x16; 3] = transmute(vld1q_u8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u16_x3() { - let a: [u16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u16x8; 3] = [u16x8::new(1, 2, 3, 4, 5, 6, 7, 8), u16x8::new(9, 10, 11, 12, 13, 14, 15, 16), u16x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [u16x8; 3] = transmute(vld1q_u16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u32_x3() { - let a: [u32; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [u32x4; 3] = [u32x4::new(1, 2, 3, 4), u32x4::new(5, 6, 7, 8), u32x4::new(9, 10, 11, 12)]; - let r: [u32x4; 3] = transmute(vld1q_u32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u64_x3() { - let a: [u64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [u64x2; 3] = [u64x2::new(1, 2), u64x2::new(3, 4), u64x2::new(5, 6)]; - let r: [u64x2; 3] = transmute(vld1q_u64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u8_x4() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8x8; 4] = [u8x8::new(1, 2, 3, 4, 5, 6, 7, 8), u8x8::new(9, 10, 11, 12, 13, 14, 15, 16), u8x8::new(17, 18, 19, 20, 21, 22, 23, 24), u8x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [u8x8; 4] = transmute(vld1_u8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u16_x4() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16x4; 4] = [u16x4::new(1, 2, 3, 4), u16x4::new(5, 6, 7, 8), u16x4::new(9, 10, 11, 12), u16x4::new(13, 14, 15, 16)]; - let r: [u16x4; 4] = transmute(vld1_u16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u32_x4() { - let a: [u32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u32x2; 4] = [u32x2::new(1, 2), u32x2::new(3, 4), u32x2::new(5, 6), u32x2::new(7, 8)]; - let r: [u32x2; 4] = transmute(vld1_u32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_u64_x4() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64x1; 4] = [u64x1::new(1), u64x1::new(2), u64x1::new(3), u64x1::new(4)]; - let r: [u64x1; 4] = transmute(vld1_u64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u8_x4() { - let a: [u8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8x16; 4] = [u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), u8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), u8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [u8x16; 4] = transmute(vld1q_u8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u16_x4() { - let a: [u16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u16x8; 4] = [u16x8::new(1, 2, 3, 4, 5, 6, 7, 8), u16x8::new(9, 10, 11, 12, 13, 14, 15, 16), u16x8::new(17, 18, 19, 20, 21, 22, 23, 24), u16x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [u16x8; 4] = transmute(vld1q_u16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u32_x4() { - let a: [u32; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u32x4; 4] = [u32x4::new(1, 2, 3, 4), u32x4::new(5, 6, 7, 8), u32x4::new(9, 10, 11, 12), u32x4::new(13, 14, 15, 16)]; - let r: [u32x4; 4] = transmute(vld1q_u32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_u64_x4() { - let a: [u64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u64x2; 4] = [u64x2::new(1, 2), u64x2::new(3, 4), u64x2::new(5, 6), u64x2::new(7, 8)]; - let r: [u64x2; 4] = transmute(vld1q_u64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p8_x2() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i8x8; 2] = transmute(vld1_p8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p8_x3() { - let a: [u8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16), i8x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [i8x8; 3] = transmute(vld1_p8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p8_x4() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 3, 4, 5, 6, 7, 8), i8x8::new(9, 10, 11, 12, 13, 14, 15, 16), i8x8::new(17, 18, 19, 20, 21, 22, 23, 24), i8x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x8; 4] = transmute(vld1_p8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p8_x2() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x16; 2] = transmute(vld1q_p8_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p8_x3() { - let a: [u8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i8x16; 3] = transmute(vld1q_p8_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p8_x4() { - let a: [u8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16), i8x16::new(17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i8x16; 4] = transmute(vld1q_p8_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p16_x2() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8)]; - let r: [i16x4; 2] = transmute(vld1_p16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p16_x3() { - let a: [u16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8), i16x4::new(9, 10, 11, 12)]; - let r: [i16x4; 3] = transmute(vld1_p16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p16_x4() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 3, 4), i16x4::new(5, 6, 7, 8), i16x4::new(9, 10, 11, 12), i16x4::new(13, 14, 15, 16)]; - let r: [i16x4; 4] = transmute(vld1_p16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p16_x2() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16)]; - let r: [i16x8; 2] = transmute(vld1q_p16_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p16_x3() { - let a: [u16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16), i16x8::new(17, 18, 19, 20, 21, 22, 23, 24)]; - let r: [i16x8; 3] = transmute(vld1q_p16_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p16_x4() { - let a: [u16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 3, 4, 5, 6, 7, 8), i16x8::new(9, 10, 11, 12, 13, 14, 15, 16), i16x8::new(17, 18, 19, 20, 21, 22, 23, 24), i16x8::new(25, 26, 27, 28, 29, 30, 31, 32)]; - let r: [i16x8; 4] = transmute(vld1q_p16_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p64_x2() { - let a: [u64; 3] = [0, 1, 2]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld1_p64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p64_x3() { - let a: [u64; 4] = [0, 1, 2, 3]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(3)]; - let r: [i64x1; 3] = transmute(vld1_p64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_p64_x4() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(3), i64x1::new(4)]; - let r: [i64x1; 4] = transmute(vld1_p64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p64_x2() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [i64x2; 2] = [i64x2::new(1, 2), i64x2::new(3, 4)]; - let r: [i64x2; 2] = transmute(vld1q_p64_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p64_x3() { - let a: [u64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [i64x2; 3] = [i64x2::new(1, 2), i64x2::new(3, 4), i64x2::new(5, 6)]; - let r: [i64x2; 3] = transmute(vld1q_p64_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_p64_x4() { - let a: [u64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i64x2; 4] = [i64x2::new(1, 2), i64x2::new(3, 4), i64x2::new(5, 6), i64x2::new(7, 8)]; - let r: [i64x2; 4] = transmute(vld1q_p64_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f32_x2() { - let a: [f32; 5] = [0., 1., 2., 3., 4.]; - let e: [f32x2; 2] = [f32x2::new(1., 2.), f32x2::new(3., 4.)]; - let r: [f32x2; 2] = transmute(vld1_f32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f32_x2() { - let a: [f32; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f32x4; 2] = [f32x4::new(1., 2., 3., 4.), f32x4::new(5., 6., 7., 8.)]; - let r: [f32x4; 2] = transmute(vld1q_f32_x2(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f32_x3() { - let a: [f32; 7] = [0., 1., 2., 3., 4., 5., 6.]; - let e: [f32x2; 3] = [f32x2::new(1., 2.), f32x2::new(3., 4.), f32x2::new(5., 6.)]; - let r: [f32x2; 3] = transmute(vld1_f32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f32_x3() { - let a: [f32; 13] = [0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12.]; - let e: [f32x4; 3] = [f32x4::new(1., 2., 3., 4.), f32x4::new(5., 6., 7., 8.), f32x4::new(9., 10., 11., 12.)]; - let r: [f32x4; 3] = transmute(vld1q_f32_x3(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1_f32_x4() { - let a: [f32; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f32x2; 4] = [f32x2::new(1., 2.), f32x2::new(3., 4.), f32x2::new(5., 6.), f32x2::new(7., 8.)]; - let r: [f32x2; 4] = transmute(vld1_f32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld1q_f32_x4() { - let a: [f32; 17] = [0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.]; - let e: [f32x4; 4] = [f32x4::new(1., 2., 3., 4.), f32x4::new(5., 6., 7., 8.), f32x4::new(9., 10., 11., 12.), f32x4::new(13., 14., 15., 16.)]; - let r: [f32x4; 4] = transmute(vld1q_f32_x4(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_s8() { - let a: [i8; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 2, 3, 2, 3, 4, 5), i8x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [i8x8; 2] = transmute(vld2_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_s16() { - let a: [i16; 9] = [0, 1, 2, 2, 3, 2, 4, 3, 5]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 2, 3), i16x4::new(2, 3, 4, 5)]; - let r: [i16x4; 2] = transmute(vld2_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_s32() { - let a: [i32; 5] = [0, 1, 2, 2, 3]; - let e: [i32x2; 2] = [i32x2::new(1, 2), i32x2::new(2, 3)]; - let r: [i32x2; 2] = transmute(vld2_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9), i8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)]; - let r: [i8x16; 2] = transmute(vld2q_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 2, 3, 2, 3, 4, 5), i16x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [i16x8; 2] = transmute(vld2q_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 3, 2, 4, 3, 5]; - let e: [i32x4; 2] = [i32x4::new(1, 2, 2, 3), i32x4::new(2, 3, 4, 5)]; - let r: [i32x4; 2] = transmute(vld2q_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_s64() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld2_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_u8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [u8x8; 2] = [u8x8::new(1, 2, 2, 3, 2, 3, 4, 5), u8x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [u8x8; 2] = transmute(vld2_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_u16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 4, 3, 5]; - let e: [u16x4; 2] = [u16x4::new(1, 2, 2, 3), u16x4::new(2, 3, 4, 5)]; - let r: [u16x4; 2] = transmute(vld2_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_u32() { - let a: [u32; 5] = [0, 1, 2, 2, 3]; - let e: [u32x2; 2] = [u32x2::new(1, 2), u32x2::new(2, 3)]; - let r: [u32x2; 2] = transmute(vld2_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [u8x16; 2] = [u8x16::new(1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9), u8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)]; - let r: [u8x16; 2] = transmute(vld2q_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [u16x8; 2] = [u16x8::new(1, 2, 2, 3, 2, 3, 4, 5), u16x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [u16x8; 2] = transmute(vld2q_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 3, 2, 4, 3, 5]; - let e: [u32x4; 2] = [u32x4::new(1, 2, 2, 3), u32x4::new(2, 3, 4, 5)]; - let r: [u32x4; 2] = transmute(vld2q_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_p8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 2, 3, 2, 3, 4, 5), i8x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [i8x8; 2] = transmute(vld2_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_p16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 4, 3, 5]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 2, 3), i16x4::new(2, 3, 4, 5)]; - let r: [i16x4; 2] = transmute(vld2_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 2] = [i8x16::new(1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9), i8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)]; - let r: [i8x16; 2] = transmute(vld2q_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 2, 3, 2, 3, 4, 5), i16x8::new(2, 3, 4, 5, 6, 7, 8, 9)]; - let r: [i16x8; 2] = transmute(vld2q_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_u64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64x1; 2] = [u64x1::new(1), u64x1::new(2)]; - let r: [u64x1; 2] = transmute(vld2_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_p64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(2)]; - let r: [i64x1; 2] = transmute(vld2_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_f32() { - let a: [f32; 5] = [0., 1., 2., 2., 3.]; - let e: [f32x2; 2] = [f32x2::new(1., 2.), f32x2::new(2., 3.)]; - let r: [f32x2; 2] = transmute(vld2_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 3., 2., 4., 3., 5.]; - let e: [f32x4; 2] = [f32x4::new(1., 2., 2., 3.), f32x4::new(2., 3., 4., 5.)]; - let r: [f32x4; 2] = transmute(vld2q_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_s8() { - let a: [i8; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 2] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 2] = transmute(vld2_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_s16() { - let a: [i16; 9] = [0, 1, 1, 2, 3, 1, 4, 3, 5]; - let e: [i16x4; 2] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 2] = transmute(vld2_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_s32() { - let a: [i32; 5] = [0, 1, 1, 2, 3]; - let e: [i32x2; 2] = [i32x2::new(1, 1), i32x2::new(1, 1)]; - let r: [i32x2; 2] = transmute(vld2_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_s8() { - let a: [i8; 33] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 2] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 2] = transmute(vld2q_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_s16() { - let a: [i16; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 2] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 2] = transmute(vld2q_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_s32() { - let a: [i32; 9] = [0, 1, 1, 2, 3, 1, 4, 3, 5]; - let e: [i32x4; 2] = [i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1)]; - let r: [i32x4; 2] = transmute(vld2q_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_s64() { - let a: [i64; 3] = [0, 1, 1]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 2] = transmute(vld2_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_u8() { - let a: [u8; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [u8x8; 2] = [u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x8; 2] = transmute(vld2_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_u16() { - let a: [u16; 9] = [0, 1, 1, 2, 3, 1, 4, 3, 5]; - let e: [u16x4; 2] = [u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1)]; - let r: [u16x4; 2] = transmute(vld2_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_u32() { - let a: [u32; 5] = [0, 1, 1, 2, 3]; - let e: [u32x2; 2] = [u32x2::new(1, 1), u32x2::new(1, 1)]; - let r: [u32x2; 2] = transmute(vld2_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_u8() { - let a: [u8; 33] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [u8x16; 2] = [u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x16; 2] = transmute(vld2q_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_u16() { - let a: [u16; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [u16x8; 2] = [u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u16x8; 2] = transmute(vld2q_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_u32() { - let a: [u32; 9] = [0, 1, 1, 2, 3, 1, 4, 3, 5]; - let e: [u32x4; 2] = [u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1)]; - let r: [u32x4; 2] = transmute(vld2q_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_p8() { - let a: [u8; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 2] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 2] = transmute(vld2_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_p16() { - let a: [u16; 9] = [0, 1, 1, 2, 3, 1, 4, 3, 5]; - let e: [i16x4; 2] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 2] = transmute(vld2_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_p8() { - let a: [u8; 33] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 2] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 2] = transmute(vld2q_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_p16() { - let a: [u16; 17] = [0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 2] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 2] = transmute(vld2q_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_u64() { - let a: [u64; 3] = [0, 1, 1]; - let e: [u64x1; 2] = [u64x1::new(1), u64x1::new(1)]; - let r: [u64x1; 2] = transmute(vld2_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_p64() { - let a: [u64; 3] = [0, 1, 1]; - let e: [i64x1; 2] = [i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 2] = transmute(vld2_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_dup_f32() { - let a: [f32; 5] = [0., 1., 1., 2., 3.]; - let e: [f32x2; 2] = [f32x2::new(1., 1.), f32x2::new(1., 1.)]; - let r: [f32x2; 2] = transmute(vld2_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_dup_f32() { - let a: [f32; 9] = [0., 1., 1., 2., 3., 1., 4., 3., 5.]; - let e: [f32x4; 2] = [f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.)]; - let r: [f32x4; 2] = transmute(vld2q_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_s8() { - let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 2] = [i8x8::new(0, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x8; 2] = transmute(vld2_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_s16() { - let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x4; 2] = [i16x4::new(0, 2, 2, 14), i16x4::new(2, 16, 17, 18)]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 2, 14), i16x4::new(2, 16, 17, 18)]; - let r: [i16x4; 2] = transmute(vld2_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_s32() { - let a: [i32; 5] = [0, 1, 2, 3, 4]; - let b: [i32x2; 2] = [i32x2::new(0, 2), i32x2::new(2, 14)]; - let e: [i32x2; 2] = [i32x2::new(1, 2), i32x2::new(2, 14)]; - let r: [i32x2; 2] = transmute(vld2_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_s16() { - let a: [i16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 2] = [i16x8::new(0, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i16x8; 2] = transmute(vld2q_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_s32() { - let a: [i32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i32x4; 2] = [i32x4::new(0, 2, 2, 14), i32x4::new(2, 16, 17, 18)]; - let e: [i32x4; 2] = [i32x4::new(1, 2, 2, 14), i32x4::new(2, 16, 17, 18)]; - let r: [i32x4; 2] = transmute(vld2q_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_u8() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u8x8; 2] = [u8x8::new(0, 2, 2, 14, 2, 16, 17, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [u8x8; 2] = [u8x8::new(1, 2, 2, 14, 2, 16, 17, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [u8x8; 2] = transmute(vld2_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_u16() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u16x4; 2] = [u16x4::new(0, 2, 2, 14), u16x4::new(2, 16, 17, 18)]; - let e: [u16x4; 2] = [u16x4::new(1, 2, 2, 14), u16x4::new(2, 16, 17, 18)]; - let r: [u16x4; 2] = transmute(vld2_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_u32() { - let a: [u32; 5] = [0, 1, 2, 3, 4]; - let b: [u32x2; 2] = [u32x2::new(0, 2), u32x2::new(2, 14)]; - let e: [u32x2; 2] = [u32x2::new(1, 2), u32x2::new(2, 14)]; - let r: [u32x2; 2] = transmute(vld2_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_u16() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u16x8; 2] = [u16x8::new(0, 2, 2, 14, 2, 16, 17, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [u16x8; 2] = [u16x8::new(1, 2, 2, 14, 2, 16, 17, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [u16x8; 2] = transmute(vld2q_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_u32() { - let a: [u32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u32x4; 2] = [u32x4::new(0, 2, 2, 14), u32x4::new(2, 16, 17, 18)]; - let e: [u32x4; 2] = [u32x4::new(1, 2, 2, 14), u32x4::new(2, 16, 17, 18)]; - let r: [u32x4; 2] = transmute(vld2q_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_p8() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 2] = [i8x8::new(0, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x8; 2] = [i8x8::new(1, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x8; 2] = transmute(vld2_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_p16() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x4; 2] = [i16x4::new(0, 2, 2, 14), i16x4::new(2, 16, 17, 18)]; - let e: [i16x4; 2] = [i16x4::new(1, 2, 2, 14), i16x4::new(2, 16, 17, 18)]; - let r: [i16x4; 2] = transmute(vld2_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_p16() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 2] = [i16x8::new(0, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i16x8; 2] = [i16x8::new(1, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i16x8; 2] = transmute(vld2q_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2_lane_f32() { - let a: [f32; 5] = [0., 1., 2., 3., 4.]; - let b: [f32x2; 2] = [f32x2::new(0., 2.), f32x2::new(2., 14.)]; - let e: [f32x2; 2] = [f32x2::new(1., 2.), f32x2::new(2., 14.)]; - let r: [f32x2; 2] = transmute(vld2_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld2q_lane_f32() { - let a: [f32; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let b: [f32x4; 2] = [f32x4::new(0., 2., 2., 14.), f32x4::new(2., 16., 17., 18.)]; - let e: [f32x4; 2] = [f32x4::new(1., 2., 2., 14.), f32x4::new(2., 16., 17., 18.)]; - let r: [f32x4; 2] = transmute(vld2q_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_s8() { - let a: [i8; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 2, 4, 2, 4, 7, 8), i8x8::new(2, 4, 7, 8, 13, 14, 15, 16), i8x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i8x8; 3] = transmute(vld3_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_s16() { - let a: [i16; 13] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 2, 4), i16x4::new(2, 4, 7, 8), i16x4::new(2, 4, 7, 8)]; - let r: [i16x4; 3] = transmute(vld3_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_s32() { - let a: [i32; 7] = [0, 1, 2, 2, 2, 4, 4]; - let e: [i32x2; 3] = [i32x2::new(1, 2), i32x2::new(2, 4), i32x2::new(2, 4)]; - let r: [i32x2; 3] = transmute(vld3_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_s8() { - let a: [i8; 49] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16), i8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48)]; - let r: [i8x16; 3] = transmute(vld3q_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_s16() { - let a: [i16; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 2, 4, 2, 4, 7, 8), i16x8::new(2, 4, 7, 8, 13, 14, 15, 16), i16x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i16x8; 3] = transmute(vld3q_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_s32() { - let a: [i32; 13] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let e: [i32x4; 3] = [i32x4::new(1, 2, 2, 4), i32x4::new(2, 4, 7, 8), i32x4::new(2, 4, 7, 8)]; - let r: [i32x4; 3] = transmute(vld3q_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_s64() { - let a: [i64; 4] = [0, 1, 2, 2]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 3] = transmute(vld3_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_u8() { - let a: [u8; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [u8x8; 3] = [u8x8::new(1, 2, 2, 4, 2, 4, 7, 8), u8x8::new(2, 4, 7, 8, 13, 14, 15, 16), u8x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [u8x8; 3] = transmute(vld3_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_u16() { - let a: [u16; 13] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let e: [u16x4; 3] = [u16x4::new(1, 2, 2, 4), u16x4::new(2, 4, 7, 8), u16x4::new(2, 4, 7, 8)]; - let r: [u16x4; 3] = transmute(vld3_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_u32() { - let a: [u32; 7] = [0, 1, 2, 2, 2, 4, 4]; - let e: [u32x2; 3] = [u32x2::new(1, 2), u32x2::new(2, 4), u32x2::new(2, 4)]; - let r: [u32x2; 3] = transmute(vld3_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_u8() { - let a: [u8; 49] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let e: [u8x16; 3] = [u8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16), u8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32), u8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48)]; - let r: [u8x16; 3] = transmute(vld3q_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_u16() { - let a: [u16; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [u16x8; 3] = [u16x8::new(1, 2, 2, 4, 2, 4, 7, 8), u16x8::new(2, 4, 7, 8, 13, 14, 15, 16), u16x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [u16x8; 3] = transmute(vld3q_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_u32() { - let a: [u32; 13] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let e: [u32x4; 3] = [u32x4::new(1, 2, 2, 4), u32x4::new(2, 4, 7, 8), u32x4::new(2, 4, 7, 8)]; - let r: [u32x4; 3] = transmute(vld3q_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_p8() { - let a: [u8; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 2, 4, 2, 4, 7, 8), i8x8::new(2, 4, 7, 8, 13, 14, 15, 16), i8x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i8x8; 3] = transmute(vld3_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_p16() { - let a: [u16; 13] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 2, 4), i16x4::new(2, 4, 7, 8), i16x4::new(2, 4, 7, 8)]; - let r: [i16x4; 3] = transmute(vld3_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_p8() { - let a: [u8; 49] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let e: [i8x16; 3] = [i8x16::new(1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16), i8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32), i8x16::new(2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48)]; - let r: [i8x16; 3] = transmute(vld3q_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_p16() { - let a: [u16; 25] = [0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 2, 4, 2, 4, 7, 8), i16x8::new(2, 4, 7, 8, 13, 14, 15, 16), i16x8::new(2, 4, 7, 8, 13, 14, 15, 16)]; - let r: [i16x8; 3] = transmute(vld3q_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_u64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [u64x1; 3] = [u64x1::new(1), u64x1::new(2), u64x1::new(2)]; - let r: [u64x1; 3] = transmute(vld3_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_p64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(2), i64x1::new(2)]; - let r: [i64x1; 3] = transmute(vld3_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_f32() { - let a: [f32; 7] = [0., 1., 2., 2., 2., 4., 4.]; - let e: [f32x2; 3] = [f32x2::new(1., 2.), f32x2::new(2., 4.), f32x2::new(2., 4.)]; - let r: [f32x2; 3] = transmute(vld3_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_f32() { - let a: [f32; 13] = [0., 1., 2., 2., 2., 4., 4., 2., 7., 7., 4., 8., 8.]; - let e: [f32x4; 3] = [f32x4::new(1., 2., 2., 4.), f32x4::new(2., 4., 7., 8.), f32x4::new(2., 4., 7., 8.)]; - let r: [f32x4; 3] = transmute(vld3q_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_s8() { - let a: [i8; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [i8x8; 3] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 3] = transmute(vld3_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_s16() { - let a: [i16; 13] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7]; - let e: [i16x4; 3] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 3] = transmute(vld3_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_s32() { - let a: [i32; 7] = [0, 1, 1, 1, 3, 1, 4]; - let e: [i32x2; 3] = [i32x2::new(1, 1), i32x2::new(1, 1), i32x2::new(1, 1)]; - let r: [i32x2; 3] = transmute(vld3_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_s8() { - let a: [i8; 49] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 3] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 3] = transmute(vld3q_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_s16() { - let a: [i16; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [i16x8; 3] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 3] = transmute(vld3q_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_s32() { - let a: [i32; 13] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7]; - let e: [i32x4; 3] = [i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1)]; - let r: [i32x4; 3] = transmute(vld3q_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_s64() { - let a: [i64; 4] = [0, 1, 1, 1]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 3] = transmute(vld3_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_u8() { - let a: [u8; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [u8x8; 3] = [u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x8; 3] = transmute(vld3_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_u16() { - let a: [u16; 13] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7]; - let e: [u16x4; 3] = [u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1)]; - let r: [u16x4; 3] = transmute(vld3_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_u32() { - let a: [u32; 7] = [0, 1, 1, 1, 3, 1, 4]; - let e: [u32x2; 3] = [u32x2::new(1, 1), u32x2::new(1, 1), u32x2::new(1, 1)]; - let r: [u32x2; 3] = transmute(vld3_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_u8() { - let a: [u8; 49] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [u8x16; 3] = [u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x16; 3] = transmute(vld3q_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_u16() { - let a: [u16; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [u16x8; 3] = [u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u16x8; 3] = transmute(vld3q_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_u32() { - let a: [u32; 13] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7]; - let e: [u32x4; 3] = [u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1)]; - let r: [u32x4; 3] = transmute(vld3q_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_p8() { - let a: [u8; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [i8x8; 3] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 3] = transmute(vld3_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_p16() { - let a: [u16; 13] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7]; - let e: [i16x4; 3] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 3] = transmute(vld3_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_p8() { - let a: [u8; 49] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17]; - let e: [i8x16; 3] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 3] = transmute(vld3q_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_p16() { - let a: [u16; 25] = [0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13]; - let e: [i16x8; 3] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 3] = transmute(vld3q_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_u64() { - let a: [u64; 4] = [0, 1, 1, 1]; - let e: [u64x1; 3] = [u64x1::new(1), u64x1::new(1), u64x1::new(1)]; - let r: [u64x1; 3] = transmute(vld3_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_p64() { - let a: [u64; 4] = [0, 1, 1, 1]; - let e: [i64x1; 3] = [i64x1::new(1), i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 3] = transmute(vld3_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_dup_f32() { - let a: [f32; 7] = [0., 1., 1., 1., 3., 1., 4.]; - let e: [f32x2; 3] = [f32x2::new(1., 1.), f32x2::new(1., 1.), f32x2::new(1., 1.)]; - let r: [f32x2; 3] = transmute(vld3_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_dup_f32() { - let a: [f32; 13] = [0., 1., 1., 1., 3., 1., 4., 3., 5., 1., 4., 3., 5.]; - let e: [f32x4; 3] = [f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.)]; - let r: [f32x4; 3] = transmute(vld3q_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_s8() { - let a: [i8; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 3] = [i8x8::new(0, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26), i8x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26), i8x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [i8x8; 3] = transmute(vld3_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_s16() { - let a: [i16; 13] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4]; - let b: [i16x4; 3] = [i16x4::new(0, 2, 2, 14), i16x4::new(2, 16, 17, 18), i16x4::new(2, 20, 21, 22)]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 2, 14), i16x4::new(2, 16, 17, 18), i16x4::new(2, 20, 21, 22)]; - let r: [i16x4; 3] = transmute(vld3_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_s32() { - let a: [i32; 7] = [0, 1, 2, 2, 4, 5, 6]; - let b: [i32x2; 3] = [i32x2::new(0, 2), i32x2::new(2, 14), i32x2::new(2, 16)]; - let e: [i32x2; 3] = [i32x2::new(1, 2), i32x2::new(2, 14), i32x2::new(2, 16)]; - let r: [i32x2; 3] = transmute(vld3_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_s16() { - let a: [i16; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 3] = [i16x8::new(0, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26), i16x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26), i16x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [i16x8; 3] = transmute(vld3q_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_s32() { - let a: [i32; 13] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4]; - let b: [i32x4; 3] = [i32x4::new(0, 2, 2, 14), i32x4::new(2, 16, 17, 18), i32x4::new(2, 20, 21, 22)]; - let e: [i32x4; 3] = [i32x4::new(1, 2, 2, 14), i32x4::new(2, 16, 17, 18), i32x4::new(2, 20, 21, 22)]; - let r: [i32x4; 3] = transmute(vld3q_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_u8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u8x8; 3] = [u8x8::new(0, 2, 2, 14, 2, 16, 17, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26), u8x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [u8x8; 3] = [u8x8::new(1, 2, 2, 14, 2, 16, 17, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26), u8x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [u8x8; 3] = transmute(vld3_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_u16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4]; - let b: [u16x4; 3] = [u16x4::new(0, 2, 2, 14), u16x4::new(2, 16, 17, 18), u16x4::new(2, 20, 21, 22)]; - let e: [u16x4; 3] = [u16x4::new(1, 2, 2, 14), u16x4::new(2, 16, 17, 18), u16x4::new(2, 20, 21, 22)]; - let r: [u16x4; 3] = transmute(vld3_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_u32() { - let a: [u32; 7] = [0, 1, 2, 2, 4, 5, 6]; - let b: [u32x2; 3] = [u32x2::new(0, 2), u32x2::new(2, 14), u32x2::new(2, 16)]; - let e: [u32x2; 3] = [u32x2::new(1, 2), u32x2::new(2, 14), u32x2::new(2, 16)]; - let r: [u32x2; 3] = transmute(vld3_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_u16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u16x8; 3] = [u16x8::new(0, 2, 2, 14, 2, 16, 17, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26), u16x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [u16x8; 3] = [u16x8::new(1, 2, 2, 14, 2, 16, 17, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26), u16x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [u16x8; 3] = transmute(vld3q_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_u32() { - let a: [u32; 13] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4]; - let b: [u32x4; 3] = [u32x4::new(0, 2, 2, 14), u32x4::new(2, 16, 17, 18), u32x4::new(2, 20, 21, 22)]; - let e: [u32x4; 3] = [u32x4::new(1, 2, 2, 14), u32x4::new(2, 16, 17, 18), u32x4::new(2, 20, 21, 22)]; - let r: [u32x4; 3] = transmute(vld3q_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_p8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 3] = [i8x8::new(0, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26), i8x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [i8x8; 3] = [i8x8::new(1, 2, 2, 14, 2, 16, 17, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26), i8x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [i8x8; 3] = transmute(vld3_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_p16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4]; - let b: [i16x4; 3] = [i16x4::new(0, 2, 2, 14), i16x4::new(2, 16, 17, 18), i16x4::new(2, 20, 21, 22)]; - let e: [i16x4; 3] = [i16x4::new(1, 2, 2, 14), i16x4::new(2, 16, 17, 18), i16x4::new(2, 20, 21, 22)]; - let r: [i16x4; 3] = transmute(vld3_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_p16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 3] = [i16x8::new(0, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26), i16x8::new(11, 12, 13, 14, 15, 16, 17, 18)]; - let e: [i16x8; 3] = [i16x8::new(1, 2, 2, 14, 2, 16, 17, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26), i16x8::new(2, 12, 13, 14, 15, 16, 17, 18)]; - let r: [i16x8; 3] = transmute(vld3q_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3_lane_f32() { - let a: [f32; 7] = [0., 1., 2., 2., 4., 5., 6.]; - let b: [f32x2; 3] = [f32x2::new(0., 2.), f32x2::new(2., 14.), f32x2::new(9., 16.)]; - let e: [f32x2; 3] = [f32x2::new(1., 2.), f32x2::new(2., 14.), f32x2::new(2., 16.)]; - let r: [f32x2; 3] = transmute(vld3_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld3q_lane_f32() { - let a: [f32; 13] = [0., 1., 2., 2., 4., 5., 6., 7., 8., 5., 6., 7., 8.]; - let b: [f32x4; 3] = [f32x4::new(0., 2., 2., 14.), f32x4::new(9., 16., 17., 18.), f32x4::new(5., 6., 7., 8.)]; - let e: [f32x4; 3] = [f32x4::new(1., 2., 2., 14.), f32x4::new(2., 16., 17., 18.), f32x4::new(2., 6., 7., 8.)]; - let r: [f32x4; 3] = transmute(vld3q_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 2, 6, 2, 6, 6, 8), i8x8::new(2, 6, 6, 8, 6, 8, 8, 16), i8x8::new(2, 6, 6, 8, 6, 8, 8, 16), i8x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [i8x8; 4] = transmute(vld4_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 2, 6), i16x4::new(2, 6, 6, 8), i16x4::new(2, 6, 6, 8), i16x4::new(6, 8, 8, 16)]; - let r: [i16x4; 4] = transmute(vld4_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i32x2; 4] = [i32x2::new(1, 2), i32x2::new(2, 6), i32x2::new(2, 6), i32x2::new(6, 8)]; - let r: [i32x2; 4] = transmute(vld4_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_s8() { - let a: [i8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16), i8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32), i8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48), i8x16::new(6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64)]; - let r: [i8x16; 4] = transmute(vld4q_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_s16() { - let a: [i16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 2, 6, 2, 6, 6, 8), i16x8::new(2, 6, 6, 8, 6, 8, 8, 16), i16x8::new(2, 6, 6, 8, 6, 8, 8, 16), i16x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [i16x8; 4] = transmute(vld4q_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_s32() { - let a: [i32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i32x4; 4] = [i32x4::new(1, 2, 2, 6), i32x4::new(2, 6, 6, 8), i32x4::new(2, 6, 6, 8), i32x4::new(6, 8, 8, 16)]; - let r: [i32x4; 4] = transmute(vld4q_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 6]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(2), i64x1::new(6)]; - let r: [i64x1; 4] = transmute(vld4_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u8x8; 4] = [u8x8::new(1, 2, 2, 6, 2, 6, 6, 8), u8x8::new(2, 6, 6, 8, 6, 8, 8, 16), u8x8::new(2, 6, 6, 8, 6, 8, 8, 16), u8x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [u8x8; 4] = transmute(vld4_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u16x4; 4] = [u16x4::new(1, 2, 2, 6), u16x4::new(2, 6, 6, 8), u16x4::new(2, 6, 6, 8), u16x4::new(6, 8, 8, 16)]; - let r: [u16x4; 4] = transmute(vld4_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u32x2; 4] = [u32x2::new(1, 2), u32x2::new(2, 6), u32x2::new(2, 6), u32x2::new(6, 8)]; - let r: [u32x2; 4] = transmute(vld4_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_u8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [u8x16; 4] = [u8x16::new(1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16), u8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32), u8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48), u8x16::new(6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64)]; - let r: [u8x16; 4] = transmute(vld4q_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_u16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u16x8; 4] = [u16x8::new(1, 2, 2, 6, 2, 6, 6, 8), u16x8::new(2, 6, 6, 8, 6, 8, 8, 16), u16x8::new(2, 6, 6, 8, 6, 8, 8, 16), u16x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [u16x8; 4] = transmute(vld4q_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_u32() { - let a: [u32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u32x4; 4] = [u32x4::new(1, 2, 2, 6), u32x4::new(2, 6, 6, 8), u32x4::new(2, 6, 6, 8), u32x4::new(6, 8, 8, 16)]; - let r: [u32x4; 4] = transmute(vld4q_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 2, 6, 2, 6, 6, 8), i8x8::new(2, 6, 6, 8, 6, 8, 8, 16), i8x8::new(2, 6, 6, 8, 6, 8, 8, 16), i8x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [i8x8; 4] = transmute(vld4_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 2, 6), i16x4::new(2, 6, 6, 8), i16x4::new(2, 6, 6, 8), i16x4::new(6, 8, 8, 16)]; - let r: [i16x4; 4] = transmute(vld4_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_p8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [i8x16; 4] = [i8x16::new(1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16), i8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32), i8x16::new(2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48), i8x16::new(6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64)]; - let r: [i8x16; 4] = transmute(vld4q_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_p16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 2, 6, 2, 6, 6, 8), i16x8::new(2, 6, 6, 8, 6, 8, 8, 16), i16x8::new(2, 6, 6, 8, 6, 8, 8, 16), i16x8::new(6, 8, 8, 16, 8, 16, 16, 32)]; - let r: [i16x8; 4] = transmute(vld4q_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [u64x1; 4] = [u64x1::new(1), u64x1::new(2), u64x1::new(2), u64x1::new(6)]; - let r: [u64x1; 4] = transmute(vld4_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(2), i64x1::new(2), i64x1::new(6)]; - let r: [i64x1; 4] = transmute(vld4_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f32x2; 4] = [f32x2::new(1., 2.), f32x2::new(2., 6.), f32x2::new(2., 6.), f32x2::new(6., 8.)]; - let r: [f32x2; 4] = transmute(vld4_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_f32() { - let a: [f32; 17] = [0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 15., 16.]; - let e: [f32x4; 4] = [f32x4::new(1., 2., 2., 6.), f32x4::new(2., 6., 6., 8.), f32x4::new(2., 6., 6., 15.), f32x4::new(6., 8., 8., 16.)]; - let r: [f32x4; 4] = transmute(vld4q_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_s8() { - let a: [i8; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 4] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 4] = transmute(vld4_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_s16() { - let a: [i16; 17] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x4; 4] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 4] = transmute(vld4_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_s32() { - let a: [i32; 9] = [0, 1, 1, 1, 1, 2, 4, 3, 5]; - let e: [i32x2; 4] = [i32x2::new(1, 1), i32x2::new(1, 1), i32x2::new(1, 1), i32x2::new(1, 1)]; - let r: [i32x2; 4] = transmute(vld4_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_s8() { - let a: [i8; 65] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x16; 4] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 4] = transmute(vld4q_dup_s8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_s16() { - let a: [i16; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 4] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 4] = transmute(vld4q_dup_s16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_s32() { - let a: [i32; 17] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i32x4; 4] = [i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1), i32x4::new(1, 1, 1, 1)]; - let r: [i32x4; 4] = transmute(vld4q_dup_s32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_s64() { - let a: [i64; 5] = [0, 1, 1, 1, 1]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(1), i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 4] = transmute(vld4_dup_s64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_u8() { - let a: [u8; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [u8x8; 4] = [u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1), u8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x8; 4] = transmute(vld4_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_u16() { - let a: [u16; 17] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [u16x4; 4] = [u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1), u16x4::new(1, 1, 1, 1)]; - let r: [u16x4; 4] = transmute(vld4_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_u32() { - let a: [u32; 9] = [0, 1, 1, 1, 1, 2, 4, 3, 5]; - let e: [u32x2; 4] = [u32x2::new(1, 1), u32x2::new(1, 1), u32x2::new(1, 1), u32x2::new(1, 1)]; - let r: [u32x2; 4] = transmute(vld4_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_u8() { - let a: [u8; 65] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [u8x16; 4] = [u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u8x16; 4] = transmute(vld4q_dup_u8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_u16() { - let a: [u16; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [u16x8; 4] = [u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1), u16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [u16x8; 4] = transmute(vld4q_dup_u16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_u32() { - let a: [u32; 17] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [u32x4; 4] = [u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1), u32x4::new(1, 1, 1, 1)]; - let r: [u32x4; 4] = transmute(vld4q_dup_u32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_p8() { - let a: [u8; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x8; 4] = [i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1), i8x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x8; 4] = transmute(vld4_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_p16() { - let a: [u16; 17] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x4; 4] = [i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1), i16x4::new(1, 1, 1, 1)]; - let r: [i16x4; 4] = transmute(vld4_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_p8() { - let a: [u8; 65] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i8x16; 4] = [i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1), i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i8x16; 4] = transmute(vld4q_dup_p8(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_p16() { - let a: [u16; 33] = [0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9]; - let e: [i16x8; 4] = [i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1), i16x8::new(1, 1, 1, 1, 1, 1, 1, 1)]; - let r: [i16x8; 4] = transmute(vld4q_dup_p16(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_u64() { - let a: [u64; 5] = [0, 1, 1, 1, 1]; - let e: [u64x1; 4] = [u64x1::new(1), u64x1::new(1), u64x1::new(1), u64x1::new(1)]; - let r: [u64x1; 4] = transmute(vld4_dup_u64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_p64() { - let a: [u64; 5] = [0, 1, 1, 1, 1]; - let e: [i64x1; 4] = [i64x1::new(1), i64x1::new(1), i64x1::new(1), i64x1::new(1)]; - let r: [i64x1; 4] = transmute(vld4_dup_p64(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_dup_f32() { - let a: [f32; 9] = [0., 1., 1., 1., 1., 6., 4., 3., 5.]; - let e: [f32x2; 4] = [f32x2::new(1., 1.), f32x2::new(1., 1.), f32x2::new(1., 1.), f32x2::new(1., 1.)]; - let r: [f32x2; 4] = transmute(vld4_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_dup_f32() { - let a: [f32; 17] = [0., 1., 1., 1., 1., 6., 4., 3., 5., 7., 4., 3., 5., 8., 4., 3., 5.]; - let e: [f32x4; 4] = [f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.), f32x4::new(1., 1., 1., 1.)]; - let r: [f32x4; 4] = transmute(vld4q_dup_f32(a[1..].as_ptr())); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 4] = [i8x8::new(0, 2, 2, 2, 2, 16, 2, 18), i8x8::new(2, 20, 21, 22, 2, 24, 25, 26), i8x8::new(11, 12, 13, 14, 15, 16, 2, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 2, 2, 2, 16, 2, 18), i8x8::new(2, 20, 21, 22, 2, 24, 25, 26), i8x8::new(2, 12, 13, 14, 15, 16, 2, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x8; 4] = transmute(vld4_lane_s8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x4; 4] = [i16x4::new(0, 2, 2, 2), i16x4::new(2, 16, 2, 18), i16x4::new(2, 20, 21, 22), i16x4::new(2, 24, 25, 26)]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 2, 2), i16x4::new(2, 16, 2, 18), i16x4::new(2, 20, 21, 22), i16x4::new(2, 24, 25, 26)]; - let r: [i16x4; 4] = transmute(vld4_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 2, 5, 6, 7, 8]; - let b: [i32x2; 4] = [i32x2::new(0, 2), i32x2::new(2, 2), i32x2::new(2, 16), i32x2::new(2, 18)]; - let e: [i32x2; 4] = [i32x2::new(1, 2), i32x2::new(2, 2), i32x2::new(2, 16), i32x2::new(2, 18)]; - let r: [i32x2; 4] = transmute(vld4_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_s16() { - let a: [i16; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 4] = [i16x8::new(0, 2, 2, 2, 2, 16, 2, 18), i16x8::new(2, 20, 21, 22, 2, 24, 25, 26), i16x8::new(11, 12, 13, 14, 15, 16, 2, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 2, 2, 2, 16, 2, 18), i16x8::new(2, 20, 21, 22, 2, 24, 25, 26), i16x8::new(2, 12, 13, 14, 15, 16, 2, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i16x8; 4] = transmute(vld4q_lane_s16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_s32() { - let a: [i32; 17] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i32x4; 4] = [i32x4::new(0, 2, 2, 2), i32x4::new(2, 16, 2, 18), i32x4::new(2, 20, 21, 22), i32x4::new(2, 24, 25, 26)]; - let e: [i32x4; 4] = [i32x4::new(1, 2, 2, 2), i32x4::new(2, 16, 2, 18), i32x4::new(2, 20, 21, 22), i32x4::new(2, 24, 25, 26)]; - let r: [i32x4; 4] = transmute(vld4q_lane_s32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u8x8; 4] = [u8x8::new(0, 2, 2, 2, 2, 16, 2, 18), u8x8::new(2, 20, 21, 22, 2, 24, 25, 26), u8x8::new(11, 12, 13, 14, 15, 16, 2, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [u8x8; 4] = [u8x8::new(1, 2, 2, 2, 2, 16, 2, 18), u8x8::new(2, 20, 21, 22, 2, 24, 25, 26), u8x8::new(2, 12, 13, 14, 15, 16, 2, 18), u8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [u8x8; 4] = transmute(vld4_lane_u8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u16x4; 4] = [u16x4::new(0, 2, 2, 2), u16x4::new(2, 16, 2, 18), u16x4::new(2, 20, 21, 22), u16x4::new(2, 24, 25, 26)]; - let e: [u16x4; 4] = [u16x4::new(1, 2, 2, 2), u16x4::new(2, 16, 2, 18), u16x4::new(2, 20, 21, 22), u16x4::new(2, 24, 25, 26)]; - let r: [u16x4; 4] = transmute(vld4_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 2, 5, 6, 7, 8]; - let b: [u32x2; 4] = [u32x2::new(0, 2), u32x2::new(2, 2), u32x2::new(2, 16), u32x2::new(2, 18)]; - let e: [u32x2; 4] = [u32x2::new(1, 2), u32x2::new(2, 2), u32x2::new(2, 16), u32x2::new(2, 18)]; - let r: [u32x2; 4] = transmute(vld4_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_u16() { - let a: [u16; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u16x8; 4] = [u16x8::new(0, 2, 2, 2, 2, 16, 2, 18), u16x8::new(2, 20, 21, 22, 2, 24, 25, 26), u16x8::new(11, 12, 13, 14, 15, 16, 2, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [u16x8; 4] = [u16x8::new(1, 2, 2, 2, 2, 16, 2, 18), u16x8::new(2, 20, 21, 22, 2, 24, 25, 26), u16x8::new(2, 12, 13, 14, 15, 16, 2, 18), u16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [u16x8; 4] = transmute(vld4q_lane_u16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_u32() { - let a: [u32; 17] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [u32x4; 4] = [u32x4::new(0, 2, 2, 2), u32x4::new(2, 16, 2, 18), u32x4::new(2, 20, 21, 22), u32x4::new(2, 24, 25, 26)]; - let e: [u32x4; 4] = [u32x4::new(1, 2, 2, 2), u32x4::new(2, 16, 2, 18), u32x4::new(2, 20, 21, 22), u32x4::new(2, 24, 25, 26)]; - let r: [u32x4; 4] = transmute(vld4q_lane_u32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i8x8; 4] = [i8x8::new(0, 2, 2, 2, 2, 16, 2, 18), i8x8::new(2, 20, 21, 22, 2, 24, 25, 26), i8x8::new(11, 12, 13, 14, 15, 16, 2, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i8x8; 4] = [i8x8::new(1, 2, 2, 2, 2, 16, 2, 18), i8x8::new(2, 20, 21, 22, 2, 24, 25, 26), i8x8::new(2, 12, 13, 14, 15, 16, 2, 18), i8x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i8x8; 4] = transmute(vld4_lane_p8::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x4; 4] = [i16x4::new(0, 2, 2, 2), i16x4::new(2, 16, 2, 18), i16x4::new(2, 20, 21, 22), i16x4::new(2, 24, 25, 26)]; - let e: [i16x4; 4] = [i16x4::new(1, 2, 2, 2), i16x4::new(2, 16, 2, 18), i16x4::new(2, 20, 21, 22), i16x4::new(2, 24, 25, 26)]; - let r: [i16x4; 4] = transmute(vld4_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_p16() { - let a: [u16; 33] = [0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8]; - let b: [i16x8; 4] = [i16x8::new(0, 2, 2, 2, 2, 16, 2, 18), i16x8::new(2, 20, 21, 22, 2, 24, 25, 26), i16x8::new(11, 12, 13, 14, 15, 16, 2, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let e: [i16x8; 4] = [i16x8::new(1, 2, 2, 2, 2, 16, 2, 18), i16x8::new(2, 20, 21, 22, 2, 24, 25, 26), i16x8::new(2, 12, 13, 14, 15, 16, 2, 18), i16x8::new(2, 20, 21, 22, 23, 24, 25, 26)]; - let r: [i16x8; 4] = transmute(vld4q_lane_p16::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4_lane_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 2., 5., 6., 7., 8.]; - let b: [f32x2; 4] = [f32x2::new(0., 2.), f32x2::new(2., 2.), f32x2::new(2., 16.), f32x2::new(2., 18.)]; - let e: [f32x2; 4] = [f32x2::new(1., 2.), f32x2::new(2., 2.), f32x2::new(2., 16.), f32x2::new(2., 18.)]; - let r: [f32x2; 4] = transmute(vld4_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vld4q_lane_f32() { - let a: [f32; 17] = [0., 1., 2., 2., 2., 5., 6., 7., 8., 5., 6., 7., 8., 1., 4., 3., 5.]; - let b: [f32x4; 4] = [f32x4::new(0., 2., 2., 2.), f32x4::new(2., 16., 2., 18.), f32x4::new(5., 6., 7., 8.), f32x4::new(1., 4., 3., 5.)]; - let e: [f32x4; 4] = [f32x4::new(1., 2., 2., 2.), f32x4::new(2., 16., 2., 18.), f32x4::new(2., 6., 7., 8.), f32x4::new(2., 4., 3., 5.)]; - let r: [f32x4; 4] = transmute(vld4q_lane_f32::<0>(a[1..].as_ptr(), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_s8() { - let a: [i8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i8; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 8] = [0i8; 8]; - vst1_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_s16() { - let a: [i16; 5] = [0, 1, 2, 3, 4]; - let e: [i16; 4] = [1, 0, 0, 0]; - let mut r: [i16; 4] = [0i16; 4]; - vst1_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_s32() { - let a: [i32; 3] = [0, 1, 2]; - let e: [i32; 2] = [1, 0]; - let mut r: [i32; 2] = [0i32; 2]; - vst1_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_s64() { - let a: [i64; 2] = [0, 1]; - let e: [i64; 1] = [1]; - let mut r: [i64; 1] = [0i64; 1]; - vst1_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_s8() { - let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8; 16] = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 16] = [0i8; 16]; - vst1q_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_s16() { - let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i16; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 8] = [0i16; 8]; - vst1q_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_s32() { - let a: [i32; 5] = [0, 1, 2, 3, 4]; - let e: [i32; 4] = [1, 0, 0, 0]; - let mut r: [i32; 4] = [0i32; 4]; - vst1q_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_s64() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64; 2] = [1, 0]; - let mut r: [i64; 2] = [0i64; 2]; - vst1q_lane_s64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_u8() { - let a: [u8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u8; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 8] = [0u8; 8]; - vst1_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_u16() { - let a: [u16; 5] = [0, 1, 2, 3, 4]; - let e: [u16; 4] = [1, 0, 0, 0]; - let mut r: [u16; 4] = [0u16; 4]; - vst1_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_u32() { - let a: [u32; 3] = [0, 1, 2]; - let e: [u32; 2] = [1, 0]; - let mut r: [u32; 2] = [0u32; 2]; - vst1_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_u64() { - let a: [u64; 2] = [0, 1]; - let e: [u64; 1] = [1]; - let mut r: [u64; 1] = [0u64; 1]; - vst1_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_u8() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 16] = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 16] = [0u8; 16]; - vst1q_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_u16() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u16; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 8] = [0u16; 8]; - vst1q_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_u32() { - let a: [u32; 5] = [0, 1, 2, 3, 4]; - let e: [u32; 4] = [1, 0, 0, 0]; - let mut r: [u32; 4] = [0u32; 4]; - vst1q_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_u64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 0]; - let mut r: [u64; 2] = [0u64; 2]; - vst1q_lane_u64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_p8() { - let a: [u8; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u8; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 8] = [0u8; 8]; - vst1_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_p16() { - let a: [u16; 5] = [0, 1, 2, 3, 4]; - let e: [u16; 4] = [1, 0, 0, 0]; - let mut r: [u16; 4] = [0u16; 4]; - vst1_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_p8() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 16] = [1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 16] = [0u8; 16]; - vst1q_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_p16() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u16; 8] = [1, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 8] = [0u16; 8]; - vst1q_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_p64() { - let a: [u64; 2] = [0, 1]; - let e: [u64; 1] = [1]; - let mut r: [u64; 1] = [0u64; 1]; - vst1_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_p64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 0]; - let mut r: [u64; 2] = [0u64; 2]; - vst1q_lane_p64::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_lane_f32() { - let a: [f32; 3] = [0., 1., 2.]; - let e: [f32; 2] = [1., 0.]; - let mut r: [f32; 2] = [0f32; 2]; - vst1_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_lane_f32() { - let a: [f32; 5] = [0., 1., 2., 3., 4.]; - let e: [f32; 4] = [1., 0., 0., 0.]; - let mut r: [f32; 4] = [0f32; 4]; - vst1q_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s8_x2() { - let a: [i8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [i8; 16] = [0i8; 16]; - vst1_s8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s16_x2() { - let a: [i16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i16; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [i16; 8] = [0i16; 8]; - vst1_s16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s32_x2() { - let a: [i32; 5] = [0, 1, 2, 3, 4]; - let e: [i32; 4] = [1, 2, 3, 4]; - let mut r: [i32; 4] = [0i32; 4]; - vst1_s32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s64_x2() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64; 2] = [1, 2]; - let mut r: [i64; 2] = [0i64; 2]; - vst1_s64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s8_x2() { - let a: [i8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [i8; 32] = [0i8; 32]; - vst1q_s8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s16_x2() { - let a: [i16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [i16; 16] = [0i16; 16]; - vst1q_s16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s32_x2() { - let a: [i32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [i32; 8] = [0i32; 8]; - vst1q_s32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s64_x2() { - let a: [i64; 5] = [0, 1, 2, 3, 4]; - let e: [i64; 4] = [1, 2, 3, 4]; - let mut r: [i64; 4] = [0i64; 4]; - vst1q_s64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s8_x3() { - let a: [i8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i8; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [i8; 24] = [0i8; 24]; - vst1_s8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s16_x3() { - let a: [i16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [i16; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let mut r: [i16; 12] = [0i16; 12]; - vst1_s16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s32_x3() { - let a: [i32; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [i32; 6] = [1, 2, 3, 4, 5, 6]; - let mut r: [i32; 6] = [0i32; 6]; - vst1_s32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s64_x3() { - let a: [i64; 4] = [0, 1, 2, 3]; - let e: [i64; 3] = [1, 2, 3]; - let mut r: [i64; 3] = [0i64; 3]; - vst1_s64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s8_x3() { - let a: [i8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i8; 48] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [i8; 48] = [0i8; 48]; - vst1q_s8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s16_x3() { - let a: [i16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [i16; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [i16; 24] = [0i16; 24]; - vst1q_s16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s32_x3() { - let a: [i32; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [i32; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let mut r: [i32; 12] = [0i32; 12]; - vst1q_s32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s64_x3() { - let a: [i64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [i64; 6] = [1, 2, 3, 4, 5, 6]; - let mut r: [i64; 6] = [0i64; 6]; - vst1q_s64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s8_x4() { - let a: [i8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [i8; 32] = [0i8; 32]; - vst1_s8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s16_x4() { - let a: [i16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [i16; 16] = [0i16; 16]; - vst1_s16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s32_x4() { - let a: [i32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [i32; 8] = [0i32; 8]; - vst1_s32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_s64_x4() { - let a: [i64; 5] = [0, 1, 2, 3, 4]; - let e: [i64; 4] = [1, 2, 3, 4]; - let mut r: [i64; 4] = [0i64; 4]; - vst1_s64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s8_x4() { - let a: [i8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [i8; 64] = [0i8; 64]; - vst1q_s8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s16_x4() { - let a: [i16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [i16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [i16; 32] = [0i16; 32]; - vst1q_s16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s32_x4() { - let a: [i32; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [i32; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [i32; 16] = [0i32; 16]; - vst1q_s32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_s64_x4() { - let a: [i64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [i64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [i64; 8] = [0i64; 8]; - vst1q_s64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u8_x2() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u8; 16] = [0u8; 16]; - vst1_u8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u16_x2() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u16; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u16; 8] = [0u16; 8]; - vst1_u16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u32_x2() { - let a: [u32; 5] = [0, 1, 2, 3, 4]; - let e: [u32; 4] = [1, 2, 3, 4]; - let mut r: [u32; 4] = [0u32; 4]; - vst1_u32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u64_x2() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst1_u64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u8_x2() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst1q_u8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u16_x2() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst1q_u16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u32_x2() { - let a: [u32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u32; 8] = [0u32; 8]; - vst1q_u32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u64_x2() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64; 4] = [1, 2, 3, 4]; - let mut r: [u64; 4] = [0u64; 4]; - vst1q_u64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u8_x3() { - let a: [u8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u8; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [u8; 24] = [0u8; 24]; - vst1_u8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u16_x3() { - let a: [u16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [u16; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let mut r: [u16; 12] = [0u16; 12]; - vst1_u16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u32_x3() { - let a: [u32; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [u32; 6] = [1, 2, 3, 4, 5, 6]; - let mut r: [u32; 6] = [0u32; 6]; - vst1_u32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u64_x3() { - let a: [u64; 4] = [0, 1, 2, 3]; - let e: [u64; 3] = [1, 2, 3]; - let mut r: [u64; 3] = [0u64; 3]; - vst1_u64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u8_x3() { - let a: [u8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 48] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u8; 48] = [0u8; 48]; - vst1q_u8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u16_x3() { - let a: [u16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u16; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [u16; 24] = [0u16; 24]; - vst1q_u16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u32_x3() { - let a: [u32; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [u32; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let mut r: [u32; 12] = [0u32; 12]; - vst1q_u32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u64_x3() { - let a: [u64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [u64; 6] = [1, 2, 3, 4, 5, 6]; - let mut r: [u64; 6] = [0u64; 6]; - vst1q_u64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u8_x4() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst1_u8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u16_x4() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst1_u16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u32_x4() { - let a: [u32; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u32; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u32; 8] = [0u32; 8]; - vst1_u32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_u64_x4() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64; 4] = [1, 2, 3, 4]; - let mut r: [u64; 4] = [0u64; 4]; - vst1_u64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u8_x4() { - let a: [u8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 64] = [0u8; 64]; - vst1q_u8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u16_x4() { - let a: [u16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u16; 32] = [0u16; 32]; - vst1q_u16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u32_x4() { - let a: [u32; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u32; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u32; 16] = [0u32; 16]; - vst1q_u32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_u64_x4() { - let a: [u64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u64; 8] = [0u64; 8]; - vst1q_u64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p8_x2() { - let a: [u8; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u8; 16] = [0u8; 16]; - vst1_p8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p8_x3() { - let a: [u8; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u8; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [u8; 24] = [0u8; 24]; - vst1_p8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p8_x4() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst1_p8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p8_x2() { - let a: [u8; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst1q_p8_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p8_x3() { - let a: [u8; 49] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u8; 48] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u8; 48] = [0u8; 48]; - vst1q_p8_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p8_x4() { - let a: [u8; 65] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u8; 64] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u8; 64] = [0u8; 64]; - vst1q_p8_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p16_x2() { - let a: [u16; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u16; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u16; 8] = [0u16; 8]; - vst1_p16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p16_x3() { - let a: [u16; 13] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let e: [u16; 12] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12]; - let mut r: [u16; 12] = [0u16; 12]; - vst1_p16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p16_x4() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst1_p16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p16_x2() { - let a: [u16; 17] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let e: [u16; 16] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst1q_p16_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p16_x3() { - let a: [u16; 25] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let e: [u16; 24] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]; - let mut r: [u16; 24] = [0u16; 24]; - vst1q_p16_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p16_x4() { - let a: [u16; 33] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let e: [u16; 32] = [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32]; - let mut r: [u16; 32] = [0u16; 32]; - vst1q_p16_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p64_x2() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst1_p64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p64_x3() { - let a: [u64; 4] = [0, 1, 2, 3]; - let e: [u64; 3] = [1, 2, 3]; - let mut r: [u64; 3] = [0u64; 3]; - vst1_p64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_p64_x4() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64; 4] = [1, 2, 3, 4]; - let mut r: [u64; 4] = [0u64; 4]; - vst1_p64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p64_x2() { - let a: [u64; 5] = [0, 1, 2, 3, 4]; - let e: [u64; 4] = [1, 2, 3, 4]; - let mut r: [u64; 4] = [0u64; 4]; - vst1q_p64_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p64_x3() { - let a: [u64; 7] = [0, 1, 2, 3, 4, 5, 6]; - let e: [u64; 6] = [1, 2, 3, 4, 5, 6]; - let mut r: [u64; 6] = [0u64; 6]; - vst1q_p64_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_p64_x4() { - let a: [u64; 9] = [0, 1, 2, 3, 4, 5, 6, 7, 8]; - let e: [u64; 8] = [1, 2, 3, 4, 5, 6, 7, 8]; - let mut r: [u64; 8] = [0u64; 8]; - vst1q_p64_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f32_x2() { - let a: [f32; 5] = [0., 1., 2., 3., 4.]; - let e: [f32; 4] = [1., 2., 3., 4.]; - let mut r: [f32; 4] = [0f32; 4]; - vst1_f32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f32_x2() { - let a: [f32; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; - let mut r: [f32; 8] = [0f32; 8]; - vst1q_f32_x2(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f32_x3() { - let a: [f32; 7] = [0., 1., 2., 3., 4., 5., 6.]; - let e: [f32; 6] = [1., 2., 3., 4., 5., 6.]; - let mut r: [f32; 6] = [0f32; 6]; - vst1_f32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f32_x3() { - let a: [f32; 13] = [0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12.]; - let e: [f32; 12] = [1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12.]; - let mut r: [f32; 12] = [0f32; 12]; - vst1q_f32_x3(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1_f32_x4() { - let a: [f32; 9] = [0., 1., 2., 3., 4., 5., 6., 7., 8.]; - let e: [f32; 8] = [1., 2., 3., 4., 5., 6., 7., 8.]; - let mut r: [f32; 8] = [0f32; 8]; - vst1_f32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst1q_f32_x4() { - let a: [f32; 17] = [0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.]; - let e: [f32; 16] = [1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16.]; - let mut r: [f32; 16] = [0f32; 16]; - vst1q_f32_x4(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_s8() { - let a: [i8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [i8; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [i8; 16] = [0i8; 16]; - vst2_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_s16() { - let a: [i16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [i16; 8] = [1, 2, 2, 3, 2, 4, 3, 5]; - let mut r: [i16; 8] = [0i16; 8]; - vst2_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_s32() { - let a: [i32; 5] = [0, 1, 2, 2, 3]; - let e: [i32; 4] = [1, 2, 2, 3]; - let mut r: [i32; 4] = [0i32; 4]; - vst2_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [i8; 32] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let mut r: [i8; 32] = [0i8; 32]; - vst2q_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [i16; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [i16; 16] = [0i16; 16]; - vst2q_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [i32; 8] = [1, 2, 2, 3, 2, 4, 3, 5]; - let mut r: [i32; 8] = [0i32; 8]; - vst2q_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_s64() { - let a: [i64; 3] = [0, 1, 2]; - let e: [i64; 2] = [1, 2]; - let mut r: [i64; 2] = [0i64; 2]; - vst2_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_u8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u8; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [u8; 16] = [0u8; 16]; - vst2_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_u16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u16; 8] = [1, 2, 2, 3, 2, 4, 3, 5]; - let mut r: [u16; 8] = [0u16; 8]; - vst2_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_u32() { - let a: [u32; 5] = [0, 1, 2, 2, 3]; - let e: [u32; 4] = [1, 2, 2, 3]; - let mut r: [u32; 4] = [0u32; 4]; - vst2_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [u8; 32] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let mut r: [u8; 32] = [0u8; 32]; - vst2q_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u16; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [u16; 16] = [0u16; 16]; - vst2q_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u32; 8] = [1, 2, 2, 3, 2, 4, 3, 5]; - let mut r: [u32; 8] = [0u32; 8]; - vst2q_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_p8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u8; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [u8; 16] = [0u8; 16]; - vst2_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_p16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u16; 8] = [1, 2, 2, 3, 2, 4, 3, 5]; - let mut r: [u16; 8] = [0u16; 8]; - vst2_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]; - let e: [u8; 32] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17]; - let mut r: [u8; 32] = [0u8; 32]; - vst2q_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u16; 16] = [1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9]; - let mut r: [u16; 16] = [0u16; 16]; - vst2q_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_u64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst2_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_p64() { - let a: [u64; 3] = [0, 1, 2]; - let e: [u64; 2] = [1, 2]; - let mut r: [u64; 2] = [0u64; 2]; - vst2_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_f32() { - let a: [f32; 5] = [0., 1., 2., 2., 3.]; - let e: [f32; 4] = [1., 2., 2., 3.]; - let mut r: [f32; 4] = [0f32; 4]; - vst2_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 3., 2., 3., 4., 5.]; - let e: [f32; 8] = [1., 2., 2., 3., 2., 4., 3., 5.]; - let mut r: [f32; 8] = [0f32; 8]; - vst2q_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_s8() { - let a: [i8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [i8; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 16] = [0i8; 16]; - vst2_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_s16() { - let a: [i16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [i16; 8] = [1, 2, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 8] = [0i16; 8]; - vst2_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_s32() { - let a: [i32; 5] = [0, 1, 2, 2, 3]; - let e: [i32; 4] = [1, 2, 0, 0]; - let mut r: [i32; 4] = [0i32; 4]; - vst2_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [i16; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 16] = [0i16; 16]; - vst2q_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [i32; 8] = [1, 2, 0, 0, 0, 0, 0, 0]; - let mut r: [i32; 8] = [0i32; 8]; - vst2q_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_u8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u8; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 16] = [0u8; 16]; - vst2_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_u16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u16; 8] = [1, 2, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 8] = [0u16; 8]; - vst2_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_u32() { - let a: [u32; 5] = [0, 1, 2, 2, 3]; - let e: [u32; 4] = [1, 2, 0, 0]; - let mut r: [u32; 4] = [0u32; 4]; - vst2_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u16; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 16] = [0u16; 16]; - vst2q_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u32; 8] = [1, 2, 0, 0, 0, 0, 0, 0]; - let mut r: [u32; 8] = [0u32; 8]; - vst2q_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_p8() { - let a: [u8; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u8; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 16] = [0u8; 16]; - vst2_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_p16() { - let a: [u16; 9] = [0, 1, 2, 2, 3, 2, 3, 4, 5]; - let e: [u16; 8] = [1, 2, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 8] = [0u16; 8]; - vst2_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9]; - let e: [u16; 16] = [1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 16] = [0u16; 16]; - vst2q_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2_lane_f32() { - let a: [f32; 5] = [0., 1., 2., 2., 3.]; - let e: [f32; 4] = [1., 2., 0., 0.]; - let mut r: [f32; 4] = [0f32; 4]; - vst2_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst2q_lane_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 3., 2., 3., 4., 5.]; - let e: [f32; 8] = [1., 2., 0., 0., 0., 0., 0., 0.]; - let mut r: [f32; 8] = [0f32; 8]; - vst2q_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_s8() { - let a: [i8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [i8; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [i8; 24] = [0i8; 24]; - vst3_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_s16() { - let a: [i16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [i16; 12] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let mut r: [i16; 12] = [0i16; 12]; - vst3_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_s32() { - let a: [i32; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [i32; 6] = [1, 2, 2, 2, 4, 4]; - let mut r: [i32; 6] = [0i32; 6]; - vst3_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_s8() { - let a: [i8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [i8; 48] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let mut r: [i8; 48] = [0i8; 48]; - vst3q_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_s16() { - let a: [i16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [i16; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [i16; 24] = [0i16; 24]; - vst3q_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_s32() { - let a: [i32; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [i32; 12] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let mut r: [i32; 12] = [0i32; 12]; - vst3q_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_s64() { - let a: [i64; 4] = [0, 1, 2, 2]; - let e: [i64; 3] = [1, 2, 2]; - let mut r: [i64; 3] = [0i64; 3]; - vst3_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_u8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u8; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [u8; 24] = [0u8; 24]; - vst3_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_u16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u16; 12] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let mut r: [u16; 12] = [0u16; 12]; - vst3_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_u32() { - let a: [u32; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u32; 6] = [1, 2, 2, 2, 4, 4]; - let mut r: [u32; 6] = [0u32; 6]; - vst3_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_u8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [u8; 48] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let mut r: [u8; 48] = [0u8; 48]; - vst3q_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_u16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u16; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [u16; 24] = [0u16; 24]; - vst3q_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_u32() { - let a: [u32; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u32; 12] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let mut r: [u32; 12] = [0u32; 12]; - vst3q_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_p8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u8; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [u8; 24] = [0u8; 24]; - vst3_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_p16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u16; 12] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8]; - let mut r: [u16; 12] = [0u16; 12]; - vst3_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_p8() { - let a: [u8; 49] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48]; - let e: [u8; 48] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48]; - let mut r: [u8; 48] = [0u8; 48]; - vst3q_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_p16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u16; 24] = [1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16]; - let mut r: [u16; 24] = [0u16; 24]; - vst3q_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_u64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [u64; 3] = [1, 2, 2]; - let mut r: [u64; 3] = [0u64; 3]; - vst3_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_p64() { - let a: [u64; 4] = [0, 1, 2, 2]; - let e: [u64; 3] = [1, 2, 2]; - let mut r: [u64; 3] = [0u64; 3]; - vst3_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_f32() { - let a: [f32; 7] = [0., 1., 2., 2., 4., 2., 4.]; - let e: [f32; 6] = [1., 2., 2., 2., 4., 4.]; - let mut r: [f32; 6] = [0f32; 6]; - vst3_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_f32() { - let a: [f32; 13] = [0., 1., 2., 2., 4., 2., 4., 7., 8., 2., 4., 7., 8.]; - let e: [f32; 12] = [1., 2., 2., 2., 4., 4., 2., 7., 7., 4., 8., 8.]; - let mut r: [f32; 12] = [0f32; 12]; - vst3q_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_s8() { - let a: [i8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [i8; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 24] = [0i8; 24]; - vst3_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_s16() { - let a: [i16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [i16; 12] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 12] = [0i16; 12]; - vst3_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_s32() { - let a: [i32; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [i32; 6] = [1, 2, 2, 0, 0, 0]; - let mut r: [i32; 6] = [0i32; 6]; - vst3_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_s16() { - let a: [i16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [i16; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 24] = [0i16; 24]; - vst3q_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_s32() { - let a: [i32; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [i32; 12] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i32; 12] = [0i32; 12]; - vst3q_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_u8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u8; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 24] = [0u8; 24]; - vst3_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_u16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u16; 12] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 12] = [0u16; 12]; - vst3_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_u32() { - let a: [u32; 7] = [0, 1, 2, 2, 4, 2, 4]; - let e: [u32; 6] = [1, 2, 2, 0, 0, 0]; - let mut r: [u32; 6] = [0u32; 6]; - vst3_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_u16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u16; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 24] = [0u16; 24]; - vst3q_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_u32() { - let a: [u32; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u32; 12] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u32; 12] = [0u32; 12]; - vst3q_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_p8() { - let a: [u8; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u8; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 24] = [0u8; 24]; - vst3_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_p16() { - let a: [u16; 13] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8]; - let e: [u16; 12] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 12] = [0u16; 12]; - vst3_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_p16() { - let a: [u16; 25] = [0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16]; - let e: [u16; 24] = [1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 24] = [0u16; 24]; - vst3q_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3_lane_f32() { - let a: [f32; 7] = [0., 1., 2., 2., 3., 2., 3.]; - let e: [f32; 6] = [1., 2., 2., 0., 0., 0.]; - let mut r: [f32; 6] = [0f32; 6]; - vst3_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst3q_lane_f32() { - let a: [f32; 13] = [0., 1., 2., 2., 3., 2., 3., 4., 5., 2., 3., 4., 5.]; - let e: [f32; 12] = [1., 2., 2., 0., 0., 0., 0., 0., 0., 0., 0., 0.]; - let mut r: [f32; 12] = [0f32; 12]; - vst3q_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i8; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [i8; 32] = [0i8; 32]; - vst4_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i16; 16] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let mut r: [i16; 16] = [0i16; 16]; - vst4_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i32; 8] = [1, 2, 2, 6, 2, 6, 6, 8]; - let mut r: [i32; 8] = [0i32; 8]; - vst4_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_s8() { - let a: [i8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [i8; 64] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let mut r: [i8; 64] = [0i8; 64]; - vst4q_s8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_s16() { - let a: [i16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i16; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [i16; 32] = [0i16; 32]; - vst4q_s16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_s32() { - let a: [i32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i32; 16] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let mut r: [i32; 16] = [0i32; 16]; - vst4q_s32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_s64() { - let a: [i64; 5] = [0, 1, 2, 2, 6]; - let e: [i64; 4] = [1, 2, 2, 6]; - let mut r: [i64; 4] = [0i64; 4]; - vst4_s64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u8; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst4_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u16; 16] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst4_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u32; 8] = [1, 2, 2, 6, 2, 6, 6, 8]; - let mut r: [u32; 8] = [0u32; 8]; - vst4_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_u8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [u8; 64] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let mut r: [u8; 64] = [0u8; 64]; - vst4q_u8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_u16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u16; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [u16; 32] = [0u16; 32]; - vst4q_u16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_u32() { - let a: [u32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u32; 16] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let mut r: [u32; 16] = [0u32; 16]; - vst4q_u32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u8; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [u8; 32] = [0u8; 32]; - vst4_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u16; 16] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let mut r: [u16; 16] = [0u16; 16]; - vst4_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_p8() { - let a: [u8; 65] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let e: [u8; 64] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64]; - let mut r: [u8; 64] = [0u8; 64]; - vst4q_p8(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_p16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u16; 32] = [1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let mut r: [u16; 32] = [0u16; 32]; - vst4q_p16(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_u64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [u64; 4] = [1, 2, 2, 6]; - let mut r: [u64; 4] = [0u64; 4]; - vst4_u64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_p64() { - let a: [u64; 5] = [0, 1, 2, 2, 6]; - let e: [u64; 4] = [1, 2, 2, 6]; - let mut r: [u64; 4] = [0u64; 4]; - vst4_p64(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f32; 8] = [1., 2., 2., 6., 2., 6., 6., 8.]; - let mut r: [f32; 8] = [0f32; 8]; - vst4_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_f32() { - let a: [f32; 17] = [0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16.]; - let e: [f32; 16] = [1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16.]; - let mut r: [f32; 16] = [0f32; 16]; - vst4q_f32(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_s8() { - let a: [i8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i8; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i8; 32] = [0i8; 32]; - vst4_lane_s8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_s16() { - let a: [i16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i16; 16] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 16] = [0i16; 16]; - vst4_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_s32() { - let a: [i32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [i32; 8] = [1, 2, 2, 6, 0, 0, 0, 0]; - let mut r: [i32; 8] = [0i32; 8]; - vst4_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_s16() { - let a: [i16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [i16; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i16; 32] = [0i16; 32]; - vst4q_lane_s16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_s32() { - let a: [i32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [i32; 16] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [i32; 16] = [0i32; 16]; - vst4q_lane_s32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_u8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u8; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 32] = [0u8; 32]; - vst4_lane_u8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_u16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u16; 16] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 16] = [0u16; 16]; - vst4_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_u32() { - let a: [u32; 9] = [0, 1, 2, 2, 6, 2, 6, 6, 8]; - let e: [u32; 8] = [1, 2, 2, 6, 0, 0, 0, 0]; - let mut r: [u32; 8] = [0u32; 8]; - vst4_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_u16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u16; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 32] = [0u16; 32]; - vst4q_lane_u16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_u32() { - let a: [u32; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u32; 16] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u32; 16] = [0u32; 16]; - vst4q_lane_u32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_p8() { - let a: [u8; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u8; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u8; 32] = [0u8; 32]; - vst4_lane_p8::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_p16() { - let a: [u16; 17] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16]; - let e: [u16; 16] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 16] = [0u16; 16]; - vst4_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_p16() { - let a: [u16; 33] = [0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32]; - let e: [u16; 32] = [1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]; - let mut r: [u16; 32] = [0u16; 32]; - vst4q_lane_p16::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4_lane_f32() { - let a: [f32; 9] = [0., 1., 2., 2., 6., 2., 6., 6., 8.]; - let e: [f32; 8] = [1., 2., 2., 6., 0., 0., 0., 0.]; - let mut r: [f32; 8] = [0f32; 8]; - vst4_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vst4q_lane_f32() { - let a: [f32; 17] = [0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16.]; - let e: [f32; 16] = [1., 2., 2., 6., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0.]; - let mut r: [f32; 16] = [0f32; 16]; - vst4q_lane_f32::<0>(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdot_s32() { - let a: i32x2 = i32x2::new(1000, -4200); - let b: u8x8 = u8x8::new(100, 205, 110, 195, 120, 185, 130, 175); - let c: i8x8 = i8x8::new(0, 1, 2, 3, -1, -2, -3, -4); - let e: i32x2 = i32x2::new(2010, -5780); - let r: i32x2 = transmute(vusdot_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdotq_s32() { - let a: i32x4 = i32x4::new(1000, -4200, -1000, 2000); - let b: u8x16 = u8x16::new(100, 205, 110, 195, 120, 185, 130, 175, 140, 165, 150, 155, 160, 145, 170, 135); - let c: i8x16 = i8x16::new(0, 1, 2, 3, -1, -2, -3, -4, 4, 5, 6, 7, -5, -6, -7, -8); - let e: i32x4 = i32x4::new(2010, -5780, 2370, -1940); - let r: i32x4 = transmute(vusdotq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdot_lane_s32() { - let a: i32x2 = i32x2::new(1000, -4200); - let b: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let c: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let e: i32x2 = i32x2::new(2100, -2700); - let r: i32x2 = transmute(vusdot_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - - let a: i32x2 = i32x2::new(1000, -4200); - let b: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let c: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let e: i32x2 = i32x2::new(260, -5180); - let r: i32x2 = transmute(vusdot_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vusdotq_lane_s32() { - let a: i32x4 = i32x4::new(1000, -4200, -1000, 2000); - let b: u8x16 = u8x16::new(100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250); - let c: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let e: i32x4 = i32x4::new(2100, -2700, 900, 4300); - let r: i32x4 = transmute(vusdotq_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - - let a: i32x4 = i32x4::new(1000, -4200, -1000, 2000); - let b: u8x16 = u8x16::new(100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250); - let c: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let e: i32x4 = i32x4::new(260, -5180, -2220, 540); - let r: i32x4 = transmute(vusdotq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vsudot_lane_s32() { - let a: i32x2 = i32x2::new(-2000, 4200); - let b: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let c: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let e: i32x2 = i32x2::new(-900, 3460); - let r: i32x2 = transmute(vsudot_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - - let a: i32x2 = i32x2::new(-2000, 4200); - let b: i8x8 = i8x8::new(4, 3, 2, 1, 0, -1, -2, -3); - let c: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let e: i32x2 = i32x2::new(-500, 3220); - let r: i32x2 = transmute(vsudot_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,i8mm")] - unsafe fn test_vsudotq_lane_s32() { - let a: i32x4 = i32x4::new(-2000, 4200, -1000, 2000); - let b: i8x16 = i8x16::new(4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11); - let c: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let e: i32x4 = i32x4::new(-900, 3460, -3580, -2420); - let r: i32x4 = transmute(vsudotq_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - - let a: i32x4 = i32x4::new(-2000, 4200, -1000, 2000); - let b: i8x16 = i8x16::new(4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11); - let c: u8x8 = u8x8::new(100, 110, 120, 130, 140, 150, 160, 170); - let e: i32x4 = i32x4::new(-500, 3220, -4460, -3940); - let r: i32x4 = transmute(vsudotq_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_s8() { - let a: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: i8x8 = transmute(vmul_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_s8() { - let a: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32); - let r: i8x16 = transmute(vmulq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_s16() { - let a: i16x4 = i16x4::new(1, 2, 1, 2); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(1, 4, 3, 8); - let r: i16x4 = transmute(vmul_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_s16() { - let a: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: i16x8 = transmute(vmulq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(1, 4); - let r: i32x2 = transmute(vmul_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_s32() { - let a: i32x4 = i32x4::new(1, 2, 1, 2); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(1, 4, 3, 8); - let r: i32x4 = transmute(vmulq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_u8() { - let a: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: u8x8 = transmute(vmul_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_u8() { - let a: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32); - let r: u8x16 = transmute(vmulq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_u16() { - let a: u16x4 = u16x4::new(1, 2, 1, 2); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(1, 4, 3, 8); - let r: u16x4 = transmute(vmul_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_u16() { - let a: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: u16x8 = transmute(vmulq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(1, 4); - let r: u32x2 = transmute(vmul_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_u32() { - let a: u32x4 = u32x4::new(1, 2, 1, 2); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(1, 4, 3, 8); - let r: u32x4 = transmute(vmulq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_p8() { - let a: i8x8 = i8x8::new(1, 3, 1, 3, 1, 3, 1, 3); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 6, 3, 12, 5, 10, 7, 24); - let r: i8x8 = transmute(vmul_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_p8() { - let a: i8x16 = i8x16::new(1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 6, 3, 12, 5, 10, 7, 24, 9, 30, 11, 20, 13, 18, 15, 48); - let r: i8x16 = transmute(vmulq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(2.0, 3.0); - let e: f32x2 = f32x2::new(2.0, 6.0); - let r: f32x2 = transmute(vmul_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 1.0, 2.0); - let b: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let e: f32x4 = f32x4::new(2.0, 6.0, 4.0, 10.0); - let r: f32x4 = transmute(vmulq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16 = 2; - let e: i16x4 = i16x4::new(2, 4, 6, 8); - let r: i16x4 = transmute(vmul_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16 = 2; - let e: i16x8 = i16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: i16x8 = transmute(vmulq_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32 = 2; - let e: i32x2 = i32x2::new(2, 4); - let r: i32x2 = transmute(vmul_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32 = 2; - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmulq_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16 = 2; - let e: u16x4 = u16x4::new(2, 4, 6, 8); - let r: u16x4 = transmute(vmul_n_u16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16 = 2; - let e: u16x8 = u16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: u16x8 = transmute(vmulq_n_u16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32 = 2; - let e: u32x2 = u32x2::new(2, 4); - let r: u32x2 = transmute(vmul_n_u32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32 = 2; - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmulq_n_u32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_n_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32 = 2.; - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmul_n_f32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_n_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32 = 2.; - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulq_n_f32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x4 = i16x4::new(2, 4, 6, 8); - let r: i16x4 = transmute(vmul_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(2, 4, 6, 8); - let r: i16x4 = transmute(vmul_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x8 = i16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: i16x8 = transmute(vmulq_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: i16x8 = transmute(vmulq_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 2); - let e: i32x2 = i32x2::new(2, 4); - let r: i32x2 = transmute(vmul_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x2 = i32x2::new(2, 4); - let r: i32x2 = transmute(vmul_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x2 = i32x2::new(0, 2); - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmulq_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmulq_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u16x4 = u16x4::new(2, 4, 6, 8); - let r: u16x4 = transmute(vmul_lane_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u16x4 = u16x4::new(2, 4, 6, 8); - let r: u16x4 = transmute(vmul_laneq_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u16x8 = u16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: u16x8 = transmute(vmulq_lane_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u16x8 = u16x8::new(2, 4, 6, 8, 10, 12, 14, 16); - let r: u16x8 = transmute(vmulq_laneq_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(0, 2); - let e: u32x2 = u32x2::new(2, 4); - let r: u32x2 = transmute(vmul_lane_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u32x2 = u32x2::new(2, 4); - let r: u32x2 = transmute(vmul_laneq_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x2 = u32x2::new(0, 2); - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmulq_lane_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmulq_laneq_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_lane_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(2., 0.); - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmul_lane_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmul_laneq_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x2 = f32x2::new(2., 4.); - let r: f32x2 = transmute(vmul_laneq_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_lane_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x2 = f32x2::new(2., 0.); - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulq_lane_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmulq_laneq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(2., 0., 0., 0.); - let e: f32x4 = f32x4::new(2., 4., 6., 8.); - let r: f32x4 = transmute(vmulq_laneq_f32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i16x8 = i16x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: i16x8 = transmute(vmull_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 1, 2); - let e: i32x4 = i32x4::new(1, 4, 3, 8); - let r: i32x4 = transmute(vmull_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let e: i64x2 = i64x2::new(1, 4); - let r: i64x2 = transmute(vmull_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u16x8 = u16x8::new(1, 4, 3, 8, 5, 12, 7, 16); - let r: u16x8 = transmute(vmull_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(1, 2, 1, 2); - let e: u32x4 = u32x4::new(1, 4, 3, 8); - let r: u32x4 = transmute(vmull_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(1, 2); - let e: u64x2 = u64x2::new(1, 4); - let r: u64x2 = transmute(vmull_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_p8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 3, 1, 3, 1, 3, 1, 3); - let e: i16x8 = i16x8::new(1, 6, 3, 12, 5, 10, 7, 24); - let r: i16x8 = transmute(vmull_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_n_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16 = 2; - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmull_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_n_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32 = 2; - let e: i64x2 = i64x2::new(2, 4); - let r: i64x2 = transmute(vmull_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_n_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16 = 2; - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmull_n_u16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_n_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32 = 2; - let e: u64x2 = u64x2::new(2, 4); - let r: u64x2 = transmute(vmull_n_u32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_lane_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmull_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_laneq_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i32x4 = i32x4::new(2, 4, 6, 8); - let r: i32x4 = transmute(vmull_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_lane_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(2, 4); - let r: i64x2 = transmute(vmull_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_laneq_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i64x2 = i64x2::new(2, 4); - let r: i64x2 = transmute(vmull_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_lane_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(0, 2, 0, 0); - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmull_lane_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_laneq_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x8 = u16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: u32x4 = u32x4::new(2, 4, 6, 8); - let r: u32x4 = transmute(vmull_laneq_u16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_lane_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(0, 2); - let e: u64x2 = u64x2::new(2, 4); - let r: u64x2 = transmute(vmull_lane_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmull_laneq_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x4 = u32x4::new(0, 2, 0, 0); - let e: u64x2 = u64x2::new(2, 4); - let r: u64x2 = transmute(vmull_laneq_u32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfma_f32() { - let a: f32x2 = f32x2::new(8.0, 18.0); - let b: f32x2 = f32x2::new(6.0, 4.0); - let c: f32x2 = f32x2::new(2.0, 3.0); - let e: f32x2 = f32x2::new(20.0, 30.0); - let r: f32x2 = transmute(vfma_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfmaq_f32() { - let a: f32x4 = f32x4::new(8.0, 18.0, 12.0, 10.0); - let b: f32x4 = f32x4::new(6.0, 4.0, 7.0, 8.0); - let c: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let e: f32x4 = f32x4::new(20.0, 30.0, 40.0, 50.0); - let r: f32x4 = transmute(vfmaq_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfma_n_f32() { - let a: f32x2 = f32x2::new(2.0, 3.0); - let b: f32x2 = f32x2::new(6.0, 4.0); - let c: f32 = 8.0; - let e: f32x2 = f32x2::new(50.0, 35.0); - let r: f32x2 = transmute(vfma_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfmaq_n_f32() { - let a: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let b: f32x4 = f32x4::new(6.0, 4.0, 7.0, 8.0); - let c: f32 = 8.0; - let e: f32x4 = f32x4::new(50.0, 35.0, 60.0, 69.0); - let r: f32x4 = transmute(vfmaq_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfms_f32() { - let a: f32x2 = f32x2::new(20.0, 30.0); - let b: f32x2 = f32x2::new(6.0, 4.0); - let c: f32x2 = f32x2::new(2.0, 3.0); - let e: f32x2 = f32x2::new(8.0, 18.0); - let r: f32x2 = transmute(vfms_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfmsq_f32() { - let a: f32x4 = f32x4::new(20.0, 30.0, 40.0, 50.0); - let b: f32x4 = f32x4::new(6.0, 4.0, 7.0, 8.0); - let c: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let e: f32x4 = f32x4::new(8.0, 18.0, 12.0, 10.0); - let r: f32x4 = transmute(vfmsq_f32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfms_n_f32() { - let a: f32x2 = f32x2::new(50.0, 35.0); - let b: f32x2 = f32x2::new(6.0, 4.0); - let c: f32 = 8.0; - let e: f32x2 = f32x2::new(2.0, 3.0); - let r: f32x2 = transmute(vfms_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vfmsq_n_f32() { - let a: f32x4 = f32x4::new(50.0, 35.0, 60.0, 69.0); - let b: f32x4 = f32x4::new(6.0, 4.0, 7.0, 8.0); - let c: f32 = 8.0; - let e: f32x4 = f32x4::new(2.0, 3.0, 4.0, 5.0); - let r: f32x4 = transmute(vfmsq_n_f32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i8x8 = i8x8::new(0, 0, 2, 2, 4, 4, 6, 6); - let r: i8x8 = transmute(vsub_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: i8x16 = i8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14); - let r: i8x16 = transmute(vsubq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 1, 2); - let e: i16x4 = i16x4::new(0, 0, 2, 2); - let r: i16x4 = transmute(vsub_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i16x8 = i16x8::new(0, 0, 2, 2, 4, 4, 6, 6); - let r: i16x8 = transmute(vsubq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vsub_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(1, 2, 1, 2); - let e: i32x4 = i32x4::new(0, 0, 2, 2); - let r: i32x4 = transmute(vsubq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u8x8 = u8x8::new(0, 0, 2, 2, 4, 4, 6, 6); - let r: u8x8 = transmute(vsub_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: u8x16 = u8x16::new(0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14); - let r: u8x16 = transmute(vsubq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(1, 2, 1, 2); - let e: u16x4 = u16x4::new(0, 0, 2, 2); - let r: u16x4 = transmute(vsub_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u16x8 = u16x8::new(0, 0, 2, 2, 4, 4, 6, 6); - let r: u16x8 = transmute(vsubq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vsub_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 1, 2); - let e: u32x4 = u32x4::new(0, 0, 2, 2); - let r: u32x4 = transmute(vsubq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vsub_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(1, 2); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vsubq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vsub_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vsubq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsub_f32() { - let a: f32x2 = f32x2::new(1.0, 4.0); - let b: f32x2 = f32x2::new(1.0, 2.0); - let e: f32x2 = f32x2::new(0.0, 2.0); - let r: f32x2 = transmute(vsub_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubq_f32() { - let a: f32x4 = f32x4::new(1.0, 4.0, 3.0, 8.0); - let b: f32x4 = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e: f32x4 = f32x4::new(0.0, 2.0, 0.0, 4.0); - let r: f32x4 = transmute(vsubq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vadd_p8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let e: i8x8 = i8x8::new(0, 3, 2, 5, 4, 7, 6, 9); - let r: i8x8 = transmute(vadd_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vadd_p16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 1, 1, 1); - let e: i16x4 = i16x4::new(0, 3, 2, 5); - let r: i16x4 = transmute(vadd_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddq_p8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let e: i8x16 = i8x16::new(0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14, 17); - let r: i8x16 = transmute(vaddq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddq_p16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let e: i16x8 = i16x8::new(0, 3, 2, 5, 4, 7, 6, 9); - let r: i16x8 = transmute(vaddq_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vadd_p64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vadd_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddq_p64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(1, 1); - let e: i64x2 = i64x2::new(0, 3); - let r: i64x2 = transmute(vaddq_p64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vaddq_p128() { - let a: p128 = 16; - let b: p128 = 1; - let e: p128 = 17; - let r: p128 = vaddq_p128(a, b); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, -32768, 1, 1, 0x7F_FF, -32768, 1, 1); - let b: i16x8 = i16x8::new(1, 0, 0, 0, 1, 0, 0, 0); - let e: i8x8 = i8x8::new(0x7F, -128, 0, 0, 0x7F, -128, 0, 0); - let r: i8x8 = transmute(vsubhn_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, -2147483648, 1, 1); - let b: i32x4 = i32x4::new(1, 0, 0, 0); - let e: i16x4 = i16x4::new(0x7F_FF, -32768, 0, 0); - let r: i16x4 = transmute(vsubhn_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_s64() { - let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, -9223372036854775808); - let b: i64x2 = i64x2::new(1, 0); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, -2147483648); - let r: i32x2 = transmute(vsubhn_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_u16() { - let a: u16x8 = u16x8::new(0xFF_FF, 0, 1, 1, 0xFF_FF, 0, 1, 1); - let b: u16x8 = u16x8::new(1, 0, 0, 0, 1, 0, 0, 0); - let e: u8x8 = u8x8::new(0xFF, 0, 0, 0, 0xFF, 0, 0, 0); - let r: u8x8 = transmute(vsubhn_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_u32() { - let a: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 1, 1); - let b: u32x4 = u32x4::new(1, 0, 0, 0); - let e: u16x4 = u16x4::new(0xFF_FF, 0, 0, 0); - let r: u16x4 = transmute(vsubhn_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_u64() { - let a: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let b: u64x2 = u64x2::new(1, 0); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let r: u32x2 = transmute(vsubhn_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_s16() { - let a: i8x8 = i8x8::new(0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0); - let b: i16x8 = i16x8::new(0x7F_FF, 1, 0x7F_FF, 1, 0x7F_FF, 1, 0x7F_FF, 1); - let c: i16x8 = i16x8::new(1, 0, 1, 0, 1, 0, 1, 0); - let e: i8x16 = i8x16::new(0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0, 0x7F, 0); - let r: i8x16 = transmute(vsubhn_high_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_s32() { - let a: i16x4 = i16x4::new(0x7F_FF, 0, 0x7F_FF, 0); - let b: i32x4 = i32x4::new(0x7F_FF_FF_FF, 1, 0x7F_FF_FF_FF, 1); - let c: i32x4 = i32x4::new(1, 0, 1, 0); - let e: i16x8 = i16x8::new(0x7F_FF, 0, 0x7F_FF, 0, 0x7F_FF, 0, 0x7F_FF, 0); - let r: i16x8 = transmute(vsubhn_high_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_s64() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0); - let b: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 1); - let c: i64x2 = i64x2::new(1, 0); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0, 0x7F_FF_FF_FF, 0); - let r: i32x4 = transmute(vsubhn_high_s64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_u16() { - let a: u8x8 = u8x8::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let b: u16x8 = u16x8::new(0xFF_FF, 1, 0xFF_FF, 1, 0xFF_FF, 1, 0xFF_FF, 1); - let c: u16x8 = u16x8::new(1, 0, 1, 0, 1, 0, 1, 0); - let e: u8x16 = u8x16::new(0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0, 0xFF, 0); - let r: u8x16 = transmute(vsubhn_high_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_u32() { - let a: u16x4 = u16x4::new(0xFF_FF, 0, 0xFF_FF, 0); - let b: u32x4 = u32x4::new(0xFF_FF_FF_FF, 1, 0xFF_FF_FF_FF, 1); - let c: u32x4 = u32x4::new(1, 0, 1, 0); - let e: u16x8 = u16x8::new(0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0, 0xFF_FF, 0); - let r: u16x8 = transmute(vsubhn_high_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubhn_high_u64() { - let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let b: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 1); - let c: u64x2 = u64x2::new(1, 0); - let e: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 0xFF_FF_FF_FF, 0); - let r: u32x4 = transmute(vsubhn_high_u64(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u8x8 = u8x8::new(0, 0, 1, 1, 2, 2, 3, 3); - let r: u8x8 = transmute(vhsub_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: u8x16 = u8x16::new(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7); - let r: u8x16 = transmute(vhsubq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(1, 2, 1, 2); - let e: u16x4 = u16x4::new(0, 0, 1, 1); - let r: u16x4 = transmute(vhsub_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: u16x8 = u16x8::new(0, 0, 1, 1, 2, 2, 3, 3); - let r: u16x8 = transmute(vhsubq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vhsub_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 1, 2); - let e: u32x4 = u32x4::new(0, 0, 1, 1); - let r: u32x4 = transmute(vhsubq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i8x8 = i8x8::new(0, 0, 1, 1, 2, 2, 3, 3); - let r: i8x8 = transmute(vhsub_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2); - let e: i8x16 = i8x16::new(0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7); - let r: i8x16 = transmute(vhsubq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 1, 2); - let e: i16x4 = i16x4::new(0, 0, 1, 1); - let r: i16x4 = transmute(vhsub_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(1, 2, 1, 2, 1, 2, 1, 2); - let e: i16x8 = i16x8::new(0, 0, 1, 1, 2, 2, 3, 3); - let r: i16x8 = transmute(vhsubq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsub_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vhsub_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vhsubq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(1, 2, 1, 2); - let e: i32x4 = i32x4::new(0, 0, 1, 1); - let r: i32x4 = transmute(vhsubq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_s8() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vsubw_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_s16() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vsubw_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_s32() { - let a: i64x2 = i64x2::new(0, 1); - let b: i32x2 = i32x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vsubw_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_u8() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vsubw_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_u16() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: u16x4 = u16x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vsubw_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubw_u32() { - let a: u64x2 = u64x2::new(0, 1); - let b: u32x2 = u32x2::new(0, 1); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vsubw_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_s8() { - let a: i8x8 = i8x8::new(0x7F, -128, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(0x7F, -128, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vsubl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, -32768, 2, 3); - let b: i16x4 = i16x4::new(0x7F_FF, -32768, 2, 3); - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vsubl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, -2147483648); - let b: i32x2 = i32x2::new(0x7F_FF_FF_FF, -2147483648); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vsubl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_u8() { - let a: u8x8 = u8x8::new(0xFF, 0, 2, 3, 4, 5, 6, 7); - let b: u8x8 = u8x8::new(0xFF, 0, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vsubl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_u16() { - let a: u16x4 = u16x4::new(0xFF_FF, 0, 2, 3); - let b: u16x4 = u16x4::new(0xFF_FF, 0, 2, 3); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vsubl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsubl_u32() { - let a: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let b: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vsubl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x2 = i32x2::new(31, 176); - let r: i32x2 = transmute(vdot_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_s32() { - let a: i32x4 = i32x4::new(1, 2, 1, 2); - let b: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(31, 176, 31, 176); - let r: i32x4 = transmute(vdotq_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x2 = u32x2::new(31, 176); - let r: u32x2 = transmute(vdot_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_u32() { - let a: u32x4 = u32x4::new(1, 2, 1, 2); - let b: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x4 = u32x4::new(31, 176, 31, 176); - let r: u32x4 = transmute(vdotq_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_lane_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i8x8 = i8x8::new(-1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x2 = i32x2::new(29, 72); - let r: i32x2 = transmute(vdot_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_lane_s32() { - let a: i32x4 = i32x4::new(1, 2, 1, 2); - let b: i8x16 = i8x16::new(-1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i32x4 = i32x4::new(29, 72, 31, 72); - let r: i32x4 = transmute(vdotq_lane_s32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdot_lane_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u8x8 = u8x8::new(255, 2, 3, 4, 5, 6, 7, 8); - let c: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x2 = u32x2::new(285, 72); - let r: u32x2 = transmute(vdot_lane_u32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,dotprod")] - unsafe fn test_vdotq_lane_u32() { - let a: u32x4 = u32x4::new(1, 2, 1, 2); - let b: u8x16 = u8x16::new(255, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8); - let c: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u32x4 = u32x4::new(285, 72, 31, 72); - let r: u32x4 = transmute(vdotq_lane_u32::<0>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i8x8 = i8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let r: i8x8 = transmute(vmax_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: i8x16 = i8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vmaxq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(16, 15, 14, 13); - let e: i16x4 = i16x4::new(16, 15, 14, 13); - let r: i16x4 = transmute(vmax_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i16x8 = i16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let r: i16x8 = transmute(vmaxq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(16, 15); - let e: i32x2 = i32x2::new(16, 15); - let r: i32x2 = transmute(vmax_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(16, 15, 14, 13); - let e: i32x4 = i32x4::new(16, 15, 14, 13); - let r: i32x4 = transmute(vmaxq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u8x8 = u8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let r: u8x8 = transmute(vmax_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: u8x16 = u8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vmaxq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(16, 15, 14, 13); - let e: u16x4 = u16x4::new(16, 15, 14, 13); - let r: u16x4 = transmute(vmax_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u16x8 = u16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let r: u16x8 = transmute(vmaxq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(16, 15); - let e: u32x2 = u32x2::new(16, 15); - let r: u32x2 = transmute(vmax_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(16, 15, 14, 13); - let e: u32x4 = u32x4::new(16, 15, 14, 13); - let r: u32x4 = transmute(vmaxq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmax_f32() { - let a: f32x2 = f32x2::new(1.0, -2.0); - let b: f32x2 = f32x2::new(0.0, 3.0); - let e: f32x2 = f32x2::new(1.0, 3.0); - let r: f32x2 = transmute(vmax_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmaxq_f32() { - let a: f32x4 = f32x4::new(1.0, -2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(0.0, 3.0, 2.0, 8.0); - let e: f32x4 = f32x4::new(1.0, 3.0, 3.0, 8.0); - let r: f32x4 = transmute(vmaxq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vmaxnm_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(8.0, 16.0); - let e: f32x2 = f32x2::new(8.0, 16.0); - let r: f32x2 = transmute(vmaxnm_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vmaxnmq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); - let e: f32x4 = f32x4::new(8.0, 16.0, 3.0, 6.0); - let r: f32x4 = transmute(vmaxnmq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vmin_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 8, 7, 6, 5, 4, 3, 2, 1); - let r: i8x16 = transmute(vminq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(16, 15, 14, 13); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vmin_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vminq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(16, 15); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vmin_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(16, 15, 14, 13); - let e: i32x4 = i32x4::new(1, 2, 3, 4); - let r: i32x4 = transmute(vminq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vmin_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: u8x16 = u8x16::new(16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1); - let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 8, 7, 6, 5, 4, 3, 2, 1); - let r: u8x16 = transmute(vminq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(16, 15, 14, 13); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vmin_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(16, 15, 14, 13, 12, 11, 10, 9); - let e: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vminq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(16, 15); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vmin_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u32x4 = u32x4::new(16, 15, 14, 13); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vminq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vmin_f32() { - let a: f32x2 = f32x2::new(1.0, -2.0); - let b: f32x2 = f32x2::new(0.0, 3.0); - let e: f32x2 = f32x2::new(0.0, -2.0); - let r: f32x2 = transmute(vmin_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vminq_f32() { - let a: f32x4 = f32x4::new(1.0, -2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(0.0, 3.0, 2.0, 8.0); - let e: f32x4 = f32x4::new(0.0, -2.0, 2.0, -4.0); - let r: f32x4 = transmute(vminq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vminnm_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(8.0, 16.0); - let e: f32x2 = f32x2::new(1.0, 2.0); - let r: f32x2 = transmute(vminnm_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[cfg_attr(target_arch = "arm", simd_test(enable = "neon,crc"))] - #[cfg_attr(target_arch = "aarch64", simd_test(enable = "neon"))] - #[cfg_attr(target_arch = "arm64ec", simd_test(enable = "neon"))] - unsafe fn test_vminnmq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, -4.0); - let b: f32x4 = f32x4::new(8.0, 16.0, -1.0, 6.0); - let e: f32x4 = f32x4::new(1.0, 2.0, -1.0, -4.0); - let r: f32x4 = transmute(vminnmq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vpadd_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(3., 4.); - let e: f32x2 = f32x2::new(3., 7.); - let r: f32x2 = transmute(vpadd_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(0, 4, 12, 24); - let r: i32x4 = transmute(vqdmull_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(1, 2); - let e: i64x2 = i64x2::new(0, 4); - let r: i64x2 = transmute(vqdmull_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_n_s16() { - let a: i16x4 = i16x4::new(2, 4, 6, 8); - let b: i16 = 2; - let e: i32x4 = i32x4::new(8, 16, 24, 32); - let r: i32x4 = transmute(vqdmull_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_n_s32() { - let a: i32x2 = i32x2::new(2, 4); - let b: i32 = 2; - let e: i64x2 = i64x2::new(8, 16); - let r: i64x2 = transmute(vqdmull_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_lane_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(0, 2, 2, 0); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vqdmull_lane_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmull_lane_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vqdmull_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_s16() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(5, 9, 13, 17); - let r: i32x4 = transmute(vqdmlal_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_s32() { - let a: i64x2 = i64x2::new(1, 1); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x2 = i32x2::new(2, 2); - let e: i64x2 = i64x2::new(5, 9); - let r: i64x2 = transmute(vqdmlal_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_n_s16() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16 = 2; - let e: i32x4 = i32x4::new(5, 9, 13, 17); - let r: i32x4 = transmute(vqdmlal_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_n_s32() { - let a: i64x2 = i64x2::new(1, 1); - let b: i32x2 = i32x2::new(1, 2); - let c: i32 = 2; - let e: i64x2 = i64x2::new(5, 9); - let r: i64x2 = transmute(vqdmlal_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_lane_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x4 = i16x4::new(0, 2, 2, 0); - let e: i32x4 = i32x4::new(5, 10, 15, 20); - let r: i32x4 = transmute(vqdmlal_lane_s16::<2>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlal_lane_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(5, 10); - let r: i64x2 = transmute(vqdmlal_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_s16() { - let a: i32x4 = i32x4::new(3, 7, 11, 15); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(-1, -1, -1, -1); - let r: i32x4 = transmute(vqdmlsl_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_s32() { - let a: i64x2 = i64x2::new(3, 7); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x2 = i32x2::new(2, 2); - let e: i64x2 = i64x2::new(-1, -1); - let r: i64x2 = transmute(vqdmlsl_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_n_s16() { - let a: i32x4 = i32x4::new(3, 7, 11, 15); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16 = 2; - let e: i32x4 = i32x4::new(-1, -1, -1, -1); - let r: i32x4 = transmute(vqdmlsl_n_s16(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_n_s32() { - let a: i64x2 = i64x2::new(3, 7); - let b: i32x2 = i32x2::new(1, 2); - let c: i32 = 2; - let e: i64x2 = i64x2::new(-1, -1); - let r: i64x2 = transmute(vqdmlsl_n_s32(transmute(a), transmute(b), c)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_lane_s16() { - let a: i32x4 = i32x4::new(3, 6, 9, 12); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x4 = i16x4::new(0, 2, 2, 0); - let e: i32x4 = i32x4::new(-1, -2, -3, -4); - let r: i32x4 = transmute(vqdmlsl_lane_s16::<2>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmlsl_lane_s32() { - let a: i64x2 = i64x2::new(3, 6); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x2 = i32x2::new(0, 2); - let e: i64x2 = i64x2::new(-1, -2); - let r: i64x2 = transmute(vqdmlsl_lane_s32::<1>(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vqdmulh_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vqdmulhq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vqdmulh_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vqdmulhq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_n_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16 = 2; - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vqdmulh_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_n_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32 = 2; - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vqdmulh_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_n_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16 = 2; - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vqdmulhq_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_n_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32 = 2; - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vqdmulhq_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_laneq_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(2, 1, 1, 1, 1, 1, 1, 1); - let e: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let r: i16x8 = transmute(vqdmulhq_laneq_s16::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_laneq_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(2, 1, 1, 1, 1, 1, 1, 1); - let e: i16x4 = i16x4::new(1, 1, 1, 1); - let r: i16x4 = transmute(vqdmulh_laneq_s16::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulhq_laneq_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(2, 1, 1, 1); - let e: i32x4 = i32x4::new(1, 1, 1, 1); - let r: i32x4 = transmute(vqdmulhq_laneq_s32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqdmulh_laneq_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(2, 1, 1, 1); - let e: i32x2 = i32x2::new(1, 1); - let r: i32x2 = transmute(vqdmulh_laneq_s32::<0>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let e: i8x8 = i8x8::new(0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F, 0x7F); - let r: i8x8 = transmute(vqmovn_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let e: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let r: i16x4 = transmute(vqmovn_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_s64() { - let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, 0x7F_FF_FF_FF_FF_FF_FF_FF); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let r: i32x2 = transmute(vqmovn_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_u16() { - let a: u16x8 = u16x8::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let e: u8x8 = u8x8::new(0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF); - let r: u8x8 = transmute(vqmovn_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_u32() { - let a: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let e: u16x4 = u16x4::new(0xFF_FF, 0xFF_FF, 0xFF_FF, 0xFF_FF); - let r: u16x4 = transmute(vqmovn_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovn_u64() { - let a: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0xFF_FF_FF_FF_FF_FF_FF_FF); - let e: u32x2 = u32x2::new(0xFF_FF_FF_FF, 0xFF_FF_FF_FF); - let r: u32x2 = transmute(vqmovn_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_s16() { - let a: i16x8 = i16x8::new(-1, -1, -1, -1, -1, -1, -1, -1); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vqmovun_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_s32() { - let a: i32x4 = i32x4::new(-1, -1, -1, -1); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vqmovun_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqmovun_s64() { - let a: i64x2 = i64x2::new(-1, -1); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vqmovun_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(2, 2, 2, 2); - let r: i16x4 = transmute(vqrdmulh_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vqrdmulhq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(2, 2); - let r: i32x2 = transmute(vqrdmulh_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(2, 2, 2, 2); - let r: i32x4 = transmute(vqrdmulhq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_n_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16 = 2; - let e: i16x4 = i16x4::new(2, 2, 2, 2); - let r: i16x4 = transmute(vqrdmulh_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_n_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16 = 2; - let e: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vqrdmulhq_n_s16(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_n_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32 = 2; - let e: i32x2 = i32x2::new(2, 2); - let r: i32x2 = transmute(vqrdmulh_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_n_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32 = 2; - let e: i32x4 = i32x4::new(2, 2, 2, 2); - let r: i32x4 = transmute(vqrdmulhq_n_s32(transmute(a), b)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_lane_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x4 = i16x4::new(2, 2, 2, 2); - let r: i16x4 = transmute(vqrdmulh_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_laneq_s16() { - let a: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x4 = i16x4::new(2, 2, 2, 2); - let r: i16x4 = transmute(vqrdmulh_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_lane_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x4 = i16x4::new(0, 2, 0, 0); - let e: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vqrdmulhq_lane_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_laneq_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF, 0x7F_FF); - let b: i16x8 = i16x8::new(0, 2, 0, 0, 0, 0, 0, 0); - let e: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let r: i16x8 = transmute(vqrdmulhq_laneq_s16::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_lane_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(0, 2); - let e: i32x2 = i32x2::new(2, 2); - let r: i32x2 = transmute(vqrdmulh_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulh_laneq_s32() { - let a: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x2 = i32x2::new(2, 2); - let r: i32x2 = transmute(vqrdmulh_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_lane_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x2 = i32x2::new(0, 2); - let e: i32x4 = i32x4::new(2, 2, 2, 2); - let r: i32x4 = transmute(vqrdmulhq_lane_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrdmulhq_laneq_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let b: i32x4 = i32x4::new(0, 2, 0, 0); - let e: i32x4 = i32x4::new(2, 2, 2, 2); - let r: i32x4 = transmute(vqrdmulhq_laneq_s32::<1>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_s8() { - let a: i8x8 = i8x8::new(2, -128, 0x7F, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(8, -128, 0x7F, 12, 16, 20, 24, 28); - let r: i8x8 = transmute(vqrshl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_s8() { - let a: i8x16 = i8x16::new(2, -128, 0x7F, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(8, -128, 0x7F, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: i8x16 = transmute(vqrshlq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_s16() { - let a: i16x4 = i16x4::new(2, -32768, 0x7F_FF, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(8, -32768, 0x7F_FF, 12); - let r: i16x4 = transmute(vqrshl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_s16() { - let a: i16x8 = i16x8::new(2, -32768, 0x7F_FF, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(8, -32768, 0x7F_FF, 12, 16, 20, 24, 28); - let r: i16x8 = transmute(vqrshlq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_s32() { - let a: i32x2 = i32x2::new(2, -2147483648); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(8, -2147483648); - let r: i32x2 = transmute(vqrshl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_s32() { - let a: i32x4 = i32x4::new(2, -2147483648, 0x7F_FF_FF_FF, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(8, -2147483648, 0x7F_FF_FF_FF, 12); - let r: i32x4 = transmute(vqrshlq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_s64() { - let a: i64x1 = i64x1::new(2); - let b: i64x1 = i64x1::new(2); - let e: i64x1 = i64x1::new(8); - let r: i64x1 = transmute(vqrshl_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_s64() { - let a: i64x2 = i64x2::new(2, -9223372036854775808); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(8, -9223372036854775808); - let r: i64x2 = transmute(vqrshlq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_u8() { - let a: u8x8 = u8x8::new(2, 0, 0xFF, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x8 = u8x8::new(8, 0, 0xFF, 12, 16, 20, 24, 28); - let r: u8x8 = transmute(vqrshl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_u8() { - let a: u8x16 = u8x16::new(2, 0, 0xFF, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x16 = u8x16::new(8, 0, 0xFF, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: u8x16 = transmute(vqrshlq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_u16() { - let a: u16x4 = u16x4::new(2, 0, 0xFF_FF, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: u16x4 = u16x4::new(8, 0, 0xFF_FF, 12); - let r: u16x4 = transmute(vqrshl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_u16() { - let a: u16x8 = u16x8::new(2, 0, 0xFF_FF, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(8, 0, 0xFF_FF, 12, 16, 20, 24, 28); - let r: u16x8 = transmute(vqrshlq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_u32() { - let a: u32x2 = u32x2::new(2, 0); - let b: i32x2 = i32x2::new(2, 2); - let e: u32x2 = u32x2::new(8, 0); - let r: u32x2 = transmute(vqrshl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_u32() { - let a: u32x4 = u32x4::new(2, 0, 0xFF_FF_FF_FF, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: u32x4 = u32x4::new(8, 0, 0xFF_FF_FF_FF, 12); - let r: u32x4 = transmute(vqrshlq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshl_u64() { - let a: u64x1 = u64x1::new(2); - let b: i64x1 = i64x1::new(2); - let e: u64x1 = u64x1::new(8); - let r: u64x1 = transmute(vqrshl_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshlq_u64() { - let a: u64x2 = u64x2::new(2, 0); - let b: i64x2 = i64x2::new(2, 2); - let e: u64x2 = u64x2::new(8, 0); - let r: u64x2 = transmute(vqrshlq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_s16() { - let a: i16x8 = i16x8::new(-32768, 4, 8, 12, 16, 20, 24, 28); - let e: i8x8 = i8x8::new(-128, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vqrshrn_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_s32() { - let a: i32x4 = i32x4::new(-2147483648, 4, 8, 12); - let e: i16x4 = i16x4::new(-32768, 1, 2, 3); - let r: i16x4 = transmute(vqrshrn_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_s64() { - let a: i64x2 = i64x2::new(-9223372036854775808, 4); - let e: i32x2 = i32x2::new(-2147483648, 1); - let r: i32x2 = transmute(vqrshrn_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_u16() { - let a: u16x8 = u16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vqrshrn_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_u32() { - let a: u32x4 = u32x4::new(0, 4, 8, 12); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vqrshrn_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrn_n_u64() { - let a: u64x2 = u64x2::new(0, 4); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vqrshrn_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_n_s16() { - let a: i16x8 = i16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vqrshrun_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_n_s32() { - let a: i32x4 = i32x4::new(0, 4, 8, 12); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vqrshrun_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqrshrun_n_s64() { - let a: i64x2 = i64x2::new(0, 4); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vqrshrun_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: i8x8 = transmute(vqshl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: i8x16 = transmute(vqshlq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(0, 4, 8, 12); - let r: i16x4 = transmute(vqshl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: i16x8 = transmute(vqshlq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_s32() { - let a: i32x2 = i32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(0, 4); - let r: i32x2 = transmute(vqshl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(0, 4, 8, 12); - let r: i32x4 = transmute(vqshlq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_s64() { - let a: i64x1 = i64x1::new(0); - let b: i64x1 = i64x1::new(2); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vqshl_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_s64() { - let a: i64x2 = i64x2::new(0, 1); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(0, 4); - let r: i64x2 = transmute(vqshlq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x8 = u8x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u8x8 = transmute(vqshl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x16 = u8x16::new(0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: u8x16 = transmute(vqshlq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: u16x4 = u16x4::new(0, 4, 8, 12); - let r: u16x4 = transmute(vqshl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u16x8 = transmute(vqshlq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_u32() { - let a: u32x2 = u32x2::new(0, 1); - let b: i32x2 = i32x2::new(2, 2); - let e: u32x2 = u32x2::new(0, 4); - let r: u32x2 = transmute(vqshl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: u32x4 = u32x4::new(0, 4, 8, 12); - let r: u32x4 = transmute(vqshlq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_u64() { - let a: u64x1 = u64x1::new(0); - let b: i64x1 = i64x1::new(2); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vqshl_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_u64() { - let a: u64x2 = u64x2::new(0, 1); - let b: i64x2 = i64x2::new(2, 2); - let e: u64x2 = u64x2::new(0, 4); - let r: u64x2 = transmute(vqshlq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x8 = i8x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: i8x8 = transmute(vqshl_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: i8x16 = transmute(vqshlq_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i16x4 = i16x4::new(0, 4, 8, 12); - let r: i16x4 = transmute(vqshl_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: i16x8 = transmute(vqshlq_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i32x2 = i32x2::new(0, 4); - let r: i32x2 = transmute(vqshl_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: i32x4 = i32x4::new(0, 4, 8, 12); - let r: i32x4 = transmute(vqshlq_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_s64() { - let a: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vqshl_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 4); - let r: i64x2 = transmute(vqshlq_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u8x8 = transmute(vqshl_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: u8x16 = transmute(vqshlq_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0, 4, 8, 12); - let r: u16x4 = transmute(vqshl_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u16x8 = transmute(vqshlq_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: u32x2 = u32x2::new(0, 4); - let r: u32x2 = transmute(vqshl_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0, 4, 8, 12); - let r: u32x4 = transmute(vqshlq_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshl_n_u64() { - let a: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vqshl_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlq_n_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: u64x2 = u64x2::new(0, 4); - let r: u64x2 = transmute(vqshlq_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlu_n_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u8x8 = transmute(vqshlu_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlu_n_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0, 4, 8, 12); - let r: u16x4 = transmute(vqshlu_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlu_n_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: u32x2 = u32x2::new(0, 4); - let r: u32x2 = transmute(vqshlu_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshlu_n_s64() { - let a: i64x1 = i64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vqshlu_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshluq_n_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60); - let r: u8x16 = transmute(vqshluq_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshluq_n_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let r: u16x8 = transmute(vqshluq_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshluq_n_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0, 4, 8, 12); - let r: u32x4 = transmute(vqshluq_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshluq_n_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u64x2 = u64x2::new(0, 4); - let r: u64x2 = transmute(vqshluq_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_s16() { - let a: i16x8 = i16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vqshrn_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_s32() { - let a: i32x4 = i32x4::new(0, 4, 8, 12); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vqshrn_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_s64() { - let a: i64x2 = i64x2::new(0, 4); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vqshrn_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_u16() { - let a: u16x8 = u16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vqshrn_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_u32() { - let a: u32x4 = u32x4::new(0, 4, 8, 12); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vqshrn_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrn_n_u64() { - let a: u64x2 = u64x2::new(0, 4); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vqshrn_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_n_s16() { - let a: i16x8 = i16x8::new(0, 4, 8, 12, 16, 20, 24, 28); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vqshrun_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_n_s32() { - let a: i32x4 = i32x4::new(0, 4, 8, 12); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vqshrun_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqshrun_n_s64() { - let a: i64x2 = i64x2::new(0, 4); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vqshrun_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrte_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let e: f32x2 = f32x2::new(0.998046875, 0.705078125); - let r: f32x2 = transmute(vrsqrte_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrteq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e: f32x4 = f32x4::new(0.998046875, 0.705078125, 0.576171875, 0.4990234375); - let r: f32x4 = transmute(vrsqrteq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrte_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(4294967295, 4294967295); - let r: u32x2 = transmute(vrsqrte_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrteq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(4294967295, 4294967295, 4294967295, 4294967295); - let r: u32x4 = transmute(vrsqrteq_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrts_f32() { - let a: f32x2 = f32x2::new(1.0, 2.0); - let b: f32x2 = f32x2::new(1.0, 2.0); - let e: f32x2 = f32x2::new(1., -0.5); - let r: f32x2 = transmute(vrsqrts_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsqrtsq_f32() { - let a: f32x4 = f32x4::new(1.0, 2.0, 3.0, 4.0); - let b: f32x4 = f32x4::new(1.0, 2.0, 3.0, 4.0); - let e: f32x4 = f32x4::new(1., -0.5, -3.0, -6.5); - let r: f32x4 = transmute(vrsqrtsq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpe_f32() { - let a: f32x2 = f32x2::new(4.0, 3.0); - let e: f32x2 = f32x2::new(0.24951171875, 0.3330078125); - let r: f32x2 = transmute(vrecpe_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpeq_f32() { - let a: f32x4 = f32x4::new(4.0, 3.0, 2.0, 1.0); - let e: f32x4 = f32x4::new(0.24951171875, 0.3330078125, 0.4990234375, 0.998046875); - let r: f32x4 = transmute(vrecpeq_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpe_u32() { - let a: u32x2 = u32x2::new(4, 3); - let e: u32x2 = u32x2::new(4294967295, 4294967295); - let r: u32x2 = transmute(vrecpe_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpeq_u32() { - let a: u32x4 = u32x4::new(4, 3, 2, 1); - let e: u32x4 = u32x4::new(4294967295, 4294967295, 4294967295, 4294967295); - let r: u32x4 = transmute(vrecpeq_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecps_f32() { - let a: f32x2 = f32x2::new(4.0, 3.0); - let b: f32x2 = f32x2::new(4.0, 3.0); - let e: f32x2 = f32x2::new(-14., -7.); - let r: f32x2 = transmute(vrecps_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrecpsq_f32() { - let a: f32x4 = f32x4::new(4.0, 3.0, 2.0, 1.0); - let b: f32x4 = f32x4::new(4.0, 3.0, 2.0, 1.0); - let e: f32x4 = f32x4::new(-14., -7., -2., 1.); - let r: f32x4 = transmute(vrecpsq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vreinterpret_s8_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_p8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vreinterpret_s8_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_p16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_s16_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_s16_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_u64() { - let a: u64x1 = u64x1::new(0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vreinterpretq_s8_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_p8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vreinterpretq_s8_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_p16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_s16_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_s16_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_p8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vreinterpret_u8_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u8x8 = transmute(vreinterpret_u8_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_p16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vreinterpret_u16_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vreinterpret_u16_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_s64() { - let a: i64x1 = i64x1::new(0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_p8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vreinterpretq_u8_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: u8x16 = transmute(vreinterpretq_u8_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_p16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vreinterpretq_u16_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vreinterpretq_u16_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_s8() { - let a: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vreinterpret_p8_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_u8() { - let a: u8x8 = u8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x8 = i8x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i8x8 = transmute(vreinterpret_p8_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_p16_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_p16_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_s8() { - let a: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vreinterpretq_p8_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_u8() { - let a: u8x16 = u8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let e: i8x16 = i8x16::new(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15); - let r: i8x16 = transmute(vreinterpretq_p8_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_p16_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_p16_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_s8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_s8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_p16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_s8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i16x4 = i16x4::new(0, 0, 1, 0); - let r: i16x4 = transmute(vreinterpret_s16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: i16x4 = i16x4::new(0, 0, 1, 0); - let r: i16x4 = transmute(vreinterpret_s16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_s64() { - let a: i64x1 = i64x1::new(0); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vreinterpret_s32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_u64() { - let a: u64x1 = u64x1::new(0); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vreinterpret_s32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_s8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_s8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_p16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_s8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i16x8 = transmute(vreinterpretq_s16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i16x8 = transmute(vreinterpretq_s16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i32x4 = i32x4::new(0, 0, 1, 0); - let r: i32x4 = transmute(vreinterpretq_s32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i32x4 = i32x4::new(0, 0, 1, 0); - let r: i32x4 = transmute(vreinterpretq_s32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_p16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: u8x8 = transmute(vreinterpret_u8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: u8x8 = transmute(vreinterpret_u8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: u8x8 = transmute(vreinterpret_u8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: u16x4 = u16x4::new(0, 0, 1, 0); - let r: u16x4 = transmute(vreinterpret_u16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: u16x4 = u16x4::new(0, 0, 1, 0); - let r: u16x4 = transmute(vreinterpret_u16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_s64() { - let a: i64x1 = i64x1::new(0); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vreinterpret_u32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_u64() { - let a: u64x1 = u64x1::new(0); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vreinterpret_u32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_p16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: u8x16 = transmute(vreinterpretq_u8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: u8x16 = transmute(vreinterpretq_u8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: u8x16 = transmute(vreinterpretq_u8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u16x8 = u16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: u16x8 = transmute(vreinterpretq_u16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: u16x8 = u16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: u16x8 = transmute(vreinterpretq_u16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u32x4 = u32x4::new(0, 0, 1, 0); - let r: u32x4 = transmute(vreinterpretq_u32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: u32x4 = u32x4::new(0, 0, 1, 0); - let r: u32x4 = transmute(vreinterpretq_u32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_p16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_p8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_s16() { - let a: i16x4 = i16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_p8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_u16() { - let a: u16x4 = u16x4::new(0, 1, 2, 3); - let e: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i8x8 = transmute(vreinterpret_p8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i16x4 = i16x4::new(0, 0, 1, 0); - let r: i16x4 = transmute(vreinterpret_p16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: i16x4 = i16x4::new(0, 0, 1, 0); - let r: i16x4 = transmute(vreinterpret_p16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_p16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_p8_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_s16() { - let a: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_p8_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_u16() { - let a: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let e: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let r: i8x16 = transmute(vreinterpretq_p8_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i16x8 = transmute(vreinterpretq_p16_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let r: i16x8 = transmute(vreinterpretq_p16_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_s32_p64() { - let a: i64x1 = i64x1::new(0); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vreinterpret_s32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_u32_p64() { - let a: i64x1 = i64x1::new(0); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vreinterpret_u32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s32_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i32x4 = i32x4::new(0, 0, 1, 0); - let r: i32x4 = transmute(vreinterpretq_s32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u32_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u32x4 = u32x4::new(0, 0, 1, 0); - let r: u32x4 = transmute(vreinterpretq_u32_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s64_p128() { - let a: p128 = 0; - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_s64_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u64_p128() { - let a: p128 = 0; - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vreinterpretq_u64_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_p128() { - let a: p128 = 0; - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_p64_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_p8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_s16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_s8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_s16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_u8() { - let a: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_s16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_p16() { - let a: i16x4 = i16x4::new(0, 0, 1, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_s16() { - let a: i16x4 = i16x4::new(0, 0, 1, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_u16() { - let a: u16x4 = u16x4::new(0, 0, 1, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_s32() { - let a: i32x2 = i32x2::new(0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_u32() { - let a: u32x2 = u32x2::new(0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_p8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_s16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_s8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_s16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_u8() { - let a: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_s16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_p16() { - let a: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_s16() { - let a: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_u16() { - let a: u16x8 = u16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_s32() { - let a: i32x4 = i32x4::new(0, 0, 1, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_u32() { - let a: u32x4 = u32x4::new(0, 0, 1, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_p8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vreinterpret_u16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_s8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vreinterpret_u16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_u8() { - let a: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u16x4 = u16x4::new(0, 1, 2, 3); - let r: u16x4 = transmute(vreinterpret_u16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_p16() { - let a: i16x4 = i16x4::new(0, 0, 1, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_s16() { - let a: i16x4 = i16x4::new(0, 0, 1, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_u16() { - let a: u16x4 = u16x4::new(0, 0, 1, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_s32() { - let a: i32x2 = i32x2::new(0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_u32() { - let a: u32x2 = u32x2::new(0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_p8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vreinterpretq_u16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_s8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vreinterpretq_u16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_u8() { - let a: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: u16x8 = u16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: u16x8 = transmute(vreinterpretq_u16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_p16() { - let a: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_s16() { - let a: i16x8 = i16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_u16() { - let a: u16x8 = u16x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_s32() { - let a: i32x4 = i32x4::new(0, 0, 1, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_u32() { - let a: u32x4 = u32x4::new(0, 0, 1, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_p8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_p16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_s8() { - let a: i8x8 = i8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_p16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_u8() { - let a: u8x8 = u8x8::new(0, 0, 1, 0, 2, 0, 3, 0); - let e: i16x4 = i16x4::new(0, 1, 2, 3); - let r: i16x4 = transmute(vreinterpret_p16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_p8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_p16_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_s8() { - let a: i8x16 = i8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_p16_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_u8() { - let a: u8x16 = u8x16::new(0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0); - let e: i16x8 = i16x8::new(0, 1, 2, 3, 4, 5, 6, 7); - let r: i16x8 = transmute(vreinterpretq_p16_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_s32() { - let a: i32x2 = i32x2::new(0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_u32() { - let a: u32x2 = u32x2::new(0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_s32() { - let a: i32x4 = i32x4::new(0, 0, 1, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_u32() { - let a: u32x4 = u32x4::new(0, 0, 1, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_s64() { - let a: i64x2 = i64x2::new(0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_s64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_u64() { - let a: u64x2 = u64x2::new(0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_u64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_p64() { - let a: i64x2 = i64x2::new(0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_p64(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_s64() { - let a: i64x1 = i64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_s16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_u64() { - let a: u64x1 = u64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_s16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_s64() { - let a: i64x1 = i64x1::new(0); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vreinterpret_u16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_u64() { - let a: u64x1 = u64x1::new(0); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vreinterpret_u16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_s32() { - let a: i32x2 = i32x2::new(0, 1); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_u32() { - let a: u32x2 = u32x2::new(0, 1); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_s64() { - let a: i64x1 = i64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_p16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_u64() { - let a: u64x1 = u64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_p16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_s32() { - let a: i32x4 = i32x4::new(0, 1, 2, 3); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_u32() { - let a: u32x4 = u32x4::new(0, 1, 2, 3); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_s16_p64() { - let a: i64x1 = i64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_s16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_u16_p64() { - let a: i64x1 = i64x1::new(0); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vreinterpret_u16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p16_p64() { - let a: i64x1 = i64x1::new(0); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_p16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s16_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u16_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p16_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s32_p128() { - let a: p128 = 0; - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vreinterpretq_s32_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u32_p128() { - let a: p128 = 0; - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vreinterpretq_u32_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i32x2 = i32x2::new(0, 1); - let r: i32x2 = transmute(vreinterpret_s32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_p16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_s16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_u16() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: i32x4 = i32x4::new(0, 1, 2, 3); - let r: i32x4 = transmute(vreinterpretq_s32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u32x2 = u32x2::new(0, 1); - let r: u32x2 = transmute(vreinterpret_u32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_p16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_s16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_u16() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0); - let e: u32x4 = u32x4::new(0, 1, 2, 3); - let r: u32x4 = transmute(vreinterpretq_u32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_p16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_s16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_u16() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 1, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_s32() { - let a: i32x4 = i32x4::new(0, 0, 0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_s32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_u32() { - let a: u32x4 = u32x4::new(0, 0, 0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_u32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_s64() { - let a: i64x1 = i64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_u64() { - let a: u64x1 = u64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_s64() { - let a: i64x1 = i64x1::new(0); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_u64() { - let a: u64x1 = u64x1::new(0); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_s64() { - let a: i64x1 = i64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_u64() { - let a: u64x1 = u64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_s64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_u64() { - let a: u64x2 = u64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_s8_p64() { - let a: i64x1 = i64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_u8_p64() { - let a: i64x1 = i64x1::new(0); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p8_p64() { - let a: i64x1 = i64x1::new(0); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s8_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u8_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p8_p64() { - let a: i64x2 = i64x2::new(0, 1); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_p64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s16_p128() { - let a: p128 = 0; - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u16_p128() { - let a: p128 = 0; - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p16_p128() { - let a: p128 = 0; - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_s64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: u64x2 = u64x2::new(0, 1); - let r: u64x2 = transmute(vreinterpretq_u64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpret_p64_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_p64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p64_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0); - let e: i64x2 = i64x2::new(0, 1); - let r: i64x2 = transmute(vreinterpretq_p64_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_s16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_u16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_p16(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_s8() { - let a: i8x16 = i8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 1; - let r: p128 = vreinterpretq_p128_s8(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_u8() { - let a: u8x16 = u8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 1; - let r: p128 = vreinterpretq_p128_u8(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p128_p8() { - let a: i8x16 = i8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: p128 = 1; - let r: p128 = vreinterpretq_p128_p8(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_s8_p128() { - let a: p128 = 1; - let e: i8x16 = i8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_u8_p128() { - let a: p128 = 1; - let e: u8x16 = u8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vreinterpretq_p8_p128() { - let a: p128 = 1; - let e: i8x16 = i8x16::new(1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s8_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_s8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s16_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_s16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s32_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i32x2 = i32x2::new(0, 0); - let r: i32x2 = transmute(vreinterpret_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_s64_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i64x1 = i64x1::new(0); - let r: i64x1 = transmute(vreinterpret_s64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s8_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_s8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s16_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_s16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s32_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i32x4 = i32x4::new(0, 0, 0, 0); - let r: i32x4 = transmute(vreinterpretq_s32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_s64_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i64x2 = i64x2::new(0, 0); - let r: i64x2 = transmute(vreinterpretq_s64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u8_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vreinterpret_u8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u16_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vreinterpret_u16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u32_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vreinterpret_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_u64_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: u64x1 = u64x1::new(0); - let r: u64x1 = transmute(vreinterpret_u64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u8_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x16 = transmute(vreinterpretq_u8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u16_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u16x8 = transmute(vreinterpretq_u16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u32_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: u32x4 = u32x4::new(0, 0, 0, 0); - let r: u32x4 = transmute(vreinterpretq_u32_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_u64_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: u64x2 = u64x2::new(0, 0); - let r: u64x2 = transmute(vreinterpretq_u64_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p8_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vreinterpret_p8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_p16_f32() { - let a: f32x2 = f32x2::new(0., 0.); - let e: i16x4 = i16x4::new(0, 0, 0, 0); - let r: i16x4 = transmute(vreinterpret_p16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p8_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let r: i8x16 = transmute(vreinterpretq_p8_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p16_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: i16x8 = transmute(vreinterpretq_p16_f32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_p128_f32() { - let a: f32x4 = f32x4::new(0., 0., 0., 0.); - let e: p128 = 0; - let r: p128 = vreinterpretq_p128_f32(transmute(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_s8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_s16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_s32() { - let a: i32x2 = i32x2::new(0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_s64() { - let a: i64x1 = i64x1::new(0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_s8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_s16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_s32() { - let a: i32x4 = i32x4::new(0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_s64() { - let a: i64x2 = i64x2::new(0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_s64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_u8() { - let a: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_u16() { - let a: u16x4 = u16x4::new(0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_u32() { - let a: u32x2 = u32x2::new(0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_u64() { - let a: u64x1 = u64x1::new(0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_u8() { - let a: u8x16 = u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_u8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_u16() { - let a: u16x8 = u16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_u16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_u32() { - let a: u32x4 = u32x4::new(0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_u32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_u64() { - let a: u64x2 = u64x2::new(0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_u64(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_p8() { - let a: i8x8 = i8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpret_f32_p16() { - let a: i16x4 = i16x4::new(0, 0, 0, 0); - let e: f32x2 = f32x2::new(0., 0.); - let r: f32x2 = transmute(vreinterpret_f32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_p8() { - let a: i8x16 = i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_p8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_p16() { - let a: i16x8 = i16x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_p16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vreinterpretq_f32_p128() { - let a: p128 = 0; - let e: f32x4 = f32x4::new(0., 0., 0., 0.); - let r: f32x4 = transmute(vreinterpretq_f32_p128(a)); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i8x8 = transmute(vrshl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: i8x16 = transmute(vrshlq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(4, 8, 12, 16); - let r: i16x4 = transmute(vrshl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i16x8 = transmute(vrshlq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(4, 8); - let r: i32x2 = transmute(vrshl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vrshlq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(2); - let e: i64x1 = i64x1::new(4); - let r: i64x1 = transmute(vrshl_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vrshlq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u8x8 = transmute(vrshl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: u8x16 = transmute(vrshlq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: u16x4 = u16x4::new(4, 8, 12, 16); - let r: u16x4 = transmute(vrshl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u16x8 = transmute(vrshlq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: i32x2 = i32x2::new(2, 2); - let e: u32x2 = u32x2::new(4, 8); - let r: u32x2 = transmute(vrshl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: u32x4 = u32x4::new(4, 8, 12, 16); - let r: u32x4 = transmute(vrshlq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshl_u64() { - let a: u64x1 = u64x1::new(1); - let b: i64x1 = i64x1::new(2); - let e: u64x1 = u64x1::new(4); - let r: u64x1 = transmute(vrshl_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshlq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: i64x2 = i64x2::new(2, 2); - let e: u64x2 = u64x2::new(4, 8); - let r: u64x2 = transmute(vrshlq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_s8() { - let a: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vrshr_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_s8() { - let a: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vrshrq_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_s16() { - let a: i16x4 = i16x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vrshr_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_s16() { - let a: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vrshrq_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_s32() { - let a: i32x2 = i32x2::new(4, 8); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vrshr_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_s32() { - let a: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i32x4 = i32x4::new(1, 2, 3, 4); - let r: i32x4 = transmute(vrshrq_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_s64() { - let a: i64x1 = i64x1::new(4); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vrshr_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_s64() { - let a: i64x2 = i64x2::new(4, 8); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vrshrq_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_u8() { - let a: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vrshr_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_u8() { - let a: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vrshrq_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_u16() { - let a: u16x4 = u16x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vrshr_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_u16() { - let a: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vrshrq_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_u32() { - let a: u32x2 = u32x2::new(4, 8); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vrshr_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_u32() { - let a: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vrshrq_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshr_n_u64() { - let a: u64x1 = u64x1::new(4); - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vrshr_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrq_n_u64() { - let a: u64x2 = u64x2::new(4, 8); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vrshrq_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_s16() { - let a: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vrshrn_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_s32() { - let a: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vrshrn_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_s64() { - let a: i64x2 = i64x2::new(4, 8); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vrshrn_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_u16() { - let a: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vrshrn_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_u32() { - let a: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vrshrn_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrshrn_n_u64() { - let a: u64x2 = u64x2::new(4, 8); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vrshrn_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: i8x8 = transmute(vrsra_n_s8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: i8x16 = i8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); - let r: i8x16 = transmute(vrsraq_n_s8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(2, 3, 4, 5); - let r: i16x4 = transmute(vrsra_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i16x8 = i16x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: i16x8 = transmute(vrsraq_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(4, 8); - let e: i32x2 = i32x2::new(2, 3); - let r: i32x2 = transmute(vrsra_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i32x4 = i32x4::new(2, 3, 4, 5); - let r: i32x4 = transmute(vrsraq_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(4); - let e: i64x1 = i64x1::new(2); - let r: i64x1 = transmute(vrsra_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_s64() { - let a: i64x2 = i64x2::new(1, 1); - let b: i64x2 = i64x2::new(4, 8); - let e: i64x2 = i64x2::new(2, 3); - let r: i64x2 = transmute(vrsraq_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: u8x8 = transmute(vrsra_n_u8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: u8x16 = u8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); - let r: u8x16 = transmute(vrsraq_n_u8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 1); - let b: u16x4 = u16x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(2, 3, 4, 5); - let r: u16x4 = transmute(vrsra_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u16x8 = u16x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: u16x8 = transmute(vrsraq_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_u32() { - let a: u32x2 = u32x2::new(1, 1); - let b: u32x2 = u32x2::new(4, 8); - let e: u32x2 = u32x2::new(2, 3); - let r: u32x2 = transmute(vrsra_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 1); - let b: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u32x4 = u32x4::new(2, 3, 4, 5); - let r: u32x4 = transmute(vrsraq_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsra_n_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(4); - let e: u64x1 = u64x1::new(2); - let r: u64x1 = transmute(vrsra_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsraq_n_u64() { - let a: u64x2 = u64x2::new(1, 1); - let b: u64x2 = u64x2::new(4, 8); - let e: u64x2 = u64x2::new(2, 3); - let r: u64x2 = transmute(vrsraq_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_s16() { - let a: i16x8 = i16x8::new(0x7F_FF, -32768, 0, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(-128, -128, 0, 0, 0, 0, 0, 0); - let r: i8x8 = transmute(vrsubhn_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_s32() { - let a: i32x4 = i32x4::new(0x7F_FF_FF_FF, -2147483648, 0, 4); - let b: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(-32768, -32768, 0, 0); - let r: i16x4 = transmute(vrsubhn_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_s64() { - let a: i64x2 = i64x2::new(0x7F_FF_FF_FF_FF_FF_FF_FF, -9223372036854775808); - let b: i64x2 = i64x2::new(1, 2); - let e: i32x2 = i32x2::new(-2147483648, -2147483648); - let r: i32x2 = transmute(vrsubhn_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_u16() { - let a: u16x8 = u16x8::new(0xFF_FF, 0, 3, 4, 5, 6, 7, 8); - let b: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(0, 0, 0, 0, 0, 0, 0, 0); - let r: u8x8 = transmute(vrsubhn_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_u32() { - let a: u32x4 = u32x4::new(0xFF_FF_FF_FF, 0, 3, 4); - let b: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(0, 0, 0, 0); - let r: u16x4 = transmute(vrsubhn_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vrsubhn_u64() { - let a: u64x2 = u64x2::new(0xFF_FF_FF_FF_FF_FF_FF_FF, 0); - let b: u64x2 = u64x2::new(1, 2); - let e: u32x2 = u32x2::new(0, 0); - let r: u32x2 = transmute(vrsubhn_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_s8() { - let a: i8 = 1; - let b: i8x8 = i8x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vset_lane_s8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_s16() { - let a: i16 = 1; - let b: i16x4 = i16x4::new(0, 2, 3, 4); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vset_lane_s16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_s32() { - let a: i32 = 1; - let b: i32x2 = i32x2::new(0, 2); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vset_lane_s32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_s64() { - let a: i64 = 1; - let b: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vset_lane_s64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_u8() { - let a: u8 = 1; - let b: u8x8 = u8x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vset_lane_u8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_u16() { - let a: u16 = 1; - let b: u16x4 = u16x4::new(0, 2, 3, 4); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vset_lane_u16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_u32() { - let a: u32 = 1; - let b: u32x2 = u32x2::new(0, 2); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vset_lane_u32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_u64() { - let a: u64 = 1; - let b: u64x1 = u64x1::new(0); - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vset_lane_u64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_p8() { - let a: p8 = 1; - let b: i8x8 = i8x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vset_lane_p8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_p16() { - let a: p16 = 1; - let b: i16x4 = i16x4::new(0, 2, 3, 4); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vset_lane_p16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vset_lane_p64() { - let a: p64 = 1; - let b: i64x1 = i64x1::new(0); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vset_lane_p64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_s8() { - let a: i8 = 1; - let b: i8x16 = i8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vsetq_lane_s8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_s16() { - let a: i16 = 1; - let b: i16x8 = i16x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vsetq_lane_s16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_s32() { - let a: i32 = 1; - let b: i32x4 = i32x4::new(0, 2, 3, 4); - let e: i32x4 = i32x4::new(1, 2, 3, 4); - let r: i32x4 = transmute(vsetq_lane_s32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_s64() { - let a: i64 = 1; - let b: i64x2 = i64x2::new(0, 2); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vsetq_lane_s64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_u8() { - let a: u8 = 1; - let b: u8x16 = u8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vsetq_lane_u8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_u16() { - let a: u16 = 1; - let b: u16x8 = u16x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vsetq_lane_u16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_u32() { - let a: u32 = 1; - let b: u32x4 = u32x4::new(0, 2, 3, 4); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vsetq_lane_u32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_u64() { - let a: u64 = 1; - let b: u64x2 = u64x2::new(0, 2); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vsetq_lane_u64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_p8() { - let a: p8 = 1; - let b: i8x16 = i8x16::new(0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vsetq_lane_p8::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_p16() { - let a: p16 = 1; - let b: i16x8 = i16x8::new(0, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vsetq_lane_p16::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon,aes")] - unsafe fn test_vsetq_lane_p64() { - let a: p64 = 1; - let b: i64x2 = i64x2::new(0, 2); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vsetq_lane_p64::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vset_lane_f32() { - let a: f32 = 1.; - let b: f32x2 = f32x2::new(0., 2.); - let e: f32x2 = f32x2::new(1., 2.); - let r: f32x2 = transmute(vset_lane_f32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsetq_lane_f32() { - let a: f32 = 1.; - let b: f32x4 = f32x4::new(0., 2., 3., 4.); - let e: f32x4 = f32x4::new(1., 2., 3., 4.); - let r: f32x4 = transmute(vsetq_lane_f32::<0>(a, transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i8x8 = transmute(vshl_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: i8x16 = transmute(vshlq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: i16x4 = i16x4::new(4, 8, 12, 16); - let r: i16x4 = transmute(vshl_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i16x8 = transmute(vshlq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(2, 2); - let e: i32x2 = i32x2::new(4, 8); - let r: i32x2 = transmute(vshl_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vshlq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(2); - let e: i64x1 = i64x1::new(4); - let r: i64x1 = transmute(vshl_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_s64() { - let a: i64x2 = i64x2::new(1, 2); - let b: i64x2 = i64x2::new(2, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vshlq_s64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u8x8 = transmute(vshl_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let b: i8x16 = i8x16::new(2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2); - let e: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: u8x16 = transmute(vshlq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(2, 2, 2, 2); - let e: u16x4 = u16x4::new(4, 8, 12, 16); - let r: u16x4 = transmute(vshl_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i16x8 = i16x8::new(2, 2, 2, 2, 2, 2, 2, 2); - let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u16x8 = transmute(vshlq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: i32x2 = i32x2::new(2, 2); - let e: u32x2 = u32x2::new(4, 8); - let r: u32x2 = transmute(vshl_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: i32x4 = i32x4::new(2, 2, 2, 2); - let e: u32x4 = u32x4::new(4, 8, 12, 16); - let r: u32x4 = transmute(vshlq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_u64() { - let a: u64x1 = u64x1::new(1); - let b: i64x1 = i64x1::new(2); - let e: u64x1 = u64x1::new(4); - let r: u64x1 = transmute(vshl_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_u64() { - let a: u64x2 = u64x2::new(1, 2); - let b: i64x2 = i64x2::new(2, 2); - let e: u64x2 = u64x2::new(4, 8); - let r: u64x2 = transmute(vshlq_u64(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i8x8 = transmute(vshl_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_s8() { - let a: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: i8x16 = transmute(vshlq_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i16x4 = i16x4::new(4, 8, 12, 16); - let r: i16x4 = transmute(vshl_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_s16() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i16x8 = transmute(vshlq_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_s32() { - let a: i32x2 = i32x2::new(1, 2); - let e: i32x2 = i32x2::new(4, 8); - let r: i32x2 = transmute(vshl_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_s32() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vshlq_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u8x8 = transmute(vshl_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_u8() { - let a: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let e: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let r: u8x16 = transmute(vshlq_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u16x4 = u16x4::new(4, 8, 12, 16); - let r: u16x4 = transmute(vshl_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_u16() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u16x8 = transmute(vshlq_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: u32x2 = u32x2::new(4, 8); - let r: u32x2 = transmute(vshl_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_u32() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(4, 8, 12, 16); - let r: u32x4 = transmute(vshlq_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_s64() { - let a: i64x1 = i64x1::new(1); - let e: i64x1 = i64x1::new(4); - let r: i64x1 = transmute(vshl_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_s64() { - let a: i64x2 = i64x2::new(1, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vshlq_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshl_n_u64() { - let a: u64x1 = u64x1::new(1); - let e: u64x1 = u64x1::new(4); - let r: u64x1 = transmute(vshl_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshlq_n_u64() { - let a: u64x2 = u64x2::new(1, 2); - let e: u64x2 = u64x2::new(4, 8); - let r: u64x2 = transmute(vshlq_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly8x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_s8() { - let a: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: i16x8 = transmute(vshll_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_s16() { - let a: i16x4 = i16x4::new(1, 2, 3, 4); - let e: i32x4 = i32x4::new(4, 8, 12, 16); - let r: i32x4 = transmute(vshll_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzp_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 2, 4, 6]); + let b0: poly16x4_t = simd_shuffle!(a, b, [1, 3, 5, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_s32() { - let a: i32x2 = i32x2::new(1, 2); - let e: i64x2 = i64x2::new(4, 8); - let r: i64x2 = transmute(vshll_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Unzip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzpq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vuzp))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(uzp) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vuzpq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 2, 4, 6, 8, 10, 12, 14]); + let b0: poly16x8_t = simd_shuffle!(a, b, [1, 3, 5, 7, 9, 11, 13, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_u8() { - let a: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let e: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let r: u16x8 = transmute(vshll_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_f32(a: float32x2_t, b: float32x2_t) -> float32x2x2_t { + let a0: float32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: float32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_u16() { - let a: u16x4 = u16x4::new(1, 2, 3, 4); - let e: u32x4 = u32x4::new(4, 8, 12, 16); - let r: u32x4 = transmute(vshll_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_s32(a: int32x2_t, b: int32x2_t) -> int32x2x2_t { + let a0: int32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: int32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshll_n_u32() { - let a: u32x2 = u32x2::new(1, 2); - let e: u64x2 = u64x2::new(4, 8); - let r: u64x2 = transmute(vshll_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vtrn))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_u32(a: uint32x2_t, b: uint32x2_t) -> uint32x2x2_t { + let a0: uint32x2_t = simd_shuffle!(a, b, [0, 2]); + let b0: uint32x2_t = simd_shuffle!(a, b, [1, 3]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_s8() { - let a: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vshr_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_s8(a: int8x8_t, b: int8x8_t) -> int8x8x2_t { + let a0: int8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_s8() { - let a: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: i8x16 = i8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: i8x16 = transmute(vshrq_n_s8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_s16(a: int16x4_t, b: int16x4_t) -> int16x4x2_t { + let a0: int16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_s16() { - let a: i16x4 = i16x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vshr_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_u8(a: uint8x8_t, b: uint8x8_t) -> uint8x8x2_t { + let a0: uint8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_s16() { - let a: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i16x8 = transmute(vshrq_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_u16(a: uint16x4_t, b: uint16x4_t) -> uint16x4x2_t { + let a0: uint16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_s32() { - let a: i32x2 = i32x2::new(4, 8); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vshr_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_p8(a: poly8x8_t, b: poly8x8_t) -> poly8x8x2_t { + let a0: poly8x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly8x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_s32() { - let a: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i32x4 = i32x4::new(1, 2, 3, 4); - let r: i32x4 = transmute(vshrq_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vzip))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzip_p16(a: poly16x4_t, b: poly16x4_t) -> poly16x4x2_t { + let a0: poly16x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: poly16x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_s64() { - let a: i64x1 = i64x1::new(4); - let e: i64x1 = i64x1::new(1); - let r: i64x1 = transmute(vshr_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_f32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_f32(a: float32x4_t, b: float32x4_t) -> float32x4x2_t { + let a0: float32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: float32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_s64() { - let a: i64x2 = i64x2::new(4, 8); - let e: i64x2 = i64x2::new(1, 2); - let r: i64x2 = transmute(vshrq_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_s8(a: int8x16_t, b: int8x16_t) -> int8x16x2_t { + let a0: int8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: int8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_u8() { - let a: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vshr_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_s16(a: int16x8_t, b: int16x8_t) -> int16x8x2_t { + let a0: int16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: int16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_u8() { - let a: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: u8x16 = u8x16::new(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16); - let r: u8x16 = transmute(vshrq_n_u8::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_s32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_s32(a: int32x4_t, b: int32x4_t) -> int32x4x2_t { + let a0: int32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: int32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_u16() { - let a: u16x4 = u16x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vshr_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_u8(a: uint8x16_t, b: uint8x16_t) -> uint8x16x2_t { + let a0: uint8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: uint8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_u16() { - let a: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u16x8 = transmute(vshrq_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_u16(a: uint16x8_t, b: uint16x8_t) -> uint16x8x2_t { + let a0: uint16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: uint16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_u32() { - let a: u32x2 = u32x2::new(4, 8); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vshr_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_u32)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_u32(a: uint32x4_t, b: uint32x4_t) -> uint32x4x2_t { + let a0: uint32x4_t = simd_shuffle!(a, b, [0, 4, 1, 5]); + let b0: uint32x4_t = simd_shuffle!(a, b, [2, 6, 3, 7]); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_u32() { - let a: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u32x4 = u32x4::new(1, 2, 3, 4); - let r: u32x4 = transmute(vshrq_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p8)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_p8(a: poly8x16_t, b: poly8x16_t) -> poly8x16x2_t { + let a0: poly8x16_t = simd_shuffle!( + a, + b, + [0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23] + ); + let b0: poly8x16_t = simd_shuffle!( + a, + b, + [8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31] + ); + transmute((a0, b0)) +} - #[simd_test(enable = "neon")] - unsafe fn test_vshr_n_u64() { - let a: u64x1 = u64x1::new(4); - let e: u64x1 = u64x1::new(1); - let r: u64x1 = transmute(vshr_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrq_n_u64() { - let a: u64x2 = u64x2::new(4, 8); - let e: u64x2 = u64x2::new(1, 2); - let r: u64x2 = transmute(vshrq_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_s16() { - let a: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: i8x8 = transmute(vshrn_n_s16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_s32() { - let a: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(1, 2, 3, 4); - let r: i16x4 = transmute(vshrn_n_s32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_s64() { - let a: i64x2 = i64x2::new(4, 8); - let e: i32x2 = i32x2::new(1, 2); - let r: i32x2 = transmute(vshrn_n_s64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_u16() { - let a: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let r: u8x8 = transmute(vshrn_n_u16::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_u32() { - let a: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(1, 2, 3, 4); - let r: u16x4 = transmute(vshrn_n_u32::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vshrn_n_u64() { - let a: u64x2 = u64x2::new(4, 8); - let e: u32x2 = u32x2::new(1, 2); - let r: u32x2 = transmute(vshrn_n_u64::<2>(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_s8() { - let a: i8x8 = i8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x8 = i8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i8x8 = i8x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: i8x8 = transmute(vsra_n_s8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_s8() { - let a: i8x16 = i8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: i8x16 = i8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: i8x16 = i8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); - let r: i8x16 = transmute(vsraq_n_s8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_s16() { - let a: i16x4 = i16x4::new(1, 1, 1, 1); - let b: i16x4 = i16x4::new(4, 8, 12, 16); - let e: i16x4 = i16x4::new(2, 3, 4, 5); - let r: i16x4 = transmute(vsra_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_s16() { - let a: i16x8 = i16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: i16x8 = i16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: i16x8 = i16x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: i16x8 = transmute(vsraq_n_s16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_s32() { - let a: i32x2 = i32x2::new(1, 1); - let b: i32x2 = i32x2::new(4, 8); - let e: i32x2 = i32x2::new(2, 3); - let r: i32x2 = transmute(vsra_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_s32() { - let a: i32x4 = i32x4::new(1, 1, 1, 1); - let b: i32x4 = i32x4::new(4, 8, 12, 16); - let e: i32x4 = i32x4::new(2, 3, 4, 5); - let r: i32x4 = transmute(vsraq_n_s32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_s64() { - let a: i64x1 = i64x1::new(1); - let b: i64x1 = i64x1::new(4); - let e: i64x1 = i64x1::new(2); - let r: i64x1 = transmute(vsra_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_s64() { - let a: i64x2 = i64x2::new(1, 1); - let b: i64x2 = i64x2::new(4, 8); - let e: i64x2 = i64x2::new(2, 3); - let r: i64x2 = transmute(vsraq_n_s64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_u8() { - let a: u8x8 = u8x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x8 = u8x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u8x8 = u8x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: u8x8 = transmute(vsra_n_u8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_u8() { - let a: u8x16 = u8x16::new(1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1); - let b: u8x16 = u8x16::new(4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64); - let e: u8x16 = u8x16::new(2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17); - let r: u8x16 = transmute(vsraq_n_u8::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_u16() { - let a: u16x4 = u16x4::new(1, 1, 1, 1); - let b: u16x4 = u16x4::new(4, 8, 12, 16); - let e: u16x4 = u16x4::new(2, 3, 4, 5); - let r: u16x4 = transmute(vsra_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_u16() { - let a: u16x8 = u16x8::new(1, 1, 1, 1, 1, 1, 1, 1); - let b: u16x8 = u16x8::new(4, 8, 12, 16, 20, 24, 28, 32); - let e: u16x8 = u16x8::new(2, 3, 4, 5, 6, 7, 8, 9); - let r: u16x8 = transmute(vsraq_n_u16::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_u32() { - let a: u32x2 = u32x2::new(1, 1); - let b: u32x2 = u32x2::new(4, 8); - let e: u32x2 = u32x2::new(2, 3); - let r: u32x2 = transmute(vsra_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_u32() { - let a: u32x4 = u32x4::new(1, 1, 1, 1); - let b: u32x4 = u32x4::new(4, 8, 12, 16); - let e: u32x4 = u32x4::new(2, 3, 4, 5); - let r: u32x4 = transmute(vsraq_n_u32::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsra_n_u64() { - let a: u64x1 = u64x1::new(1); - let b: u64x1 = u64x1::new(4); - let e: u64x1 = u64x1::new(2); - let r: u64x1 = transmute(vsra_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vsraq_n_u64() { - let a: u64x2 = u64x2::new(1, 1); - let b: u64x2 = u64x2::new(4, 8); - let e: u64x2 = u64x2::new(2, 3); - let r: u64x2 = transmute(vsraq_n_u64::<2>(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_s8() { - let a: i8x8 = i8x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: i8x8 = i8x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [i8; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [i8; 16] = transmute(vtrn_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_s16() { - let a: i16x4 = i16x4::new(0, 2, 2, 6); - let b: i16x4 = i16x4::new(1, 3, 3, 7); - let e: [i16; 8] = [0, 1, 2, 3, 2, 3, 6, 7]; - let r: [i16; 8] = transmute(vtrn_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_s8() { - let a: i8x16 = i8x16::new(0, 2, 2, 6, 2, 10, 6, 14, 2, 18, 6, 22, 10, 26, 14, 30); - let b: i8x16 = i8x16::new(1, 3, 3, 7, 3, 1, 7, 15, 3, 19, 7, 23, 1, 27, 15, 31); - let e: [i8; 32] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15, 2, 3, 6, 7, 10, 1, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31]; - let r: [i8; 32] = transmute(vtrnq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_s16() { - let a: i16x8 = i16x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: i16x8 = i16x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [i16; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [i16; 16] = transmute(vtrnq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_s32() { - let a: i32x4 = i32x4::new(0, 2, 2, 6); - let b: i32x4 = i32x4::new(1, 3, 3, 7); - let e: [i32; 8] = [0, 1, 2, 3, 2, 3, 6, 7]; - let r: [i32; 8] = transmute(vtrnq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_u8() { - let a: u8x8 = u8x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: u8x8 = u8x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [u8; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [u8; 16] = transmute(vtrn_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_u16() { - let a: u16x4 = u16x4::new(0, 2, 2, 6); - let b: u16x4 = u16x4::new(1, 3, 3, 7); - let e: [u16; 8] = [0, 1, 2, 3, 2, 3, 6, 7]; - let r: [u16; 8] = transmute(vtrn_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_u8() { - let a: u8x16 = u8x16::new(0, 2, 2, 6, 2, 10, 6, 14, 2, 18, 6, 22, 10, 26, 14, 30); - let b: u8x16 = u8x16::new(1, 3, 3, 7, 3, 1, 7, 15, 3, 19, 7, 23, 1, 27, 15, 31); - let e: [u8; 32] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15, 2, 3, 6, 7, 10, 1, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31]; - let r: [u8; 32] = transmute(vtrnq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_u16() { - let a: u16x8 = u16x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: u16x8 = u16x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [u16; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [u16; 16] = transmute(vtrnq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_u32() { - let a: u32x4 = u32x4::new(0, 2, 2, 6); - let b: u32x4 = u32x4::new(1, 3, 3, 7); - let e: [u32; 8] = [0, 1, 2, 3, 2, 3, 6, 7]; - let r: [u32; 8] = transmute(vtrnq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_p8() { - let a: i8x8 = i8x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: i8x8 = i8x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [u8; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [u8; 16] = transmute(vtrn_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_p16() { - let a: i16x4 = i16x4::new(0, 2, 2, 6); - let b: i16x4 = i16x4::new(1, 3, 3, 7); - let e: [u16; 8] = [0, 1, 2, 3, 2, 3, 6, 7]; - let r: [u16; 8] = transmute(vtrn_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_p8() { - let a: i8x16 = i8x16::new(0, 2, 2, 6, 2, 10, 6, 14, 2, 18, 6, 22, 10, 26, 14, 30); - let b: i8x16 = i8x16::new(1, 3, 3, 7, 3, 1, 7, 15, 3, 19, 7, 23, 1, 27, 15, 31); - let e: [u8; 32] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15, 2, 3, 6, 7, 10, 1, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31]; - let r: [u8; 32] = transmute(vtrnq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_p16() { - let a: i16x8 = i16x8::new(0, 2, 2, 6, 2, 10, 6, 14); - let b: i16x8 = i16x8::new(1, 3, 3, 7, 3, 1, 7, 15); - let e: [u16; 16] = [0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15]; - let r: [u16; 16] = transmute(vtrnq_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: [i32; 4] = [0, 1, 2, 3]; - let r: [i32; 4] = transmute(vtrn_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: [u32; 4] = [0, 1, 2, 3]; - let r: [u32; 4] = transmute(vtrn_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrn_f32() { - let a: f32x2 = f32x2::new(0., 2.); - let b: f32x2 = f32x2::new(1., 3.); - let e: [f32; 4] = [0., 1., 2., 3.]; - let r: [f32; 4] = transmute(vtrn_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vtrnq_f32() { - let a: f32x4 = f32x4::new(0., 2., 2., 6.); - let b: f32x4 = f32x4::new(1., 3., 3., 7.); - let e: [f32; 8] = [0., 1., 2., 3., 2., 3., 6., 7.]; - let r: [f32; 8] = transmute(vtrnq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_s8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [i8; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [i8; 16] = transmute(vzip_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_s16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: [i16; 8] = [0, 1, 2, 3, 4, 5, 6, 7]; - let r: [i16; 8] = transmute(vzip_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_u8() { - let a: u8x8 = u8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u8x8 = u8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [u8; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [u8; 16] = transmute(vzip_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_u16() { - let a: u16x4 = u16x4::new(0, 2, 4, 6); - let b: u16x4 = u16x4::new(1, 3, 5, 7); - let e: [u16; 8] = [0, 1, 2, 3, 4, 5, 6, 7]; - let r: [u16; 8] = transmute(vzip_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_p8() { - let a: i8x8 = i8x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i8x8 = i8x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [u8; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [u8; 16] = transmute(vzip_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_p16() { - let a: i16x4 = i16x4::new(0, 2, 4, 6); - let b: i16x4 = i16x4::new(1, 3, 5, 7); - let e: [u16; 8] = [0, 1, 2, 3, 4, 5, 6, 7]; - let r: [u16; 8] = transmute(vzip_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_s32() { - let a: i32x2 = i32x2::new(0, 2); - let b: i32x2 = i32x2::new(1, 3); - let e: [i32; 4] = [0, 1, 2, 3]; - let r: [i32; 4] = transmute(vzip_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_u32() { - let a: u32x2 = u32x2::new(0, 2); - let b: u32x2 = u32x2::new(1, 3); - let e: [u32; 4] = [0, 1, 2, 3]; - let r: [u32; 4] = transmute(vzip_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_s8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: [i8; 32] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]; - let r: [i8; 32] = transmute(vzipq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_s16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [i16; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [i16; 16] = transmute(vzipq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_s32() { - let a: i32x4 = i32x4::new(0, 2, 4, 6); - let b: i32x4 = i32x4::new(1, 3, 5, 7); - let e: [i32; 8] = [0, 1, 2, 3, 4, 5, 6, 7]; - let r: [i32; 8] = transmute(vzipq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_u8() { - let a: u8x16 = u8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: u8x16 = u8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: [u8; 32] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]; - let r: [u8; 32] = transmute(vzipq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_u16() { - let a: u16x8 = u16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: u16x8 = u16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [u16; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [u16; 16] = transmute(vzipq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_u32() { - let a: u32x4 = u32x4::new(0, 2, 4, 6); - let b: u32x4 = u32x4::new(1, 3, 5, 7); - let e: [u32; 8] = [0, 1, 2, 3, 4, 5, 6, 7]; - let r: [u32; 8] = transmute(vzipq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_p8() { - let a: i8x16 = i8x16::new(0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30); - let b: i8x16 = i8x16::new(1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31); - let e: [u8; 32] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]; - let r: [u8; 32] = transmute(vzipq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_p16() { - let a: i16x8 = i16x8::new(0, 2, 4, 6, 8, 10, 12, 14); - let b: i16x8 = i16x8::new(1, 3, 5, 7, 9, 11, 13, 15); - let e: [u16; 16] = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]; - let r: [u16; 16] = transmute(vzipq_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzip_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(5., 6.); - let e: [f32; 4] = [1., 5., 2., 6.]; - let r: [f32; 4] = transmute(vzip_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vzipq_f32() { - let a: f32x4 = f32x4::new(1., 2., 3., 4.); - let b: f32x4 = f32x4::new(5., 6., 7., 8.); - let e: [f32; 8] = [1., 5., 2., 6., 3., 7., 4., 8.]; - let r: [f32; 8] = transmute(vzipq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_s8() { - let a: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: i8x8 = i8x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [i8; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [i8; 16] = transmute(vuzp_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_s16() { - let a: i16x4 = i16x4::new(1, 2, 2, 3); - let b: i16x4 = i16x4::new(2, 3, 3, 8); - let e: [i16; 8] = [1, 2, 2, 3, 2, 3, 3, 8]; - let r: [i16; 8] = transmute(vuzp_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_s8() { - let a: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 15, 8, 16); - let b: i8x16 = i8x16::new(2, 3, 3, 8, 3, 15, 8, 16, 3, 29, 8, 30, 15, 31, 16, 32); - let e: [i8; 32] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16, 2, 3, 3, 8, 3, 8, 15, 16, 3, 8, 15, 16, 29, 30, 31, 32]; - let r: [i8; 32] = transmute(vuzpq_s8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_s16() { - let a: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: i16x8 = i16x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [i16; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [i16; 16] = transmute(vuzpq_s16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_s32() { - let a: i32x4 = i32x4::new(1, 2, 2, 3); - let b: i32x4 = i32x4::new(2, 3, 3, 8); - let e: [i32; 8] = [1, 2, 2, 3, 2, 3, 3, 8]; - let r: [i32; 8] = transmute(vuzpq_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_u8() { - let a: u8x8 = u8x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: u8x8 = u8x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [u8; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [u8; 16] = transmute(vuzp_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_u16() { - let a: u16x4 = u16x4::new(1, 2, 2, 3); - let b: u16x4 = u16x4::new(2, 3, 3, 8); - let e: [u16; 8] = [1, 2, 2, 3, 2, 3, 3, 8]; - let r: [u16; 8] = transmute(vuzp_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_u8() { - let a: u8x16 = u8x16::new(1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 15, 8, 16); - let b: u8x16 = u8x16::new(2, 3, 3, 8, 3, 15, 8, 16, 3, 29, 8, 30, 15, 31, 16, 32); - let e: [u8; 32] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16, 2, 3, 3, 8, 3, 8, 15, 16, 3, 8, 15, 16, 29, 30, 31, 32]; - let r: [u8; 32] = transmute(vuzpq_u8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_u16() { - let a: u16x8 = u16x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: u16x8 = u16x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [u16; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [u16; 16] = transmute(vuzpq_u16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_u32() { - let a: u32x4 = u32x4::new(1, 2, 2, 3); - let b: u32x4 = u32x4::new(2, 3, 3, 8); - let e: [u32; 8] = [1, 2, 2, 3, 2, 3, 3, 8]; - let r: [u32; 8] = transmute(vuzpq_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_p8() { - let a: i8x8 = i8x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: i8x8 = i8x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [u8; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [u8; 16] = transmute(vuzp_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_p16() { - let a: i16x4 = i16x4::new(1, 2, 2, 3); - let b: i16x4 = i16x4::new(2, 3, 3, 8); - let e: [u16; 8] = [1, 2, 2, 3, 2, 3, 3, 8]; - let r: [u16; 8] = transmute(vuzp_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_p8() { - let a: i8x16 = i8x16::new(1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 15, 8, 16); - let b: i8x16 = i8x16::new(2, 3, 3, 8, 3, 15, 8, 16, 3, 29, 8, 30, 15, 31, 16, 32); - let e: [u8; 32] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16, 2, 3, 3, 8, 3, 8, 15, 16, 3, 8, 15, 16, 29, 30, 31, 32]; - let r: [u8; 32] = transmute(vuzpq_p8(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_p16() { - let a: i16x8 = i16x8::new(1, 2, 2, 3, 2, 3, 3, 8); - let b: i16x8 = i16x8::new(2, 3, 3, 8, 3, 15, 8, 16); - let e: [u16; 16] = [1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16]; - let r: [u16; 16] = transmute(vuzpq_p16(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_s32() { - let a: i32x2 = i32x2::new(1, 2); - let b: i32x2 = i32x2::new(2, 3); - let e: [i32; 4] = [1, 2, 2, 3]; - let r: [i32; 4] = transmute(vuzp_s32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_u32() { - let a: u32x2 = u32x2::new(1, 2); - let b: u32x2 = u32x2::new(2, 3); - let e: [u32; 4] = [1, 2, 2, 3]; - let r: [u32; 4] = transmute(vuzp_u32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzp_f32() { - let a: f32x2 = f32x2::new(1., 2.); - let b: f32x2 = f32x2::new(2., 6.); - let e: [f32; 4] = [1., 2., 2., 6.]; - let r: [f32; 4] = transmute(vuzp_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vuzpq_f32() { - let a: f32x4 = f32x4::new(1., 2., 2., 4.); - let b: f32x4 = f32x4::new(2., 6., 6., 8.); - let e: [f32; 8] = [1., 2., 2., 6., 2., 4., 6., 8.]; - let r: [f32; 8] = transmute(vuzpq_f32(transmute(a), transmute(b))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_u8() { - let a: u16x8 = u16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: u8x8 = u8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: u8x8 = u8x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: u16x8 = u16x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let r: u16x8 = transmute(vabal_u8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_u16() { - let a: u32x4 = u32x4::new(1, 2, 3, 4); - let b: u16x4 = u16x4::new(1, 2, 3, 4); - let c: u16x4 = u16x4::new(10, 10, 10, 10); - let e: u32x4 = u32x4::new(10, 10, 10, 10); - let r: u32x4 = transmute(vabal_u16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_u32() { - let a: u64x2 = u64x2::new(1, 2); - let b: u32x2 = u32x2::new(1, 2); - let c: u32x2 = u32x2::new(10, 10); - let e: u64x2 = u64x2::new(10, 10); - let r: u64x2 = transmute(vabal_u32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_s8() { - let a: i16x8 = i16x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let b: i8x8 = i8x8::new(1, 2, 3, 4, 5, 6, 7, 8); - let c: i8x8 = i8x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let e: i16x8 = i16x8::new(10, 10, 10, 10, 10, 10, 10, 10); - let r: i16x8 = transmute(vabal_s8(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_s16() { - let a: i32x4 = i32x4::new(1, 2, 3, 4); - let b: i16x4 = i16x4::new(1, 2, 3, 4); - let c: i16x4 = i16x4::new(10, 10, 10, 10); - let e: i32x4 = i32x4::new(10, 10, 10, 10); - let r: i32x4 = transmute(vabal_s16(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vabal_s32() { - let a: i64x2 = i64x2::new(1, 2); - let b: i32x2 = i32x2::new(1, 2); - let c: i32x2 = i32x2::new(10, 10); - let e: i64x2 = i64x2::new(10, 10); - let r: i64x2 = transmute(vabal_s32(transmute(a), transmute(b), transmute(c))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabs_s8() { - let a: i8x8 = i8x8::new(-128, 0x7F, -6, -5, -4, -3, -2, -1); - let e: i8x8 = i8x8::new(0x7F, 0x7F, 6, 5, 4, 3, 2, 1); - let r: i8x8 = transmute(vqabs_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsq_s8() { - let a: i8x16 = i8x16::new(-128, 0x7F, -6, -5, -4, -3, -2, -1, 0, -127, 127, 1, 2, 3, 4, 5); - let e: i8x16 = i8x16::new(0x7F, 0x7F, 6, 5, 4, 3, 2, 1, 0, 127, 127, 1, 2, 3, 4, 5); - let r: i8x16 = transmute(vqabsq_s8(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabs_s16() { - let a: i16x4 = i16x4::new(-32768, 0x7F_FF, -6, -5); - let e: i16x4 = i16x4::new(0x7F_FF, 0x7F_FF, 6, 5); - let r: i16x4 = transmute(vqabs_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsq_s16() { - let a: i16x8 = i16x8::new(-32768, 0x7F_FF, -6, -5, -4, -3, -2, -1); - let e: i16x8 = i16x8::new(0x7F_FF, 0x7F_FF, 6, 5, 4, 3, 2, 1); - let r: i16x8 = transmute(vqabsq_s16(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabs_s32() { - let a: i32x2 = i32x2::new(-2147483648, 0x7F_FF_FF_FF); - let e: i32x2 = i32x2::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF); - let r: i32x2 = transmute(vqabs_s32(transmute(a))); - assert_eq!(r, e); - } - - #[simd_test(enable = "neon")] - unsafe fn test_vqabsq_s32() { - let a: i32x4 = i32x4::new(-2147483648, 0x7F_FF_FF_FF, -6, -5); - let e: i32x4 = i32x4::new(0x7F_FF_FF_FF, 0x7F_FF_FF_FF, 6, 5); - let r: i32x4 = transmute(vqabsq_s32(transmute(a))); - assert_eq!(r, e); - } +#[doc = "Zip vectors"] +#[doc = "[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzipq_p16)"] +#[doc = "## Safety"] +#[doc = " * Neon instrinsic unsafe"] +#[inline] +#[target_feature(enable = "neon")] +#[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +#[cfg_attr(all(test, target_arch = "arm"), assert_instr(vorr))] +#[cfg_attr( + all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), + assert_instr(zip) +)] +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub unsafe fn vzipq_p16(a: poly16x8_t, b: poly16x8_t) -> poly16x8x2_t { + let a0: poly16x8_t = simd_shuffle!(a, b, [0, 8, 1, 9, 2, 10, 3, 11]); + let b0: poly16x8_t = simd_shuffle!(a, b, [4, 12, 5, 13, 6, 14, 7, 15]); + transmute((a0, b0)) } diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index 19bdca228b..33065b0b9d 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -11,6 +11,142 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::* #[cfg(test)] use stdarch_test::assert_instr; +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub trait AsUnsigned { + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + type Unsigned: ?Sized; + + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + unsafe fn as_unsigned(self) -> Self::Unsigned; +} + +#[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") +)] +#[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") +)] +pub trait AsSigned { + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + type Signed: ?Sized; + + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + unsafe fn as_signed(self) -> Self::Signed; +} + +macro_rules! impl_sign_conversions { + ($(($signed:ty, $unsigned:ty))*) => ($( + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + unsafe fn as_unsigned(self) -> $unsigned { + crate::mem::transmute(self) + } + } + + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + unsafe fn as_signed(self) -> $signed { + crate::mem::transmute(self) + } + } + )*) +} + +macro_rules! impl_sign_conversions_neon { + ($(($signed:ty, $unsigned:ty))*) => ($( + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + impl AsUnsigned for $signed { + type Unsigned = $unsigned; + + #[inline] + unsafe fn as_unsigned(self) -> $unsigned { + crate::mem::transmute(self) + } + } + + #[cfg_attr( + not(target_arch = "arm"), + stable(feature = "neon_intrinsics", since = "1.59.0") + )] + #[cfg_attr( + target_arch = "arm", + unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") + )] + impl AsSigned for $unsigned { + type Signed = $signed; + + #[inline] + unsafe fn as_signed(self) -> $signed { + crate::mem::transmute(self) + } + } + )*) +} + pub(crate) type p8 = u8; pub(crate) type p16 = u16; pub(crate) type p64 = u64; @@ -1033,6 +1169,88 @@ pub struct poly64x2x4_t( pub poly64x2_t, ); +impl_sign_conversions! { + (i8, u8) + (i16, u16) + (i32, u32) + (i64, u64) + (*const i8, *const u8) + (*const i16, *const u16) + (*const i32, *const u32) + (*const i64, *const u64) + (*mut i8, *mut u8) + (*mut i16, *mut u16) + (*mut i32, *mut u32) + (*mut i64, *mut u64) + (int16x4_t, uint16x4_t) + (int16x8_t, uint16x8_t) + (int32x2_t, uint32x2_t) + (int32x4_t, uint32x4_t) + (int64x1_t, uint64x1_t) + (int64x2_t, uint64x2_t) + (int8x16_t, uint8x16_t) + (int8x8_t, uint8x8_t) + (uint16x4_t, int16x4_t) + (uint16x8_t, int16x8_t) + (uint32x2_t, int32x2_t) + (uint32x4_t, int32x4_t) + (uint64x1_t, int64x1_t) + (uint64x2_t, int64x2_t) + (uint8x16_t, int8x16_t) + (uint8x8_t, int8x8_t) +} + +impl_sign_conversions_neon! { + (int16x4x2_t, uint16x4x2_t) + (int16x4x3_t, uint16x4x3_t) + (int16x4x4_t, uint16x4x4_t) + (int16x8x2_t, uint16x8x2_t) + (int16x8x3_t, uint16x8x3_t) + (int16x8x4_t, uint16x8x4_t) + (int32x2x2_t, uint32x2x2_t) + (int32x2x3_t, uint32x2x3_t) + (int32x2x4_t, uint32x2x4_t) + (int32x4x2_t, uint32x4x2_t) + (int32x4x3_t, uint32x4x3_t) + (int32x4x4_t, uint32x4x4_t) + (int64x1x2_t, uint64x1x2_t) + (int64x1x3_t, uint64x1x3_t) + (int64x1x4_t, uint64x1x4_t) + (int64x2x2_t, uint64x2x2_t) + (int64x2x3_t, uint64x2x3_t) + (int64x2x4_t, uint64x2x4_t) + (int8x16x2_t, uint8x16x2_t) + (int8x16x3_t, uint8x16x3_t) + (int8x16x4_t, uint8x16x4_t) + (int8x8x2_t, uint8x8x2_t) + (int8x8x3_t, uint8x8x3_t) + (int8x8x4_t, uint8x8x4_t) + (uint16x4x2_t, int16x4x2_t) + (uint16x4x3_t, int16x4x3_t) + (uint16x4x4_t, int16x4x4_t) + (uint16x8x2_t, int16x8x2_t) + (uint16x8x3_t, int16x8x3_t) + (uint16x8x4_t, int16x8x4_t) + (uint32x2x2_t, int32x2x2_t) + (uint32x2x3_t, int32x2x3_t) + (uint32x2x4_t, int32x2x4_t) + (uint32x4x2_t, int32x4x2_t) + (uint32x4x3_t, int32x4x3_t) + (uint32x4x4_t, int32x4x4_t) + (uint64x1x2_t, int64x1x2_t) + (uint64x1x3_t, int64x1x3_t) + (uint64x1x4_t, int64x1x4_t) + (uint64x2x2_t, int64x2x2_t) + (uint64x2x3_t, int64x2x3_t) + (uint64x2x4_t, int64x2x4_t) + (uint8x16x2_t, int8x16x2_t) + (uint8x16x3_t, int8x16x3_t) + (uint8x16x4_t, int8x16x4_t) + (uint8x8x2_t, int8x8x2_t) + (uint8x8x3_t, int8x8x3_t) + (uint8x8x4_t, int8x8x4_t) +} + #[allow(improper_ctypes)] extern "unadjusted" { // absolute value (64-bit) diff --git a/crates/stdarch-gen2/spec/neon/aarch64.spec.yml b/crates/stdarch-gen2/spec/neon/aarch64.spec.yml new file mode 100644 index 0000000000..fd704c305e --- /dev/null +++ b/crates/stdarch-gen2/spec/neon/aarch64.spec.yml @@ -0,0 +1,9852 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [neon] + llvm_prefix: llvm.aarch64.neon + +# Repeatedly used anchors +# #[stable(feature = "neon_intrinsics", since = "1.59.0")] +neon-stable: &neon-stable + FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + +# #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +neon-unstable: &neon-unstable + FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + +# #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +neon-v7: &neon-v7 + FnCall: [cfg_attr, ['target_arch = "arm"', { FnCall: [target_feature, [ 'enable = "v7"']]} ]] + +# #[target_feature(enable = "neon,v7")] +enable-v7: &enable-v7 + FnCall: [target_feature, ['enable = "neon,v7"']] + +# #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +neon-v8: &neon-v8 + FnCall: [cfg_attr, ['target_arch = "arm"', { FnCall: [target_feature, [ 'enable = "v8"']]} ]] + +target-is-arm: &target-is-arm + FnCall: [cfg, ['target_arch = "arm"']] + +# #[cfg(not(target_arch = "arm"))] +target-not-arm: &target-not-arm + FnCall: [cfg, [{ FnCall: [not, ['target_arch = "arm"']]}]] + +neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec + FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]] + +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] +neon-stable-not-arm: &neon-stable-not-arm + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, *neon-stable]] + +#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +neon-unstable-is-arm: &neon-unstable-is-arm + FnCall: [ cfg_attr, ['target_arch = "arm"', *neon-unstable]] + +# #[cfg_attr(all(test, not(target_env = "msvc"))] +msvc-disabled: &msvc-disabled + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]] + +# all(test, target_arch = "arm") +test-is-arm: &test-is-arm + FnCall: [all, [test, 'target_arch = "arm"']] + +# #[target_feature(enable = "neon,aes")] +neon-aes: &neon-aes + FnCall: [target_feature, ['enable = "neon,aes"']] + +# #[target_feature(enable = "neon,i8mm")] +neon-i8mm: &neon-i8mm + FnCall: [target_feature, ['enable = "neon,i8mm"']] + +#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] +neon-unstable-i8mm: &neon-unstable-i8mm + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']] }, { FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] } ]] + +# #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +neon-unstable-fcma: &neon-unstable-fcma + FnCall: [unstable, ['feature = "stdarch_neon_fcma"', 'issue = "117222"']] + +intrinsics: + - name: "vaddd_{type}" + doc: Add + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - i64 + - u64 + compose: + - MethodCall: + - a + - wrapping_add + - - b + + - name: "veor3{neon_type.no}" + doc: Three-way exclusive OR + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + assert_instr: [eor3] + safety: + unsafe: [neon] + types: + - int8x16_t + - int16x8_t + - int32x4_t + - int64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.crypto.eor3s.{neon_type}" + links: + - link: "llvm.aarch64.crypto.eor3s.{neon_type}" + arch: aarch64,arm64ec + + - name: "veor3{neon_type.no}" + doc: Three-way exclusive OR + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + assert_instr: [eor3] + safety: + unsafe: [neon] + types: + - uint8x16_t + - uint16x8_t + - uint32x4_t + - uint64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.crypto.eor3u.{neon_type}" + links: + - link: "llvm.aarch64.crypto.eor3u.{neon_type}" + arch: aarch64,arm64ec + + - name: "vabd{neon_type.no}" + doc: Absolute difference between the arguments of Floating + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fabd] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fabd.{neon_type}" + links: + - link: "llvm.aarch64.neon.fabd.{neon_type}" + arch: aarch64,arm64ec + + - name: "vabd{type[0]}" + doc: "Floating-point absolute difference" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [fabd] + safety: + unsafe: [neon] + types: + - ['s_f32', 'f32'] + - ['d_f64', 'f64'] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vabd_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[1]}", [b]] + - 0 + + - name: "vabdl_high{neon_type[0].noq}" + doc: Signed Absolute difference Long + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [sabdl] + safety: + unsafe: [neon] + types: + - [int8x16_t, int16x8_t, int8x8_t, uint8x8_t] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - a + - a + - [8, 9, 10, 11, 12, 13, 14, 15] + - Let: + - d + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - b + - b + - [8, 9, 10, 11, 12, 13, 14, 15] + - Let: + - e + - "{neon_type[3]}" + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - c + - d + - FnCall: + - simd_cast + - - e + + - name: "vabdl_high{neon_type[0].noq}" + doc: Signed Absolute difference Long + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + assert_instr: [sabdl] + safety: + unsafe: [neon] + types: + - [int16x8_t, int32x4_t, int16x4_t, uint16x4_t] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - a + - a + - [4, 5, 6, 7] + - Let: + - d + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - b + - b + - [4, 5, 6, 7] + - Let: + - e + - "{neon_type[3]}" + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - c + - d + - FnCall: + - simd_cast + - - e + + - name: "vabdl_high{neon_type[0].noq}" + doc: Signed Absolute difference Long + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + assert_instr: [sabdl] + safety: + unsafe: [neon] + types: + - [int32x4_t, int64x2_t, int32x2_t, uint32x2_t] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - a + - a + - [2, 3] + - Let: + - d + - "{neon_type[2]}" + - FnCall: + - simd_shuffle! + - - b + - b + - [2, 3] + - Let: + - e + - "{neon_type[3]}" + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - c + - d + - FnCall: + - simd_cast + - - e + + - name: "vceq{neon_type[0].no}" + doc: "Compare bitwise Equal (vector)" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint64x1_t, uint64x1_t] + - [uint64x2_t, uint64x2_t] + - [int64x1_t, uint64x1_t] + - [int64x2_t, uint64x2_t] + - [poly64x1_t, uint64x1_t] + - [poly64x2_t, uint64x2_t] + compose: + - FnCall: [simd_eq, [a, b]] + + - name: "vceq{neon_type[0].no}" + doc: "Floating-point compare equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: [simd_eq, [a, b]] + + - name: "vceq{type[0]}" + doc: "Floating-point compare equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vceq_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[1]}", [b]] + - '0' + + - name: "vceqd_{type[0]}" + doc: "Compare bitwise equal" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64", "s64"] + - ["u64", "u64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - "vceq_{type[2]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vtst{neon_type[0].no}" + doc: "Signed compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + - [poly64x1_t, uint64x1_t, 'i64x1', 'i64x1::new(0)'] + - [poly64x2_t, uint64x2_t, 'i64x2', 'i64x2::new(0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[2]}", "{type[3]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] + + - name: "vtstd_{type[0]}" + doc: "Compare bitwise test bits nonzero" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [tst]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64", "s64"] + - ["u64", "u64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - "vtst_{type[2]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vuqadd{type[0]}" + doc: "Signed saturating accumulate of unsigned value" + arguments: ["a: {type[1]}", "b: {type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_s32", "i32", "u32"] + - ["d_s64", "i64", "u64"] + compose: + - LLVMLink: + name: "vuqadd{type[0]}" + links: + - link: "llvm.aarch64.neon.suqadd.{type[1]}" + arch: aarch64,arm64ec + + - name: "vuqadd{type[0]}" + doc: "Signed saturating accumulate of unsigned value" + arguments: ["a: {type[1]}", "b: {type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [suqadd]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["b_s8", "i8", "u8", "s8"] + - ["h_s16", "i16", "u16", "s16"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vuqadd_{type[3]}" + - - FnCall: ["vdup_n_{type[3]}", [a]] + - FnCall: ["vdup_n_{type[2]}", [b]] + - '0' + + - name: "vabs{neon_type.no}" + doc: "Floating-point absolute value" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fabs]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_fabs, [a]] + + - name: "vcgt{neon_type[0].no}" + doc: "Compare signed greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, uint64x1_t] + - [int64x2_t, uint64x2_t] + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vcgt{neon_type.no}" + doc: "Compare unsigned greater than" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - uint64x1_t + - uint64x2_t + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vcgt{neon_type[0].no}" + doc: "Floating-point compare greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vcgt{type[0]}" + doc: "Floating-point compare greater than" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - 'simd_extract!' + - - FnCall: + - "vcgt_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[1]}", [b]] + - '0' + + - name: "vclt{neon_type[0].no}" + doc: "Compare signed less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, uint64x1_t] + - [int64x2_t, uint64x2_t] + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vcle{neon_type[0].no}" + doc: "Compare signed less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, uint64x1_t] + - [int64x2_t, uint64x2_t] + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vcle{neon_type[0].no}" + doc: "Floating-point compare less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vcle{type[0]}" + doc: "Floating-point compare less than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vcle_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[1]}", [b]] + - '0' + + - name: "vcge{neon_type[0].no}" + doc: "Compare signed greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, uint64x1_t] + - [int64x2_t, uint64x2_t] + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vcgez{neon_type[0].no}" + doc: "Compare signed greater than or equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [int64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: [simd_ge, [a, {FnCall: [transmute, [b]]}]] + + - name: "vcgezd_s64" + doc: "Compare signed greater than or equal to zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - vcgez_s64 + - - FnCall: [transmute, [a]] + + - name: "vclez{neon_type[0].no}" + doc: "Compare signed less than or equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmle]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [int64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_le + - - a + - FnCall: [transmute, [b]] + + - name: "vclez{neon_type[0].no}" + doc: "Floating-point compare less than or equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmle]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] + - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] + - [float64x1_t, uint64x1_t, f64, '0.0'] + - [float64x2_t, uint64x2_t, f64x2, 'f64x2::new(0.0, 0.0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_le + - - a + - FnCall: [transmute, [b]] + + - name: "vclez{type[0]}" + doc: "Floating-point compare less than or equal to zero" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vclez_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - '0' + + - name: "vcltz{neon_type[0].no}" + doc: "Compare signed less than zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmlt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [int64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_lt + - - a + - FnCall: [transmute, [b]] + + - name: "vcltz{neon_type[0].no}" + doc: "Floating-point compare less than zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmlt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] + - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] + - [float64x1_t, uint64x1_t, f64, '0.0'] + - [float64x2_t, uint64x2_t, f64x2, 'f64x2::new(0.0, 0.0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_lt + - - a + - FnCall: [transmute, [b]] + + - name: "vcltz{type[0]}" + doc: "Floating-point compare less than zero" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vcltz_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - '0' + + - name: "vcltzd_s64" + doc: "Compare less than zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [asr]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - vcltz_s64 + - - FnCall: [transmute, [a]] + + - name: "vcagt{neon_type[0].no}" + doc: "Floating-point absolute compare greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcagt{neon_type[0].no}" + links: + - link: "llvm.aarch64.neon.facgt.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcagt{type[0]}" + doc: "Floating-point absolute compare greater than" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32", i32] + - ["d_f64", "f64", "u64", i64] + compose: + - LLVMLink: + name: "vcagt{type[0]}" + links: + - link: "llvm.aarch64.neon.facgt.{type[3]}.{type[1]}" + arch: aarch64,arm64ec + + - name: "vcage{neon_type[0].no}" + doc: "Floating-point absolute compare greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcage{neon_type[0].no}" + links: + - link: "llvm.aarch64.neon.facge.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcage{type[0]}" + doc: "Floating-point absolute compare greater than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32", i32] + - ["d_f64", "f64", "u64", i64] + compose: + - LLVMLink: + name: "vcage{type[0]}" + links: + - link: "llvm.aarch64.neon.facge.{type[3]}.{type[1]}" + arch: aarch64,arm64ec + + - name: "vcalt{neon_type[0].no}" + doc: "Floating-point absolute compare less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: ["vcagt{neon_type[0].no}", [b, a]] + + - name: "vcalt{type[0]}" + doc: "Floating-point absolute compare less than" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: ["vcagt{type[0]}", [b, a]] + + - name: "vcale{neon_type[0].no}" + doc: "Floating-point absolute compare less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: ["vcage{neon_type[0].no}", [b, a]] + + - name: "vcale{type[0]}" + doc: "Floating-point absolute compare less than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: ["vcage{type[0]}", [b, a]] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int64x1_t, float64x1_t] + - [int64x2_t, float64x2_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt{type[0]}_{type[3]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "i32", "f32", s32] + - ["d_f64", "i64", "f64", s64] + compose: + - Identifier: ["a as {type[2]}", Symbol] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint64x1_t, float64x1_t] + - [uint64x2_t, float64x2_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt{type[2]}_{type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u32", "f32", "s_f32"] + - ["u64", "f64", "d_f64"] + compose: + - Identifier: ["a as {type[1]}", Symbol] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x1_t, float64x1_t] + - [int64x2_t, float64x2_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i32", "f32", 's_n_f32_s32', 'N >= 1 && N <= 32'] + - ["i64", "f64", 'd_n_f64_s64', 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: + - "a: {type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxs2fp.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint64x1_t, float64x1_t] + - [uint64x2_t, float64x2_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a.as_signed()", N]] + + - name: "vcvt{type[2]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["u32", "f32", 's_n_f32_u32', 'N >= 1 && N <= 32'] + - ["u64", "f64", 'd_n_f64_u64', 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: + - "a: {type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxu2fp.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", ["a.as_signed()", N]] + + - name: "vcvt{type[2]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "i32", "s_s32_f32", "32"] + - ["f64", "i64", "d_s64_f64", "64"] + compose: + - Identifier: ["a as i{type[3]}", Symbol] + + - name: "vcvt{type[2]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", "s_u32_f32"] + - ["f64", "u64", "d_u64_f64"] + compose: + - Identifier: ["a as {type[1]}", Symbol] + + - name: "vcvt_f64_f32" + doc: "Floating-point convert to higher precision long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, float64x2_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt_high_f64_f32" + doc: "Floating-point convert to higher precision long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x4_t, float64x2_t] + compose: + - Let: + - b + - float32x2_t + - FnCall: + - simd_shuffle! + - - a + - a + - '[2, 3]' + - FnCall: [simd_cast, [b]] + + - name: "vcvt_f32_f64" + doc: "Floating-point convert to lower precision narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x2_t, float32x2_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt_high_f32_f64" + doc: "Floating-point convert to lower precision narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, float64x2_t, float32x4_t] + compose: + - FnCall: + - simd_shuffle! + - - a + - FnCall: [simd_cast, [b]] + - '[0, 1, 2, 3]' + + - name: "vcvtx_f32_f64" + doc: "Floating-point convert to lower precision narrow, rounding to odd" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x2_t, float32x2_t] + compose: + - LLVMLink: + name: "vcvtx_f32_f64" + links: + - link: "llvm.aarch64.neon.fcvtxn.v2f32.v2f64" + arch: aarch64,arm64ec + + - name: "vcvtxd_f32_f64" + doc: "Floating-point convert to lower precision narrow, rounding to odd" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f64", "f32"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - vcvtx_f32_f64 + - - FnCall: [vdupq_n_f64, [a]] + - '0' + + - name: "vcvtx_high_f32_f64" + doc: "Floating-point convert to lower precision narrow, rounding to odd" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtxn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, float64x2_t, float32x4_t] + compose: + - FnCall: + - simd_shuffle! + - - a + - FnCall: [vcvtx_f32_f64, [b]] + - '[0, 1, 2, 3]' + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float64x1_t, int64x1_t, _n_s64_f64, '64'] + - [float64x2_t, int64x2_t, q_n_s64_f64, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[3]}']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.aarch64.neon.vcvtfp2fxs.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["f32", "i32", s_n_s32_f32, '32'] + - ["f64", "i64", d_n_s64_f64, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[3]}']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.aarch64.neon.vcvtfp2fxs.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t, _n_u64_f64, '64'] + - [float64x2_t, uint64x2_t, q_n_u64_f64, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[3]}']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.aarch64.neon.vcvtfp2fxu.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["f32", "u32", s_n_u32_f32, '32'] + - ["f64", "u64", d_n_u64_f64, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[3]}']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.aarch64.neon.vcvtfp2fxu.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvta{type[2]}" + doc: "Floating-point convert to signed integer, rounding to nearest with ties to away" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t, _s32_f32] + - [float32x4_t, int32x4_t, q_s32_f32] + - [float64x1_t, int64x1_t, _s64_f64] + - [float64x2_t, int64x2_t, q_s64_f64] + compose: + - LLVMLink: + name: "vcvta{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtas.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvta{type[2]}" + doc: "Floating-point convert to integer, rounding to nearest with ties to away" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtas]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "i32", 's_s32_f32'] + - ["f64", "i64", 'd_s64_f64'] + compose: + - LLVMLink: + name: "vcvta{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtas.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvta{type[2]}" + doc: "Floating-point convert to integer, rounding to nearest with ties to away" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", 's_u32_f32'] + - ["f64", "u64", 'd_u64_f64'] + compose: + - LLVMLink: + name: "vcvta{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtau.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtn{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to signed integer, rounding to nearest with ties to even" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vcvtn{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtns.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtn{type[2]}" + doc: "Floating-point convert to signed integer, rounding to nearest with ties to even" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtns]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "i32", 's_s32_f32'] + - ["f64", "i64", 'd_s64_f64'] + compose: + - LLVMLink: + name: "vcvtn{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtns.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtm{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to signed integer, rounding toward minus infinity" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vcvtm{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtms.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtm{type[2]}" + doc: "Floating-point convert to signed integer, rounding toward minus infinity" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtms]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "i32", 's_s32_f32'] + - ["f64", "i64", 'd_s64_f64'] + compose: + - LLVMLink: + name: "vcvtm{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtms.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtp{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to signed integer, rounding toward plus infinity" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vcvtp{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtps.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtp{type[2]}" + doc: "Floating-point convert to signed integer, rounding toward plus infinity" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtps]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "i32", 's_s32_f32'] + - ["f64", "i64", 'd_s64_f64'] + compose: + - LLVMLink: + name: "vcvtp{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtps.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtn{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcvtn{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtnu.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtn{type[2]}" + doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to even" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtnu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", 's_u32_f32'] + - ["f64", "u64", 'd_u64_f64'] + compose: + - LLVMLink: + name: "vcvtn{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtnu.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtm{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned integer, rounding toward minus infinity" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcvtm{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtmu.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtm{type[2]}" + doc: "Floating-point convert to unsigned integer, rounding toward minus infinity" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtmu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", s_u32_f32] + - ["f64", "u64", d_u64_f64] + compose: + - LLVMLink: + name: "vcvtm{type[2]}" + links: + - link: "llvm.aarch64.neon.fcvtmu.{type[1]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtp{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned integer, rounding toward plus infinity" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcvtp{neon_type[1].no}_{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.fcvtpu.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvtp{type[2]}" + doc: "Floating-point convert to unsigned integer, rounding toward plus infinity" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtpu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", s_u32_f32, 'i32'] + - ["f64", "u64", d_u64_f64, 'u64'] + compose: + - LLVMLink: + name: "vcvtp{type[2]}" + arguments: + - "a: {type[0]}" + return_type: "{type[1]}" + links: + - link: "llvm.aarch64.neon.fcvtpu.{type[3]}.{type[0]}" + arch: aarch64,arm64ec + + - name: "vdup{neon_type.laneq_nox}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - poly64x2_t + - float64x2_t + compose: + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_shuffle!, [a, a, '[N as u32, N as u32]']] + + - name: "vdup{neon_type[1].lane_nox}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [dup, 'N = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [poly64x1_t, poly64x2_t] + - [float64x1_t, float64x2_t] + compose: + - FnCall: [static_assert!, ['N == 0']] + - FnCall: [simd_shuffle!, [a, a, '[N as u32, N as u32]']] + + - name: "vdup{neon_type.lane_nox}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - poly64x1_t + - float64x1_t + compose: + - FnCall: [static_assert!, ['N == 0']] + - Identifier: [a, Symbol] + + - name: "vdupd{neon_type[0].lane_nox}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x1_t, "i64"] + - [uint64x1_t, "u64"] + - [float64x1_t, "f64"] + compose: + - FnCall: [static_assert!, ['N == 0']] + - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vdup_laneq_{neon_type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [poly64x2_t, poly64x1_t, 'u64'] + - [float64x2_t, float64x1_t, 'f64'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: + - "transmute::<{type[2]}, _>" + - - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vdup{type[2]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, "i32", s_lane_s32] + - [int64x2_t, "i64", d_laneq_s64] + - [uint32x2_t, "u32", s_lane_u32] + - [uint64x2_t, "u64", d_laneq_u64] + - [float32x2_t, "f32", s_lane_f32] + - [float64x2_t, "f64", d_laneq_f64] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vdup{type[2]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 4']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, "i8", b_lane_s8] + - [int16x8_t, "i16", h_laneq_s16] + - [uint8x8_t, "u8", b_lane_u8] + - [uint16x8_t, "u16", h_laneq_u16] + - [poly8x8_t, "p8", b_lane_p8] + - [poly16x8_t, "p16", h_laneq_p16] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vdup{type[2]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 8']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x16_t, "i8", b_laneq_s8] + - [uint8x16_t, "u8", b_laneq_u8] + - [poly8x16_t, "p8", b_laneq_p8] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 4]] + - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vdup{type[2]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", h_lane_s16] + - [int32x4_t, "i32", s_laneq_s32] + - [uint16x4_t, "u16", h_lane_u16] + - [uint32x4_t, "u32", s_laneq_u32] + - [poly16x4_t, "p16", h_lane_p16] + - [float32x4_t, "f32", s_laneq_f32] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ext, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [poly64x2_t, ' static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [float64x2_t, ' static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vmla{neon_type.no}" + doc: "Floating-point multiply-add to accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_add, [a, {FnCall: [simd_mul, [b, c]]}]] + + - name: "vmlal_high_{neon_type[1]}" + doc: "Signed multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] + - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]', '[2, 3]'] + compose: + - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[4]}"]]}] + - FnCall: ["vmlal_{neon_type[2]}", [a, b, c]] + + - name: "vmlal_high_{neon_type[1]}" + doc: "Unsigned multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + compose: + - Let: + - b + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - Let: + - c + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ["vmlal_{neon_type[1]}", [a, b, c]] + + - name: "vmlsl_high_{neon_type[1]}" + doc: "Signed multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] + - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + compose: + - Let: + - b + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - Let: + - c + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] + + - name: "vmlsl_high_{neon_type[1]}" + doc: "Unsigned multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + compose: + - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - FnCall: ["vmlsl_{neon_type[1]}", [a, b, c]] + + - name: "vmovn_high{neon_type[1].noq}" + doc: Extract narrow + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: [*neon-stable] + assert_instr: [xtn2] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + compose: + - Let: + - c + - "{neon_type[0]}" + - FnCall: + - simd_cast + - - b + - FnCall: + - simd_shuffle! + - - a + - c + - "{type[3]}" + + - name: "vneg{neon_type.no}" + doc: Negate + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [neg] + safety: + unsafe: [neon] + types: + - int64x1_t + - int64x2_t + compose: + - FnCall: + - simd_neg + - - a + + - name: "vnegd_s64" + doc: Negate + arguments: ["a: {type}"] + return_type: "{type}" + attr: [*neon-stable] + assert_instr: [neg] + safety: + unsafe: [neon] + types: + - i64 + compose: + - MethodCall: [a, wrapping_neg, []] + + - name: "vneg{neon_type.no}" + doc: Negate + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + assert_instr: [fneg] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: + - simd_neg + - - a + + - name: "vqneg{type[1]}" + doc: Signed saturating negate + arguments: ["a: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqneg] + safety: + unsafe: [neon] + types: + - [i8, 'b_s8', 's8'] + - [i16, 'h_s16', 's16'] + - [i32, 's_s32', 's32'] + - [i64, 'd_s64', 's64'] + compose: + - FnCall: + - 'simd_extract!' + - - FnCall: + - 'vqneg_{type[2]}' + - - FnCall: ['vdup_n_{type[2]}', [a]] + - 0 + + - name: "vqneg{neon_type[0].no}" + doc: Signed saturating negate + arguments: ["a: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqneg] + safety: + unsafe: [neon] + types: + - [int64x1_t, 'i64'] + - [int64x2_t, 'i64'] + compose: + - LLVMLink: + name: "sqneg.{neon_type[0].no}" + links: + - link: "llvm.aarch64.neon.sqneg.v{neon_type[0].lane}{type[1]}" + arch: aarch64,arm64ec + + - name: "vqsub{type[1]}" + doc: Saturating subtract + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqsub] + safety: + unsafe: [neon] + types: + - [i32, 's_s32', 'i32'] + - [i64, 'd_s64', 'i64'] + compose: + - LLVMLink: + name: "sqsub.{type[0]}" + links: + - link: "llvm.aarch64.neon.sqsub.{type[2]}" + arch: aarch64,arm64ec + + - name: "vqsub{type[1]}" + doc: Saturating subtract + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [uqsub] + safety: + unsafe: [neon] + types: + - [u32, 's_u32', 'i32'] + - [u64, 'd_u64', 'i64'] + compose: + - LLVMLink: + name: "uqsub.{type[0]}" + links: + - link: "llvm.aarch64.neon.uqsub.{type[2]}" + arch: aarch64,arm64ec + + - name: "vqsub{type[3]}" + doc: Saturating subtract + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqsub] + safety: + unsafe: [neon] + types: + - [i8, int8x8_t, s8, 'b_s8'] + - [i16, int16x4_t, s16, 'h_s16'] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[2]}" + - - a + - Let: + - b + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[2]}" + - - b + - FnCall: + - 'simd_extract!' + - - FnCall: + - "vqsub_{type[2]}" + - - a + - b + - "0" + + - name: "vqsub{type[3]}" + doc: Saturating subtract + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [uqsub] + safety: + unsafe: [neon] + types: + - [u8, uint8x8_t, u8, 'b_u8'] + - [u16, uint16x4_t, u16, 'h_u16'] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[2]}" + - - a + - Let: + - b + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[2]}" + - - b + - FnCall: + - 'simd_extract!' + - - FnCall: + - "vqsub_{type[2]}" + - - a + - b + - "0" + + - name: "vrbit{neon_type.no}" + doc: Reverse bit order + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [rbit] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + compose: + - LLVMLink: + name: "rbit.{neon_type}" + links: + - link: "llvm.aarch64.neon.rbit.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrbit{neon_type[0].no}" + doc: Reverse bit order + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: [*neon-stable] + assert_instr: [rbit] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [poly8x8_t, int8x8_t] + - [poly8x16_t, int8x16_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vrbit{neon_type[1].no}" + - - FnCall: [transmute, [a]] + + - name: "vrndx{neon_type.no}" + doc: "Floating-point round to integral exact, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frintx] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.rint.{neon_type}" + links: + - link: "llvm.rint.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnda{neon_type.no}" + doc: "Floating-point round to integral, to nearest with ties to away" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frinta] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.round.{neon_type}" + links: + - link: "llvm.round.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrndn{neon_type.no}" + doc: "Floating-point round to integral, to nearest with ties to even" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frintn] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "frintn.{neon_type}" + links: + - link: "llvm.aarch64.neon.frintn.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrndns_{type}" + doc: "Floating-point round to integral, to nearest with ties to even" + arguments: ["a: {type}"] + return_type: "{type}" + attr: [*neon-stable] + assert_instr: [frintn] + safety: + unsafe: [neon] + types: + - f32 + compose: + - LLVMLink: + name: "roundeven.{type}" + links: + - link: "llvm.roundeven.{type}" + arch: aarch64,arm64ec + + - name: "vrndm{neon_type.no}" + doc: "Floating-point round to integral, toward minus infinity" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frintm] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.floor.{neon_type}" + links: + - link: "llvm.floor.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrndp{neon_type.no}" + doc: "Floating-point round to integral, toward plus infinity" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frintp] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.ceil.{neon_type}" + links: + - link: "llvm.ceil.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnd{neon_type.no}" + doc: "Floating-point round to integral, toward zero" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frintz] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.trunc.{neon_type}" + links: + - link: "llvm.trunc.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrndi{neon_type.no}" + doc: "Floating-point round to integral, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [frinti] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.nearbyint.{neon_type}" + links: + - link: "llvm.nearbyint.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqadd{type[1]}" + doc: Saturating add + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [uqadd] + safety: + unsafe: [neon] + types: + - [u32, 's_u32', i32] + - [u64, 'd_u64', i64] + compose: + - LLVMLink: + name: "uqadd.{type[2]}" + links: + - link: "llvm.aarch64.neon.uqadd.{type[2]}" + arch: aarch64,arm64ec + + - name: "vqadd{type[1]}" + doc: Saturating add + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqadd] + safety: + unsafe: [neon] + types: + - [i32, 's_s32', i32] + - [i64, 'd_s64', i64] + compose: + - LLVMLink: + name: "uqadd.{type[2]}" + links: + - link: "llvm.aarch64.neon.sqadd.{type[2]}" + arch: aarch64,arm64ec + + - name: "vqadd{type[2]}" + doc: Saturating add + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [sqadd] + safety: + unsafe: [neon] + types: + - [i8, int8x8_t, 'b_s8'] + - [i16, int16x4_t, 'h_s16'] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[0]}" + - - a + - Let: + - b + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[0]}" + - - b + - FnCall: + - simd_extract! + - - FnCall: + - "vqadd_{type[0]}" + - - a + - b + - "0" + + - name: "vqadd{type[2]}" + doc: Saturating add + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: [*neon-stable] + assert_instr: [uqadd] + safety: + unsafe: [neon] + types: + - [u8, uint8x8_t, 'b_u8'] + - [u16, uint16x4_t, 'h_u16'] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[0]}" + - - a + - Let: + - b + - "{neon_type[1]}" + - FnCall: + - "vdup_n_{type[0]}" + - - b + - FnCall: + - simd_extract! + - - FnCall: + - "vqadd_{type[0]}" + - - a + - b + - "0" + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld1] + safety: + unsafe: [neon] + types: + - ["*const f64", float64x1x2_t] + - ["*const f64", float64x2x2_t] + - ["*const f64", float64x1x3_t] + - ["*const f64", float64x2x3_t] + - ["*const f64", float64x1x4_t] + - ["*const f64", float64x2x4_t] + compose: + - LLVMLink: + name: "vld1{neon_type[1].no}" + links: + - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0f64" + arch: aarch64,arm64ec + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const i8", int8x16x2_t, i8, int8x16_t, "4"] + - ["*const i64", int64x2x2_t, i64, int64x2_t, "1"] + - ["*const f64", float64x2x2_t, f64, float64x2_t, "1"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[4]}" + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "a: {neon_type[3]}" + - "b: {neon_type[3]}" + - "n: i64" + - "ptr: *const i8" + links: + - link: "llvm.aarch64.neon.ld2lane.v{neon_type[1].lane}{type[2]}.p0i8" + arch: aarch64,arm64ec + - FnCall: ["_vld2{neon_type[1].lane_nox}", ["b.0", "b.1", "LANE as i64", "a as _"]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x2_t, i64, int64x1_t] + - ["*const f64", float64x1x2_t, f64, float64x1_t] + compose: + - FnCall: ["static_assert!", ['LANE == 0']] + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "a: {neon_type[3]}" + - "b: {neon_type[3]}" + - "n: i64" + - "ptr: *const i8" + links: + - link: "llvm.aarch64.neon.ld2lane.v{neon_type[1].lane}{type[2]}.p0i8" + arch: aarch64,arm64ec + - FnCall: ["_vld2{neon_type[1].lane_nox}", ["b.0", "b.1", "LANE as i64", "a as _"]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - "static_assert!" + - - 'LANE == 0' + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - "static_assert!" + - - 'LANE == 0' + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x16x2_t, int8x16x2_t, "4"] + - ["*const p8", poly8x16x2_t, int8x16x2_t, "4"] + - ["*const u64", uint64x2x2_t, int64x2x2_t, "1"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[3]}" + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x2_t, int64x2x2_t, "1"] + compose: + - FnCall: ["static_assert_uimm_bits!", [LANE, '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld2] + safety: + unsafe: [neon] + types: + - ["*const f64", float64x2x2_t, f64, float64x2_t] + - ["*const i64", int64x2x2_t, i64, int64x2_t] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const {neon_type[3]}" + links: + - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as _" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["*const f64", float64x1x2_t, f64, float64x1_t] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const {neon_type[3]}" + links: + - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as _" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld2] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-stable + assert_instr: [ld2] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-stable + assert_instr: [ld2r] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x2x2_t, i64] + - ["*const f64", float64x1x2_t, f64] + - ["*const f64", float64x2x2_t, f64] + compose: + - LLVMLink: + name: "vld2dup.{neon_type[1]}" + arguments: + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.ld2r.v{neon_type[1].lane}{type[2]}.p0{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].dup_nox}" + - - "a as _" + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-stable + assert_instr: [ld2r] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-aes + - *neon-stable + assert_instr: [ld2r] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].lane_nox}" + doc: "Load multiple 3-element structures to two registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i8', int8x16x3_t, int8x16_t, i8, '3'] + - ['*const i64', int64x2x3_t, int64x2_t, i64, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - LLVMLink: + name: 'ld3lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: "Load multiple 3-element structures to three registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const f64', float64x2x3_t, float64x2_t, f64, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - LLVMLink: + name: 'ld3lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const f64', float64x1x3_t, float64x1_t, f64] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'vld3.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: "Load multiple 3-element structures to two registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i64', int64x1x3_t, int64x1_t, i64] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'vld3.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const p8', poly8x16x3_t, int8x16x3_t, '4'] + - ['*const u8', uint8x16x3_t, int8x16x3_t, '4'] + - ['*const u64', uint64x2x3_t, int64x2x3_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const u64', uint64x1x3_t, int64x1x3_t, '1'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x2x3_t, int64x2x3_t] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', 1]] + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x1x3_t, int64x1x3_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + safety: + unsafe: [neon] + assert_instr: [ld3] + types: + - ['*const i64', int64x2x3_t, '*const int64x2_t', i64] + - ['*const f64', float64x2x3_t, '*const float64x2_t', f64] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].nox}' + arguments: + - 'ptr: {type[2]}' + links: + - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0v{neon_type[1].lane}{type[3]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + safety: + unsafe: [neon] + assert_instr: [nop] + types: + - ['*const f64', float64x1x3_t, '*const float64x1_t', f64] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].nox}' + arguments: + - 'ptr: {type[2]}' + links: + - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0v{neon_type[1].lane}{type[3]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + safety: + unsafe: [neon] + assert_instr: [ld3] + types: + - ['*const u64', uint64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-stable + safety: + unsafe: [neon] + assert_instr: [ld3] + types: + - ['*const p64', poly64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld3r] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x2x3_t, i64] + - ["*const f64", float64x1x3_t, f64] + - ["*const f64", float64x2x3_t, f64] + compose: + - LLVMLink: + name: 'ld3r{neon_type[1].dup_nox}' + arguments: + - 'ptr: {type[0]}' + links: + - link: 'llvm.aarch64.neon.ld3r.v{neon_type[1].lane}{type[2]}.p0{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].dup_nox}', ['a as _']] + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld3r] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld3{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-stable + assert_instr: [ld3r] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld3{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + assert_instr: [ld4] + safety: + unsafe: [neon] + types: + - ['*const f64', float64x2x4_t, f64, '*const float64x2_t'] + - ['*const i64', int64x2x4_t, i64, '*const int64x2_t'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: {type[3]}' + links: + - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ['*const f64', float64x1x4_t, f64, '*const float64x1_t'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: {type[3]}' + links: + - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ld4] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - *neon-aes + assert_instr: [ld4] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i8', int8x16x4_t, int8x16_t, i8, '3'] + - ['*const i64', int64x2x4_t, int64x2_t, i64, '1'] + - ['*const f64', float64x2x4_t, float64x2_t, f64, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - LLVMLink: + name: 'ld4lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld4lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i64', int64x1x4_t, int64x1_t, i64] + - ['*const f64', float64x1x4_t, float64x1_t, f64] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'ld4lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld4lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const p8', poly8x16x4_t, int8x16x4_t, '4'] + - ['*const u8', uint8x16x4_t, int8x16x4_t, '4'] + - ['*const u64', uint64x2x4_t, int64x2x4_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x2x4_t, int64x2x4_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const u64', uint64x1x4_t, int64x1x4_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: + - target_feature + - - 'enable = "neon,aes"' + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x1x4_t, int64x1x4_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + types: + - ['*mut f64', float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + types: + - ['*mut f64', float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *neon-stable + assert_instr: [st1] + types: + - ['f64', float64x1x2_t, float64x1_t] + compose: + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *neon-stable + assert_instr: [st2] + types: + - [i64, int64x2x2_t, int64x2_t] + - [f64, float64x2x2_t, float64x2_t] + compose: + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [i64, int64x1x2_t, int64x1_t] + - [f64, float64x1x2_t, float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].lane_nox}', ['b.0', 'b.1', 'LANE as i64', 'a as _']] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [i8, int8x16x2_t, int8x16_t, '4'] + - [i64, int64x2x2_t, int64x2_t, '1'] + - [f64, float64x2x2_t, float64x2_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].lane_nox}', ['b.0', 'b.1', 'LANE as i64', 'a as _']] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [u8, uint8x16x2_t, int8x16x2_t, '4'] + - [u64, uint64x2x2_t, int64x2x2_t, '1'] + - [p8, poly8x16x2_t, int8x16x2_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] + - FnCall: + - "vst2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [u64, uint64x1x2_t, int64x1x2_t, '1'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + assert_instr: [st2] + safety: + unsafe: [neon] + types: + - [u64, uint64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - "vst2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [p64, poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [p64, poly64x2x2_t, int64x2x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '1']] + - FnCall: + - "vst2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2]]}]] + - *neon-stable + safety: + unsafe: [neon] + types: + - [p64, poly64x2x2_t, int64x2x2_t] + compose: + - FnCall: + - "vst2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [f64, float64x1x3_t, float64x1_t] + compose: + - LLVMLink: + name: 'st3.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [p64, poly64x1x3_t, int64x1x3_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst3{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [p64, poly64x2x3_t, int64x2x3_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: + - "vst3{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + assert_instr: [st3] + safety: + unsafe: [neon] + types: + - [p64, poly64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - "vst3{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [st3] + safety: + unsafe: [neon] + types: + - [i64, int64x2x3_t, int64x2_t] + - [f64, float64x2x3_t, float64x2_t] + compose: + - LLVMLink: + name: 'st3.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [st3] + safety: + unsafe: [neon] + types: + - [u64, uint64x2x3_t, int64x2x3_t] + compose: + - FnCall: + - "vst3{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [u64, uint64x1x3_t, int64x1x3_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst3{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [u8, uint8x16x3_t, int8x16x3_t, '4'] + - [u64, uint64x2x3_t, int64x2x3_t, '1'] + - [p8, poly8x16x3_t, int8x16x3_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vst3{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [f64, float64x2x3_t, float64x2_t, '1'] + - [i8, int8x16x3_t, int8x16_t, '4'] + - [i64, int64x2x3_t, int64x2_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - LLVMLink: + name: 'st3lane.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i64, int64x1x3_t, int64x1_t, '1'] + - [f64, float64x1x3_t, float64x1_t, '1'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'st3lane.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [f64, float64x1x4_t, float64x1_t] + compose: + - LLVMLink: + name: 'st4.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [p64, poly64x1x4_t, int64x1x4_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst4{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [p64, poly64x2x4_t, int64x2x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: + - "vst4{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - *neon-aes + assert_instr: [st4] + safety: + unsafe: [neon] + types: + - [p64, poly64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - "vst4{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [st4] + safety: + unsafe: [neon] + types: + - [i64, int64x2x4_t, int64x2_t] + - [f64, float64x2x4_t, float64x2_t] + compose: + - LLVMLink: + name: 'st4.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*neon-stable] + assert_instr: [st4] + safety: + unsafe: [neon] + types: + - [u64, uint64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - "vst4{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [u64, uint64x1x4_t, int64x1x4_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vst4{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-stable + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [u8, uint8x16x4_t, int8x16x4_t, '4'] + - [u64, uint64x2x4_t, int64x2x4_t, '1'] + - [p8, poly8x16x4_t, int8x16x4_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vst4{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [f64, float64x2x4_t, float64x2_t, '1'] + - [i8, int8x16x4_t, int8x16_t, '4'] + - [i64, int64x2x4_t, int64x2_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - LLVMLink: + name: 'st4lane.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i64, int64x1x4_t, int64x1_t, '1'] + - [f64, float64x1x4_t, float64x1_t, '1'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - LLVMLink: + name: 'st4lane.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vusdot{neon_type[0].laneq_nox}" + doc: "Dot product index form with unsigned and signed integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-i8mm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usdot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [int32x2_t, uint8x8_t, int8x16_t, '[LANE as u32, LANE as u32]'] + - [int32x4_t, uint8x16_t, int8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: [c, int32x4_t, {FnCall: [transmute, [c]]}] + - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[3]}"]]}] + - FnCall: ["vusdot{neon_type[0].no}", [a, b, {FnCall: [transmute, [c]]}]] + + - name: "vsudot{neon_type[0].laneq_nox}" + doc: "Dot product index form with signed and unsigned integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-i8mm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sudot, 'LANE = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [int32x2_t, int8x8_t, uint8x16_t, '[LANE as u32, LANE as u32]', uint32x2_t] + - [int32x4_t, int8x16_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 2]] + - Let: + - c + - uint32x4_t + - FnCall: [transmute, [c]] + - Let: + - c + - "{type[4]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ["vusdot{neon_type[0].no}", [a, {FnCall: [transmute, [c]]}, b]] + + - name: "vmul{neon_type.no}" + doc: Multiply + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fmul] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_mul, [a, b]] + + - name: "vmull_high{neon_type[0].noq}" + doc: Signed multiply long + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[3]}" + attr: [*neon-stable] + assert_instr: [smull2] + safety: + unsafe: [neon] + types: + - [int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int16x8_t] + - [int16x8_t, int16x4_t, '[4, 5, 6, 7]', int32x4_t] + - [int32x4_t, int32x2_t, '[2, 3]', int64x2_t] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] + - Let: + - b + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: ["vmull_{neon_type[0]}", [a, b]] + + - name: "vmull_high{neon_type[0].noq}" + doc: "Unsigned multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[3]}" + attr: [*neon-stable] + assert_instr: [umull2] + safety: + unsafe: [neon] + types: + - [uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint16x8_t] + - [uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', uint32x4_t] + - [uint32x4_t, uint32x2_t, '[2, 3]', uint64x2_t] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] + - Let: + - b + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: ["vmull_{neon_type[0]}", [a, b]] + + - name: "vmull_p64" + doc: "Polynomial multiply long" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-aes + - *neon-stable + safety: + unsafe: [neon] + assert_instr: [pmull] + types: + - ["p64", "p128"] + compose: + - LLVMLink: + name: "pmull.{type[0]}" + return_type: "int8x16_t" + links: + - link: "llvm.aarch64.neon.pmull64" + arch: aarch64,arm64ec + - FnCall: [transmute, [{FnCall: ["_vmull_p64", [a, b]]}]] + + - name: "vmull_high{neon_type[0].noq}" + doc: "Polynomial multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[3]}" + attr: + - *neon-stable + safety: + unsafe: [neon] + assert_instr: [pmull] + types: + - [poly8x16_t, poly8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', poly16x8_t] + compose: + - Let: + - a + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] + - Let: + - b + - "{neon_type[1]}" + - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - FnCall: ["vmull_{neon_type[0]}", [a, b]] + + - name: "vmull_high{neon_type[0].noq}" + doc: "Polynomial multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-aes + - *neon-stable + safety: + unsafe: [neon] + assert_instr: [pmull] + types: + - [poly64x2_t, "p128"] + compose: + - FnCall: + - "vmull_{neon_type[0]}" + - - FnCall: [simd_extract!, [a, '1']] + - FnCall: [simd_extract!, [b, '1']] + + - name: "vmulx{neon_type.no}" + doc: Floating-point multiply extended + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fmulx] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fmulx.{neon_type.no}" + links: + - link: "llvm.aarch64.neon.fmulx.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmulx{type[0]}" + doc: Floating-point multiply extended + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [fmulx] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32"] + - ["d_f64", "f64"] + compose: + - LLVMLink: + name: "fmulx.{type[1]}" + links: + - link: "llvm.aarch64.neon.fmulx.{type[1]}" + arch: aarch64,arm64ec + + - name: "vmulx_lane_f64" + doc: Floating-point multiply extended + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - vmulx_f64 + - - a + - FnCall: + - 'transmute::' + - - FnCall: + - "simd_extract!" + - - b + - 'LANE as u32' + + - name: "vmulx{type[0]}" + doc: Floating-point multiply extended + arguments: ["a: {type[1]}", "b: {neon_type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ["q_lane_f64", float64x2_t, float64x1_t, "q_f64", '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vmulx{type[3]}" + - - a + - FnCall: + - "simd_shuffle!" + - - b + - b + - "{type[4]}" + + - name: "vmulx{type[0]}" + doc: Floating-point multiply extended + arguments: ["a: {type[1]}", "b: {neon_type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ["d_lane_f64", "f64", float64x1_t, "d_f64", 'LANE as u32'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - "vmulx{type[3]}" + - - a + - FnCall: + - "simd_extract!" + - - b + - "{type[4]}" + + - name: "vmulx_laneq_f64" + doc: Floating-point multiply extended + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float64x1_t, float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '1']] + - FnCall: + - vmulx_f64 + - - a + - FnCall: + - 'transmute::' + - - FnCall: + - "simd_extract!" + - - b + - 'LANE as u32' + + - name: "vmulx{type[0]}" + doc: Floating-point multiply extended + arguments: ["a: {type[1]}", "b: {neon_type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['_lane_f32', float32x2_t, float32x2_t, '1', '_f32', '[LANE as u32, LANE as u32]'] + - ['_laneq_f32', float32x2_t, float32x4_t, '2', '_f32', '[LANE as u32, LANE as u32]'] + - ['q_lane_f32', float32x4_t, float32x2_t, '1', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - ['q_laneq_f32', float32x4_t, float32x4_t, '2', 'q_f32', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - ['q_laneq_f64', float64x2_t, float64x2_t, '1', 'q_f64', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] + - FnCall: + - "vmulx{type[4]}" + - - a + - FnCall: + - "simd_shuffle!" + - - b + - b + - "{type[5]}" + + - name: "vmulx{type[0]}" + doc: Floating-point multiply extended + arguments: ["a: {type[1]}", "b: {neon_type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmulx, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['s_lane_f32', f32, float32x2_t, '1', 's_f32', 'LANE as u32'] + - ['s_laneq_f32', f32, float32x4_t, '2', 's_f32', 'LANE as u32'] + - ['d_laneq_f64', f64, float64x2_t, '1', 'd_f64', 'LANE as u32'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] + - FnCall: + - "vmulx{type[4]}" + - - a + - FnCall: + - "simd_extract!" + - - b + - "{type[5]}" + + - name: "vfma{neon_type.no}" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-stable + assert_instr: [fmadd] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - LLVMLink: + name: "_vfma{neon_type.no}" + arguments: ["a: {type}", "b: {type}", "c: {type}"] + links: + - link: "llvm.fma.{neon_type}" + arch: aarch64,arm64ec + - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + + - name: "vfma{neon_type.no}" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-stable + assert_instr: [fmla] + safety: + unsafe: [neon] + types: + - float64x2_t + compose: + - LLVMLink: + name: "_vfma{neon_type.no}" + arguments: ["a: {type}", "b: {type}", "c: {type}"] + links: + - link: "llvm.fma.{neon_type}" + arch: aarch64,arm64ec + - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + + - name: "vfma_n_f64" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + assert_instr: [fmadd] + safety: + unsafe: [neon] + types: + - [float64x1_t, f64] + compose: + - FnCall: + - "vfma_f64" + - - a + - b + - FnCall: + - "vdup_n_f64" + - - c + + - name: "vfmaq_n_f64" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + assert_instr: [fmla] + safety: + unsafe: [neon] + types: + - [float64x2_t, f64] + compose: + - FnCall: + - "vfmaq_f64" + - - a + - b + - FnCall: + - "vdupq_n_f64" + - - c + + - name: "vdiv{neon_type.no}" + doc: "Divide" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fdiv] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_div, [a, b]] + + - name: "vsub{neon_type.no}" + doc: "Subtract" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fsub] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_sub, [a, b]] + + - name: "vsub{type[0]}" + doc: "Subtract" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ['d_s64', 'i64'] + - ['d_u64', 'u64'] + compose: + - MethodCall: [a, wrapping_sub, [b]] + + - name: "vaddv{neon_type[0].no}" + doc: Floating-point add across vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + assert_instr: [faddp] + safety: + unsafe: [neon] + types: + - [float32x2_t, f32] + - [float32x4_t, f32] + - [float64x2_t, f64] + compose: + - LLVMLink: + name: "faddv.{type[1]}.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.faddv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vaddlv{neon_type[0].no}" + doc: Signed Add Long across Vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [saddlv] + safety: + unsafe: [neon] + types: + - [int16x4_t, i32] + - [int16x8_t, i32] + - [int32x4_t, i64] + compose: + - LLVMLink: + name: "llvm.aarch64.neon.saddlv.{type[1]}.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.saddlv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vaddlv{neon_type.no}" + doc: Signed Add Long across Vector + arguments: ["a: {neon_type}"] + return_type: "i64" + attr: [*neon-stable] + assert_instr: [saddlp] + safety: + unsafe: [neon] + types: + - int32x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.saddlv.i64.v2i32" + links: + - link: "llvm.aarch64.neon.saddlv.i64.v2i32" + arch: aarch64,arm64ec + + - name: "vaddlv{neon_type[0].no}" + doc: Unsigned Add Long across Vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [uaddlv] + safety: + unsafe: [neon] + types: + - [uint16x4_t, u32, i32] + - [uint16x8_t, u32, i32] + - [uint32x4_t, u64, i64] + compose: + - LLVMLink: + name: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vaddlv{neon_type[0].no}" + doc: Unsigned Add Long across Vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [uaddlp] + safety: + unsafe: [neon] + types: + - [uint32x2_t, u64, i64] + compose: + - LLVMLink: + name: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.uaddlv.{type[2]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vsubw_high{neon_type[1].noq}" + doc: Signed Subtract Wide + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: [*neon-stable] + assert_instr: [ssubw] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x16_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [int32x4_t, int16x8_t, int16x4_t, '[4, 5, 6, 7]'] + - [int64x2_t, int32x4_t, int32x2_t, '[2, 3]'] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: + - simd_sub + - - a + - FnCall: [simd_cast, [c]] + + - name: "vsubw_high{neon_type[1].noq}" + doc: Unsigned Subtract Wide + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: [*neon-stable] + assert_instr: [usubw] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]'] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - FnCall: + - simd_sub + - - a + - FnCall: [simd_cast, [c]] + + - name: "vsubl_high{neon_type[0].noq}" + doc: "Signed Subtract Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [ssubl] + safety: + unsafe: [neon] + types: + - [int8x16_t, int16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t] + - [int16x8_t, int32x4_t, '[4, 5, 6, 7]', int16x4_t] + - [int32x4_t, int64x2_t, '[2, 3]', int32x2_t] + compose: + - Let: + - c + - "{neon_type[3]}" + - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] + - Let: + - d + - "{neon_type[1]}" + - FnCall: [simd_cast, [c]] + - Let: + - e + - "{neon_type[3]}" + - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: + - f + - "{neon_type[1]}" + - FnCall: [simd_cast, [e]] + - FnCall: [simd_sub, [d, f]] + + - name: "vsubl_high{neon_type[0].noq}" + doc: "Unsigned Subtract Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [usubl] + safety: + unsafe: [neon] + types: + - [uint8x16_t, uint16x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', uint8x8_t] + - [uint16x8_t, uint32x4_t, '[4, 5, 6, 7]', uint16x4_t] + - [uint32x4_t, uint64x2_t, '[2, 3]', uint32x2_t] + compose: + - Let: + - c + - "{neon_type[3]}" + - FnCall: [simd_shuffle!, [a, a, "{type[2]}"]] + - Let: + - d + - "{neon_type[1]}" + - FnCall: [simd_cast, [c]] + - Let: + - e + - "{neon_type[3]}" + - FnCall: [simd_shuffle!, [b, b, "{type[2]}"]] + - Let: + - f + - "{neon_type[1]}" + - FnCall: [simd_cast, [e]] + - FnCall: [simd_sub, [d, f]] + + - name: "vbcax{neon_type.no}" + doc: Bit clear and exclusive OR + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + assert_instr: [bcax] + safety: + unsafe: [neon] + types: + - int8x16_t + - int16x8_t + - int32x4_t + - int64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.crypto.bcaxs.{neon_type}" + links: + - link: "llvm.aarch64.crypto.bcaxs.{neon_type}" + arch: aarch64,arm64ec + + - name: "vbcax{neon_type.no}" + doc: Bit clear and exclusive OR + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + assert_instr: [bcax] + safety: + unsafe: [neon] + types: + - uint8x16_t + - uint16x8_t + - uint32x4_t + - uint64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.crypto.bcaxu.{neon_type}" + links: + - link: "llvm.aarch64.crypto.bcaxu.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcadd{neon_type.rot270}" + doc: "Floating-point complex add" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcadd] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcadd.rot270.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcadd.rot270.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcadd{neon_type.rot90}" + doc: "Floating-point complex add" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcadd] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcadd.rot90.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcadd.rot90.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcmla{neon_type.no}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcmla] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcmla.rot0.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcmla.rot0.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcmla{neon_type.rot90}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcmla] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcmla.rot90.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcmla.rot90.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcmla{neon_type.rot270}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcmla] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcmla.rot270.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcmla.rot270.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcmla{neon_type[0].laneq_nox}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 1]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] + + - name: "vcmla{neon_type[0].rot90_laneq}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 1]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] + + - name: "vcmla{neon_type[0].rot90_lane}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].rot90}", [a, b, c]] + + - name: "vcmla{neon_type.rot180}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - *neon-unstable-fcma + assert_instr: [fcmla] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "llvm.aarch64.neon.vcmla.rot180.{neon_type}" + links: + - link: "llvm.aarch64.neon.vcmla.rot180.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcmla{neon_type[0].rot180_laneq}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 1]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] + + - name: "vcmla{type[3]}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]', '_rot180_lane_f32'] + - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]', 'q_rot180_lane_f32'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].rot180}", [a, b, c]] + + - name: "vcmla{neon_type[0].rot270_laneq}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x4_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, 1]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] + + - name: "vcmla{neon_type[0].lane_nox}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, "{type[2]}"]] + - FnCall: ["vcmla{neon_type[0].no}", [a, b, c]] + + - name: "vcmla{neon_type[0].rot270_lane}" + doc: Floating-point complex multiply accumulate + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [target_feature, ['enable = "neon,fcma"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-fcma + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1]'] + - [float32x4_t, float32x2_t, '[2 * LANE as u32, 2 * LANE as u32 + 1, 2 * LANE as u32, 2 * LANE as u32 + 1]'] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Let: [c, "{neon_type[0]}", {FnCall: [simd_shuffle!, [c, c, "{type[2]}"]]}] + - FnCall: ["vcmla{neon_type[0].rot270}", [a, b, c]] + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + attr: + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: + unsafe: [neon] + types: + - [int32x2_t, int8x8_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32]'] + - [int32x4_t, int8x16_t, int8x16_t, int32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + + - name: "vdot{neon_type[0].laneq_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + attr: + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']] + safety: + unsafe: [neon] + types: + - [uint32x2_t, uint8x8_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint8x16_t, uint8x16_t, uint32x4_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '2']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + + - name: "vmax{neon_type.no}" + doc: Maximum (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fmax] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fmax.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmax.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmaxnm{neon_type.no}" + doc: Floating-point Maximum Number (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fmaxnm] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmaxnmv{neon_type[0].no}" + doc: Floating-point maximum number across vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [fmaxnmp] + safety: + unsafe: [neon] + types: + - [float32x2_t, f32] + - [float64x2_t, f64] + compose: + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vmaxnmv{neon_type[0].no}" + doc: Floating-point maximum number across vector + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [fmaxnmv] + safety: + unsafe: [neon] + types: + - [float32x4_t, f32] + compose: + - LLVMLink: + name: "fmaxnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vpmax{type[0]}" + doc: "Floating-point maximum pairwise" + arguments: ["a: {neon_type[1]}"] + return_type: "{type[2]}" + attr: [*neon-stable] + assert_instr: [fmaxp] + safety: + unsafe: [neon] + types: + - ["s_f32", float32x2_t, f32] + - ["qd_f64", float64x2_t, f64] + compose: + - LLVMLink: + name: "fmaxv.{type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxv.{type[2]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vmin{neon_type.no}" + doc: "Minimum (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fmin] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fmin.{neon_type}" + links: + - link: "llvm.aarch64.neon.fmin.{neon_type}" + arch: aarch64,arm64ec + + - name: "vminnm{neon_type.no}" + doc: "Floating-point Minimum Number (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: [*neon-stable] + assert_instr: [fminnm] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec + + - name: "vminnmv{neon_type[0].no}" + doc: "Floating-point minimum number across vector" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, "f32"] + - [float64x2_t, "f64"] + compose: + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vminnmv{neon_type[0].no}" + doc: "Floating-point minimum number across vector" + arguments: ["a: {neon_type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmv]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x4_t, "f32"] + compose: + - LLVMLink: + name: "vminnmv.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vmovl_high{neon_type[0].noq}" + doc: Vector move + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [sxtl2] + safety: + unsafe: [neon] + types: + - [int8x16_t, int16x8_t, int8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] + - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + compose: + - Let: + - a + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ["vmovl{neon_type[0].noq}", [a]] + + - name: "vmovl_high{neon_type[0].noq}" + doc: Vector move + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: [*neon-stable] + assert_instr: [uxtl2] + safety: + unsafe: [neon] + types: + - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] + - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + compose: + - Let: + - a + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + - FnCall: ["vmovl{neon_type[0].noq}", [a]] + + - name: "vpadd{neon_type.no}" + doc: Floating-point add pairwise + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{type}" + attr: [*neon-stable] + assert_instr: [faddp] + safety: + unsafe: [neon] + types: + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "faddp.{neon_type}" + links: + - link: "llvm.aarch64.neon.faddp.{neon_type}" + arch: aarch64,arm64ec + + - name: "vpadd{type[0]}" + doc: "Floating-point add pairwise" + arguments: ["a: {neon_type[1]}"] + return_type: "{type[2]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["s_f32", float32x2_t, f32] + - ["d_f64", float64x2_t, f64] + compose: + - Let: + - a1 + - "{type[2]}" + - FnCall: [simd_extract!, [a, '0']] + - Let: + - a2 + - "{type[2]}" + - FnCall: [simd_extract!, [a, '1']] + - Identifier: ['a1 + a2', Symbol] + + - name: "vpmin{type[0]}" + doc: Floating-point minimum pairwise + arguments: ["a: {neon_type[1]}"] + return_type: "{type[2]}" + attr: [*neon-stable] + assert_instr: [fminp] + safety: + unsafe: [neon] + types: + - ["s_f32", float32x2_t, f32] + - ["qd_f64", float64x2_t, f64] + compose: + - LLVMLink: + name: "fminv.{type[2]}.{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.fminv.{type[2]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqdmullh_s16" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i16", "i32"] + compose: + - Let: [a, int16x4_t, {FnCall: [vdup_n_s16, [a]]}] + - Let: [b, int16x4_t, {FnCall: [vdup_n_s16, [b]]}] + - FnCall: [simd_extract!, [{FnCall: [vqdmull_s16, [a, b]]}, '0']] + + - name: "vqdmulls_s32" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i32", "i64"] + compose: + - LLVMLink: + name: "vqdmulls_s32" + links: + - link: "llvm.aarch64.neon.sqdmulls.scalar" + arch: aarch64,arm64ec + + - name: "vqdmull_high{neon_type[0].noq}" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]'] + - [int32x4_t, int64x2_t, int32x2_t, '[2, 3]'] + compose: + - Let: [a, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, '{type[3]}']]}] + - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, '{type[3]}']]}] + - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] + + - name: "vqdmull_high_n_{type[1]}" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int16x8_t, "i16", int32x4_t, int16x4_t, '[4, 5, 6, 7]'] + - [int32x4_t, "i32", int64x2_t, int32x2_t, '[2, 3]'] + compose: + - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}] + - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] + + - name: "vqdmull{type[3]}" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, "i32", 'h_lane_s16', 'h_s16'] + - ["i32", int32x4_t, "i64", 's_laneq_s32', 's_s32'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 2]] + - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - FnCall: ["vqdmull{type[4]}", [a, b]] + + - name: "vqdmullh_laneq_s16" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, N = 4]]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x8_t, "i32"] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 3]] + - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - FnCall: ["vqdmullh_s16", [a, b]] + + - name: "vqdmulls_lane_s32" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i32", int32x2_t, "i64"] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - Let: [b, "{type[0]}", {FnCall: [simd_extract!, [b, 'N as u32']]}] + - FnCall: ["vqdmulls_s32", [a, b]] + + - name: "vqdmull{type[6]}" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int16x4_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]', '_high_lane_s16'] + - [int32x4_t, int32x4_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]', '_high_laneq_s32'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] + + - name: "vqdmull_high_lane_s32" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int32x2_t, int64x2_t, int32x2_t, '[2, 3]', '[N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '1']] + - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] + + - name: "vqdmull_high_laneq_s16" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull2, N = 4]]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int16x8_t, int32x4_t, int16x4_t, '[4, 5, 6, 7]', '[N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '3']] + - Let: [a, "{neon_type[3]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - Let: [b, "{neon_type[3]}", {FnCall: [simd_shuffle!, [b, b, "{type[5]}"]]}] + - FnCall: ["vqdmull{neon_type[0].noq}", [a, b]] + + - name: "vqdmull_laneq_s16" + doc: "Vector saturating doubling long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 4']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x8_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '3']] + - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - FnCall: [vqdmull_s16, [a, b]] + + - name: "vqdmull_laneq_s32" + doc: "Vector saturating doubling long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, int32x4_t, int64x2_t, '[N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - FnCall: [vqdmull_s32, [a, b]] + + - name: "vqdmlal{type[4]}" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] + - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, _high_s32] + - [int32x4_t, int16x8_t, "i16", int32x4_t, _high_n_s16] + - [int64x2_t, int32x4_t, "i32", int64x2_t, _high_n_s32] + compose: + - FnCall: ["vqadd{neon_type[0].no}", [a, {FnCall: ["vqdmull{type[4]}", [b, c]]}]] + + - name: "vqdmlal{type[4]}" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal2, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x4_t, int32x4_t, _high_lane_s16, '2'] + - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_laneq_s16, '3'] + - [int64x2_t, int32x4_t, int32x2_t, int64x2_t, _high_lane_s32, '1'] + - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, _high_laneq_s32, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[5]}"]] + - FnCall: ["vqadd{neon_type[0].no}", [a, {FnCall: ["vqdmull{type[4]}::", [b, c]]}]] + + - name: "vqdmlalh_{type[2]}" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i32", "i16", "s16"] + compose: + - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] + - FnCall: [vqadds_s32, [a, {FnCall: [simd_extract!, [x, 0]]}]] + + - name: "vqdmlals_s32" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "i32", "i32", "i64"] + compose: + - Let: [x, i64, {FnCall: [vqaddd_s64, [a, {FnCall: [vqdmulls_s32, [b, c]]}]]}] + - Identifier: ['x as i64', Symbol] + + - name: "vqdmlal{type[4]}" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i32", "i16", int16x4_t, "i32", h_lane_s16, '2', h_s16] + - ["i32", "i16", int16x8_t, "i32", h_laneq_s16, '3', h_s16] + - ["i64", "i32", int32x2_t, "i64", s_lane_s32, '1', s_s32] + - ["i64", "i32", int32x4_t, "i64", s_laneq_s32, '2', s_s32] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] + - FnCall: ["vqdmlal{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vqdmlal_laneq_s16" + doc: "Vector widening saturating doubling multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x8_t, int32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '3']] + - FnCall: [vqaddq_s32, [a, {FnCall: ["vqdmull_laneq_s16::", [b, c]]}]] + + - name: "vqdmlal_laneq_s32" + doc: "Vector widening saturating doubling multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int32x2_t, int32x4_t, int64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - FnCall: [vqaddq_s64, [a, {FnCall: ["vqdmull_laneq_s32::", [b, c]]}]] + + - name: "vqdmlsl{type[4]}" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, _high_s16] + - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, _high_s32] + - [int32x4_t, int16x8_t, "i16", int32x4_t, _high_n_s16] + - [int64x2_t, int32x4_t, "i32", int64x2_t, _high_n_s32] + compose: + - FnCall: ["vqsub{neon_type[0].no}", [a, {FnCall: ["vqdmull{type[4]}", [b, c]]}]] + + - name: "vqdmlsl{type[4]}" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl2, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x4_t, int32x4_t, '_high_lane_s16', '2'] + - [int32x4_t, int16x8_t, int16x8_t, int32x4_t, '_high_laneq_s16', '3'] + - [int64x2_t, int32x4_t, int32x2_t, int64x2_t, '_high_lane_s32', '1'] + - [int64x2_t, int32x4_t, int32x4_t, int64x2_t, '_high_laneq_s32', '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[5]}"]] + - FnCall: ["vqsub{neon_type[0].no}", [a, {FnCall: ["vqdmull{type[4]}::", [b, c]]}]] + + - name: "vqdmlslh_s16" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i32", "i16"] + compose: + - Let: [x, int32x4_t, {FnCall: [vqdmull_s16, [{FnCall: [vdup_n_s16, [b]]}, {FnCall: [vdup_n_s16, [c]]}]]}] + - FnCall: [vqsubs_s32, [a, {FnCall: [simd_extract!, [x, '0']]}]] + + - name: "vqdmlsls_s32" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "i32", "i32", "i64"] + compose: + - Let: [x, i64, {FnCall: [vqsubd_s64, [a, {FnCall: [vqdmulls_s32, [b, c]]}]]}] + - Identifier: ['x as i64', Symbol] + + - name: "vqdmlsl{type[4]}" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {type[0]}", "b: {type[1]}", "c: {neon_type[2]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i32", "i16", int16x4_t, "i32", 'h_lane_s16', '2', 'h_s16'] + - ["i32", "i16", int16x8_t, "i32", 'h_laneq_s16', '3', 'h_s16'] + - ["i64", "i32", int32x2_t, "i64", 's_lane_s32', '1', 's_s32'] + - ["i64", "i32", int32x4_t, "i64", 's_laneq_s32', '2', 's_s32'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[5]}"]] + - FnCall: ["vqdmlsl{type[6]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vqdmlsl_laneq_s16" + doc: "Vector widening saturating doubling multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x8_t, int32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '3']] + - FnCall: ["vqsubq_s32", [a, {FnCall: ["vqdmull_laneq_s16::", [b, c]]}]] + + - name: "vqdmlsl_laneq_s32" + doc: "Vector widening saturating doubling multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int32x2_t, int32x4_t, int64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - FnCall: [vqsubq_s64, [a, {FnCall: ["vqdmull_laneq_s32::", [b, c]]}]] + + - name: "vqdmulh{type[4]}" + doc: "Signed saturating doubling multiply returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i16", "i16", "i16", int16x4_t, 'h_s16'] + - ["i32", "i32", "i32", int32x2_t, 's_s32'] + compose: + - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [a]]}] + - Let: [b, "{neon_type[3]}", {FnCall: ["vdup_n{neon_type[3].no}", [b]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqdmulh{neon_type[3].no}", [a, b]]}, '0']] + + - name: "vqdmulhh{type[3]}" + doc: "Signed saturating doubling multiply returning high half" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, "i16", '_lane_s16', '2'] + - ["i16", int16x8_t, "i16", '_laneq_s16', '3'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] + - Let: [b, 'i16', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - FnCall: ['vqdmulhh_s16', [a, b]] + + - name: "vqdmulhs{type[3]}" + doc: "Signed saturating doubling multiply returning high half" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i32", int32x2_t, "i32", "_lane_s32", '1'] + - ["i32", int32x4_t, "i32", "_laneq_s32", '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[4]}"]] + - Let: [b, 'i32', {FnCall: [simd_extract!, [b, 'N as u32']]}] + - FnCall: ['vqdmulhs_s32', [a, b]] + + - name: "vqmovn_high{neon_type[1].noq}" + doc: "Signed saturating extract narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + compose: + - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + + - name: "vqmovn_high{neon_type[1].noq}" + doc: "Signed saturating extract narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + compose: + - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovn{neon_type[1].noq}", [b]]}, "{type[3]}"]] + + - name: "vqmovn{type[2]}" + doc: "Saturating extract narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i16", "i8", 'h_s16', s16] + - ["i32", "i16", 's_s32', s32] + compose: + - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + + - name: "vqmovn{type[2]}" + doc: "Saturating extract narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u16", "u8", 'h_u16', 'u16'] + - ["u32", "u16", 's_u32', 'u32'] + compose: + - FnCall: [simd_extract!, [{FnCall: ["vqmovn_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + + - name: "vqmovnd_s64" + doc: "Saturating extract narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "i32"] + compose: + - LLVMLink: + name: "vqmovnd_s64" + links: + - link: "llvm.aarch64.neon.scalar.sqxtn.i32.i64" + arch: aarch64,arm64ec + + - name: "vqmovnd_u64" + doc: "Saturating extract narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqxtn]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u64", "u32"] + compose: + - LLVMLink: + name: "vqmovnd_u64" + links: + - link: "llvm.aarch64.neon.scalar.uqxtn.i32.i64" + arch: aarch64,arm64ec + + - name: "vqmovun{type[2]}" + doc: "Signed saturating extract unsigned narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i16", "u8", 'h_s16', s16] + - ["i32", "u16", 's_s32', s32] + - ["i64", "u32", 'd_s64', s64] + compose: + - FnCall: [simd_extract!, [{FnCall: ["vqmovun_{type[3]}", [{FnCall: ["vdupq_n_{type[3]}", [a]]}]]}, '0']] + + - name: "vqmovun_high_{neon_type[1]}" + doc: "Signed saturating extract unsigned narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqxtun2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int16x8_t, uint8x16_t, s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, int32x4_t, uint16x8_t, s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, int64x2_t, uint32x4_t, s64, '[0, 1, 2, 3]'] + compose: + - FnCall: [simd_shuffle!, [a, {FnCall: ["vqmovun_{type[3]}", [b]]}, "{type[4]}"]] + + - name: "vqrdmulh{type[1]}" + doc: "Signed saturating rounding doubling multiply returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i16", 'h_s16', 's16'] + - ["i32", 's_s32', 's32'] + compose: + - FnCall: [simd_extract!, [{FnCall: ["vqrdmulh_{type[2]}", [{FnCall: ["vdup_n_{type[2]}", [a]]}, {FnCall: ["vdup_n_{type[2]}", [b]]}]]}, '0']] + + - name: "vqrdmulh{type[2]}" + doc: "Signed saturating rounding doubling multiply returning high half" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmulh, LANE = 1]]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, 'h_lane_s16', 'h_s16', '2'] + - ["i16", int16x8_t, 'h_laneq_s16', 'h_s16', '3'] + - ["i32", int32x2_t, 's_lane_s32', 's_s32', '1'] + - ["i32", int32x4_t, 's_laneq_s32', 's_s32', '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: ["vqrdmulh{type[3]}", [a, {FnCall: [simd_extract!, [b, 'LANE as u32']]}]] + + - name: "vqrdmlah{neon_type.no}" + doc: "Signed saturating rounding doubling multiply accumulate returning high half" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah]]}]] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + safety: + unsafe: [neon] + types: + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "vqrdmlah{neon_type.no}" + links: + - link: "llvm.aarch64.neon.sqrdmlah.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqrdmlah{type[3]}" + doc: "Signed saturating rounding doubling multiply accumulate returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah]]}]] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, s16, 'h_s16'] + - ["i32", int32x2_t, s32, 's_s32'] + compose: + - Let: [a, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [a]]}] + - Let: [b, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [b]]}] + - Let: [c, "{neon_type[1]}", {FnCall: ["vdup_n_{type[2]}", [c]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrdmlah_{type[2]}", [a, b, c]]}, '0']] + + - name: "vqrdmlah{type[0]}" + doc: "Signed saturating rounding doubling multiply accumulate returning high half" + arguments: ["a: {type[1]}", "b: {type[2]}", "c: {neon_type[3]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - FnCall: ["vqrdmlah{neon_type[2].no}", [a, b, c]] + + - name: "vqrdmlah{type[4]}" + doc: "Signed saturating rounding doubling multiply accumulate returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlah, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, '2', "h_s16", h_lane_s16, h_s16] + - ["i16", int16x8_t, '3', "h_s16", h_laneq_s16, h_s16] + - ["i32", int32x2_t, '1', "s_s32", s_lane_s32, s_s32] + - ["i32", int32x4_t, '2', "s_s32", s_laneq_s32, s_s32] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - FnCall: ["vqrdmlah{type[5]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vqrdmlsh{neon_type.no}" + doc: "Signed saturating rounding doubling multiply subtract returning high half" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh]]}]] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + safety: + unsafe: [neon] + types: + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "vqrdmlsh{neon_type.no}" + links: + - link: "llvm.aarch64.neon.sqrdmlsh.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqrdmlsh{type[1]}" + doc: "Signed saturating rounding doubling multiply subtract returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh]]}]] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + safety: + unsafe: [neon] + types: + - ["i16", "h_s16", int16x4_t, s16] + - ["i32", "s_s32", int32x2_t, s32] + compose: + - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] + - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] + - Let: [c, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [c]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrdmlsh_{type[3]}", [a, b, c]]}, '0']] + + - name: "vqrdmlsh{type[0]}" + doc: "Signed saturating rounding doubling multiply subtract returning high half" + arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}", "c: {neon_type[3]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh, LANE = 1]]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_s16, int16x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_s16, int16x8_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_s32, int32x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_s32, int32x4_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s32, int32x4_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - Let: [c, "{type[1]}", {FnCall: [simd_shuffle!, [c, c, "{type[5]}"]]}] + - FnCall: ["vqrdmlsh{neon_type[2].no}", [a, b, c]] + + - name: "vqrdmlsh{type[3]}" + doc: "Signed saturating rounding doubling multiply subtract returning high half" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [target_feature, ['enable = "rdm"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrdmlsh, LANE = 1]]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "rdm_intrinsics"', 'since = "1.62.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i16", int16x4_t, '2', h_lane_s16, h_s16] + - ["i16", int16x8_t, '3', h_laneq_s16, h_s16] + - ["i32", int32x2_t, '1', s_lane_s32, s_s32] + - ["i32", int32x4_t, '2', s_laneq_s32, s_s32] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - FnCall: ["vqrdmlsh{type[4]}", [a, b, {FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vqrshl{type[0]}" + doc: "Signed saturating rounding shift left" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['s_s32', "i32"] + - ['d_s64', "i64"] + compose: + - LLVMLink: + name: "vqrshl{type[0]}" + links: + - link: "llvm.aarch64.neon.sqrshl.{type[1]}" + arch: aarch64,arm64ec + + - name: "vqrshl{type[1]}" + doc: "Signed saturating rounding shift left" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i8", 'b_s8', int8x8_t, s8] + - ["i16", 'h_s16', int16x4_t, s16] + compose: + - Let: [a, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [a]]}] + - Let: [b, "{neon_type[2]}", {FnCall: ["vdup_n_{type[3]}", [b]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[3]}", [a, b]]}, '0']] + + - name: "vqrshl{type[2]}" + doc: "Unsigned signed saturating rounding shift left" + arguments: ["a: {type[0]}", "b: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u32", "i32", 's_u32'] + - ["u64", "i64", 'd_u64'] + compose: + - LLVMLink: + name: "vqrshl{type[2]}" + links: + - link: "llvm.aarch64.neon.uqrshl.{type[1]}" + arch: aarch64,arm64ec + + - name: "vqrshl{type[2]}" + doc: "Unsigned signed saturating rounding shift left" + arguments: ["a: {type[0]}", "b: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u8", "i8", "b_u8", uint8x8_t, int8x8_t, s8] + - ["u16", "i16", "h_u16", uint16x4_t, int16x4_t, s16] + compose: + - Let: [a, "{neon_type[3]}", {FnCall: ["vdup_n_{type[0]}", [a]]}] + - Let: [b, "{neon_type[4]}", {FnCall: ["vdup_n_{type[5]}", [b]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrshl_{type[0]}", [a, b]]}, '0']] + + - name: "vqrshrn{type[2]}" + doc: "Signed saturating rounded shift right narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i16", "i8", 'h_n_s16', 'N >= 1 && N <= 8', int16x8_t, q_n_s16] + - ["i32", "i16", 's_n_s32', 'N >= 1 && N <= 16', int32x4_t, q_n_s32] + - ["i64", "i32", 'd_n_s64', 'N >= 1 && N <= 32', int64x2_t, q_n_s64] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrshrn_n{neon_type[4].noq}::", [a]]}, '0']] + + - name: "vqrshrn{type[3]}" + doc: "Signed saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, '_high_n_s16', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', 'N >= 1 && N <= 8'] + - [int16x4_t, int32x4_t, int16x8_t, '_high_n_s32', '[0, 1, 2, 3, 4, 5, 6, 7]', 'N >= 1 && N <= 16'] + - [int32x2_t, int64x2_t, int32x4_t, '_high_n_s64', '[0, 1, 2, 3]', 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[5]}"]] + - FnCall: [simd_shuffle!, [a, {FnCall: ["vqrshrn_n{neon_type[1].noq}::", [b]]}, "{type[4]}"]] + + - name: "vqrshrn{type[0]}" + doc: "Unsigned saturating rounded shift right narrow" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [h_n_u16, u16, u8, 'N >= 1 && N <= 8', uint16x8_t, q_n_u16, _n_u16] + - [s_n_u32, u32, u16, 'N >= 1 && N <= 16', uint32x4_t, q_n_u32, _n_u32] + - [d_n_u64, u64, u32, 'N >= 1 && N <= 32', uint64x2_t, q_n_u64, _n_u64] + compose: + - FnCall: [static_assert!, ['{type[3]}']] + - Let: [a, "{neon_type[4]}", {FnCall: ["vdup{type[5]}", [a]]}] + - FnCall: [simd_extract!, [{FnCall: ["vqrshrn{type[6]}::", [a]]}, '0']] + + - name: "vqrshrn_high_n{neon_type[1].noq}" + doc: "Unsigned saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ['{type[3]}']] + - FnCall: + - simd_shuffle! + - - a + - FnCall: + - "vqrshrn_n{neon_type[1].noq}::" + - - b + - "{type[4]}" + + - name: "vqrshrun{type[0]}" + doc: "Signed saturating rounded shift right unsigned narrow" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [h_n_s16, "i16", "u8", 'N >= 1 && N <= 8', int16x8_t, s16] + - [s_n_s32, "i32", "u16", 'N >= 1 && N <= 16', int32x4_t, s32] + - [d_n_s64, "i64", "u32", 'N >= 1 && N <= 32', int64x2_t, s64] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - Let: + - a + - "{neon_type[4]}" + - FnCall: ["vdupq_n_{type[5]}", [a]] + - FnCall: + - simd_extract! + - - FnCall: + - "vqrshrun_n_{type[5]}::" + - - a + - '0' + + - name: "vqrshrun_high_n{neon_type[1].noq}" + doc: "Signed saturating rounded shift right unsigned narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', s16, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', s32, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', s64, '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: + - "vqrshrun_n_{type[4]}::" + - - b + - "{type[5]}" + + - name: "vqshld_{type}" + doc: "Signed saturating shift left" + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - i64 + compose: + - LLVMLink: + name: "vqshld{type}" + links: + - link: "llvm.aarch64.neon.sqshl.{type}" + arch: aarch64,arm64ec + + - name: "vqshl{type[0]}" + doc: "Signed saturating shift left" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [b_s8, "i8", int8x8_t] + - [h_s16, "i16", int16x4_t] + - [s_s32, "i32", int32x2_t] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: + - "vqshl{neon_type[2].noq}" + - - FnCall: ["vdup_n{neon_type[2].no}", [a]] + - FnCall: ["vdup_n{neon_type[2].no}", [b]] + - FnCall: [simd_extract!, [c, '0']] + + - name: "vqshl{type[0]}" + doc: "Signed saturating shift left" + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [b_n_s8, "i8", "3", s8] + - [h_n_s16, "i16", "4", s16] + - [s_n_s32, "i32", "5", s32] + - [d_n_s64, "i64", "6", s64] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] + - FnCall: + - simd_extract! + - - FnCall: + - "vqshl_n_{type[3]}::" + - - FnCall: ["vdup_n_{type[3]}", [a]] + - '0' + + - name: "vqshld_{type[0]}" + doc: "Unsigned saturating shift left" + arguments: ["a: {type[0]}", "b: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u64", "i64"] + compose: + - LLVMLink: + name: "vqshld{type[0]}" + links: + - link: "llvm.aarch64.neon.uqshl.{type[1]}" + arch: aarch64,arm64ec + + - name: "vqshl{type[0]}" + doc: "Unsigned saturating shift left" + arguments: ["a: {type[1]}", "b: {type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [b_u8, "u8", "i8", uint8x8_t, int8x8_t] + - [h_u16, "u16", "i16", uint16x4_t, int16x4_t] + - [s_u32, "u32", "i32", uint32x2_t, int32x2_t] + compose: + - Let: + - c + - "{neon_type[3]}" + - FnCall: + - "vqshl{neon_type[3].noq}" + - - FnCall: ["vdup{neon_type[3].N}", [a]] + - FnCall: ["vdup{neon_type[4].N}", [b]] + - FnCall: [simd_extract!, [c, '0']] + + - name: "vqshl{type[0]}" + doc: "Unsigned saturating shift left" + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [b_n_u8, "u8", '3'] + - [h_n_u16, "u16", '4'] + - [s_n_u32, "u32", '5'] + - [d_n_u64, "u64", '6'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] + - FnCall: + - simd_extract! + - - FnCall: ["vqshl_n_{type[1]}::", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] + - '0' + + - name: "vqshrnd_n_s64" + doc: "Signed saturating shift right narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i64", "i32"] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vqshrnd{type[1]}" + arguments: + - "a: {type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.sqshrn.{type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqshrnd_n_s64", [a, N]] + + - name: "vqshrn{type[0]}" + doc: "Signed saturating shift right narrow" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [h_n_s16, "i16", "i8", 'N >= 1 && N <= 8', s16] + - [s_n_s32, "i32", "i16", 'N >= 1 && N <= 16', s32] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_extract! + - - FnCall: + - "vqshrn_n_{type[4]}::" + - - FnCall: ["vdupq_n_{type[4]}", [a]] + - '0' + + - name: "vqshrn{type[0]}" + doc: "Signed saturating shift right narrow" + arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] + return_type: "{neon_type[3]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_high_n_s16, int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]', s16] + - [_high_n_s32, int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]', s32] + - [_high_n_s64, int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]', s64] + compose: + - FnCall: [static_assert!, ["{type[4]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: ["vqshrn_n_{type[6]}::", [b]] + - "{type[5]}" + + - name: "vqshrnd_n_u64" + doc: "Unsigned saturating shift right narrow" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["u64", "u32"] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vqshrnd_n_u64" + arguments: + - "a: u64" + - "n: i32" + links: + - link: "llvm.aarch64.neon.uqshrn.i32" + arch: aarch64,arm64ec + - FnCall: ["_vqshrnd_n_u64", ["a.as_signed()", N]] + + - name: "vqshrn{type[0]}" + doc: "Unsigned saturating shift right narrow" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ['h_n_u16', "u16", "u8", 'N >= 1 && N <= 8'] + - ['s_n_u32', "u32", "u16", 'N >= 1 && N <= 16'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - "simd_extract!" + - - FnCall: + - "vqshrn_n_{type[1]}::" + - - FnCall: ["vdupq_n_{type[1]}", [a]] + - '0' + + - name: "vqshrn{type[0]}" + doc: "Unsigned saturating shift right narrow" + arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] + return_type: "{neon_type[3]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_high_n_u16, uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [_high_n_u32, uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [_high_n_u64, uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[4]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: ["vqshrn_n_{neon_type[2]}::", [b]] + - "{type[5]}" + + - name: "vqshrun{type[0]}" + doc: "Signed saturating shift right unsigned narrow" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [h_n_s16, "i16", "u8", 'N >= 1 && N <= 8', s16] + - [s_n_s32, "i32", "u16", 'N >= 1 && N <= 16', s32] + - [d_n_s64, "i64", "u32", 'N >= 1 && N <= 32', s64] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_extract! + - - FnCall: + - "vqshrun_n_{type[4]}::" + - - FnCall: ["vdupq_n_{type[4]}", [a]] + - '0' + + - name: "vqshrun_high_n_{neon_type[1]}" + doc: "Signed saturating shift right unsigned narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, int32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, int64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: ["vqshrun_n_{neon_type[1]}::", [b]] + - "{type[4]}" + + - name: "vsqadd{type[0]}" + doc: "Unsigned saturating accumulate of signed value" + arguments: ["a: {type[1]}", "b: {type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [b_u8, "u8", "i8", s8] + - [h_u16, "u16", "i16", s16] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vsqadd_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[2]}", [b]] + - '0' + + - name: "vsqadd{type[0]}" + doc: "Unsigned saturating accumulate of signed value" + arguments: ["a: {type[1]}", "b: {type[2]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [usqadd]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [s_u32, "u32", "i32"] + - [d_u64, "u64", "i64"] + compose: + - LLVMLink: + name: "vsqadd{type[0]}" + links: + - link: "llvm.aarch64.neon.usqadd.{type[2]}" + arch: aarch64,arm64ec + + - name: "vsqrt{neon_type.no}" + doc: "Calculates the square root of each lane." + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fsqrt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_fsqrt, [a]] + + - name: "vrsqrts{type[0]}" + doc: "Floating-point reciprocal square root step" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [_f64, float64x1_t, v1f64] + - [q_f64, float64x2_t, v2f64] + compose: + - LLVMLink: + name: "vrsqrts{type[0]}" + links: + - link: "llvm.aarch64.neon.frsqrts.{type[2]}" + arch: aarch64,arm64ec + + - name: "vrsqrts{type[0]}" + doc: "Floating-point reciprocal square root step" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrts]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [s_f32, "f32"] + - [d_f64, "f64"] + compose: + - LLVMLink: + name: "vrsqrts{type[0]}" + links: + - link: "llvm.aarch64.neon.frsqrts.{type[1]}" + arch: aarch64,arm64ec + + - name: "vrecpe{type[0]}" + doc: "Reciprocal estimate." + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [_f64, float64x1_t, v1f64] + - [q_f64, float64x2_t, v2f64] + compose: + - LLVMLink: + name: "vrecpe{type[0]}" + links: + - link: "llvm.aarch64.neon.frecpe.{type[2]}" + arch: aarch64,arm64ec + + - name: "vrecpe{type[0]}" + doc: "Reciprocal estimate." + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpe]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [s_f32, "f32"] + - [d_f64, "f64"] + compose: + - LLVMLink: + name: "vrecpe{type[0]}" + links: + - link: "llvm.aarch64.neon.frecpe.{type[1]}" + arch: aarch64,arm64ec + + - name: "vrecps{type[0]}" + doc: "Floating-point reciprocal step" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [_f64, float64x1_t, v1f64] + - [q_f64, float64x2_t, v2f64] + compose: + - LLVMLink: + name: "vrecps{type[0]}" + links: + - link: "llvm.aarch64.neon.frecps.{type[2]}" + arch: aarch64,arm64ec + + - name: "vrecps{type[0]}" + doc: "Floating-point reciprocal step" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecps]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [s_f32, "f32"] + - [d_f64, "f64"] + compose: + - LLVMLink: + name: "vrecps{type[0]}" + links: + - link: "llvm.aarch64.neon.frecps.{type[1]}" + arch: aarch64,arm64ec + + - name: "vrecpx{type[0]}" + doc: "Floating-point reciprocal exponent" + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frecpx]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [s_f32, "f32"] + - [d_f64, "f64"] + compose: + - LLVMLink: + name: "vrecpxs{type[0]}" + links: + - link: "llvm.aarch64.neon.frecpx.{type[1]}" + arch: aarch64,arm64ec + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: [*neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [poly64x1_t, int64x1_t] + - [poly64x1_t, uint64x1_t] + - [int64x1_t, poly64x1_t] + - [uint64x1_t, poly64x1_t] + - [poly64x2_t, int64x2_t] + - [poly64x2_t, uint64x2_t] + - [int64x2_t, poly64x2_t] + - [uint64x2_t, poly64x2_t] + - [float64x1_t, int8x8_t] + - [float64x1_t, int16x4_t] + - [float64x1_t, int32x2_t] + - [float64x1_t, int64x1_t] + - [float64x2_t, int8x16_t] + - [float64x2_t, int16x8_t] + - [float64x2_t, int32x4_t] + - [float64x2_t, int64x2_t] + - [float64x1_t, uint8x8_t] + - [float64x1_t, uint16x4_t] + - [float64x1_t, uint32x2_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint8x16_t] + - [float64x2_t, uint16x8_t] + - [float64x2_t, uint32x4_t] + - [float64x2_t, uint64x2_t] + - [float64x1_t, poly8x8_t] + - [float64x1_t, poly16x4_t] + - [float32x2_t, poly64x1_t] + - [float64x1_t, poly64x1_t] + - [float64x2_t, poly8x16_t] + - [float64x2_t, poly16x8_t] + - [float32x4_t, poly64x2_t] + - [float64x2_t, poly64x2_t] + - [float64x2_t, p128] + - [int8x8_t, float64x1_t] + - [int16x4_t, float64x1_t] + - [int32x2_t, float64x1_t] + - [int64x1_t, float64x1_t] + - [int8x16_t, float64x2_t] + - [int16x8_t, float64x2_t] + - [int32x4_t, float64x2_t] + - [int64x2_t, float64x2_t] + - [poly8x8_t, float64x1_t] + - [uint16x4_t, float64x1_t] + - [uint32x2_t, float64x1_t] + - [uint64x1_t, float64x1_t] + - [poly8x16_t, float64x2_t] + - [uint16x8_t, float64x2_t] + - [uint32x4_t, float64x2_t] + - [uint64x2_t, float64x2_t] + - [uint8x8_t, float64x1_t] + - [poly16x4_t, float64x1_t] + - [poly64x1_t, float64x1_t] + - [poly64x1_t, float32x2_t] + - [uint8x16_t, float64x2_t] + - [poly16x8_t, float64x2_t] + - [poly64x2_t, float64x2_t] + - [poly64x2_t, float32x4_t] + - [p128, float64x2_t] + - [float32x2_t, float64x1_t] + - [float64x1_t, float32x2_t] + - [float32x4_t, float64x2_t] + - [float64x2_t, float32x4_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vrshld_s64" + doc: "Signed rounding shift left" + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - "i64" + compose: + - LLVMLink: + name: "vrshld_{type}" + links: + - link: "llvm.aarch64.neon.srshl.{type}" + arch: aarch64,arm64ec + + - name: "vrshld_{type[0]}" + doc: "Unsigned rounding shift left" + arguments: ["a: {type[0]}", "b: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u64", "i64"] + compose: + - LLVMLink: + name: "vrshld_{type[0]}" + links: + - link: "llvm.aarch64.neon.urshl.{type[1]}" + arch: aarch64,arm64ec + + - name: "vrshrd_n_s64" + doc: "Signed rounding shift right" + arguments: ["a: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - ["i64", 'N >= 1 && N <= 64', '-N as i64'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - FnCall: [vrshld_s64, [a, "{type[2]}"]] + + - name: "vrshrd_n_u64" + doc: "Unsigned rounding shift right" + arguments: ["a: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - "u64" + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - FnCall: ["vrshld_u64", [a, '-N as i64']] + + - name: "vrshrn_high_n_{neon_type[1]}" + doc: "Rounding shift right narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: ["vrshrn_n_{neon_type[1]}::", [b]] + - "{type[4]}" + + - name: "vrsubhn_high_{neon_type[1]}" + doc: "Rounding subtract returning high narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[3]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rsubhn2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + compose: + - Let: + - x + - "{neon_type[0]}" + - FnCall: ["vrsubhn_{neon_type[1]}", [b, c]] + - FnCall: [simd_shuffle!, [a, x, "{type[4]}"]] + + - name: "vcopy{neon_type[0].lane_nox}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, int8x8_t, int8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int16x4_t, int16x4_t, int16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int32x2_t, int32x2_t, int32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint8x8_t, uint8x8_t, uint8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint16x4_t, uint16x4_t, uint16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint32x2_t, uint32x2_t, uint32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly8x8_t, poly8x8_t, poly8x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly16x4_t, poly16x4_t, poly16x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float32x2_t, float32x2_t, float32x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int8x16_t, int8x8_t, int8x16_t, '4', '3', ' let b: int8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int16x8_t, int16x4_t, int16x8_t, '3', '2', ' let b: int16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int32x4_t, int32x2_t, int32x4_t, '2', '1', ' let b: int32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint8x16_t, uint8x8_t, uint8x16_t, '4', '3', ' let b: uint8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint16x8_t, uint16x4_t, uint16x8_t, '3', '2', ' let b: uint16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint32x4_t, uint32x2_t, uint32x4_t, '2', '1', ' let b: uint32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly8x16_t, poly8x8_t, poly8x16_t, '4', '3', ' let b: poly8x16_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly16x8_t, poly16x4_t, poly16x8_t, '3', '2', ' let b: poly16x8_t = simd_shuffle!(b, b, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] + - Identifier: ["{type[5]}", Symbol] + + - name: "vcopy{neon_type[0].laneq_nox}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 0', 'LANE2 = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: + unsafe: [neon] + types: + - [int8x16_t, int8x16_t, int8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int16x8_t, int16x8_t, int16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int32x4_t, int32x4_t, int32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int64x2_t, int64x2_t, int64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint8x16_t, uint8x16_t, uint8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint16x8_t, uint16x8_t, uint16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint32x4_t, uint32x4_t, uint32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint64x2_t, uint64x2_t, uint64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly8x16_t, poly8x16_t, poly8x16_t, '4', '4', ' match LANE1 & 0b1111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32, 8, 9, 10, 11, 12, 13, 14, 15]), 8 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 16 + LANE2 as u32, 9, 10, 11, 12, 13, 14, 15]), 9 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 16 + LANE2 as u32, 10, 11, 12, 13, 14, 15]), 10 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 16 + LANE2 as u32, 11, 12, 13, 14, 15]), 11 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 16 + LANE2 as u32, 12, 13, 14, 15]), 12 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 16 + LANE2 as u32, 13, 14, 15]), 13 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 16 + LANE2 as u32, 14, 15]), 14 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 16 + LANE2 as u32, 15]), 15 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly16x8_t, poly16x8_t, poly16x8_t, '3', '3', ' match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 8 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 8 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 8 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly64x2_t, poly64x2_t, poly64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float32x4_t, float32x4_t, float32x4_t, '2', '2', ' match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float64x2_t, float64x2_t, float64x2_t, '1', '1', ' match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int8x8_t, int8x16_t, int8x8_t, '3', '4', ' let a: int8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int16x4_t, int16x8_t, int16x4_t, '2', '3', ' let a: int16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [int32x2_t, int32x4_t, int32x2_t, '1', '2', ' let a: int32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint8x8_t, uint8x16_t, uint8x8_t, '3', '4', ' let a: uint8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint16x4_t, uint16x8_t, uint16x4_t, '2', '3', ' let a: uint16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint32x2_t, uint32x4_t, uint32x2_t, '1', '2', 'let a: uint32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly8x8_t, poly8x16_t, poly8x8_t, '3', '4', ' let a: poly8x16_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]); match LANE1 & 0b111 { 0 => simd_shuffle!(a, b, [16 + LANE2 as u32, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [0, 16 + LANE2 as u32, 2, 3, 4, 5, 6, 7]), 2 => simd_shuffle!(a, b, [0, 1, 16 + LANE2 as u32, 3, 4, 5, 6, 7]), 3 => simd_shuffle!(a, b, [0, 1, 2, 16 + LANE2 as u32, 4, 5, 6, 7]), 4 => simd_shuffle!(a, b, [0, 1, 2, 3, 16 + LANE2 as u32, 5, 6, 7]), 5 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 16 + LANE2 as u32, 6, 7]), 6 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 16 + LANE2 as u32, 7]), 7 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 16 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly16x4_t, poly16x8_t, poly16x4_t, '2', '3', ' let a: poly16x8_t = simd_shuffle!(a, a, [0, 1, 2, 3, 4, 5, 6, 7]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [8 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 8 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 8 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 8 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float32x2_t, float32x4_t, float32x2_t, '1', '2', ' let a: float32x4_t = simd_shuffle!(a, a, [0, 1, 2, 3]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '{type[3]}']] + - FnCall: [static_assert_uimm_bits!, [LANE2, '{type[4]}']] + - Identifier: ["{type[5]}", Symbol] + + - name: "vcopyq_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int64x1_t, 'let b: int64x2_t = simd_shuffle!(b, b, [0, 1]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [uint64x2_t, uint64x1_t, 'let b: uint64x2_t = simd_shuffle!(b, b, [0, 1]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [poly64x2_t, poly64x1_t, 'let b: poly64x2_t = simd_shuffle!(b, b, [0, 1]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + - [float64x2_t, float64x1_t, ' let b: float64x2_t = simd_shuffle!(b, b, [0, 1]); match LANE1 & 0b1 { 0 => simd_shuffle!(a, b, [2 + LANE2 as u32, 1]), 1 => simd_shuffle!(a, b, [0, 2 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, '1']] + - FnCall: [static_assert!, ['LANE2 == 0']] + - Identifier: ['{type[2]}', Symbol] + + - name: "vcopyq_lane_f32" + doc: "Insert vector element from another vector element" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [mov, 'LANE1 = 1', 'LANE2 = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1', '3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE1: i32, const LANE2: i32'] + safety: + unsafe: [neon] + types: + - [float32x4_t, float32x2_t, ' let b: float32x4_t = simd_shuffle!(b, b, [0, 1, 2, 3]); match LANE1 & 0b11 { 0 => simd_shuffle!(a, b, [4 + LANE2 as u32, 1, 2, 3]), 1 => simd_shuffle!(a, b, [0, 4 + LANE2 as u32, 2, 3]), 2 => simd_shuffle!(a, b, [0, 1, 4 + LANE2 as u32, 3]), 3 => simd_shuffle!(a, b, [0, 1, 2, 4 + LANE2 as u32]), _ => unreachable_unchecked(), }'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE1, 2]] + - FnCall: [static_assert_uimm_bits!, [LANE2, 1]] + - Identifier: ["{type[2]}", Symbol] + + - name: "vcreate_f64" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u64", float64x1_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vset_lane_f64" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f64", float64x1_t, float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vsetq_lane_f64" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f64", float64x2_t, float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vshld_s64" + doc: "Signed Shift left" + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - "i64" + compose: + - FnCall: + - transmute + - - FnCall: + - vshl_s64 + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vshld_{type[0]}" + doc: "Unsigned Shift left" + arguments: ["a: {type[0]}", "b: {type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["u64", "i64"] + compose: + - FnCall: + - transmute + - - FnCall: + - vshl_u64 + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vshll_high_n_{neon_type[0]}" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sshll2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x16_t, int16x8_t, int8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x8_t, int32x4_t, int16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] + - [int32x4_t, int64x2_t, int32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + + - name: "vshll_high_n_{neon_type[0]}" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ushll2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x16_t, uint16x8_t, uint8x8_t, 'N >= 0 && N <= 8', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x8_t, uint32x4_t, uint16x4_t, 'N >= 0 && N <= 16', '[4, 5, 6, 7]'] + - [uint32x4_t, uint64x2_t, uint32x2_t, 'N >= 0 && N <= 32', '[2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - Let: [b, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[4]}"]]}] + - FnCall: ["vshll_n_{neon_type[2]}::", [b]] + + - name: "vshrn_high_n_{neon_type[1]}" + doc: "Shift right narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [shrn2, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, 'N >= 1 && N <= 8', '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, 'N >= 1 && N <= 16', '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, 'N >= 1 && N <= 32', '[0, 1, 2, 3]'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_shuffle! + - - a + - FnCall: ["vshrn_n_{neon_type[1]}::", [b]] + - "{type[4]}" + + - name: "vsm3partw1{neon_type.no}" + doc: "SM3PARTW1" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sm4"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw1]]}]] + - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] + safety: + unsafe: [neon] + types: + - uint32x4_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sm3partw1 + links: + - link: "llvm.aarch64.crypto.sm3partw1" + arch: aarch64,arm64ec + + - name: "vsm3partw2{neon_type.no}" + doc: "SM3PARTW2" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sm4"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3partw2]]}]] + - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] + safety: + unsafe: [neon] + types: + - uint32x4_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sm3partw2 + links: + - link: "llvm.aarch64.crypto.sm3partw2" + arch: aarch64,arm64ec + + - name: "vsm3ss1{neon_type.no}" + doc: "SM3SS1" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sm4"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm3ss1]]}]] + - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] + safety: + unsafe: [neon] + types: + - uint32x4_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sm3ss1 + links: + - link: "llvm.aarch64.crypto.sm3ss1" + arch: aarch64,arm64ec + + - name: "vsm4ekey{neon_type.no}" + doc: "SM4 key" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sm4"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4ekey]]}]] + - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] + safety: + unsafe: [neon] + types: + - uint32x4_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sm4ekey + links: + - link: "llvm.aarch64.crypto.sm4ekey" + arch: aarch64,arm64ec + + - name: "vsm4e{neon_type.no}" + doc: "SM4 encode" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sm4"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sm4e]]}]] + - FnCall: [unstable, ['feature = "stdarch_neon_sm4"', 'issue = "117226"']] + safety: + unsafe: [neon] + types: + - uint32x4_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sm4e + links: + - link: "llvm.aarch64.crypto.sm4e" + arch: aarch64,arm64ec + + - name: "vrax1{neon_type.no}" + doc: "Rotate and exclusive OR" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rax1]]}]] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + safety: + unsafe: [neon] + types: + - uint64x2_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.rax1 + links: + - link: "llvm.aarch64.crypto.rax1" + arch: aarch64,arm64ec + + - name: "vsha512h{neon_type.no}" + doc: "SHA512 hash update part 1" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h]]}]] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + safety: + unsafe: [neon] + types: + - uint64x2_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sha512h + links: + - link: "llvm.aarch64.crypto.sha512h" + arch: aarch64,arm64ec + + - name: "vsha512h2{neon_type.no}" + doc: "SHA512 hash update part 2" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512h2]]}]] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + safety: + unsafe: [neon] + types: + - uint64x2_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sha512h2 + links: + - link: "llvm.aarch64.crypto.sha512h2" + arch: aarch64,arm64ec + + - name: "vsha512su0{neon_type.no}" + doc: "SHA512 schedule update 0" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su0]]}]] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + safety: + unsafe: [neon] + types: + - uint64x2_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sha512su0 + links: + - link: "llvm.aarch64.crypto.sha512su0" + arch: aarch64,arm64ec + + - name: "vsha512su1{neon_type.no}" + doc: "SHA512 schedule update 1" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,sha3"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sha512su1]]}]] + - FnCall: [stable, ['feature = "stdarch_neon_sha3"', 'since = "1.79.0"']] + safety: + unsafe: [neon] + types: + - uint64x2_t + compose: + - LLVMLink: + name: llvm.aarch64.crypto.sha512su1 + links: + - link: "llvm.aarch64.crypto.sha512su1" + arch: aarch64,arm64ec + + - name: "vrnd32x{neon_type.no}" + doc: "Floating-point round to 32-bit integer, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32x]]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "vrnd32x{neon_type.no}" + links: + - link: "llvm.aarch64.neon.frint32x.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnd32x{neon_type.no}" + doc: "Floating-point round to 32-bit integer, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32x]]}]] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - LLVMLink: + name: "vrnd32x{neon_type.no}" + arguments: + - "a: f64" + return_type: "f64" + links: + - link: "llvm.aarch64.frint32x.f64" + arch: aarch64,arm64ec + - FnCall: + - transmute + - - FnCall: + - _vrnd32x_f64 + - - FnCall: [simd_extract!, [a, 0]] + + - name: "vrnd32z{neon_type.no}" + doc: "Floating-point round to 32-bit integer toward zero" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32z]]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "vrnd32z{neon_type.no}" + links: + - link: "llvm.aarch64.neon.frint32z.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnd32z{neon_type.no}" + doc: "Floating-point round to 32-bit integer toward zero" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint32z]]}]] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - LLVMLink: + name: "vrnd32z{neon_type.no}" + arguments: + - "a: f64" + return_type: "f64" + links: + - link: "llvm.aarch64.frint32z.f64" + arch: aarch64,arm64ec + - FnCall: + - transmute + - - FnCall: [_vrnd32z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + + - name: "vrnd64x{neon_type.no}" + doc: "Floating-point round to 64-bit integer, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64x]]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "vrnd64x{neon_type.no}" + links: + - link: "llvm.aarch64.neon.frint64x.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnd64x{neon_type.no}" + doc: "Floating-point round to 64-bit integer, using current rounding mode" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64x]]}]] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - LLVMLink: + name: "vrnd64x{neon_type.no}" + arguments: + - "a: f64" + return_type: "f64" + links: + - link: "llvm.aarch64.frint64x.f64" + arch: aarch64,arm64ec + - FnCall: + - transmute + - - FnCall: [_vrnd64x_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + + - name: "vrnd64z{neon_type.no}" + doc: "Floating-point round to 64-bit integer toward zero" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64z]]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + - float64x2_t + compose: + - LLVMLink: + name: "vrnd64z{neon_type.no}" + links: + - link: "llvm.aarch64.neon.frint64z.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrnd64z{neon_type.no}" + doc: "Floating-point round to 64-bit integer toward zero" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [target_feature, ['enable = "neon,frintts"']] + - FnCall: [unstable, ['feature = "stdarch_neon_ftts"', 'issue = "117227"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [frint64z]]}]] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - LLVMLink: + name: "vrnd64z{neon_type.no}" + arguments: + - "a: f64" + return_type: "f64" + links: + - link: "llvm.aarch64.frint64z.f64" + arch: aarch64,arm64ec + - FnCall: + - transmute + - - FnCall: [_vrnd64z_f64, [{FnCall: [simd_extract!, [a, 0]]}]] + + - name: "vtrn1{neon_type[0].no}" + doc: Transpose vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn1]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [int8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] + - [int16x4_t, '[0, 4, 2, 6]'] + - [int16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [int32x4_t, '[0, 4, 2, 6]'] + - [uint8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [uint8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] + - [uint16x4_t, '[0, 4, 2, 6]'] + - [uint16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [uint32x4_t, '[0, 4, 2, 6]'] + - [poly8x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [poly8x16_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]'] + - [poly16x4_t, '[0, 4, 2, 6]'] + - [poly16x8_t, '[0, 8, 2, 10, 4, 12, 6, 14]'] + - [float32x4_t, '[0, 4, 2, 6]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vtrn1{neon_type[0].no}" + doc: Transpose vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, '[0, 2]'] + - [int64x2_t, '[0, 2]'] + - [uint32x2_t, '[0, 2]'] + - [uint64x2_t, '[0, 2]'] + - [poly64x2_t, '[0, 2]'] + - [float32x2_t, '[0, 2]'] + - [float64x2_t, '[0, 2]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vtrn2{neon_type[0].no}" + doc: Transpose vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [trn2]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [int8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [int16x4_t, '[1, 5, 3, 7]'] + - [int16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [int32x4_t, '[1, 5, 3, 7]'] + - [uint8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [uint8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [uint16x4_t, '[1, 5, 3, 7]'] + - [uint16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [uint32x4_t, '[1, 5, 3, 7]'] + - [poly8x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [poly8x16_t, '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [poly16x4_t, '[1, 5, 3, 7]'] + - [poly16x8_t, '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [float32x4_t, '[1, 5, 3, 7]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vtrn2{neon_type[0].no}" + doc: Transpose vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, '[1, 3]'] + - [int64x2_t, '[1, 3]'] + - [uint32x2_t, '[1, 3]'] + - [uint64x2_t, '[1, 3]'] + - [poly64x2_t, '[1, 3]'] + - [float32x2_t, '[1, 3]'] + - [float64x2_t, '[1, 3]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vzip2{neon_type[0].no}" + doc: Zip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [int8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [int16x4_t, '[2, 6, 3, 7]'] + - [int16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [int32x2_t, '[1, 3]'] + - [int32x4_t, '[2, 6, 3, 7]'] + - [int64x2_t, '[1, 3]'] + - [uint8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [uint8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [uint16x4_t, '[2, 6, 3, 7]'] + - [uint16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [uint32x2_t, '[1, 3]'] + - [uint32x4_t, '[2, 6, 3, 7]'] + - [uint64x2_t, '[1, 3]'] + - [poly8x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [poly8x16_t, '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [poly16x4_t, '[2, 6, 3, 7]'] + - [poly16x8_t, '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [poly64x2_t, '[1, 3]'] + - [float32x2_t, '[1, 3]'] + - [float32x4_t, '[2, 6, 3, 7]'] + - [float64x2_t, '[1, 3]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vzip1{neon_type[0].no}" + doc: Zip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [int8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] + - [int16x4_t, '[0, 4, 1, 5]'] + - [int16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [int32x2_t, '[0, 2]'] + - [int32x4_t, '[0, 4, 1, 5]'] + - [int64x2_t, '[0, 2]'] + - [uint8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [uint8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] + - [uint16x4_t, '[0, 4, 1, 5]'] + - [uint16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [uint32x2_t, '[0, 2]'] + - [uint32x4_t, '[0, 4, 1, 5]'] + - [uint64x2_t, '[0, 2]'] + - [poly8x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [poly8x16_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]'] + - [poly16x4_t, '[0, 4, 1, 5]'] + - [poly16x8_t, '[0, 8, 1, 9, 2, 10, 3, 11]'] + - [poly64x2_t, '[0, 2]'] + - [float32x2_t, '[0, 2]'] + - [float32x4_t, '[0, 4, 1, 5]'] + - [float64x2_t, '[0, 2]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vuzp1{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip1]]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, '[0, 2]'] + - [int64x2_t, '[0, 2]'] + - [uint32x2_t, '[0, 2]'] + - [uint64x2_t, '[0, 2]'] + - [poly64x2_t, '[0, 2]'] + - [float32x2_t, '[0, 2]'] + - [float64x2_t, '[0, 2]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vuzp1{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp1]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [int8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] + - [int16x4_t, '[0, 2, 4, 6]'] + - [int16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [int32x4_t, '[0, 2, 4, 6]'] + - [uint8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [uint8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] + - [uint16x4_t, '[0, 2, 4, 6]'] + - [uint16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [uint32x4_t, '[0, 2, 4, 6] '] + - [poly8x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [poly8x16_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]'] + - [poly16x4_t, '[0, 2, 4, 6]'] + - [poly16x8_t, '[0, 2, 4, 6, 8, 10, 12, 14]'] + - [float32x4_t, '[0, 2, 4, 6]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vuzp2{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [zip2]]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, '[1, 3]'] + - [int64x2_t, '[1, 3]'] + - [uint32x2_t, '[1, 3]'] + - [uint64x2_t, '[1, 3]'] + - [poly64x2_t, '[1, 3]'] + - [float32x2_t, '[1, 3]'] + - [float64x2_t, '[1, 3]'] + compose: + - FnCall: ["simd_shuffle!", [a, b, "{type[1]}"]] + + - name: "vuzp2{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uzp2]]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [int8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [int16x4_t, '[1, 3, 5, 7]'] + - [int16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [int32x4_t, '[1, 3, 5, 7]'] + - [uint8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [uint8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [uint16x4_t, '[1, 3, 5, 7]'] + - [uint16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [uint32x4_t, '[1, 3, 5, 7]'] + - [poly8x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [poly8x16_t, '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [poly16x4_t, '[1, 3, 5, 7]'] + - [poly16x8_t, '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [float32x4_t, '[1, 3, 5, 7]'] + compose: + - FnCall: + - "simd_shuffle!" + - - a + - b + - "{type[1]}" + + - name: "vabal_high_{neon_type[1]}" + doc: "Unsigned Absolute difference and Accumulate Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [uabal]]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x16_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]', '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint32x4_t, uint16x8_t, uint16x4_t, '[4, 5, 6, 7]', '[4, 5, 6, 7]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '[2, 3]', '[2, 3]'] + compose: + - Let: + - d + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [b, b, "{type[3]}"]] + - Let: + - e + - "{neon_type[2]}" + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + - Let: [f, "{neon_type[2]}", {FnCall: ["vabd_{neon_type[2]}", [d, e]]}] + - FnCall: + - simd_add + - - a + - FnCall: [simd_cast, [f]] + + - name: "vabal_high{neon_type[1].noq}" + doc: Signed Absolute difference and Accumulate Long + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sabal]]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x16_t, int8x16_t, '[8, 9, 10, 11, 12, 13, 14, 15]', int8x8_t, uint8x8_t] + - [int32x4_t, int16x8_t, int16x8_t, '[4, 5, 6, 7]', int16x4_t, uint16x4_t] + - [int64x2_t, int32x4_t, int32x4_t, '[2, 3]', int32x2_t, uint32x2_t] + compose: + - Let: + - d + - "{neon_type[4]}" + - FnCall: + - simd_shuffle! + - - b + - b + - "{type[3]}" + - Let: + - e + - "{neon_type[4]}" + - FnCall: + - simd_shuffle! + - - c + - c + - "{type[3]}" + - Let: + - f + - "{neon_type[4]}" + - FnCall: + - "vabd{neon_type[4].no}" + - - d + - e + - Let: + - f + - "{neon_type[5]}" + - FnCall: + - simd_cast + - - f + - FnCall: + - simd_add + - - a + - FnCall: + - simd_cast + - - f + + - name: "vqabs{neon_type.no}" + doc: Signed saturating Absolute value + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-stable + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] + safety: + unsafe: [neon] + types: + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "sqabs.{neon_type}" + links: + - link: "llvm.aarch64.neon.sqabs.{neon_type}" + arch: aarch64,arm64ec + + - name: "vslid_n_{type}" + doc: Shift left and insert + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + static_defs: + - "const N: i32" + attr: + - *neon-stable + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sli, 'N = 2']]}]] + safety: + unsafe: [neon] + types: + - i64 + - u64 + compose: + - FnCall: + - "static_assert!" + - - 'N >= 0 && N <= 63' + - FnCall: + - transmute + - - FnCall: + - "vsli_n_{type}::" + - - FnCall: + - transmute + - - a + - FnCall: + - transmute + - - b + + - name: "vsrid_n_{type}" + doc: Shift right and insert + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + static_defs: + - "const N: i32" + attr: + - *neon-stable + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sri, 'N = 2']]}]] + safety: + unsafe: [neon] + types: + - i64 + - u64 + compose: + - FnCall: + - "static_assert!" + - - 'N >= 1 && N <= 64' + - FnCall: + - transmute + - - FnCall: + - "vsri_n_{type}::" + - - FnCall: + - transmute + - - a + - FnCall: + - transmute + - - b + + - name: "vpmaxnm{neon_type.no}" + doc: "Floating-point Maximum Number Pairwise (vector)." + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float32x2_t + - float64x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vpmaxnm{neon_type}" + links: + - link: "llvm.aarch64.neon.fmaxnmp.{neon_type}" + arch: aarch64,arm64ec + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['*mut f64', float64x1x2_t, float64x1_t] + - ['*mut f64', float64x2x2_t, float64x2_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x{neon_type[1].tuple}.{neon_type[2]}.p0f64" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', 'a']] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['*mut f64', float64x1x3_t, float64x1_t] + - ['*mut f64', float64x2x3_t, float64x2_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "c: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x{neon_type[1].tuple}.{neon_type[2]}.p0f64" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', 'b.2', 'a']] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['*mut f64', float64x1x4_t, float64x1_t] + - ['*mut f64', float64x2x4_t, float64x2_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "c: {neon_type[2]}" + - "d: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x{neon_type[1].tuple}.{neon_type[2]}.p0f64" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', 'b.2', 'b.3', 'a']] + + - name: "vfma{type[3]}" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '1', '_lane_f32'] + - [float32x2_t, float32x4_t, '2', '_laneq_f32'] + - [float32x4_t, float32x2_t, '1', 'q_lane_f32'] + - [float32x4_t, float32x4_t, '2', 'q_laneq_f32'] + - [float64x2_t, float64x2_t, '1', 'q_laneq_f64'] + compose: + - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] + - FnCall: + - "vfma{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vfma_lane_f64" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - FnCall: ["static_assert!", ["LANE == 0"]] + - FnCall: + - "vfma{neon_type.no}" + - - a + - b + - FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vfma_laneq_f64" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x1_t, float64x2_t] + compose: + - FnCall: ["static_assert_uimm_bits!", ["LANE", "1"]] + - FnCall: + - "vfma{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vfmaq_lane_f64" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmla, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x2_t, float64x1_t] + compose: + - FnCall: ["static_assert!", ["LANE == 0"]] + - FnCall: + - "vfma{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]] + + - name: "vfma{type[2]}" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f32", float32x2_t, "s_lane_f32", '1'] + - ["f32", float32x4_t, "s_laneq_f32", '2'] + - ["f64", float64x2_t, "d_laneq_f64", '1'] + compose: + - LLVMLink: + name: "_vfma{type[2]}" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {type[0]}"] + links: + - link: "llvm.fma.{type[0]}" + arch: aarch64,arm64ec + - FnCall: [static_assert_uimm_bits!, ['LANE', "{type[3]}"]] + - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - FnCall: ["_vfma{type[2]}", [b, c, a]] + + - name: "vfmad_lane_f64" + doc: "Floating-point fused multiply-add to accumulator" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmadd, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f64", float64x1_t] + compose: + - LLVMLink: + name: "_vfmad_lane_f64" + arguments: ["a: f64", "b: f64", "c: f64"] + links: + - link: "llvm.fma.{type[0]}" + arch: aarch64,arm64ec + - FnCall: [static_assert!, ['LANE == 0']] + - Let: [c, "{type[0]}", {FnCall: [simd_extract!, [c, 'LANE as u32']]}] + - FnCall: ["_vfmad_lane_f64", [b, c, a]] + + - name: "vfms_f64" + doc: "Floating-point fused multiply-subtract from accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - Let: [b, "{neon_type}", {FnCall: [simd_neg, [b]]}] + - FnCall: [vfma_f64, [a, b, c]] + + - name: "vfms{neon_type.no}" + doc: "Floating-point fused multiply-subtract from accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x2_t + compose: + - Let: [b, "{neon_type}", {FnCall: [simd_neg, [b]]}] + - FnCall: [vfmaq_f64, [a, b, c]] + + - name: "vmls{neon_type.no}" + doc: "Floating-point multiply-subtract from accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - FnCall: [simd_sub, [a, {FnCall: [simd_mul, [b, c]]}]] + + - name: "vfms{type[3]}" + doc: "Floating-point fused multiply-subtract to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '1', _lane_f32] + - [float32x2_t, float32x4_t, '2', _laneq_f32] + - [float32x4_t, float32x2_t, '1', q_lane_f32] + - [float32x4_t, float32x4_t, '2', q_laneq_f32] + - [float64x2_t, float64x2_t, '1', q_laneq_f64] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[2]}']] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + + - name: "vfms_lane_f64" + doc: "Floating-point fused multiply-subtract to accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: ["vfms{neon_type.no}", [a, b, {FnCall: ["vdup{neon_type.N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + + - name: "vfms_laneq_f64" + doc: "Floating-point fused multiply-subtract to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x1_t, float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + + - name: "vfmsq_lane_f64" + doc: "Floating-point fused multiply-subtract to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x2_t, float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: ["vfms{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [{FnCall: [simd_extract!, [c, 'LANE as u32']]}]]}]] + + - name: "vfms{type[2]}" + doc: "Floating-point fused multiply-subtract to accumulator" + arguments: ["a: {type[0]}", "b: {type[0]}", "c: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f32", float32x2_t, "s_lane_f32"] + - ["f32", float32x4_t, "s_laneq_f32"] + - ["f64", float64x1_t, "d_lane_f64"] + - ["f64", float64x2_t, "d_laneq_f64"] + compose: + - FnCall: ["vfma{type[2]}::", ['a', '-b', 'c']] + + - name: "vceqz{neon_type[0].no}" + doc: "Floating-point compare bitwise equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmeq]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, 'f32x2', 'f32x2::new(0.0, 0.0)'] + - [float32x4_t, uint32x4_t, 'f32x4', 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] + - [float64x1_t, uint64x1_t, 'f64', '0.0'] + - [float64x2_t, uint64x2_t, 'f64x2', 'f64x2::new(0.0, 0.0)'] + compose: + - Let: [b, '{type[2]}', '{type[3]}'] + - FnCall: [simd_eq, [a, {FnCall: [transmute, [b]]}]] + + - name: "vceqz{type[2]}" + doc: "Floating-point compare bitwise equal to zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", "s_f32"] + - ["f64", "u64", "d_f64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vceqz_{type[0]}" + - - FnCall: ["vdup_n_{type[0]}", [a]] + - '0' + + - name: "vceqzd_{type[2]}" + doc: "Compare bitwise equal to zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64", "s64"] + - ["u64", "u64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - "vceqz_{type[2]}" + - - FnCall: [transmute, [a]] + + - name: "vceqz{neon_type[0].no}" + doc: "Signed compare bitwise equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [int64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + - [poly8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [poly8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [poly64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [poly64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_eq + - - a + - FnCall: [transmute, [b]] + + - name: "vceqz{neon_type[0].no}" + doc: "Unsigned compare bitwise equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmeq]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint8x16_t, uint8x16_t, u8x16, 'u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint16x4_t, uint16x4_t, u16x4, 'u16x4::new(0, 0, 0, 0)'] + - [uint16x8_t, uint16x8_t, u16x8, 'u16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint32x2_t, uint32x2_t, u32x2, 'u32x2::new(0, 0)'] + - [uint32x4_t, uint32x4_t, u32x4, 'u32x4::new(0, 0, 0, 0)'] + - [uint64x1_t, uint64x1_t, u64x1, 'u64x1::new(0)'] + - [uint64x2_t, uint64x2_t, u64x2, 'u64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_eq + - - a + - FnCall: [transmute, [b]] + + - name: "vcge{neon_type.no}" + doc: "Compare unsigned greater than or equal" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - uint64x1_t + - uint64x2_t + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vcge{type[0]}" + doc: "Floating-point compare greater than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vcge_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - FnCall: ["vdup_n_{type[1]}", [b]] + - '0' + + - name: "vcge{neon_type[0].no}" + doc: "Floating-point compare greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vcge{type[0]}" + doc: "Compare greater than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["d_s64", "i64", "u64", s64] + - ["d_u64", "u64", "u64", u64] + compose: + - FnCall: + - transmute + - - FnCall: + - "vcge_{type[3]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vclt{neon_type.no}" + doc: "Compare unsigned less than" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhi]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - uint64x1_t + - uint64x2_t + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vcltd_{type[0]}" + doc: "Compare less than" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s64", "i64", "u64"] + - ["u64", "u64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - "vclt_{type[0]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vtst{neon_type[0].no}" + doc: "Unsigned compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint64x1_t, u64x1, 'u64x1::new(0)'] + - [uint64x2_t, u64x2, 'u64x2::new(0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[1]}", "{type[2]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] + + - name: "vcgez{neon_type[0].no}" + doc: "Floating-point compare greater than or equal to zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmge]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] + - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] + - [float64x1_t, uint64x1_t, f64, '0.0'] + - [float64x2_t, uint64x2_t, f64x2, 'f64x2::new(0.0, 0.0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_ge + - - a + - FnCall: [transmute, [b]] + + - name: "vcgez{type[0]}" + doc: "Floating-point compare greater than or equal to zero" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vcgez_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - '0' + + - name: "vclezd_s64" + doc: "Compare less than or equal to zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: [vclez_s64, [{FnCall: [transmute, [a]]}]] + + - name: "vcgtd_{type[2]}" + doc: "Compare greater than" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64", 's64'] + - ["u64", "u64", 'u64'] + compose: + - FnCall: + - transmute + - - FnCall: + - "vcgt_{type[2]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vcgtz{neon_type[0].no}" + doc: "Compare signed greater than zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [int64x1_t, uint64x1_t, i64x1, 'i64x1::new(0)'] + - [int64x2_t, uint64x2_t, i64x2, 'i64x2::new(0, 0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_gt + - - a + - FnCall: [transmute, [b]] + + - name: "vcgtzd_s64" + doc: "Compare signed greater than zero" + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["i64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - vcgtz_s64 + - - FnCall: [transmute, [a]] + + - name: "vcgtz{neon_type[0].no}" + doc: "Floating-point compare greater than zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, f32x2, 'f32x2::new(0.0, 0.0)'] + - [float32x4_t, uint32x4_t, f32x4, 'f32x4::new(0.0, 0.0, 0.0, 0.0)'] + - [float64x1_t, uint64x1_t, f64, '0.0'] + - [float64x2_t, uint64x2_t, f64x2, 'f64x2::new(0.0, 0.0)'] + compose: + - Let: [b, "{type[2]}", "{type[3]}"] + - FnCall: [simd_gt, [a, {FnCall: [transmute, [b]]}]] + + - name: "vcgtz{type[0]}" + doc: "Floating-point compare greater than zero" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32", "u32"] + - ["d_f64", "f64", "u64"] + compose: + - FnCall: + - "simd_extract!" + - - FnCall: + - "vcgtz_{type[1]}" + - - FnCall: ["vdup_n_{type[1]}", [a]] + - '0' + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcvt{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.fptoui.sat.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vmul{neon_type[0].N}" + doc: "Vector multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, "f64"] + - [float64x2_t, "f64"] + compose: + - FnCall: + - simd_mul + - - a + - FnCall: ["vdup{neon_type[0].N}", [b]] + + - name: "vmul_lane_f64" + doc: "Floating-point multiply" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - float64x1_t + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - simd_mul + - - a + - FnCall: + - "transmute::" + - - FnCall: [simd_extract!, [b, 'LANE as u32']] + + - name: "vmulq_lane_f64" + doc: "Floating-point multiply" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x2_t, float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: + - simd_mul + - - a + - FnCall: ["simd_shuffle!", [b, b, '[LANE as u32, LANE as u32]']] + + - name: "vmuld_lane_f64" + doc: "Floating-point multiply" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f64", float64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Identifier: ['a * b', Symbol] + + - name: "vmul_laneq_f64" + doc: "Floating-point multiply" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x1_t, float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: + - simd_mul + - - a + - FnCall: + - "transmute::" + - - FnCall: [simd_extract!, [b, 'LANE as u32']] + + - name: "vmulq_laneq_f64" + doc: "Floating-point multiply" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float64x2_t, float64x2_t, float64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: + - simd_mul + - - a + - FnCall: [simd_shuffle!, [b, b, '[LANE as u32, LANE as u32]']] + + - name: "vmul{type[2]}" + doc: "Floating-point multiply" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["f32", float32x2_t, "s_lane_f32", '1'] + - ["f32", float32x4_t, "s_laneq_f32", '2'] + - ["f64", float64x2_t, "d_laneq_f64", '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - Let: [b, '{type[0]}', {FnCall: [simd_extract!, [b, 'LANE as u32']]}] + - Identifier: ['a * b', Symbol] + + - name: "vrsrad_n_s64" + doc: "Signed rounding shift right and accumulate." + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - "i64" + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - Let: [b, "{type}", {FnCall: ["vrshrd_n_s64::", [b]]}] + - Identifier: ['a.wrapping_add(b)', Symbol] + + - name: "vmlsl_high_n_{neon_type[1]}" + doc: "Multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, "i16"] + - [int64x2_t, int32x4_t, "i32"] + compose: + - FnCall: ["vmlsl_high_{neon_type[1]}", [a, b, {FnCall: ["vdupq_n_{neon_type[1]}", [c]]}]] + + - name: "vmlsl_high_n_{neon_type[1]}" + doc: "Multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x8_t, "u16"] + - [uint64x2_t, uint32x4_t, "u32"] + compose: + - FnCall: ["vmlsl_high_{neon_type[1]}", [a, b, {FnCall: ["vdupq_n_{neon_type[1]}", [c]]}]] + + - name: "vmlsl_high_lane{neon_type[2].no}" + doc: "Multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlsl2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmlsl_high_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmlsl_high_lane{neon_type[2].no}" + doc: "Multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlsl2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmlsl_high_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vclt{neon_type[0].no}" + doc: "Floating-point compare less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmgt]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vclt{type[2]}" + doc: "Floating-point compare less than" + arguments: ["a: {type[0]}", "b: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["f32", "u32", 's_f32'] + - ["f64", "u64", 'd_f64'] + compose: + - FnCall: + - simd_extract! + - - FnCall: + - "vclt_{type[0]}" + - - FnCall: ["vdup_n_{type[0]}", [a]] + - FnCall: ["vdup_n_{type[0]}", [b]] + - '0' + + - name: "vabdl_high_{neon_type[0]}" + doc: "Unsigned Absolute difference Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uabdl]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint8x16_t, uint16x8_t, uint8x8_t, '[8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x8_t, uint32x4_t, uint16x4_t, '[4, 5, 6, 7]'] + - [uint32x4_t, uint64x2_t, uint32x2_t, '[2, 3]'] + compose: + - Let: [c, "{neon_type[2]}", {FnCall: [simd_shuffle!, [a, a, "{type[3]}"]]}] + - Let: [d, "{neon_type[2]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - FnCall: [simd_cast, [{FnCall: ["vabd_{neon_type[0]}", [c, d]]}]] + + - name: "vfms_n_f64" + doc: "Floating-point fused Multiply-subtract to accumulator(vector)" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmsub]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, "f64"] + compose: + - FnCall: + - "vfms{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [c]] + + - name: "vfmsq_n_f64" + doc: "Floating-point fused Multiply-subtract to accumulator(vector)" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmls]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x2_t, "f64"] + compose: + - FnCall: + - "vfms{neon_type[1].no}" + - - a + - b + - FnCall: ["vdup{neon_type[1].N}", [c]] + + - name: "vpminnm{type[0]}" + doc: "Floating-point minimum number pairwise" + arguments: ["a: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['s_f32', float32x2_t, "f32"] + - ['qd_f64', float64x2_t, "f64"] + compose: + - LLVMLink: + name: "vpminnm{type[0]}" + links: + - link: "llvm.aarch64.neon.fminnmv.{type[2]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vpmaxnm{type[0]}" + doc: "Floating-point maximum number pairwise" + arguments: ["a: {neon_type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fmaxnmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ['s_f32', float32x2_t, "f32"] + - ['qd_f64', float64x2_t, "f64"] + compose: + - LLVMLink: + name: "vpmaxnm{type[0]}" + links: + - link: "llvm.aarch64.neon.fmaxnmv.{type[2]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vcled_{type[0]}" + doc: "Compare less than or equal" + arguments: ["a: {type[1]}", "b: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s64", "i64", "u64"] + - ["u64", "u64", "u64"] + compose: + - FnCall: + - transmute + - - FnCall: + - "vcle_{type[0]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vqdmulh{neon_type[0].lane_nox}" + doc: "Vector saturating doubling multiply high by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqdmulh, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, '2'] + - [int16x8_t, int16x4_t, '2'] + - [int32x2_t, int32x2_t, '1'] + - [int32x4_t, int32x2_t, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - FnCall: + - "vqdmulh{neon_type[0].no}" + - - a + - FnCall: + - "vdup{neon_type[0].N}" + - - FnCall: [simd_extract!, [b, 'LANE as u32']] + + - name: "vqabs{type[2]}" + doc: "Signed saturating absolute value" + arguments: ["a: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] + safety: + unsafe: [neon] + types: + - ["i8", "s8", 'b_s8'] + - ["i16", "s16", 'h_s16'] + compose: + - FnCall: + - "simd_extract!" + - - FnCall: ["vqabs_{type[1]}", [{FnCall: ["vdup_n_{type[1]}", [a]]}]] + - '0' + + - name: "vqabs{type[1]}" + doc: "Signed saturating absolute value" + arguments: ["a: {type[0]}"] + return_type: "{type[0]}" + attr: + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]]}, {FnCall: [assert_instr, [sqabs]]}]] + safety: + unsafe: [neon] + types: + - ["i32", "s_s32"] + - ["i64", "d_s64"] + compose: + - LLVMLink: + name: "vqabs{type[1]}" + links: + - link: "llvm.aarch64.neon.sqabs.{type[0]}" + arch: aarch64,arm64ec + + - name: "vmull_high_n_{neon_type[0]}" + doc: "Multiply long" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int16x8_t, "i16", int32x4_t] + - [int32x4_t, "i32", int64x2_t] + compose: + - FnCall: + - "vmull_high_{neon_type[0]}" + - - a + - FnCall: ["vdupq_n_{neon_type[0]}", [b]] + + - name: "vmull_high_n_{neon_type[0]}" + doc: "Multiply long" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint16x8_t, "u16", uint32x4_t] + - [uint32x4_t, "u32", uint64x2_t] + compose: + - FnCall: + - "vmull_high_{neon_type[0]}" + - - a + - FnCall: ["vdupq_n_{neon_type[0]}", [b]] + + - name: "vmull_high_lane{neon_type[1].no}" + doc: "Multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smull2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x8_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmull_high_{neon_type[0]}" + - - a + - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + + - name: "vmull_high_lane{neon_type[1].no}" + doc: "Multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umull2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x8_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmull_high_{neon_type[0]}" + - - a + - FnCall: [simd_shuffle!, [b, b, '{type[4]}']] + + - name: "vrsqrte{neon_type.no}" + doc: "Reciprocal square-root estimate." + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float64x1_t + - float64x2_t + compose: + - LLVMLink: + name: "vrsqrte{neon_type.no}" + links: + - link: "llvm.aarch64.neon.frsqrte.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrsqrte{type[0]}" + doc: "Reciprocal square-root estimate." + arguments: ["a: {type[1]}"] + return_type: "{type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [frsqrte]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["s_f32", "f32"] + - ["d_f64", "f64"] + compose: + - LLVMLink: + name: "vrsqrte{neon_type[1].no}" + links: + - link: "llvm.aarch64.neon.frsqrte.{type[1]}" + arch: aarch64,arm64ec + + - name: "vpminnm{neon_type.no}" + doc: "Floating-point Minimum Number Pairwise (vector)." + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fminnmp]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - float32x2_t + - float64x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vpminnm{neon_type.no}" + links: + - link: "llvm.aarch64.neon.fminnmp.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqshlu{type[0]}" + doc: "Signed saturating shift left unsigned" + arguments: ["a: {type[1]}"] + return_type: "{type[2]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshlu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [b_n_s8, i8, u8, '3', s8] + - [h_n_s16, i16, u16, '4', s16] + - [s_n_s32, i32, u32, '5', s32] + - [d_n_s64, i64, u64, '6', s64] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: + - simd_extract! + - - FnCall: + - "vqshlu_n_{type[4]}::" + - - FnCall: ["vdup_n_{type[4]}", [a]] + - '0' + + - name: "vcvta{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned integer, rounding to nearest with ties to away" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtau]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + - [float64x1_t, uint64x1_t] + - [float64x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "vcvta{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.fcvtau.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to signed fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [float64x1_t, int64x1_t] + - [float64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vcvt{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.fptosi.sat.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vmlal_high_n_{neon_type[1]}" + doc: "Multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, "i16"] + - [int64x2_t, int32x4_t, "i32"] + compose: + - FnCall: + - "vmlal_high_{neon_type[1]}" + - - a + - b + - FnCall: ["vdupq_n_{neon_type[1]}", [c]] + + - name: "vmlal_high_n_{neon_type[1]}" + doc: "Multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x8_t, "u16"] + - [uint64x2_t, uint32x4_t, "u32"] + compose: + - FnCall: + - "vmlal_high_{neon_type[1]}" + - - a + - b + - FnCall: ["vdupq_n_{neon_type[1]}", [c]] + + - name: "vmlal_high_lane{neon_type[2].no}" + doc: "Multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [smlal2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int64x2_t, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int64x2_t, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + + - name: "vmlal_high_lane{neon_type[2].no}" + doc: "Multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [umlal2, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: ['vmlal_high_{neon_type[2]}', [a, b, {FnCall: [simd_shuffle!, [c, c, '{type[4]}']]}]] + + - name: "vrsrad_n_u64" + doc: "Unsigned rounding shift right and accumulate." + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - "u64" + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 64']] + - Let: [b, u64, {FnCall: ["vrshrd_n_u64::", [b]]}] + - Identifier: ['a.wrapping_add(b)', Symbol] + + - name: "vcle{neon_type.no}" + doc: "Compare unsigned less than or equal" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [cmhs]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - uint64x1_t + - uint64x2_t + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x2x4_t, "v2i64", "p0i64"] + - ["*const f64", float64x1x4_t, "v1f64", "p0f64"] + - ["*const f64", float64x2x4_t, "v2f64", "p0f64"] + compose: + - LLVMLink: + name: "vld4{neon_type[1].dup_nox}" + arguments: + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.ld4r.{type[2]}.{type[3]}" + arch: aarch64,arm64ec + - FnCall: ["_vld4{neon_type[1].dup_nox}", ['a as _']] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x2x4_t, "q_dup_s64"] + compose: + - FnCall: + - transmute + - - FnCall: ["vld4{type[2]}", [{FnCall: [transmute, [a]]}]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x2x4_t, "q_dup_s64"] + compose: + - FnCall: + - transmute + - - FnCall: ["vld4{type[2]}", [{FnCall: [transmute, [a]]}]] + diff --git a/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml new file mode 100644 index 0000000000..87559963ed --- /dev/null +++ b/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml @@ -0,0 +1,9789 @@ +arch_cfgs: + - arch_name: aarch64 + target_feature: [neon] + llvm_prefix: llvm.aarch64.neon + +# Repeatedly used anchors +# #[stable(feature = "neon_intrinsics", since = "1.59.0")] +neon-stable: &neon-stable + FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + +# #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] +neon-unstable: &neon-unstable + FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + +# #[cfg_attr(target_arch = "arm", target_feature(enable = "v7"))] +neon-v7: &neon-v7 + FnCall: [cfg_attr, ['target_arch = "arm"', { FnCall: [target_feature, [ 'enable = "v7"']]} ]] + +# #[target_feature(enable = "neon,v7")] +enable-v7: &enable-v7 + FnCall: [target_feature, ['enable = "neon,v7"']] + +# #[cfg_attr(target_arch = "arm", target_feature(enable = "v8"))] +neon-v8: &neon-v8 + FnCall: [cfg_attr, ['target_arch = "arm"', { FnCall: [target_feature, [ 'enable = "v8"']]} ]] + +target-is-arm: &target-is-arm + FnCall: [cfg, ['target_arch = "arm"']] + +# #[cfg(not(target_arch = "arm"))] +target-not-arm: &target-not-arm + FnCall: [cfg, [{ FnCall: [not, ['target_arch = "arm"']]}]] + +neon-target-aarch64-arm64ec: &neon-target-aarch64-arm64ec + FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]] + +# #[cfg_attr(not(target_arch = "arm"), stable(feature = "neon_intrinsics", since = "1.59.0"))] +neon-stable-not-arm: &neon-stable-not-arm + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']]}, *neon-stable]] + +#[cfg_attr(target_arch = "arm", unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800"))] +neon-unstable-is-arm: &neon-unstable-is-arm + FnCall: [ cfg_attr, ['target_arch = "arm"', *neon-unstable]] + +# #[cfg_attr(all(test, not(target_env = "msvc"))] +msvc-disabled: &msvc-disabled + FnCall: [all, [test, {FnCall: [not, ['target_env = "msvc"']]}]] + +# all(test, target_arch = "arm") +test-is-arm: &test-is-arm + FnCall: [all, [test, 'target_arch = "arm"']] + +# #[target_feature(enable = "neon,aes")] +neon-aes: &neon-aes + FnCall: [target_feature, ['enable = "neon,aes"']] + +# #[target_feature(enable = "neon,i8mm")] +neon-i8mm: &neon-i8mm + FnCall: [target_feature, ['enable = "neon,i8mm"']] + +#[cfg_attr(not(target_arch = "arm"), unstable(feature = "stdarch_neon_i8mm", issue = "117223"))] +neon-unstable-i8mm: &neon-unstable-i8mm + FnCall: [cfg_attr, [{ FnCall: [not, ['target_arch = "arm"']] }, { FnCall: [unstable, ['feature = "stdarch_neon_i8mm"', 'issue = "117223"']] } ]] + +# #[unstable(feature = "stdarch_neon_fcma", issue = "117222")] +neon-unstable-fcma: &neon-unstable-fcma + FnCall: [unstable, ['feature = "stdarch_neon_fcma"', 'issue = "117222"']] + +intrinsics: + - name: "vand{neon_type.no}" + doc: Vector bitwise and + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vand]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [and]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + - int64x1_t + - int64x2_t + - uint64x1_t + - uint64x2_t + compose: + - FnCall: + - simd_and + - - a + - b + + - name: "vorr{neon_type.no}" + doc: "Vector bitwise or (immediate, inclusive)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vorr]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [orr]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + - int64x1_t + - int64x2_t + - uint64x1_t + - uint64x2_t + compose: + - FnCall: + - simd_or + - - a + - b + + - name: "veor{neon_type.no}" + doc: Vector bitwise exclusive or (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [veor]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [eor]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + - int64x1_t + - int64x2_t + - uint64x1_t + - uint64x2_t + compose: + - FnCall: + - simd_xor + - - a + - b + + - name: "vabd{neon_type.no}" + doc: Absolute difference between the arguments + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vabd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sabd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "sabd.{neon_type}" + links: + - link: "llvm.aarch64.neon.sabd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vabds.{neon_type}" + arch: arm + + - name: "vabd{neon_type.no}" + doc: Absolute difference between the arguments + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vabd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uabd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "uabd.{neon_type}" + links: + - link: "llvm.aarch64.neon.uabd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vabdu.{neon_type}" + arch: arm + + - name: "vabd{neon_type.no}" + doc: Absolute difference between the arguments of Floating + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vabd.f32"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fabd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "fabd.{neon_type}" + links: + - link: "llvm.arm.neon.vabds.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fabd.{neon_type}" + arch: aarch64,arm64ec + + - name: "vabdl{neon_type[0].noq}" + doc: Signed Absolute difference Long + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - target_feature + - - 'enable = "v7"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - '"vabdl.{neon_type[0]}"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - sabdl + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, uint8x8_t] + - [int16x4_t, int32x4_t, uint16x4_t] + - [int32x2_t, int64x2_t, uint32x2_t] + compose: + - Let: + - c + - "{neon_type[2]}" + - FnCall: + - simd_cast + - - FnCall: + - "vabd_{neon_type[0]}" + - - a + - b + - FnCall: + - simd_cast + - - c + + - name: "vceq{neon_type[0].no}" + doc: "Compare bitwise Equal (vector)" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vceq{type[2]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmeq]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint8x8_t, ".i8"] + - [uint8x16_t, uint8x16_t, ".i8"] + - [int8x8_t, uint8x8_t, ".i8"] + - [int8x16_t, uint8x16_t, ".i8"] + - [poly8x8_t, uint8x8_t, ".i8"] + - [poly8x16_t, uint8x16_t, ".i8"] + - [uint16x4_t, uint16x4_t, ".i16"] + - [uint16x8_t, uint16x8_t, ".i16"] + - [int16x4_t, uint16x4_t, ".i16"] + - [int16x8_t, uint16x8_t, ".i16"] + - [uint32x2_t, uint32x2_t, ".i32"] + - [uint32x4_t, uint32x4_t, ".i32"] + - [int32x2_t, uint32x2_t, ".i32"] + - [int32x4_t, uint32x4_t, ".i32"] + compose: + - FnCall: [simd_eq, [a, b]] + + - name: "vceq{neon_type[0].no}" + doc: "Floating-point compare equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vceq.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmeq]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: [simd_eq, [a, b]] + + - name: "vtst{neon_type[0].no}" + doc: "Signed compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vtst]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [int16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [int16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [int32x2_t, uint32x2_t, i32x2, 'i32x2::new(0, 0)'] + - [int32x4_t, uint32x4_t, i32x4, 'i32x4::new(0, 0, 0, 0)'] + - [poly8x8_t, uint8x8_t, i8x8, 'i8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [poly8x16_t, uint8x16_t, i8x16, 'i8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [poly16x4_t, uint16x4_t, i16x4, 'i16x4::new(0, 0, 0, 0)'] + - [poly16x8_t, uint16x8_t, i16x8, 'i16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[2]}", "{type[3]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] + + - name: "vabs{neon_type.no}" + doc: "Floating-point absolute value" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vabs]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fabs]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - FnCall: [simd_fabs, [a]] + + - name: "vcgt{neon_type[0].no}" + doc: "Compare signed greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.{type[2]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, "s8"] + - [int8x16_t, uint8x16_t, "s8"] + - [int16x4_t, uint16x4_t, s16] + - [int16x8_t, uint16x8_t, s16] + - [int32x2_t, uint32x2_t, "s32"] + - [int32x4_t, uint32x4_t, "s32"] + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vcgt{neon_type.no}" + doc: "Compare unsigned greater than" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.{neon_type}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhi]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vcgt{neon_type[0].no}" + doc: "Floating-point compare greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: [simd_gt, [a, b]] + + - name: "vclt{neon_type[0].no}" + doc: "Compare signed less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.{neon_type[0]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t] + - [int8x16_t, uint8x16_t] + - [int16x4_t, uint16x4_t] + - [int16x8_t, uint16x8_t] + - [int32x2_t, uint32x2_t] + - [int32x4_t, uint32x4_t] + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vcle{neon_type[0].no}" + doc: "Compare signed less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.{neon_type[0]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t] + - [int8x16_t, uint8x16_t] + - [int16x4_t, uint16x4_t] + - [int16x8_t, uint16x8_t] + - [int32x2_t, uint32x2_t] + - [int32x4_t, uint32x4_t] + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vcle{neon_type[0].no}" + doc: "Floating-point compare less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vcge{neon_type[0].no}" + doc: "Compare signed greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.{neon_type[0]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t] + - [int8x16_t, uint8x16_t] + - [int16x4_t, uint16x4_t] + - [int16x8_t, uint16x8_t] + - [int32x2_t, uint32x2_t] + - [int32x4_t, uint32x4_t] + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vcls{neon_type.no}" + doc: "Count leading sign bits" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcls.{neon_type}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "vcls{neon_type.no}" + links: + - link: "llvm.arm.neon.vcls.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.cls.{neon_type}" + arch: aarch64,arm64ec + + - name: "vcls{neon_type[0].no}" + doc: "Count leading sign bits" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vcls]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [uint16x4_t, int16x4_t] + - [uint16x8_t, int16x8_t] + - [uint32x2_t, int32x2_t] + - [uint32x4_t, int32x4_t] + compose: + - FnCall: + - "vcls{neon_type[1].no}" + - - FnCall: [transmute, [a]] + + - name: "vclz{neon_type.no}" + doc: "Count leading zero bits" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vclz.i8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + compose: + - FnCall: ["vclz{neon_type.no}_", [a]] + + - name: "vclz{neon_type[0].no}" + doc: "Count leading zero bits" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vclz.i8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vclz{neon_type[1].no}_" + - - FnCall: [transmute, [a]] + + - name: "vclz{neon_type[0].no}" + doc: "Count leading zero bits" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vclz{type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, '.i16'] + - [int16x8_t, '.i16'] + - [int32x2_t, '.i32'] + - [int32x4_t, '.i32'] + compose: + - FnCall: ["vclz{neon_type[0].no}_", [a]] + + - name: "vclz{neon_type[0].no}" + doc: "Count leading zero bits" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vclz{type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [clz]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint32x2_t, '.i32', int32x2_t] + - [uint32x4_t, '.i32', int32x4_t] + - [uint16x4_t, '.i16', int16x4_t] + - [uint16x8_t, '.i16', int16x8_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vclz{neon_type[2].no}_" + - - FnCall: [transmute, [a]] + + - name: "vcagt{neon_type[0].no}" + doc: "Floating-point absolute compare greater than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vacgt.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - LLVMLink: + name: "vcagt{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vacgt.{neon_type[1]}.{neon_type[0]}" + arch: arm + - link: "llvm.aarch64.neon.facgt.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcage{neon_type[0].no}" + doc: "Floating-point absolute compare greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vacge.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - LLVMLink: + name: "vcage{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vacge.{neon_type[1]}.{neon_type[0]}" + arch: arm + - link: "llvm.aarch64.neon.facge.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vcalt{neon_type[0].no}" + doc: "Floating-point absolute compare less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vacgt.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: ["vcagt{neon_type[0].no}", [b, a]] + + - name: "vcale{neon_type[0].no}" + doc: "Floating-point absolute compare less than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vacge.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [facge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: ["vcage{neon_type[0].no}", [b, a]] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vcvt]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [scvtf]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, float32x2_t] + - [int32x4_t, float32x4_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vcvt]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ucvtf]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint32x2_t, float32x2_t] + - [uint32x4_t, float32x4_t] + compose: + - FnCall: [simd_cast, [a]] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vcvt, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint32x2_t, float32x2_t] + - [uint32x4_t, float32x4_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.arm.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" + arch: arm + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a.as_signed()", N]] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vcvt, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, float32x2_t] + - [int32x4_t, float32x4_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.arm.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" + arch: arm + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [scvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, float32x2_t] + - [int32x4_t, float32x4_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxs2fp.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", [a, N]] + + - name: "vcvt{neon_type[1].N}_{neon_type[0]}" + doc: "Fixed-point convert to floating-point" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ucvtf, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint32x2_t, float32x2_t] + - [uint32x4_t, float32x4_t] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{neon_type[1].N}_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfxu2fp.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{neon_type[1].N}_{neon_type[0]}", ["a.as_signed()", N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vcvt, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t, _n_s32_f32] + - [float32x4_t, int32x4_t, q_n_s32_f32] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.arm.neon.vcvtfp2fxs.{neon_type[1]}.{neon_type[0]}" + arch: arm + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vcvt, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, _n_u32_f32] + - [float32x4_t, uint32x4_t, q_n_u32_f32] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.arm.neon.vcvtfp2fxu.{neon_type[1]}.{neon_type[0]}" + arch: arm + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzs, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t, _n_s32_f32] + - [float32x4_t, int32x4_t, q_n_s32_f32] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: ["a: {type[0]}", "n: i32"] + links: + - link: "llvm.aarch64.neon.vcvtfp2fxs.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vcvt{type[2]}" + doc: "Floating-point convert to fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [fcvtzu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t, _n_u32_f32] + - [float32x4_t, uint32x4_t, q_n_u32_f32] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - LLVMLink: + name: "vcvt{type[2]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.vcvtfp2fxu.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vcvt{type[2]}", [a, N]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.8"', 'N = 4']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 4']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s8, int8x8_t, int8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_s8, int8x8_t, int8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_u8, uint8x8_t, uint8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_u8, uint8x8_t, uint8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_p8, poly8x8_t, poly8x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_p8, poly8x8_t, poly8x16_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.8"', 'N = 8']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 8']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [q_laneq_s8, int8x16_t, int8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_s8, int8x16_t, int8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_u8, uint8x16_t, uint8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_u8, uint8x16_t, uint8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_p8, poly8x16_t, poly8x16_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_p8, poly8x16_t, poly8x8_t, '4', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.16"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_s16, int16x4_t, int16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_u16, uint16x4_t, uint16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_lane_p16, poly16x4_t, poly16x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_lane_p16, poly16x4_t, poly16x8_t, '2', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.16"', 'N = 4']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 4']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_s16, int16x8_t, int16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_u16, uint16x8_t, uint16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + - [q_laneq_p16, poly16x8_t, poly16x8_t, '3', '[N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_p16, poly16x8_t, poly16x4_t, '3', '[N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.32"', 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s32, int32x2_t, int32x2_t, '1', '[N as u32, N as u32]'] + - [q_lane_s32, int32x2_t, int32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[N as u32, N as u32]'] + - [q_lane_u32, uint32x2_t, uint32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] + - [_lane_f32, float32x2_t, float32x2_t, '1', '[N as u32, N as u32]'] + - [q_lane_f32, float32x2_t, float32x4_t, '1', '[N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vdup.32"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_s32, int32x4_t, int32x2_t, '2', '[N as u32, N as u32]'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_u32, uint32x4_t, uint32x2_t, '2', '[N as u32, N as u32]'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[N as u32, N as u32, N as u32, N as u32]'] + - [_laneq_f32, float32x4_t, float32x2_t, '2', '[N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[3]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[4]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmov, 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [q_laneq_s64, int64x2_t, '1', '[N as u32, N as u32]'] + - [q_laneq_u64, uint64x2_t, '1', '[N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] + - FnCall: [simd_shuffle!, [a, a, "{type[3]}"]] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmov, 'N = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [dup, 'N = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [q_lane_s64, int64x1_t, int64x2_t] + - [q_lane_u64, uint64x1_t, uint64x2_t] + compose: + - FnCall: [static_assert!, ['N == 0']] + - FnCall: [simd_shuffle!, [a, a, '[N as u32, N as u32]']] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop, 'N = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'N = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s64, int64x1_t] + - [_lane_u64, uint64x1_t] + compose: + - FnCall: [static_assert!, ['N == 0']] + - Identifier: [a, Symbol] + + - name: "vdup{type[0]}" + doc: "Set all vector lanes to the same value" + arguments: ["a: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmov, 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [_laneq_s64, int64x2_t, int64x1_t, '::'] + - [_laneq_u64, uint64x2_t, uint64x1_t, '::'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, 1]] + - FnCall: + - "transmute{type[3]}" + - - FnCall: [simd_extract!, [a, 'N as u32']] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vext.8"', 'N = 7']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ext, 'N = 7']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [int16x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [uint8x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [uint16x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [poly8x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + - [poly16x8_t, ' static_assert_uimm_bits!(N, 3); match N & 0b111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vext.8"', 'N = 15']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ext, 'N = 15']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x16_t, ' static_assert_uimm_bits!(N, 4); match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] + - [uint8x16_t, ' static_assert_uimm_bits!(N, 4); match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] + - [poly8x16_t, ' static_assert_uimm_bits!(N, 4); match N & 0b1111 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18]), 4 => simd_shuffle!(a, b, [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19]), 5 => simd_shuffle!(a, b, [5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20]), 6 => simd_shuffle!(a, b, [6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21]), 7 => simd_shuffle!(a, b, [7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22]), 8 => simd_shuffle!(a, b, [8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23]), 9 => simd_shuffle!(a, b, [9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24]), 10 => simd_shuffle!(a, b, [10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25]), 11 => simd_shuffle!(a, b, [11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26]), 12 => simd_shuffle!(a, b, [12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27]), 13 => simd_shuffle!(a, b, [13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28]), 14 => simd_shuffle!(a, b, [14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29]), 15 => simd_shuffle!(a, b, [15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vext.8"', 'N = 3']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ext, 'N = 3']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, 'static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [int32x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [uint16x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [uint32x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [poly16x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + - [float32x4_t, ' static_assert_uimm_bits!(N, 2); match N & 0b11 { 0 => simd_shuffle!(a, b, [0, 1, 2, 3]), 1 => simd_shuffle!(a, b, [1, 2, 3, 4]), 2 => simd_shuffle!(a, b, [2, 3, 4, 5]), 3 => simd_shuffle!(a, b, [3, 4, 5, 6]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vext.8"', 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ext, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, ' static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [uint32x2_t, ' static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [float32x2_t, ' static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vext{neon_type[0].no}" + doc: "Extract vector from pair of vectors" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmov, 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ext, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, 'static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + - [uint64x2_t, 'static_assert_uimm_bits!(N, 1); match N & 0b1 { 0 => simd_shuffle!(a, b, [0, 1]), 1 => simd_shuffle!(a, b, [1, 2]), _ => unreachable_unchecked(), }'] + compose: + - Identifier: ["{type[1]}", Symbol] + + - name: "vmla{neon_type[0].no}" + doc: "Multiply-add to accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla{type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, ".i8"] + - [int8x16_t, ".i8"] + - [uint8x8_t, ".i8"] + - [uint8x16_t, ".i8"] + - [int16x4_t, ".i16"] + - [int16x8_t, ".i16"] + - [uint16x4_t, ".i16"] + - [uint16x8_t, ".i16"] + - [int32x2_t, ".i32"] + - [int32x4_t, ".i32"] + - [uint32x2_t, ".i32"] + - [uint32x4_t, ".i32"] + compose: + - FnCall: [simd_add, [a, {FnCall: [simd_mul, [b, c]]}]] + + - name: "vmla{neon_type.no}" + doc: "Floating-point multiply-add to accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - FnCall: [simd_add, [a, {FnCall: [simd_mul, [b, c]]}]] + + - name: "vmlal{neon_type[1].no}" + doc: "Signed multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{type[2]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, "s8"] + - [int32x4_t, int16x4_t, "s16"] + - [int64x2_t, int32x2_t, "s32"] + compose: + - FnCall: [simd_add, [a, {FnCall: ["vmull_{type[2]}", [b, c]]}]] + + - name: "vmlal_n_{type[4]}" + doc: "Vector widening multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{type[4]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, "i16", int32x4_t, 's16'] + - [int64x2_t, int32x2_t, "i32", int64x2_t, 's32'] + compose: + - FnCall: + - "vmlal{neon_type[1].noq}" + - - a + - b + - FnCall: ["vdup_n_{neon_type[1]}", [c]] + + - name: "vmlal_n_{type[2]}" + doc: "Vector widening multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{type[2]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x4_t, "u16", uint32x4_t] + - [uint64x2_t, uint32x2_t, "u32", uint64x2_t] + compose: + - FnCall: + - "vmlal{neon_type[1].noq}" + - - a + - b + - FnCall: ["vdup_n_{neon_type[1]}", [c]] + + - name: "vmlal_lane{neon_type[2].no}" + doc: "Vector widening multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{neon_type[1]}"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlal, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int64x2_t, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [int64x2_t, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmlal_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + + - name: "vmlal_lane{neon_type[2].no}" + doc: "Vector widening multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{neon_type[1]}"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlal, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: + - "vmlal_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, '{type[5]}']] + + - name: "vmlal_{neon_type[1]}" + doc: "Unsigned multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlal.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t] + - [uint32x4_t, uint16x4_t] + - [uint64x2_t, uint32x2_t] + compose: + - FnCall: + - simd_add + - - a + - FnCall: ["vmull_{neon_type[1]}", [b, c]] + + - name: "vmls{neon_type[0].no}" + doc: "Multiply-subtract from accumulator" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls{type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, '.i8'] + - [int8x16_t, '.i8'] + - [uint8x8_t, '.i8'] + - [uint8x16_t, '.i8'] + - [int16x4_t, ".i16"] + - [int16x8_t, ".i16"] + - [uint16x4_t, ".i16"] + - [uint16x8_t, ".i16"] + - [int32x2_t, ".i32"] + - [int32x4_t, ".i32"] + - [uint32x2_t, ".i32"] + - [uint32x4_t, ".i32"] + compose: + - FnCall: + - simd_sub + - - a + - FnCall: [simd_mul, [b, c]] + + - name: "vmlsl_{neon_type[1]}" + doc: "Signed multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t] + - [int32x4_t, int16x4_t] + - [int64x2_t, int32x2_t] + compose: + - FnCall: [simd_sub, [a, {FnCall: ["vmull_{neon_type[1]}", [b, c]]}]] + + - name: "vmlsl_n_{neon_type[1]}" + doc: "Vector widening multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, "i16"] + - [int64x2_t, int32x2_t, "i32"] + compose: + - FnCall: ["vmlsl_{neon_type[1]}", [a, b, {FnCall: ["vdup_n_{neon_type[1]}", [c]]}]] + + - name: "vmlsl_n_{neon_type[1]}" + doc: "Vector widening multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x4_t, "u16"] + - [uint64x2_t, uint32x2_t, "u32"] + compose: + - FnCall: ["vmlsl_{neon_type[1]}", [a, b, {FnCall: ["vdup_n_{neon_type[1]}", [c]]}]] + + - name: "vmlsl_lane{neon_type[2].no}" + doc: "Vector widening multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x4_t, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmlsl_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmlsl_lane{neon_type[2].no}" + doc: "Vector widening multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smlsl, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int32x2_t, int32x2_t, '[LANE as u32, LANE as u32]', '1'] + - [int64x2_t, int32x2_t, int32x4_t, '[LANE as u32, LANE as u32]', '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[4]}"]] + - FnCall: + - "vmlsl_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + + - name: "vmlsl_lane{neon_type[2].no}" + doc: "Vector widening multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlsl, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint32x4_t, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x4_t, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [uint64x2_t, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmlsl_{neon_type[1]}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmlsl_{neon_type[1]}" + doc: "Unsigned multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmlsl.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t] + - [uint32x4_t, uint16x4_t] + - [uint64x2_t, uint32x2_t] + compose: + - FnCall: [simd_sub, [a, {FnCall: ["vmull_{neon_type[1]}", [b, c]]}]] + + - name: "vneg{neon_type[0].no}" + doc: Negate + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vneg.{type[1]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [neg]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, 's8'] + - [int8x16_t, 's8'] + - [int16x4_t, 's16'] + - [int16x8_t, 's16'] + - [int32x2_t, 's32'] + - [int32x4_t, 's32'] + compose: + - FnCall: [simd_neg, [a]] + + - name: "vneg{neon_type[0].no}" + doc: Negate + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vneg.{type[1]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fneg]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [float32x2_t, 'f32'] + - [float32x4_t, 'f32'] + compose: + - FnCall: [simd_neg, [a]] + + - name: "vqneg{neon_type[0].no}" + doc: Signed saturating negate + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqneg.{type[1]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqneg]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, 's8', 'i8'] + - [int8x16_t, 's8', 'i8'] + - [int16x4_t, 's16', 'i16'] + - [int16x8_t, 's16', 'i16'] + - [int32x2_t, 's32', 'i32'] + - [int32x4_t, 's32', 'i32'] + compose: + - LLVMLink: + name: "sqneg.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.sqneg.v{neon_type[0].lane}{type[2]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vqneg.v{neon_type[0].lane}{type[2]}" + arch: arm + + - name: "vqsub{neon_type[0].no}" + doc: Saturating subtract + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqsub.{type[1]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uqsub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint8x8_t, u8, i8] + - [uint8x16_t, u8, i8] + - [uint16x4_t, u16, i16] + - [uint16x8_t, u16, i16] + - [uint32x2_t, u32, i32] + - [uint32x4_t, u32, i32] + - [uint64x1_t, u64, i64] + - [uint64x2_t, u64, i64] + compose: + - LLVMLink: + name: "uqsub.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.uqsub.v{neon_type[0].lane}{type[2]}" + arch: aarch64,arm64ec + - link: "llvm.usub.sat.{neon_type[0].lane}{type[2]}" + arch: arm + + - name: "vqsub{neon_type[0].no}" + doc: Saturating subtract + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqsub.{type[1]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqsub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, s8, i8] + - [int8x16_t, s8, i8] + - [int16x4_t, s16, i16] + - [int16x8_t, s16, i16] + - [int32x2_t, s32, i32] + - [int32x4_t, s32, i32] + - [int64x1_t, s64, i64] + - [int64x2_t, s64, i64] + compose: + - LLVMLink: + name: "sqsub.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.sqsub.v{neon_type[0].lane}{type[2]}" + arch: aarch64,arm64ec + - link: "llvm.ssub.sat.{neon_type[0].lane}{type[2]}" + arch: arm + + - name: "vhadd{neon_type.no}" + doc: Halving add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - target_feature + - - 'enable = "v7"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - '"vhadd.{neon_type}"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - uhadd + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "uhadd.{neon_type}" + links: + - link: "llvm.aarch64.neon.uhadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vhaddu.{neon_type}" + arch: arm + + - name: "vhadd{neon_type.no}" + doc: Halving add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - target_feature + - - 'enable = "v7"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - '"vhadd.{neon_type}"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - shadd + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "shadd.{neon_type}" + links: + - link: "llvm.aarch64.neon.shadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vhadds.{neon_type}" + arch: arm + + - name: "vrhadd{neon_type.no}" + doc: Rounding halving add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vrhadd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [srhadd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "vrhadd.{neon_type}" + links: + - link: "llvm.aarch64.neon.srhadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vrhadds.{neon_type}" + arch: arm + + - name: "vrhadd{neon_type.no}" + doc: Rounding halving add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vrhadd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [urhadd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "vrhaddu.{neon_type}" + links: + - link: "llvm.aarch64.neon.urhadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vrhaddu.{neon_type}" + arch: arm + + - name: "vrndn{neon_type.no}" + doc: "Floating-point round to integral, to nearest with ties to even" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [target_feature, ['enable = "fp-armv8,v8"']]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vrintn]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [frintn]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "llvm.frinn.{neon_type}" + links: + - link: "llvm.aarch64.neon.frintn.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vrintn.{neon_type}" + arch: arm + + - name: "vqadd{neon_type.no}" + doc: Saturating add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqadd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uqadd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + - uint64x1_t + - uint64x2_t + compose: + - LLVMLink: + name: "uqadd.{neon_type}" + links: + - link: "llvm.aarch64.neon.uqadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.uadd.sat.{neon_type}" + arch: arm + + - name: "vqadd{neon_type.no}" + doc: Saturating add + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqadd.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqadd]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "sqadd.{neon_type}" + links: + - link: "llvm.aarch64.neon.sqadd.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.sadd.sat.{neon_type}" + arch: arm + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const f32", float32x2x2_t] + - ["*const f32", float32x4x2_t] + - ["*const f32", float32x2x3_t] + - ["*const f32", float32x4x3_t] + - ["*const f32", float32x2x4_t] + - ["*const f32", float32x4x4_t] + compose: + - LLVMLink: + name: "vld1x{neon_type[1].tuple}.{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0f{neon_type[1].base}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}f{neon_type[1].base}.p0f{neon_type[1].base}" + arch: arm + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t] + - ["*const i8", int8x16x2_t] + - ["*const i8", int8x8x3_t] + - ["*const i8", int8x16x3_t] + - ["*const i8", int8x8x4_t] + - ["*const i8", int8x16x4_t] + - ["*const i16", int16x4x2_t] + - ["*const i16", int16x8x2_t] + - ["*const i16", int16x4x3_t] + - ["*const i16", int16x8x3_t] + - ["*const i16", int16x4x4_t] + - ["*const i16", int16x8x4_t] + - ["*const i32", int32x2x2_t] + - ["*const i32", int32x4x2_t] + - ["*const i32", int32x2x3_t] + - ["*const i32", int32x4x3_t] + - ["*const i32", int32x2x4_t] + - ["*const i32", int32x4x4_t] + - ["*const i64", int64x1x2_t] + - ["*const i64", int64x1x3_t] + - ["*const i64", int64x1x4_t] + - ["*const i64", int64x2x2_t] + - ["*const i64", int64x2x3_t] + - ["*const i64", int64x2x4_t] + compose: + - LLVMLink: + name: "ld1x{neon_type[1].tuple}.{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.ld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0i{neon_type[1].base}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vld1x{neon_type[1].tuple}.v{neon_type[1].lane}i{neon_type[1].base}.p0i{neon_type[1].base}" + arch: arm + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x8x2_t, int8x8x2_t] + - ["*const u8", uint8x16x2_t, int8x16x2_t] + - ["*const u8", uint8x8x3_t, int8x8x3_t] + - ["*const u8", uint8x16x3_t, int8x16x3_t] + - ["*const u8", uint8x8x4_t, int8x8x4_t] + - ["*const u8", uint8x16x4_t, int8x16x4_t] + - ["*const u16", uint16x4x2_t, int16x4x2_t] + - ["*const u16", uint16x8x2_t, int16x8x2_t] + - ["*const u16", uint16x4x3_t, int16x4x3_t] + - ["*const u16", uint16x8x3_t, int16x8x3_t] + - ["*const u16", uint16x4x4_t, int16x4x4_t] + - ["*const u16", uint16x8x4_t, int16x8x4_t] + - ["*const u32", uint32x2x2_t, int32x2x2_t] + - ["*const u32", uint32x4x2_t, int32x4x2_t] + - ["*const u32", uint32x2x3_t, int32x2x3_t] + - ["*const u32", uint32x4x3_t, int32x4x3_t] + - ["*const u32", uint32x2x4_t, int32x2x4_t] + - ["*const u32", uint32x4x4_t, int32x4x4_t] + - ["*const u64", uint64x1x2_t, int64x1x2_t] + - ["*const u64", uint64x1x3_t, int64x1x3_t] + - ["*const u64", uint64x1x4_t, int64x1x4_t] + - ["*const u64", uint64x2x2_t, int64x2x2_t] + - ["*const u64", uint64x2x3_t, int64x2x3_t] + - ["*const u64", uint64x2x4_t, int64x2x4_t] + - ["*const p8", poly8x8x2_t, int8x8x2_t] + - ["*const p8", poly8x8x3_t, int8x8x3_t] + - ["*const p8", poly8x8x4_t, int8x8x4_t] + - ["*const p8", poly8x16x2_t, int8x16x2_t] + - ["*const p8", poly8x16x3_t, int8x16x3_t] + - ["*const p8", poly8x16x4_t, int8x16x4_t] + - ["*const p16", poly16x4x2_t, int16x4x2_t] + - ["*const p16", poly16x4x3_t, int16x4x3_t] + - ["*const p16", poly16x4x4_t, int16x4x4_t] + - ["*const p16", poly16x8x2_t, int16x8x2_t] + - ["*const p16", poly16x8x3_t, int16x8x3_t] + - ["*const p16", poly16x8x4_t, int16x8x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld1{neon_type[2].no}" + - - FnCall: + - transmute + - - a + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x3_t, int64x1x3_t] + - ["*const p64", poly64x1x4_t, int64x1x4_t] + - ["*const p64", poly64x2x2_t, int64x2x2_t] + - ["*const p64", poly64x2x3_t, int64x2x3_t] + - ["*const p64", poly64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld1{neon_type[2].no}" + - - FnCall: + - transmute + - - a + + - name: "vld1{neon_type[1].no}" + doc: "Load multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld1]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld1]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld1{neon_type[2].no}" + - - FnCall: + - transmute + - - a + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [vld2] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8] + - ["*const i16", int16x4x2_t, i16] + - ["*const i32", int32x2x2_t, i32] + - ["*const i8", int8x16x2_t, i8] + - ["*const i16", int16x8x2_t, i16] + - ["*const i32", int32x4x2_t, i32] + - ["*const f32", float32x2x2_t, f32] + - ["*const f32", float32x4x2_t, f32] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as *const i8" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x2_t, i64] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as *const i8" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - *neon-stable + assert_instr: [ld2] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8, int8x8_t] + - ["*const i16", int16x4x2_t, i16, int16x4_t] + - ["*const i32", int32x2x2_t, i32, int32x2_t] + - ["*const i8", int8x16x2_t, i8, int8x16_t] + - ["*const i16", int16x8x2_t, i16, int16x8_t] + - ["*const i32", int32x4x2_t, i32, int32x4_t] + - ["*const f32", float32x2x2_t, f32, float32x2_t] + - ["*const f32", float32x4x2_t, f32, float32x4_t] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const {neon_type[3]}" + links: + - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as _" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - *neon-stable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x2_t, i64, int64x1_t] + compose: + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const {neon_type[3]}" + links: + - link: "llvm.aarch64.neon.ld2.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].nox}" + - - "a as _" + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld2]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x8x2_t, int8x8x2_t] + - ["*const u16", uint16x4x2_t, int16x4x2_t] + - ["*const u32", uint32x2x2_t, int32x2x2_t] + - ["*const u8", uint8x16x2_t, int8x16x2_t] + - ["*const u16", uint16x8x2_t, int16x8x2_t] + - ["*const u32", uint32x4x2_t, int32x4x2_t] + - ["*const p8", poly8x8x2_t, int8x8x2_t] + - ["*const p16", poly16x4x2_t, int16x4x2_t] + - ["*const p8", poly8x16x2_t, int8x16x2_t] + - ["*const p16", poly16x8x2_t, int16x8x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + + - name: "vld2{neon_type[1].nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - FnCall: + - cfg_attr + - - test + - FnCall: + - assert_instr + - - vld2 + - "LANE = 0" + - FnCall: + - rustc_legacy_const_generics + - - "2" + - *neon-unstable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8, int8x8_t, "3"] + - ["*const i16", int16x4x2_t, i16, int16x4_t, "2"] + - ["*const i32", int32x2x2_t, i32, int32x2_t, "1"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[4]}" + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "a: {neon_type[3]}" + - "b: {neon_type[3]}" + - "n: i32" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2lane.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2_lane{neon_type[1].nox}" + - - "a as _" + - "b.0" + - "b.1" + - "LANE" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld2, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x8x2_t, int8x8_t, "3"] + - ["*const u16", uint16x4x2_t, int16x4_t, "2"] + - ["*const u32", uint32x2x2_t, int32x2_t, "1"] + - ["*const u16", uint16x8x2_t, int16x8_t, "3"] + - ["*const u32", uint32x4x2_t, int32x4_t, "2"] + - ["*const p8", poly8x8x2_t, int8x8_t, "3"] + - ["*const p16", poly16x4x2_t, int16x4_t, "2"] + - ["*const p16", poly16x8x2_t, int16x8_t, "3"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[3]}" + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - FnCall: + - cfg_attr + - - test + - FnCall: + - assert_instr + - - ld2 + - "LANE = 0" + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8, int8x8_t, "3"] + - ["*const i16", int16x4x2_t, i16, int16x4_t, "2"] + - ["*const i32", int32x2x2_t, i32, int32x2_t, "1"] + - ["*const i16", int16x8x2_t, i16, int16x8_t, "3"] + - ["*const i32", int32x4x2_t, i32, int32x4_t, "2"] + - ["*const f32", float32x2x2_t, f32, float32x2_t, "2"] + - ["*const f32", float32x4x2_t, f32, float32x4_t, "2"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[4]}" + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "a: {neon_type[3]}" + - "b: {neon_type[3]}" + - "n: i64" + - "ptr: *const i8" + links: + - link: "llvm.aarch64.neon.ld2lane.v{neon_type[1].lane}{type[2]}.p0i8" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].lane_nox}" + - - "b.0" + - "b.1" + - "LANE as i64" + - "a as _" + + - name: "vld2{neon_type[1].lane_nox}" + doc: Load multiple 2-element structures to two registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - FnCall: + - cfg_attr + - - test + - FnCall: + - assert_instr + - - vld2 + - "LANE = 0" + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ["*const i16", int16x8x2_t, i16, int16x8_t, "3"] + - ["*const i32", int32x4x2_t, i32, int32x4_t, "2"] + - ["*const f32", float32x2x2_t, f32, float32x2_t, "1"] + - ["*const f32", float32x4x2_t, f32, float32x4_t, "2"] + compose: + - FnCall: + - "static_assert_uimm_bits!" + - - LANE + - "{type[4]}" + - LLVMLink: + name: "vld2.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "a: {neon_type[3]}" + - "b: {neon_type[3]}" + - "n: i32" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2lane.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2{neon_type[1].lane_nox}" + - - "a as _" + - "b.0" + - "b.1" + - "LANE" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x2_t, i64] + compose: + - LLVMLink: + name: "vld2dup.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2dup.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2{neon_type[1].dup_nox}" + - - "a as *const i8" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - *neon-stable + assert_instr: [ld2r] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x2_t, i64] + compose: + - LLVMLink: + name: "vld2dup.{neon_type[1]}" + arguments: + - "ptr: *const i64" + links: + - link: "llvm.aarch64.neon.ld2r.v{neon_type[1].lane}{type[2]}.p0i64" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].dup_nox}" + - - "a as _" + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [vld2] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8] + - ["*const i16", int16x4x2_t, i16] + - ["*const i32", int32x2x2_t, i32] + - ["*const i8", int8x16x2_t, i8] + - ["*const i16", int16x8x2_t, i16] + - ["*const i32", int32x4x2_t, i32] + - ["*const f32", float32x2x2_t, f32] + - ["*const f32", float32x4x2_t, f32] + compose: + - LLVMLink: + name: "vld2dup.{neon_type[1]}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld2dup.v{neon_type[1].lane}{type[2]}.p0i8" + arch: arm + - FnCall: + - "_vld2{neon_type[1].dup_nox}" + - - "a as *const i8" + - "{neon_type[1].base_byte_size}" + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld2]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x8x2_t, int8x8x2_t] + - ["*const u16", uint16x4x2_t, int16x4x2_t] + - ["*const u32", uint32x2x2_t, int32x2x2_t] + - ["*const u8", uint8x16x2_t, int8x16x2_t] + - ["*const u16", uint16x8x2_t, int16x8x2_t] + - ["*const u32", uint32x4x2_t, int32x4x2_t] + - ["*const p8", poly8x8x2_t, int8x8x2_t] + - ["*const p16", poly16x4x2_t, int16x4x2_t] + - ["*const p8", poly8x16x2_t, int8x16x2_t] + - ["*const p16", poly16x8x2_t, int16x8x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld2r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - transmute + - - FnCall: + - "vld2{neon_type[2].dup_nox}" + - - FnCall: + - transmute + - - a + + - name: "vld2{neon_type[1].dup_nox}" + doc: Load single 2-element structure and replicate to all lanes of two registers + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - FnCall: + - cfg + - - FnCall: + - not + - - 'target_arch = "arm"' + - *neon-stable + assert_instr: [ld2r] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x2_t, i8] + - ["*const i16", int16x4x2_t, i16] + - ["*const i32", int32x2x2_t, i32] + - ["*const i8", int8x16x2_t, i8] + - ["*const i16", int16x8x2_t, i16] + - ["*const i32", int32x4x2_t, i32] + - ["*const f32", float32x2x2_t, f32] + - ["*const f32", float32x4x2_t, f32] + compose: + - LLVMLink: + name: "vld2dup.{neon_type[1]}" + arguments: + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.ld2r.v{neon_type[1].lane}{type[2]}.p0{type[2]}" + arch: aarch64,arm64ec + - FnCall: + - "_vld2{neon_type[1].dup_nox}" + - - "a as _" + + - name: "vld3{neon_type[1].lane_nox}" + doc: "Load multiple 3-element structures to two registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x3_t, int8x8_t, i8, '3'] + - ['*const i16', int16x8x3_t, int16x8_t, i16, '4'] + - ['*const i32', int32x4x3_t, int32x4_t, i32, '2'] + - ['*const i16', int16x4x3_t, int16x4_t, i16, '2'] + - ['*const i32', int32x2x3_t, int32x2_t, i32, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - LLVMLink: + name: 'ld3lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - *target-not-arm + assert_instr: [ld3] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x3_t, '*const int8x8_t', i8] + - ['*const i16', int16x4x3_t, '*const int16x4_t', i16] + - ['*const i32', int32x2x3_t, '*const int32x2_t', i32] + - ['*const i8', int8x16x3_t, '*const int8x16_t', i8] + - ['*const i16', int16x8x3_t, '*const int16x8_t', i16] + - ['*const i32', int32x4x3_t, '*const int32x4_t', i32] + - ['*const f32', float32x2x3_t, '*const float32x2_t', f32] + - ['*const f32', float32x4x3_t, '*const float32x4_t', f32] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].nox}' + arguments: + - 'ptr: {type[2]}' + links: + - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0v{neon_type[1].lane}{type[3]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-stable + - *target-not-arm + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ['*const i64', int64x1x3_t, '*const int64x1_t', i64] + compose: + - LLVMLink: + name: "vld3{neon_type[1].nox}" + arguments: + - 'ptr: {type[2]}' + links: + - link: 'llvm.aarch64.neon.ld3.v{neon_type[1].lane}{type[3]}.p0v{neon_type[1].lane}{type[3]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].nox}', ['a as _']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vld3] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x3_t, i8] + - ['*const i16', int16x4x3_t, i16] + - ['*const i32', int32x2x3_t, i32] + - ['*const i8', int8x16x3_t, i8] + - ['*const i16', int16x8x3_t, i16] + - ['*const i32', int32x4x3_t, i32] + - ['*const f32', float32x2x3_t, f32] + - ['*const f32', float32x4x3_t, f32] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].nox}', ['a as *const i8', '{neon_type[1].base_byte_size}']] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [nop] + types: + - ['*const i64', int64x1x3_t, i64] + safety: + unsafe: [neon] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].nox}', ['a as *const i8', '{neon_type[1].base_byte_size}']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ['*const f32', float32x4x3_t, float32x4_t, f32, '2'] + - ['*const f32', float32x2x3_t, float32x2_t, f32, '1'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[4]}']] + - LLVMLink: + name: 'vld3{neon_type[1].lane_nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vld3{neon_type[2].lane_nox}" + doc: "Load multiple 3-element structures to three registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ['*const f32', float32x2x3_t, float32x2_t, f32, '1', '4'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[4]}']] + - LLVMLink: + name: 'vld3{neon_type[1].lane_nox}' + arguments: + - 'ptr: *const i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', '{type[5]}']] + + - name: "vld3{neon_type[2].lane_nox}" + doc: "Load multiple 3-element structures to two registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x3_t, int8x8_t, i8, '3', '1'] + - ['*const i16', int16x4x3_t, int16x4_t, i16, '2', '2'] + - ['*const i32', int32x2x3_t, int32x2_t, i32, '1', '4'] + - ['*const i16', int16x8x3_t, int16x8_t, i16, '3', '2'] + - ['*const i32', int32x4x3_t, int32x4_t, i32, '2', '4'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[4]}']] + - LLVMLink: + name: 'vld3{neon_type[1].lane_nox}' + arguments: + - 'ptr: *const i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', '{type[5]}']] + + - name: "vld3{neon_type[2].lane_nox}" + doc: "Load multiple 3-element structures to three registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ['*const f32', float32x4x3_t, float32x4_t, f32, '2', '4'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[4]}']] + - LLVMLink: + name: 'vld3{neon_type[1].lane_nox}' + arguments: + - 'ptr: *const i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', '{type[5]}']] + + - name: "vld3{neon_type[1].lane_nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld3, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ['*const u8', uint8x8x3_t, int8x8x3_t, '3'] + - ['*const u16', uint16x4x3_t, int16x4x3_t, '2'] + - ['*const u32', uint32x2x3_t, int32x2x3_t, '1'] + - ['*const p8', poly8x8x3_t, int8x8x3_t, '3'] + - ['*const u16', uint16x8x3_t, int16x8x3_t, '3'] + - ['*const p16', poly16x4x3_t, int16x4x3_t, '2'] + - ['*const p16', poly16x8x3_t, int16x8x3_t, '3'] + - ['*const u32', uint32x4x3_t, int32x4x3_t, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld3]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const u8', uint8x8x3_t, int8x8x3_t] + - ['*const u8', uint8x16x3_t, int8x16x3_t] + - ['*const u16', uint16x4x3_t, int16x4x3_t] + - ['*const u32', uint32x2x3_t, int32x2x3_t] + - ['*const u16', uint16x8x3_t, int16x8x3_t] + - ['*const u32', uint32x4x3_t, int32x4x3_t] + - ['*const p8', poly8x8x3_t, int8x8x3_t] + - ['*const p8', poly8x16x3_t, int8x16x3_t] + - ['*const p16', poly16x4x3_t, int16x4x3_t] + - ['*const p16', poly16x8x3_t, int16x8x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].nox}' + - - FnCall: [transmute, [a]] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const u64', uint64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].nox}' + - - FnCall: [transmute, [a]] + + - name: "vld3{neon_type[1].nox}" + doc: Load multiple 3-element structures to three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*target-not-arm, *neon-stable] + assert_instr: [ld3r] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x3_t, i8] + - ["*const i16", int16x4x3_t, i16] + - ["*const i32", int32x2x3_t, i32] + - ["*const i32", int32x4x3_t, i32] + - ["*const i16", int16x8x3_t, i16] + - ["*const i8", int8x16x3_t, i8] + - ["*const i64", int64x1x3_t, i64] + - ["*const f32", float32x4x3_t, f32] + - ["*const f32", float32x2x3_t, f32] + compose: + - LLVMLink: + name: 'ld3r{neon_type[1].dup_nox}' + arguments: + - 'ptr: {type[0]}' + links: + - link: 'llvm.aarch64.neon.ld3r.v{neon_type[1].lane}{type[2]}.p0{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld3{neon_type[1].dup_nox}', ['a as _']] + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*enable-v7, *target-is-arm, *neon-unstable] + assert_instr: [vld3] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x3_t, i8, '1'] + - ["*const i16", int16x4x3_t, i16, '2'] + - ["*const i32", int32x2x3_t, i32, '4'] + - ["*const i8", int8x16x3_t, i8, '1'] + - ["*const i16", int16x8x3_t, i16, '2'] + - ["*const i32", int32x4x3_t, i32, '4'] + - ["*const f32", float32x4x3_t, f32, '4'] + - ["*const f32", float32x2x3_t, f32, '4'] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].dup_nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3dup.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].dup_nox}', ['a as *const i8', '{type[3]}']] + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld3]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const u8', uint8x8x3_t, int8x8x3_t] + - ['*const u16', uint16x4x3_t, int16x4x3_t] + - ['*const u32', uint32x2x3_t, int32x2x3_t] + - ['*const u8', uint8x16x3_t, int8x16x3_t] + - ['*const u16', uint16x8x3_t, int16x8x3_t] + - ['*const u32', uint32x4x3_t, int32x4x3_t] + - ['*const p8', poly8x8x3_t, int8x8x3_t] + - ['*const p16', poly16x4x3_t, int16x4x3_t] + - ['*const p8', poly8x16x3_t, int8x16x3_t] + - ['*const p16', poly16x8x3_t, int16x8x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].dup_nox}' + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*target-is-arm, *enable-v7, *neon-unstable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x3_t, i64, '8'] + compose: + - LLVMLink: + name: 'vld3{neon_type[1].dup_nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld3dup.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld3{neon_type[1].dup_nox}', ['a as *const i8', '{type[3]}']] + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].dup_nox}' + - - FnCall: + - transmute + - - a + + - name: "vld3{neon_type[1].dup_nox}" + doc: Load single 3-element structure and replicate to all lanes of three registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld3r]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld3{neon_type[2].dup_nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - *neon-stable + assert_instr: [ld4] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x4_t, i8, '*const int8x8_t'] + - ['*const i32', int32x4x4_t, i32, '*const int32x4_t'] + - ['*const i16', int16x4x4_t, i16, '*const int16x4_t'] + - ['*const i32', int32x2x4_t, i32, '*const int32x2_t'] + - ['*const i8', int8x16x4_t, i8, '*const int8x16_t'] + - ['*const i16', int16x8x4_t, i16, '*const int16x8_t'] + - ['*const f32', float32x2x4_t, f32, '*const float32x2_t'] + - ['*const f32', float32x4x4_t, f32, '*const float32x4_t'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: {type[3]}' + links: + - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: [*target-not-arm, *neon-stable] + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ['*const i64', int64x1x4_t, i64, '*const int64x1_t'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: {type[3]}' + links: + - link: 'llvm.aarch64.neon.ld4.v{neon_type[1].lane}{type[2]}.p0v{neon_type[1].lane}{type[2]}' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].nox}', ['a as _']] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable + static_defs: + - "const LANE: i32" + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x4_t, int8x8_t, i8, '3'] + - ['*const i16', int16x4x4_t, int16x4_t, i16, '2'] + - ['*const i16', int16x8x4_t, int16x8_t, i16, '3'] + - ['*const i32', int32x2x4_t, int32x2_t, i32, '1'] + - ['*const i32', int32x4x4_t, int32x4_t, i32, '2'] + - ['*const f32', float32x2x4_t, float32x2_t, f32, '1'] + - ['*const f32', float32x4x4_t, float32x4_t, f32, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[4]}']] + - LLVMLink: + name: 'ld4lane.{neon_type[2]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i64' + - 'ptr: *const i8' + links: + - link: 'llvm.aarch64.neon.ld4lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vld4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [vld4] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x4_t, i8, '1'] + - ['*const i16', int16x4x4_t, i16, '2'] + - ['*const i32', int32x2x4_t, i32, '4'] + - ['*const i8', int8x16x4_t, i8, '1'] + - ['*const i16', int16x8x4_t, i16, '2'] + - ['*const i32', int32x4x4_t, i32, '4'] + - ['*const f32', float32x4x4_t, f32, '4'] + - ['*const f32', float32x2x4_t, f32, '4'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld4.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld4{neon_type[1].nox}', ['a as *const i8', '{type[3]}']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - ['*const i64', int64x1x4_t, i64, '8'] + compose: + - LLVMLink: + name: 'vld4{neon_type[1].nox}' + arguments: + - 'ptr: *const i8' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld4.v{neon_type[1].lane}{type[2]}.p0i8' + arch: arm + - FnCall: ['_vld4{neon_type[1].nox}', ['a as *const i8', '{type[3]}']] + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld4]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const u8', uint8x8x4_t, int8x8x4_t] + - ['*const u16', uint16x4x4_t, int16x4x4_t] + - ['*const u32', uint32x2x4_t, int32x2x4_t] + - ['*const u8', uint8x16x4_t, int8x16x4_t] + - ['*const u16', uint16x8x4_t, int16x8x4_t] + - ['*const u32', uint32x4x4_t, int32x4x4_t] + - ['*const p8', poly8x8x4_t, int8x8x4_t] + - ['*const p16', poly16x4x4_t, int16x4x4_t] + - ['*const p8', poly8x16x4_t, int8x16x4_t] + - ['*const p16', poly16x8x4_t, int16x8x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const u64', uint64x1x4_t, int64x1x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v8 + - FnCall: + - target_feature + - - 'enable = "neon,aes"' + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['*const p64', poly64x1x4_t, int64x1x4_t] + compose: + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].nox}' + - - FnCall: + - transmute + - - a + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *enable-v7 + - *target-is-arm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-unstable + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['*const i8', int8x8x4_t, int8x8_t, i8, '1', '3'] + - ['*const i16', int16x4x4_t, int16x4_t, i16, '2', '2'] + - ['*const i32', int32x2x4_t, int32x2_t, i32, '4', '1'] + - ['*const i16', int16x8x4_t, int16x8_t, i16, '2', '3'] + - ['*const i32', int32x4x4_t, int32x4_t, i32, '4', '2'] + - ['*const f32', float32x2x4_t, float32x2_t, f32, '4', '1'] + - ['*const f32', float32x4x4_t, float32x4_t, f32, '4', '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[5]}']] + - LLVMLink: + name: 'ld4lane.{neon_type[2]}' + arguments: + - 'ptr: *const i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vld4lane.v{neon_type[1].lane}{type[3]}.p0i8' + arch: arm + - FnCall: ['vld4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', LANE, '{type[4]}']] + + - name: "vld4{neon_type[1].lane_nox}" + doc: Load multiple 4-element structures to four registers + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vld4, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ld4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['*const u8', uint8x8x4_t, int8x8x4_t, '3'] + - ['*const u16', uint16x4x4_t, int16x4x4_t, '2'] + - ['*const u32', uint32x2x4_t, int32x2x4_t, '1'] + - ['*const u16', uint16x8x4_t, int16x8x4_t, '3'] + - ['*const u32', uint32x4x4_t, int32x4x4_t, '2'] + - ['*const p8', poly8x8x4_t, int8x8x4_t, '3'] + - ['*const p16', poly16x4x4_t, int16x4x4_t, '2'] + - ['*const p16', poly16x8x4_t, int16x8x4_t, '3'] + compose: + - FnCall: [static_assert_uimm_bits!, ['LANE', '{type[3]}']] + - FnCall: + - transmute + - - FnCall: + - 'vld4{neon_type[2].lane_nox}::' + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + types: + - ['*mut i64', int64x1_t] + - ['*mut u64', uint64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - *neon-v8 + - FnCall: + - target_feature + - - 'enable = "neon,aes"' + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + types: + - ['*mut p64', poly64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - *neon-v8 + - FnCall: + - target_feature + - - 'enable = "neon,aes"' + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + types: + - ['*mut p64', poly64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: "vst1{neon_type[1].lane_nox}" + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ["2"]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + types: + - ['*mut i8', int8x8_t, '3'] + - ['*mut i16', int16x4_t, '2'] + - ['*mut i32', int32x2_t, '1'] + - ['*mut i8', int8x16_t, '4'] + - ['*mut i16', int16x8_t, '3'] + - ['*mut i32', int32x4_t, '2'] + - ['*mut i64', int64x2_t, '1'] + - ['*mut u8', uint8x8_t, '3'] + - ['*mut u16', uint16x4_t, '2'] + - ['*mut u32', uint32x2_t, '1'] + - ['*mut u8', uint8x16_t, '4'] + - ['*mut u16', uint16x8_t, '3'] + - ['*mut u32', uint32x4_t, '2'] + - ['*mut u64', uint64x2_t, '1'] + - ['*mut p8', poly8x8_t, '3'] + - ['*mut p16', poly16x4_t, '2'] + - ['*mut p8', poly8x16_t, '4'] + - ['*mut p16', poly16x8_t, '3'] + - ['*mut f32', float32x2_t, '1'] + - ['*mut f32', float32x4_t, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - Assign: + - "*a" + - FnCall: [simd_extract!, [b, 'LANE as u32']] + - Identifier: [';', Symbol] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [st1] + types: + - [i8, int8x8x2_t, int8x8_t] + - [i16, int16x4x2_t, int16x4_t] + - [i32, int32x2x2_t, int32x2_t] + - [i64, int64x1x2_t, int64x1_t] + - [i8, int8x16x2_t, int8x16_t] + - [i16, int16x8x2_t, int16x8_t] + - [i32, int32x4x2_t, int32x4_t] + - [i64, int64x2x2_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'ptr: *mut {type[0]}' + links: + - link: 'llvm.aarch64.neon.st1x2.v{neon_type[1].lane}{type[0]}.p0{type[0]}' + arch: aarch64,arm64ec + - FnCall: ['_vst1{neon_type[1].no}', ['b.0', 'b.1', 'a']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [st1] + types: + - [i8, int8x8x3_t, int8x8_t] + - [i16, int16x4x3_t, int16x4_t] + - [i32, int32x2x3_t, int32x2_t] + - [i64, int64x1x3_t, int64x1_t] + - [i8, int8x16x3_t, int8x16_t] + - [i16, int16x8x3_t, int16x8_t] + - [i32, int32x4x3_t, int32x4_t] + - [i64, int64x2x3_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x3.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'ptr: *mut {type[0]}' + links: + - link: 'llvm.aarch64.neon.st1x3.v{neon_type[1].lane}{type[0]}.p0{type[0]}' + arch: aarch64,arm64ec + - FnCall: ['_vst1{neon_type[1].no}', ['b.0', 'b.1', 'b.2', 'a']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [st1] + types: + - [i8, int8x8x4_t, int8x8_t] + - [i16, int16x4x4_t, int16x4_t] + - [i32, int32x2x4_t, int32x2_t] + - [i64, int64x1x4_t, int64x1_t] + - [i8, int8x16x4_t, int8x16_t] + - [i16, int16x8x4_t, int16x8_t] + - [i32, int32x4x4_t, int32x4_t] + - [i64, int64x2x4_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x4.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'ptr: *mut {type[0]}' + links: + - link: 'llvm.aarch64.neon.st1x4.v{neon_type[1].lane}{type[0]}.p0{type[0]}' + arch: aarch64,arm64ec + - FnCall: ['_vst1{neon_type[1].no}', ['b.0', 'b.1', 'b.2', 'b.3', 'a']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [vst1] + types: + - [i8, int8x8x2_t, int8x8_t] + - [i16, int16x4x2_t, int16x4_t] + - [i32, int32x2x2_t, int32x2_t] + - [i64, int64x1x2_t, int64x1_t] + - [i8, int8x16x2_t, int8x16_t] + - [i16, int16x8x2_t, int16x8_t] + - [i32, int32x4x2_t, int32x4_t] + - [i64, int64x2x2_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x2.{neon_type[1]}' + arguments: + - 'ptr: *mut {type[0]}' + - 'a: {type[2]}' + - 'b: {type[2]}' + links: + - link: 'llvm.arm.neon.vst1x2.p0{type[0]}.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst1{neon_type[1].no}', ['a', 'b.0', 'b.1']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *enable-v7 + - *target-is-arm + - *neon-unstable + assert_instr: [vst1] + types: + - [i8, int8x8x3_t, int8x8_t] + - [i16, int16x4x3_t, int16x4_t] + - [i32, int32x2x3_t, int32x2_t] + - [i64, int64x1x3_t, int64x1_t] + - [i8, int8x16x3_t, int8x16_t] + - [i16, int16x8x3_t, int16x8_t] + - [i32, int32x4x3_t, int32x4_t] + - [i64, int64x2x3_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x3.{neon_type[1]}' + arguments: + - 'ptr: *mut {type[0]}' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + links: + - link: 'llvm.arm.neon.vst1x3.p0{type[0]}.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst1{neon_type[1].no}', ['a', 'b.0', 'b.1', 'b.2']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures from one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vst1] + types: + - [i8, int8x8x4_t, int8x8_t] + - [i16, int16x4x4_t, int16x4_t] + - [i32, int32x2x4_t, int32x2_t] + - [i64, int64x1x4_t, int64x1_t] + - [i8, int8x16x4_t, int8x16_t] + - [i16, int16x8x4_t, int16x8_t] + - [i32, int32x4x4_t, int32x4_t] + - [i64, int64x2x4_t, int64x2_t] + compose: + - LLVMLink: + name: 'st1x4.{neon_type[1]}' + arguments: + - 'ptr: *mut {type[0]}' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + links: + - link: 'llvm.arm.neon.vst1x4.p0{type[0]}.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst1{neon_type[1].no}', ['a', 'b.0', 'b.1', 'b.2', 'b.3']] + + - name: 'vst1{neon_type[1].no}' + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + safety: + unsafe: [neon] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vst1] + types: + - [f32, float32x2x4_t, float32x2_t] + - [f32, float32x4x4_t, float32x4_t] + compose: + - LLVMLink: + name: 'st1x4.{neon_type[1]}' + arguments: + - 'ptr: *mut {type[0]}' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + links: + - link: 'llvm.arm.neon.vst1x4.p0{type[0]}.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst1{neon_type[1].no}', ['a', 'b.0', 'b.1', 'b.2', 'b.3']] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v8 + - *neon-aes + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [p64, poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - "vst2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x2_t, int64x1_t] + compose: + - LLVMLink: + name: 'vst2.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst2.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', '8']] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u64, uint64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - "vst2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x2_t, int64x1_t] + compose: + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [st2] + safety: + unsafe: [neon] + types: + - [i8, int8x8x2_t, int8x8_t] + - [i16, int16x4x2_t, int16x4_t] + - [i32, int32x2x2_t, int32x2_t] + - [i8, int8x16x2_t, int8x16_t] + - [i16, int16x8x2_t, int16x8_t] + - [i32, int32x4x2_t, int32x4_t] + - [f32, float32x2x2_t, float32x2_t] + - [f32, float32x4x2_t, float32x4_t] + compose: + - LLVMLink: + name: 'st2.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].nox}', ['b.0', 'b.1', 'a as _']] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst2]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st2]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u8, uint8x8x2_t, int8x8x2_t] + - [u16, uint16x4x2_t, int16x4x2_t] + - [u32, uint32x2x2_t, int32x2x2_t] + - [u8, uint8x16x2_t, int8x16x2_t] + - [u16, uint16x8x2_t, int16x8x2_t] + - [u32, uint32x4x2_t, int32x4x2_t] + - [p8, poly8x8x2_t, int8x8x2_t] + - [p16, poly16x4x2_t, int16x4x2_t] + - [p8, poly8x16x2_t, int8x16x2_t] + - [p16, poly16x8x2_t, int16x8x2_t] + compose: + - FnCall: + - "vst2{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x2_t, '3', int8x8_t] + - [i16, int16x4x2_t, '2', int16x4_t] + - [i32, int32x2x2_t, '1', int32x2_t] + - [i16, int16x8x2_t, '3', int16x8_t] + - [i32, int32x4x2_t, '2', int32x4_t] + - [f32, float32x2x2_t, '1', float32x2_t] + - [f32, float32x4x2_t, '2', float32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst2.{neon_type[1].lane_nox}' + arguments: + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st2lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst2{neon_type[1].lane_nox}', ['b.0', 'b.1', 'LANE as i64', 'a as _']] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst2, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [u8, uint8x8x2_t, int8x8x2_t, '3'] + - [u16, uint16x4x2_t, int16x4x2_t, '2'] + - [u32, uint32x2x2_t, int32x2x2_t, '1'] + - [u16, uint16x8x2_t, int16x8x2_t, '3'] + - [u32, uint32x4x2_t, int32x4x2_t, '2'] + - [p8, poly8x8x2_t, int8x8x2_t, '3'] + - [p16, poly16x4x2_t, int16x4x2_t, '2'] + - [p16, poly16x8x2_t, int16x8x2_t, '3'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vst2{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst2{neon_type[1].nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vst2] + safety: + unsafe: [neon] + types: + - [i8, int8x8x2_t, int8x8_t, '1'] + - [i16, int16x4x2_t, int16x4_t, '2'] + - [i32, int32x2x2_t, int32x2_t, '4'] + - [i8, int8x16x2_t, int8x16_t, '1'] + - [i16, int16x8x2_t, int16x8_t, '2'] + - [i32, int32x4x2_t, int32x4_t, '4'] + - [f32, float32x2x2_t, float32x2_t, '4'] + - [f32, float32x4x2_t, float32x4_t, '4'] + compose: + - LLVMLink: + name: 'vst2.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst2.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', "{type[3]}"]] + + - name: "vst2{neon_type[1].lane_nox}" + doc: "Store multiple 2-element structures from two registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst2, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x2_t, '3', int8x8_t, '1'] + - [i16, int16x4x2_t, '2', int16x4_t, '2'] + - [i32, int32x2x2_t, '1', int32x2_t, '4'] + - [i16, int16x8x2_t, '3', int16x8_t, '2'] + - [i32, int32x4x2_t, '2', int32x4_t, '4'] + - [f32, float32x4x2_t, '2', float32x4_t, '4'] + - [f32, float32x2x2_t, '1', float32x2_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst2lane.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst2lane.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'LANE', "{type[4]}"]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x3_t, int64x1_t] + compose: + - LLVMLink: + name: 'st3.{neon_type[1].nox}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v8 + - *neon-aes + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [p64, poly64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - "vst3{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x3_t, int64x1_t] + compose: + - LLVMLink: + name: 'vst3.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst3.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', '8']] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u64, uint64x1x3_t, int64x1x3_t] + compose: + - FnCall: + - "vst3{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst3, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [u8, uint8x8x3_t, int8x8x3_t, '3'] + - [u16, uint16x4x3_t, int16x4x3_t, '2'] + - [u32, uint32x2x3_t, int32x2x3_t, '1'] + - [u16, uint16x8x3_t, int16x8x3_t, '3'] + - [u32, uint32x4x3_t, int32x4x3_t, '2'] + - [p8, poly8x8x3_t, int8x8x3_t, '3'] + - [p16, poly16x4x3_t, int16x4x3_t, '2'] + - [p16, poly16x8x3_t, int16x8x3_t, '3'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vst3{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst3]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st3]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u8, uint8x8x3_t, int8x8x3_t] + - [u16, uint16x4x3_t, int16x4x3_t] + - [u32, uint32x2x3_t, int32x2x3_t] + - [u8, uint8x16x3_t, int8x16x3_t] + - [u16, uint16x8x3_t, int16x8x3_t] + - [u32, uint32x4x3_t, int32x4x3_t] + - [p8, poly8x8x3_t, int8x8x3_t] + - [p16, poly16x4x3_t, int16x4x3_t] + - [p8, poly8x16x3_t, int8x16x3_t] + - [p16, poly16x8x3_t, int16x8x3_t] + compose: + - FnCall: + - "vst3{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vst3] + safety: + unsafe: [neon] + types: + - [i8, int8x8x3_t, int8x8_t, '1'] + - [i16, int16x4x3_t, int16x4_t, '2'] + - [i32, int32x2x3_t, int32x2_t, '4'] + - [i8, int8x16x3_t, int8x16_t, '1'] + - [i16, int16x8x3_t, int16x8_t, '2'] + - [i32, int32x4x3_t, int32x4_t, '4'] + - [f32, float32x2x3_t, float32x2_t, '4'] + - [f32, float32x4x3_t, float32x4_t, '4'] + compose: + - LLVMLink: + name: 'vst3.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst3.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', "{type[3]}"]] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst3, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x3_t, '3', int8x8_t, '1'] + - [i16, int16x4x3_t, '2', int16x4_t, '2'] + - [i32, int32x2x3_t, '1', int32x2_t, '4'] + - [i16, int16x8x3_t, '3', int16x8_t, '2'] + - [i32, int32x4x3_t, '2', int32x4_t, '4'] + - [f32, float32x2x3_t, '1', float32x2_t, '4'] + - [f32, float32x4x3_t, '2', float32x4_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst3lane.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'c: {type[3]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst3lane.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', "{type[4]}"]] + + - name: "vst3{neon_type[1].nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*target-not-arm, *neon-stable] + assert_instr: [st3] + safety: + unsafe: [neon] + types: + - [i8, int8x8x3_t, int8x8_t] + - [i16, int16x4x3_t, int16x4_t] + - [i32, int32x2x3_t, int32x2_t] + - [i8, int8x16x3_t, int8x16_t] + - [i16, int16x8x3_t, int16x8_t] + - [i32, int32x4x3_t, int32x4_t] + - [f32, float32x2x3_t, float32x2_t] + - [f32, float32x4x3_t, float32x4_t] + compose: + - LLVMLink: + name: 'vst3.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'a as _']] + + - name: "vst3{neon_type[1].lane_nox}" + doc: "Store multiple 3-element structures from three registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st3, 'LANE = 0']]}]] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x3_t, '3', int8x8_t] + - [i16, int16x4x3_t, '2', int16x4_t] + - [i32, int32x2x3_t, '1', int32x2_t] + - [i16, int16x8x3_t, '3', int16x8_t] + - [i32, int32x4x3_t, '2', int32x4_t] + - [f32, float32x2x3_t, '1', float32x2_t] + - [f32, float32x4x3_t, '2', float32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst3.{neon_type[1].lane_nox}' + arguments: + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'c: {type[3]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st3lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst3{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'LANE as i64', 'a as _']] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v8 + - *neon-aes + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [p64, poly64x1x4_t, int64x1x4_t] + compose: + - FnCall: + - "vst4{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x4_t, int64x1_t] + compose: + - LLVMLink: + name: 'vst4.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst4.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', '8']] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - *neon-stable + assert_instr: [nop] + safety: + unsafe: [neon] + types: + - [i64, int64x1x4_t, int64x1_t] + compose: + - LLVMLink: + name: 'vst4.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4.{neon_type[2]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u64, uint64x1x4_t, int64x1x3_t] + compose: + - FnCall: + - "vst4{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst4, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [u8, uint8x8x4_t, int8x8x4_t, '3'] + - [u16, uint16x4x4_t, int16x4x4_t, '2'] + - [u32, uint32x2x4_t, int32x2x4_t, '1'] + - [u16, uint16x8x4_t, int16x8x4_t, '3'] + - [u32, uint32x4x4_t, int32x4x4_t, '2'] + - [p8, poly8x8x4_t, int8x8x4_t, '3'] + - [p16, poly16x4x4_t, int16x4x4_t, '2'] + - [p16, poly16x8x4_t, int16x8x4_t, '3'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vst4{neon_type[2].lane_nox}::" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vst4]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [st4]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [u8, uint8x8x4_t, int8x8x4_t] + - [u16, uint16x4x4_t, int16x4x4_t] + - [u32, uint32x2x4_t, int32x2x4_t] + - [u8, uint8x16x4_t, int8x16x4_t] + - [u16, uint16x8x4_t, int16x8x4_t] + - [u32, uint32x4x4_t, int32x4x4_t] + - [p8, poly8x8x4_t, int8x8x4_t] + - [p16, poly16x4x4_t, int16x4x4_t] + - [p8, poly8x16x4_t, int8x16x4_t] + - [p16, poly16x8x4_t, int16x8x4_t] + compose: + - FnCall: + - "vst4{neon_type[2].nox}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - *neon-unstable + assert_instr: [vst4] + safety: + unsafe: [neon] + types: + - [i8, int8x8x4_t, int8x8_t, '1'] + - [i16, int16x4x4_t, int16x4_t, '2'] + - [i32, int32x2x4_t, int32x2_t, '4'] + - [i8, int8x16x4_t, int8x16_t, '1'] + - [i16, int16x8x4_t, int16x8_t, '2'] + - [i32, int32x4x4_t, int32x4_t, '4'] + - [f32, float32x2x4_t, float32x2_t, '4'] + - [f32, float32x4x4_t, float32x4_t, '4'] + compose: + - LLVMLink: + name: 'vst4.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst4.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', "{type[3]}"]] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst4, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-unstable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x4_t, '3', int8x8_t, '1'] + - [i16, int16x4x4_t, '2', int16x4_t, '2'] + - [i32, int32x2x4_t, '1', int32x2_t, '4'] + - [i16, int16x8x4_t, '3', int16x8_t, '2'] + - [i32, int32x4x4_t, '2', int32x4_t, '4'] + - [f32, float32x2x4_t, '1', float32x2_t, '4'] + - [f32, float32x4x4_t, '2', float32x4_t, '4'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst4lane.{neon_type[1]}' + arguments: + - 'ptr: *mut i8' + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'c: {type[3]}' + - 'd: {type[3]}' + - 'n: i32' + - 'size: i32' + links: + - link: 'llvm.arm.neon.vst4lane.p0i8.v{neon_type[1].lane}{type[0]}' + arch: arm + - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', 'LANE', "{type[4]}"]] + + - name: "vst4{neon_type[1].nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: [*target-not-arm, *neon-stable] + assert_instr: [st4] + safety: + unsafe: [neon] + types: + - [i8, int8x8x4_t, int8x8_t] + - [i16, int16x4x4_t, int16x4_t] + - [i32, int32x2x4_t, int32x2_t] + - [i8, int8x16x4_t, int8x16_t] + - [i16, int16x8x4_t, int16x8_t] + - [i32, int32x4x4_t, int32x4_t] + - [f32, float32x2x4_t, float32x2_t] + - [f32, float32x4x4_t, float32x4_t] + compose: + - LLVMLink: + name: 'vst4.{neon_type[1]}' + arguments: + - 'a: {type[2]}' + - 'b: {type[2]}' + - 'c: {type[2]}' + - 'd: {type[2]}' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'a as _']] + + - name: "vst4{neon_type[1].lane_nox}" + doc: "Store multiple 4-element structures from four registers" + arguments: ["a: *mut {type[0]}", "b: {neon_type[1]}"] + attr: + - *target-not-arm + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st4, 'LANE = 0']]}]] + - *neon-stable + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [i8, int8x8x4_t, '3', int8x8_t] + - [i16, int16x4x4_t, '2', int16x4_t] + - [i32, int32x2x4_t, '1', int32x2_t] + - [i16, int16x8x4_t, '3', int16x8_t] + - [i32, int32x4x4_t, '2', int32x4_t] + - [f32, float32x2x4_t, '1', float32x2_t] + - [f32, float32x4x4_t, '2', float32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - LLVMLink: + name: 'vst4.{neon_type[1].lane_nox}' + arguments: + - 'a: {type[3]}' + - 'b: {type[3]}' + - 'c: {type[3]}' + - 'd: {type[3]}' + - 'n: i64' + - 'ptr: *mut i8' + links: + - link: 'llvm.aarch64.neon.st4lane.v{neon_type[1].lane}{type[0]}.p0i8' + arch: aarch64,arm64ec + - FnCall: ['_vst4{neon_type[1].lane_nox}', ['b.0', 'b.1', 'b.2', 'b.3', 'LANE as i64', 'a as _']] + + - name: "vusdot{neon_type[0].no}" + doc: "Dot product vector form with unsigned and signed integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-i8mm + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot]]}]] + - *neon-unstable-i8mm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int32x2_t, uint8x8_t, int8x8_t] + - [int32x4_t, uint8x16_t, int8x16_t] + compose: + - LLVMLink: + name: "usdot.{neon_type[0]}" + links: + - link: "llvm.aarch64.neon.usdot.v{neon_type[0].lane}i32.v{neon_type[1].lane}i8" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.usdot.v{neon_type[0].lane}i32.v{neon_type[1].lane}i8" + arch: arm + + - name: "vusdot{type[0]}" + doc: "Dot product index form with unsigned and signed integers" + arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}", "c: int8x8_t"] + return_type: "{neon_type[1]}" + attr: + - *neon-i8mm + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vusdot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usdot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-i8mm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - ['_lane_s32', int32x2_t, uint8x8_t, '[LANE as u32, LANE as u32]'] + - ['q_lane_s32', int32x4_t, uint8x16_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Let: + - c + - int32x2_t + - FnCall: [transmute, [c]] + - Let: + - c + - "{type[1]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ["vusdot{neon_type[1].no}", [a, b, {FnCall: [transmute, [c]]}]] + + - name: "vsudot{neon_type[0].lane_nox}" + doc: "Dot product index form with signed and unsigned integers" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-i8mm + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sudot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - *neon-unstable-i8mm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [int32x2_t, int8x8_t, uint8x8_t, '[LANE as u32, LANE as u32]', uint32x2_t] + - [int32x4_t, int8x16_t, uint8x8_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]', uint32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Let: + - c + - uint32x2_t + - FnCall: [transmute, [c]] + - Let: + - c + - "{type[4]}" + - FnCall: [simd_shuffle!, [c, c, "{type[3]}"]] + - FnCall: ["vusdot{neon_type[0].no}", [a, {FnCall: [transmute, [c]]}, b]] + + - name: "vmul{neon_type[1].no}" + doc: Multiply + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmul{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [mul]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['.i8', int8x8_t] + - ['.i8', int8x16_t] + - ['.i16', int16x4_t] + - ['.i16', int16x8_t] + - ['.i32', int32x2_t] + - ['.i32', int32x4_t] + - ['.i8', uint8x8_t] + - ['.i8', uint8x16_t] + - ['.i16', uint16x4_t] + - ['.i16', uint16x8_t] + - ['.i32', uint32x2_t] + - ['.i32', uint32x4_t] + compose: + - FnCall: [simd_mul, [a, b]] + + - name: "vmul{neon_type[1].no}" + doc: Multiply + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmul.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmul]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [f32, float32x2_t] + - [f32, float32x4_t] + compose: + - FnCall: [simd_mul, [a, b]] + + - name: "vmul{neon_type[0].lane_nox}" + doc: Multiply + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmul, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [mul, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] + - FnCall: + - simd_mul + - - a + - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + + - name: "vmul{neon_type[0].laneq_nox}" + doc: Multiply + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmul, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [mul, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - *neon-stable-not-arm + - *neon-unstable-is-arm + static_defs: ["const LANE: i32"] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: ["static_assert_uimm_bits!", [LANE, "{type[2]}"]] + - FnCall: + - simd_mul + - - a + - FnCall: ["simd_shuffle!", [b, b, "{type[3]}"]] + + - name: "vmull{neon_type[1].no}" + doc: Signed multiply long + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmull.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smull]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["s8", int8x8_t, int16x8_t] + - ["s16", int16x4_t, int32x4_t] + - ["s32", int32x2_t, int64x2_t] + compose: + - LLVMLink: + name: "smull.{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.smull.{neon_type[1]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vmulls.{neon_type[1]}" + arch: arm + + - name: "vmull{neon_type[1].no}" + doc: "Unsigned multiply long" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmull.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umull]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["u8", uint8x8_t, uint16x8_t] + - ["u16", uint16x4_t, uint32x4_t] + - ["u32", uint32x2_t, uint64x2_t] + compose: + - LLVMLink: + name: "smull.{neon_type[1]}" + links: + - link: "llvm.aarch64.neon.umull.{neon_type[1]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vmullu.{neon_type[1]}" + arch: arm + + - name: "vmull{neon_type[1].no}" + doc: "Polynomial multiply long" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vmull.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [pmull]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ["p8", poly8x8_t, poly16x8_t, int8x8_t] + compose: + - LLVMLink: + name: "pmull.{neon_type[1].no}" + links: + - link: "llvm.aarch64.neon.pmull.{neon_type[3]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vmullp.{neon_type[3]}" + arch: arm + + - name: "vmull_n{neon_type[0].no}" + doc: Vector long multiply with scalar + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vmull"]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smull]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", int32x4_t] + - [int32x2_t, "i32", int64x2_t] + compose: + - FnCall: + - "vmull{neon_type[0].no}" + - - a + - FnCall: + - "vdup_n{neon_type[0].no}" + - - b + + - name: "vmull_n{neon_type[0].no}" + doc: Vector long multiply with scalar + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vmull"]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umull]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint16x4_t, "u16", uint32x4_t] + - [uint32x2_t, "u32", uint64x2_t] + compose: + - FnCall: + - "vmull{neon_type[0].no}" + - - a + - FnCall: + - "vdup_n{neon_type[0].no}" + - - b + + - name: "vfma{neon_type.no}" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "vfp4"']]}]] + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - vfma + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - fmla + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "fma.{neon_type}" + links: + - link: "llvm.fma.{neon_type}" + arch: aarch64 + - link: "llvm.fma.{neon_type}" + arch: arm + - FnCall: ["_vfma{neon_type.no}", [b, c, a]] + + - name: "vfma{neon_type[0].N}" + doc: Floating-point fused Multiply-Add to accumulator(vector) + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "vfp4"']]}]] + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - vfma + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - fmla + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - [float32x2_t, f32] + - [float32x4_t, f32] + compose: + - FnCall: + - "vfma{neon_type[0].no}" + - - a + - b + - FnCall: + - "vdup{neon_type[0].N}_vfp4" + - - c + + - name: "vsub{neon_type[1].no}" + doc: "Subtract" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vsub{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['.i8', int8x8_t] + - ['.i8', int8x16_t] + - ['.i16', int16x4_t] + - ['.i16', int16x8_t] + - ['.i32', int32x2_t] + - ['.i32', int32x4_t] + - ['.i8', uint8x8_t] + - ['.i8', uint8x16_t] + - ['.i16', uint16x4_t] + - ['.i16', uint16x8_t] + - ['.i32', uint32x2_t] + - ['.i32', uint32x4_t] + - ['.i64', int64x1_t] + - ['.i64', int64x2_t] + - ['.i64', uint64x1_t] + - ['.i64', uint64x2_t] + compose: + - FnCall: [simd_sub, [a, b]] + + - name: "vsub{neon_type[1].no}" + doc: "Subtract" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vsub.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fsub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['f32', float32x2_t] + - ['f32', float32x4_t] + compose: + - FnCall: [simd_sub, [a, b]] + + - name: "vadd{neon_type.no}" + doc: Bitwise exclusive OR + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - target_feature + - - 'enable = "v7"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - nop + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - nop + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - poly8x8_t + - poly16x4_t + - poly8x16_t + - poly16x8_t + - poly64x1_t + - poly64x2_t + compose: + - FnCall: + - simd_xor + - - a + - b + + - name: "vaddq_{type}" + doc: Bitwise exclusive OR + arguments: ["a: {type}", "b: {type}"] + return_type: "{type}" + attr: + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - target_feature + - - 'enable = "v7"' + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - 'target_arch = "arm"' + - FnCall: + - assert_instr + - - nop + - FnCall: + - cfg_attr + - - FnCall: + - all + - - test + - FnCall: + - any + - - 'target_arch = "aarch64"' + - 'target_arch = "arm64ec"' + - FnCall: + - assert_instr + - - nop + - FnCall: + - cfg_attr + - - FnCall: + - not + - - 'target_arch = "arm"' + - FnCall: + - stable + - - 'feature = "neon_intrinsics"' + - 'since = "1.59.0"' + - FnCall: + - cfg_attr + - - 'target_arch = "arm"' + - FnCall: + - unstable + - - 'feature = "stdarch_arm_neon_intrinsics"' + - 'issue = "111800"' + safety: + unsafe: [neon] + types: + - p128 + compose: + - Xor: + - a + - b + + - name: "vsubhn{neon_type[0].noq}" + doc: Subtract returning high narrow + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'i16x8', 'i16x8::new(8, 8, 8, 8, 8, 8, 8, 8)'] + - [int32x4_t, int16x4_t, 'i32x4', 'i32x4::new(16, 16, 16, 16)'] + - [int64x2_t, int32x2_t, 'i64x2', 'i64x2::new(32, 32)'] + - [uint16x8_t, uint8x8_t, 'u16x8', 'u16x8::new(8, 8, 8, 8, 8, 8, 8, 8)'] + - [uint32x4_t, uint16x4_t, 'u32x4', 'u32x4::new(16, 16, 16, 16)'] + - [uint64x2_t, uint32x2_t, 'u64x2', 'u64x2::new(32, 32)'] + compose: + - Let: [c, "{type[2]}", "{type[3]}"] + - FnCall: + - simd_cast + - - FnCall: + - simd_shr + - - FnCall: [simd_sub, [a, b]] + - FnCall: [transmute, [c]] + + - name: "vsubhn_high{neon_type[1].noq}" + doc: Subtract returning high narrow + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ["vsubhn"]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [subhn2]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, int8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [int16x4_t, int32x4_t, int16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [int32x2_t, int64x2_t, int32x4_t, '[0, 1, 2, 3]'] + - [uint8x8_t, uint16x8_t, uint8x16_t, '[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]'] + - [uint16x4_t, uint32x4_t, uint16x8_t, '[0, 1, 2, 3, 4, 5, 6, 7]'] + - [uint32x2_t, uint64x2_t, uint32x4_t, '[0, 1, 2, 3]'] + compose: + - Let: + - d + - "{neon_type[0]}" + - FnCall: ["vsubhn{neon_type[1].noq}", [b, c]] + - FnCall: [simd_shuffle!, [a, d, "{type[3]}"]] + + - name: "vhsub{neon_type[1].no}" + doc: "Signed halving subtract" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vhsub.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uhsub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['u8', uint8x8_t] + - ['u8', uint8x16_t] + - ['u16', uint16x4_t] + - ['u16', uint16x8_t] + - ['u32', uint32x2_t] + - ['u32', uint32x4_t] + compose: + - LLVMLink: + name: "uhsub.{neon_type[1].no}" + links: + - link: "llvm.aarch64.neon.uhsub.{neon_type[1]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vhsubu.{neon_type[1]}" + arch: arm + + - name: "vhsub{neon_type[1].no}" + doc: "Signed halving subtract" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vhsub.{type[0]}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [shsub]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - ['s8', int8x8_t] + - ['s8', int8x16_t] + - ['s16', int16x4_t] + - ['s16', int16x8_t] + - ['s32', int32x2_t] + - ['s32', int32x4_t] + compose: + - LLVMLink: + name: "shsub.{neon_type[1].no}" + links: + - link: "llvm.aarch64.neon.shsub.{neon_type[1]}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vhsubs.{neon_type[1]}" + arch: arm + + - name: "vsubw{neon_type[1].noq}" + doc: Signed Subtract Wide + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsubw]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ssubw]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t] + - [int32x4_t, int16x4_t] + - [int64x2_t, int32x2_t] + compose: + - FnCall: + - simd_sub + - - a + - FnCall: [simd_cast, [b]] + + - name: "vsubw{neon_type[1].noq}" + doc: Unsigned Subtract Wide + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsubw]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usubw]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t] + - [uint32x4_t, uint16x4_t] + - [uint64x2_t, uint32x2_t] + compose: + - FnCall: + - simd_sub + - - a + - FnCall: [simd_cast, [b]] + + - name: "vsubl{neon_type[0].noq}" + doc: "Signed Subtract Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsubl]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [ssubl]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t] + - [int16x4_t, int32x4_t] + - [int32x2_t, int64x2_t] + compose: + - Let: + - c + - "{neon_type[1]}" + - FnCall: [simd_cast, [a]] + - Let: + - d + - "{neon_type[1]}" + - FnCall: [simd_cast, [b]] + - FnCall: [simd_sub, [c, d]] + + - name: "vsubl{neon_type[0].noq}" + doc: "Unsigned Subtract Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsubl]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [usubl]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint16x8_t] + - [uint16x4_t, uint32x4_t] + - [uint32x2_t, uint64x2_t] + compose: + - Let: + - c + - "{neon_type[1]}" + - FnCall: [simd_cast, [a]] + - Let: + - d + - "{neon_type[1]}" + - FnCall: [simd_cast, [b]] + - FnCall: [simd_sub, [c, d]] + + - name: "vdot{neon_type[0].no}" + doc: Dot product arithmetic (vector) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int32x2_t, int8x8_t] + - [int32x4_t, int8x16_t] + compose: + - LLVMLink: + name: "sdot.{neon_type[0]}.{neon_type[1]}" + links: + - link: "llvm.arm.neon.sdot.{neon_type[0]}.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.sdot.{neon_type[0]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vdot{neon_type[0].no}" + doc: Dot product arithmetic (vector) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint32x2_t, uint8x8_t] + - [uint32x4_t, uint8x16_t] + compose: + - LLVMLink: + name: "udot.{neon_type[0]}.{neon_type[1]}" + links: + - link: "llvm.arm.neon.udot.{neon_type[0]}.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.udot.{neon_type[0]}.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vdot{neon_type[0].lane_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vsdot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sdot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int32x2_t, int8x8_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32]'] + - [int32x4_t, int8x16_t, int8x8_t, int32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + + - name: "vdot{neon_type[0].lane_nox}" + doc: Dot product arithmetic (indexed) + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[0]}" + static_defs: ["const LANE: i32"] + attr: + - *neon-v8 + - FnCall: [target_feature, ['enable = "neon,dotprod"']] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vudot, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [udot, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [unstable, ['feature = "stdarch_neon_dotprod"', 'issue = "117224"']]}]] + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint32x2_t, uint8x8_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32]'] + - [uint32x4_t, uint8x16_t, uint8x8_t, uint32x2_t, '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - Let: + - c + - "{neon_type[3]}" + - FnCall: [transmute, [c]] + - Let: + - c + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [c, c, '{type[4]}']] + - FnCall: + - "vdot{neon_type[0].no}" + - - a + - b + - FnCall: [transmute, [c]] + + - name: "vmax{neon_type.no}" + doc: Maximum (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmax]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smax]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "smax.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxs.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.smax.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmax{neon_type.no}" + doc: Maximum (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmax]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umax]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "smax.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxu.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.umax.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmax{neon_type.no}" + doc: Maximum (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmax]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmax]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "smax.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxs.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmax.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmaxnm{neon_type.no}" + doc: Floating-point Maximum Number (vector) + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [target_feature, ['enable = "fp-armv8,v8"']]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmaxnm]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmaxnm]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "fmaxnm.{neon_type}" + links: + - link: "llvm.arm.neon.vmaxnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmaxnm.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmin{neon_type.no}" + doc: "Minimum (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmin]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [smin]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "smin.{neon_type}" + links: + - link: "llvm.arm.neon.vmins.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.smin.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmin{neon_type.no}" + doc: "Minimum (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmin]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [umin]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "umin.{neon_type}" + links: + - link: "llvm.arm.neon.vminu.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.umin.{neon_type}" + arch: aarch64,arm64ec + + - name: "vmin{neon_type.no}" + doc: "Minimum (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vmin]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fmin]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "fmin.{neon_type}" + links: + - link: "llvm.arm.neon.vmins.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fmin.{neon_type}" + arch: aarch64,arm64ec + + - name: "vminnm{neon_type.no}" + doc: "Floating-point Minimum Number (vector)" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [target_feature, ['enable = "fp-armv8,v8"']]}]] + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vminnm]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [fminnm]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "fminnm.{neon_type}" + links: + - link: "llvm.arm.neon.vminnm.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.fminnm.{neon_type}" + arch: aarch64,arm64ec + + - name: "vpadd{neon_type.no}" + doc: Floating-point add pairwise + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vpadd]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [faddp]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - float32x2_t + compose: + - LLVMLink: + name: "faddp.{neon_type}" + links: + - link: "llvm.arm.neon.vpadd.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.faddp.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqdmull{neon_type[0].noq}" + doc: "Signed saturating doubling multiply long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmull]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, int32x4_t] + - [int32x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vqdmull{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vqdmull.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.sqdmull.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqdmull_n{neon_type[0].no}" + doc: "Vector saturating doubling long multiply with scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmull]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", int32x4_t] + - [int32x2_t, "i32", int64x2_t] + compose: + - FnCall: ["vqdmull{neon_type[0].noq}", [a, {FnCall: ["vdup_n{neon_type[0].noq}", [b]]}]] + + - name: "vqdmull_lane_s16" + doc: "Vector saturating doubling long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmull, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, int32x4_t, '[N as u32, N as u32, N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - FnCall: [vqdmull_s16, [a, b]] + + - name: "vqdmull_lane_s32" + doc: "Vector saturating doubling long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmull, 'N = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmull, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, int32x2_t, int64x2_t, '[N as u32, N as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '1']] + - Let: [b, "{neon_type[0]}", {FnCall: [simd_shuffle!, [b, b, "{type[3]}"]]}] + - FnCall: [vqdmull_s32, [a, b]] + + - name: "vqdmlal{neon_type[1].noq}" + doc: "Signed saturating doubling multiply-add long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] + - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] + compose: + - FnCall: ["vqadd{neon_type[0].no}", [a, {FnCall: ["vqdmull{neon_type[2].noq}", [b, c]]}]] + + - name: "vqdmlal_n{neon_type[1].noq}" + doc: "Vector widening saturating doubling multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, "i16", int32x4_t] + - [int64x2_t, int32x2_t, "i32", int64x2_t] + compose: + - FnCall: ["vqadd{neon_type[0].no}", [a, {FnCall: ["vqdmull_n{neon_type[1].noq}", [b, c]]}]] + + - name: "vqdmlal_lane_s16" + doc: "Vector widening saturating doubling multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlal, N = 2]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - FnCall: [vqaddq_s32, [a, {FnCall: ["vqdmull_lane_s16::", [b, c]]}]] + + - name: "vqdmlal_lane_s32" + doc: "Vector widening saturating doubling multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlal, N = 1]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlal, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '1']] + - FnCall: [vqaddq_s64, [a, {FnCall: ["vqdmull_lane_s32::", [b, c]]}]] + + - name: "vqdmlsl{neon_type[1].noq}" + doc: "Signed saturating doubling multiply-subtract long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] + - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] + compose: + - FnCall: ["vqsub{neon_type[0].no}", [a, {FnCall: ["vqdmull{neon_type[1].noq}", [b, c]]}]] + + - name: "vqdmlsl{type[4]}" + doc: "Vector widening saturating doubling multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {type[2]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, "i16", int32x4_t, '_n_s16'] + - [int64x2_t, int32x2_t, "i32", int64x2_t, '_n_s32'] + compose: + - FnCall: ["vqsub{neon_type[0].no}", [a, {FnCall: ["vqdmull{type[4]}", [b, c]]}]] + + - name: "vqdmlsl_lane_s16" + doc: "Vector widening saturating doubling multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlsl, N = 2]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x4_t, int16x4_t, int16x4_t, int32x4_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '2']] + - FnCall: [vqsubq_s32, [a, {FnCall: ["vqdmull_lane_s16::", [b, c]]}]] + + - name: "vqdmlsl_lane_s32" + doc: "Vector widening saturating doubling multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmlsl, N = 1]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmlsl, 'N = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int64x2_t, int32x2_t, int32x2_t, int64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, '1']] + - FnCall: [vqsubq_s64, [a, {FnCall: ["vqdmull_lane_s32::", [b, c]]}]] + + - name: "vqdmulh{neon_type[0].no}" + doc: "Signed saturating doubling multiply returning high half" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, int16x4_t] + - [int16x8_t, int16x8_t, int16x8_t] + - [int32x2_t, int32x2_t, int32x2_t] + - [int32x4_t, int32x4_t, int32x4_t] + compose: + - LLVMLink: + name: "vqdmulh{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vqdmulh.{neon_type[0]}" + arch: arm + - link: "llvm.aarch64.neon.sqdmulh.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vqdmulh{type[3]}" + doc: "Vector saturating doubling multiply high with scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", int16x4_t, '_n_s16'] + - [int32x2_t, "i32", int32x2_t, '_n_s32'] + - [int16x8_t, "i16", int16x8_t, 'q_n_s16'] + - [int32x4_t, "i32", int32x4_t, 'q_n_s32'] + compose: + - Let: [b, "{neon_type[0]}", {FnCall: ["vdup{type[3]}", [b]]}] + - FnCall: ["vqdmulh{neon_type[0].no}", [a, b]] + + - name: "vqmovn{neon_type[0].noq}" + doc: "Signed saturating extract narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqmovn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqxtn]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t] + - [int32x4_t, int16x4_t] + - [int64x2_t, int32x2_t] + compose: + - LLVMLink: + name: "vqmovn{neon_type[0].noq}" + links: + - link: "llvm.arm.neon.vqmovns.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.sqxtn.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqmovun{neon_type[0].noq}" + doc: "Signed saturating extract unsigned narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqmovun]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqxtun]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, uint8x8_t] + - [int32x4_t, uint16x4_t] + - [int64x2_t, uint32x2_t] + compose: + - LLVMLink: + name: "vqmovun{neon_type[0].noq}" + links: + - link: "llvm.arm.neon.vqmovnsu.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.sqxtun.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqrdmulh{neon_type[0].no}" + doc: "Signed saturating rounding doubling multiply returning high half" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqrdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, int16x4_t] + - [int16x8_t, int16x8_t, int16x8_t] + - [int32x2_t, int32x2_t, int32x2_t] + - [int32x4_t, int32x4_t, int32x4_t] + compose: + - LLVMLink: + name: "vqrdmulh{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vqrdmulh.{neon_type[0]}" + arch: arm + - link: "llvm.aarch64.neon.sqrdmulh.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vqrshl{neon_type.no}" + doc: "Signed saturating rounding shift left" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "vqrshl{neon_type}" + links: + - link: "llvm.arm.neon.vqrshifts.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.sqrshl.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqrshl{neon_type[0].no}" + doc: "Unsigned signed saturating rounding shift left" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [uint16x4_t, int16x4_t] + - [uint16x8_t, int16x8_t] + - [uint32x2_t, int32x2_t] + - [uint32x4_t, int32x4_t] + - [uint64x1_t, int64x1_t] + - [uint64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vqrshl{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vqrshiftu.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.uqrshl.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqrshrn_n{neon_type[0].noq}" + doc: "Signed saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int16x8_t([-N as i64, -N as i64]) }'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqrshrn{neon_type[0].noq}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqrshiftns.{neon_type[1]}" + arch: arm + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, '{type[3]}']] + + - name: "vqrshrn_n{neon_type[0].noq}" + doc: "Signed saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqrshrn{neon_type[0].no}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.sqrshrn.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", [a, N]] + + - name: "vqrshrun_n{neon_type[0].noq}" + doc: "Signed saturating rounded shift right unsigned narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqrshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] + - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - LLVMLink: + name: "vqrshrun_n{neon_type[0].noq}" + arguments: + - 'a: {neon_type[0]}' + - 'n: {neon_type[0]}' + links: + - link: "llvm.arm.neon.vqrshiftnsu.{neon_type[1]}" + arch: arm + - FnCall: + - "_vqrshrun_n{neon_type[0].noq}" + - - a + - "{type[3]}" + + - name: "vqrshrun_n{neon_type[0].noq}" + doc: "Signed saturating rounded shift right unsigned narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqrshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] + - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] + - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqrshrun_n{neon_type[0].noq}" + arguments: + - 'a: {neon_type[0]}' + - 'n: i32' + links: + - link: "llvm.aarch64.neon.sqrshrun.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqrshrun_n{neon_type[0].noq}", [a, N]] + + - name: "vqshl{neon_type.no}" + doc: "Signed saturating shift left" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "vqshl{neon_type}" + links: + - link: "llvm.arm.neon.vqshifts.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.sqshl.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqshl{neon_type[0].N}" + doc: "Signed saturating shift left" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqshl, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqshl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, '3'] + - [int8x16_t, '3'] + - [int16x4_t, '4'] + - [int16x8_t, '4'] + - [int32x2_t, '5'] + - [int32x4_t, '5'] + - [int64x1_t, '6'] + - [int64x2_t, '6'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[1]}"]] + - FnCall: + - "vqshl{neon_type[0].no}" + - - a + - FnCall: ["vdup{neon_type[0].N}", ['N as _']] + + - name: "vqshl{neon_type[0].no}" + doc: "Unsigned saturating shift left" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [uint16x4_t, int16x4_t] + - [uint16x8_t, int16x8_t] + - [uint32x2_t, int32x2_t] + - [uint32x4_t, int32x4_t] + - [uint64x1_t, int64x1_t] + - [uint64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vqshl{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vqshiftu.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.uqshl.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vqshl{neon_type[0].N}" + doc: "Unsigned saturating shift left" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqshl, N = 2]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqshl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, '3', int8x8_t] + - [uint8x16_t, '3', int8x16_t] + - [uint16x4_t, '4', int16x4_t] + - [uint16x8_t, '4', int16x8_t] + - [uint32x2_t, '5', int32x2_t] + - [uint32x4_t, '5', int32x4_t] + - [uint64x1_t, '6', int64x1_t] + - [uint64x2_t, '6', int64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[1]}"]] + - FnCall: + - "vqshl{neon_type[0].no}" + - - a + - FnCall: ["vdup{neon_type[2].N}", ['N as _']] + + - name: "vqshrn_n{neon_type[0].noq}" + doc: "Signed saturating shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrn{neon_type[0].no}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqshiftns.{neon_type[1]}" + arch: arm + - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, "{type[3]}"]] + + - name: "vqshrn_n{neon_type[0].noq}" + doc: "Signed saturating shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrn_n{neon_type[0].noq}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.sqshrn.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqshrn_n{neon_type[0].noq}", [a, N]] + + - name: "vqshrn_n_{neon_type[0]}" + doc: "Unsigned saturating shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrn_n_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqshiftnu.{neon_type[1]}" + arch: arm + - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a.as_signed()", "{type[3]}"]] + + - name: "vqshrn_n_{neon_type[0]}" + doc: "Unsigned saturating shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrn{neon_type[1].no}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.uqshrn.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqshrn_n_{neon_type[0]}", ["a.as_signed()", N]] + + - name: "vqshrun_n_{neon_type[0]}" + doc: "Signed saturating shift right unsigned narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] + - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrun_n_{neon_type[1]}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqshiftnsu.{neon_type[1]}" + arch: arm + - FnCall: ["_vqshrun_n_{neon_type[1]}", [a, "{type[3]}"]] + + - name: "vqshrun_n_{neon_type[0]}" + doc: "Signed saturating shift right unsigned narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshrun, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, uint8x8_t, 'N >= 1 && N <= 8'] + - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16'] + - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vqshrun_n_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.sqshrun.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, N]] + + - name: "vrsqrts{neon_type.no}" + doc: "Floating-point reciprocal square root step" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsqrts]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrts]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vrsqrts{neon_type.no}" + links: + - link: "llvm.arm.neon.vrsqrts.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.frsqrts.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrecpe{neon_type.no}" + doc: "Reciprocal estimate." + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrecpe]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecpe]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vrecpe{neon_type.no}" + links: + - link: "llvm.arm.neon.vrecpe.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.frecpe.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrecps{neon_type.no}" + doc: "Floating-point reciprocal step" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrecps]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frecps]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vrecps{neon_type.no}" + links: + - link: "llvm.arm.neon.vrecps.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.frecps.{neon_type}" + arch: aarch64,arm64ec + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-aes + - *neon-v8 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [poly64x1_t, int32x2_t] + - [poly64x1_t, uint32x2_t] + - [poly64x2_t, int32x4_t] + - [poly64x2_t, uint32x4_t] + - [p128, int64x2_t] + - [p128, uint64x2_t] + - [p128, poly64x2_t] + - [poly8x16_t, p128] + - [p128, int8x16_t] + - [p128, uint8x16_t] + - [p128, poly8x16_t] + - [int32x2_t, poly64x1_t] + - [uint32x2_t, poly64x1_t] + - [int32x4_t, poly64x2_t] + - [uint32x4_t, poly64x2_t] + - [int64x2_t, p128] + - [uint64x2_t, p128] + - [poly64x2_t, p128] + - [poly64x1_t, int16x4_t] + - [poly64x1_t, uint16x4_t] + - [poly64x1_t, poly16x4_t] + - [poly64x2_t, int16x8_t] + - [poly64x2_t, uint16x8_t] + - [poly64x2_t, poly16x8_t] + - [p128, int32x4_t] + - [p128, uint32x4_t] + - [poly16x4_t, poly64x1_t] + - [int16x4_t, poly64x1_t] + - [uint16x4_t, poly64x1_t] + - [poly16x8_t, poly64x2_t] + - [int16x8_t, poly64x2_t] + - [uint16x8_t, poly64x2_t] + - [int32x4_t, p128] + - [uint32x4_t, p128] + - [poly64x1_t, int8x8_t] + - [poly64x1_t, uint8x8_t] + - [poly64x1_t, poly8x8_t] + - [poly64x2_t, int8x16_t] + - [poly64x2_t, uint8x16_t] + - [poly64x2_t, poly8x16_t] + - [p128, int16x8_t] + - [p128, uint16x8_t] + - [p128, poly16x8_t] + - [poly8x8_t, poly64x1_t] + - [int8x8_t, poly64x1_t] + - [uint8x8_t, poly64x1_t] + - [poly8x16_t, poly64x2_t] + - [int8x16_t, poly64x2_t] + - [uint8x16_t, poly64x2_t] + - [int16x8_t, p128] + - [uint16x8_t, p128] + - [poly16x8_t, p128] + - [int8x16_t, p128] + - [uint8x16_t, p128] + compose: + - FnCall: [transmute, [a]] + + - name: "vreinterpret{neon_type[1].no}{neon_type[0].noq}" + doc: Vector reinterpret cast operation + arguments: ["a: {type[0]}"] + return_type: "{type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [nop]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [poly8x8_t, int8x8_t] + - [poly16x4_t, int16x4_t] + - [uint16x4_t, int16x4_t] + - [uint32x2_t, int32x2_t] + - [uint64x1_t, int64x1_t] + - [uint8x16_t, int8x16_t] + - [poly8x16_t, int8x16_t] + - [poly16x8_t, int16x8_t] + - [uint16x8_t, int16x8_t] + - [uint32x4_t, int32x4_t] + - [uint64x2_t, int64x2_t] + - [poly8x8_t, uint8x8_t] + - [int8x8_t, uint8x8_t] + - [poly16x4_t, uint16x4_t] + - [int16x4_t, uint16x4_t] + - [int32x2_t, uint32x2_t] + - [int64x1_t, uint64x1_t] + - [poly8x16_t, uint8x16_t] + - [int8x16_t, uint8x16_t] + - [poly16x8_t, uint16x8_t] + - [int16x8_t, uint16x8_t] + - [int32x4_t, uint32x4_t] + - [int64x2_t, uint64x2_t] + - [int8x8_t, poly8x8_t] + - [uint8x8_t, poly8x8_t] + - [int16x4_t, poly16x4_t] + - [uint16x4_t, poly16x4_t] + - [int8x16_t, poly8x16_t] + - [uint8x16_t, poly8x16_t] + - [int16x8_t, poly16x8_t] + - [uint16x8_t, poly16x8_t] + - [int16x4_t, int8x8_t] + - [uint16x4_t, int8x8_t] + - [poly16x4_t, int8x8_t] + - [int32x2_t, int16x4_t] + - [uint32x2_t, int16x4_t] + - [int64x1_t, int32x2_t] + - [uint64x1_t, int32x2_t] + - [int16x8_t, int8x16_t] + - [uint16x8_t, int8x16_t] + - [poly16x8_t, int8x16_t] + - [int32x4_t, int16x8_t] + - [uint32x4_t, int16x8_t] + - [int64x2_t, int32x4_t] + - [uint64x2_t, int32x4_t] + - [poly16x4_t, uint8x8_t] + - [int16x4_t, uint8x8_t] + - [uint16x4_t, uint8x8_t] + - [int32x2_t, uint16x4_t] + - [uint32x2_t, uint16x4_t] + - [int64x1_t, uint32x2_t] + - [uint64x1_t, uint32x2_t] + - [poly16x8_t, uint8x16_t] + - [int16x8_t, uint8x16_t] + - [uint16x8_t, uint8x16_t] + - [int32x4_t, uint16x8_t] + - [uint32x4_t, uint16x8_t] + - [int64x2_t, uint32x4_t] + - [uint64x2_t, uint32x4_t] + - [poly16x4_t, poly8x8_t] + - [int16x4_t, poly8x8_t] + - [uint16x4_t, poly8x8_t] + - [int32x2_t, poly16x4_t] + - [uint32x2_t, poly16x4_t] + - [poly16x8_t, poly8x16_t] + - [int16x8_t, poly8x16_t] + - [uint16x8_t, poly8x16_t] + - [int32x4_t, poly16x8_t] + - [uint32x4_t, poly16x8_t] + - [poly8x8_t, int16x4_t] + - [int8x8_t, int16x4_t] + - [uint8x8_t, int16x4_t] + - [poly16x4_t, int32x2_t] + - [int16x4_t, int32x2_t] + - [uint16x4_t, int32x2_t] + - [int32x2_t, int64x1_t] + - [uint32x2_t, int64x1_t] + - [poly8x16_t, int16x8_t] + - [int8x16_t, int16x8_t] + - [uint8x16_t, int16x8_t] + - [poly16x8_t, int32x4_t] + - [int16x8_t, int32x4_t] + - [uint16x8_t, int32x4_t] + - [int32x4_t, int64x2_t] + - [uint32x4_t, int64x2_t] + - [poly8x8_t, uint16x4_t] + - [int8x8_t, uint16x4_t] + - [uint8x8_t, uint16x4_t] + - [poly16x4_t, uint32x2_t] + - [int16x4_t, uint32x2_t] + - [uint16x4_t, uint32x2_t] + - [int32x2_t, uint64x1_t] + - [uint32x2_t, uint64x1_t] + - [poly8x16_t, uint16x8_t] + - [int8x16_t, uint16x8_t] + - [uint8x16_t, uint16x8_t] + - [poly16x8_t, uint32x4_t] + - [int16x8_t, uint32x4_t] + - [uint16x8_t, uint32x4_t] + - [int32x4_t, uint64x2_t] + - [uint32x4_t, uint64x2_t] + - [poly8x8_t, poly16x4_t] + - [int8x8_t, poly16x4_t] + - [uint8x8_t, poly16x4_t] + - [poly8x16_t, poly16x8_t] + - [int8x16_t, poly16x8_t] + - [uint8x16_t, poly16x8_t] + - [int32x2_t, int8x8_t] + - [uint32x2_t, int8x8_t] + - [int64x1_t, int16x4_t] + - [uint64x1_t, int16x4_t] + - [int32x4_t, int8x16_t] + - [uint32x4_t, int8x16_t] + - [int64x2_t, int16x8_t] + - [uint64x2_t, int16x8_t] + - [int32x2_t, uint8x8_t] + - [uint32x2_t, uint8x8_t] + - [int64x1_t, uint16x4_t] + - [uint64x1_t, uint16x4_t] + - [int32x4_t, uint8x16_t] + - [uint32x4_t, uint8x16_t] + - [int64x2_t, uint16x8_t] + - [uint64x2_t, uint16x8_t] + - [int32x2_t, poly8x8_t] + - [uint32x2_t, poly8x8_t] + - [int64x1_t, poly16x4_t] + - [uint64x1_t, poly16x4_t] + - [int32x4_t, poly8x16_t] + - [uint32x4_t, poly8x16_t] + - [int64x2_t, poly16x8_t] + - [uint64x2_t, poly16x8_t] + - [poly8x8_t, int32x2_t] + - [int8x8_t, int32x2_t] + - [uint8x8_t, int32x2_t] + - [poly16x4_t, int64x1_t] + - [int16x4_t, int64x1_t] + - [uint16x4_t, int64x1_t] + - [poly8x16_t, int32x4_t] + - [int8x16_t, int32x4_t] + - [uint8x16_t, int32x4_t] + - [poly16x8_t, int64x2_t] + - [int16x8_t, int64x2_t] + - [uint16x8_t, int64x2_t] + - [poly8x8_t, uint32x2_t] + - [int8x8_t, uint32x2_t] + - [uint8x8_t, uint32x2_t] + - [poly16x4_t, uint64x1_t] + - [int16x4_t, uint64x1_t] + - [uint16x4_t, uint64x1_t] + - [poly8x16_t, uint32x4_t] + - [int8x16_t, uint32x4_t] + - [uint8x16_t, uint32x4_t] + - [poly16x8_t, uint64x2_t] + - [int16x8_t, uint64x2_t] + - [uint16x8_t, uint64x2_t] + - [int64x1_t, int8x8_t] + - [uint64x1_t, int8x8_t] + - [int64x1_t, uint8x8_t] + - [uint64x1_t, uint8x8_t] + - [int64x1_t, poly8x8_t] + - [uint64x1_t, poly8x8_t] + - [int64x2_t, int8x16_t] + - [uint64x2_t, int8x16_t] + - [int64x2_t, uint8x16_t] + - [uint64x2_t, uint8x16_t] + - [int64x2_t, poly8x16_t] + - [uint64x2_t, poly8x16_t] + - [poly8x8_t, int64x1_t] + - [int8x8_t, int64x1_t] + - [uint8x8_t, int64x1_t] + - [poly8x8_t, uint64x1_t] + - [int8x8_t, uint64x1_t] + - [uint8x8_t, uint64x1_t] + - [poly8x16_t, int64x2_t] + - [int8x16_t, int64x2_t] + - [uint8x16_t, int64x2_t] + - [poly8x16_t, uint64x2_t] + - [int8x16_t, uint64x2_t] + - [uint8x16_t, uint64x2_t] + - [float32x2_t, int8x8_t] + - [float32x2_t, int16x4_t] + - [float32x2_t, int32x2_t] + - [float32x2_t, int64x1_t] + - [float32x4_t, int8x16_t] + - [float32x4_t, int16x8_t] + - [float32x4_t, int32x4_t] + - [float32x4_t, int64x2_t] + - [float32x2_t, uint8x8_t] + - [float32x2_t, uint16x4_t] + - [float32x2_t, uint32x2_t] + - [float32x2_t, uint64x1_t] + - [float32x4_t, uint8x16_t] + - [float32x4_t, uint16x8_t] + - [float32x4_t, uint32x4_t] + - [float32x4_t, uint64x2_t] + - [float32x2_t, poly8x8_t] + - [float32x2_t, poly16x4_t] + - [float32x4_t, poly8x16_t] + - [float32x4_t, poly16x8_t] + - [float32x4_t, p128] + - [int8x8_t, float32x2_t] + - [int16x4_t, float32x2_t] + - [int32x2_t, float32x2_t] + - [int64x1_t, float32x2_t] + - [int8x16_t, float32x4_t] + - [int16x8_t, float32x4_t] + - [int32x4_t, float32x4_t] + - [int64x2_t, float32x4_t] + - [uint8x8_t, float32x2_t] + - [uint16x4_t, float32x2_t] + - [uint32x2_t, float32x2_t] + - [uint64x1_t, float32x2_t] + - [uint8x16_t, float32x4_t] + - [uint16x8_t, float32x4_t] + - [uint32x4_t, float32x4_t] + - [uint64x2_t, float32x4_t] + - [poly8x8_t, float32x2_t] + - [poly16x4_t, float32x2_t] + - [poly8x16_t, float32x4_t] + - [poly16x8_t, float32x4_t] + - [p128, float32x4_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vrshl{neon_type.no}" + doc: "Signed rounding shift left" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [srshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "vrshl{neon_type.no}" + links: + - link: "llvm.arm.neon.vrshifts.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.srshl.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrshl{neon_type[0].no}" + doc: "Unsigned rounding shift left" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [urshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [uint16x4_t, int16x4_t] + - [uint16x8_t, int16x8_t] + - [uint32x2_t, int32x2_t] + - [uint32x4_t, int32x4_t] + - [uint64x1_t, int64x1_t] + - [uint64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vrshl{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vrshiftu.{neon_type[0]}" + arch: arm + - link: "llvm.aarch64.neon.urshl.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vrshr{neon_type[0].N}" + doc: "Signed rounding shift right" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrshr, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [srshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, 'N >= 1 && N <= 8'] + - [int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, 'N >= 1 && N <= 16'] + - [int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, 'N >= 1 && N <= 32'] + - [int32x4_t, 'N >= 1 && N <= 32'] + - [int64x1_t, 'N >= 1 && N <= 64'] + - [int64x2_t, 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - FnCall: + - "vrshl{neon_type[0].no}" + - - a + - FnCall: ["vdup{neon_type[0].N}", ['-N as _']] + + - name: "vrshr{neon_type[0].N}" + doc: "Unsigned rounding shift right" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrshr, N = 2]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [urshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t, 'N >= 1 && N <= 8'] + - [uint8x16_t, int8x16_t, 'N >= 1 && N <= 8'] + - [uint16x4_t, int16x4_t, 'N >= 1 && N <= 16'] + - [uint16x8_t, int16x8_t, 'N >= 1 && N <= 16'] + - [uint32x2_t, int32x2_t, 'N >= 1 && N <= 32'] + - [uint32x4_t, int32x4_t, 'N >= 1 && N <= 32'] + - [uint64x1_t, int64x1_t, 'N >= 1 && N <= 64'] + - [uint64x2_t, int64x2_t, 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - FnCall: + - "vrshl{neon_type[0].no}" + - - a + - FnCall: ["vdup{neon_type[1].N}", ['-N as _']] + + - name: "vrshrn_n_{neon_type[0]}" + doc: "Rounding shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vrshrn_n_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vrshiftn.{neon_type[1]}" + arch: arm + - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, "{type[3]}"]] + + - name: "vrshrn_n_{neon_type[0]}" + doc: "Rounding shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [rshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - LLVMLink: + name: "vrshrn_n_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.rshrn.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vrshrn_n_{neon_type[0]}", [a, N]] + + - name: "vrshrn_n_{neon_type[0]}" + doc: "Rounding shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrshrn, N = 2]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [rshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', s16] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', s32] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', s64] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - FnCall: + - transmute + - - FnCall: + - "vrshrn_n_{type[3]}::" + - - FnCall: [transmute, [a]] + + - name: "vrsra{neon_type[0].N}" + doc: "Signed rounding shift right and accumulate" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsra, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [srsra, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, 'N >= 1 && N <= 8'] + - [int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, 'N >= 1 && N <= 16'] + - [int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, 'N >= 1 && N <= 32'] + - [int32x4_t, 'N >= 1 && N <= 32'] + - [int64x1_t, 'N >= 1 && N <= 64'] + - [int64x2_t, 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - FnCall: + - simd_add + - - a + - FnCall: ["vrshr{neon_type[0].N}::", [b]] + + - name: "vrsubhn_{neon_type[0]}" + doc: "Rounding subtract returning high narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsubhn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [rsubhn]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int16x8_t, int8x8_t] + - [int32x4_t, int32x4_t, int16x4_t] + - [int64x2_t, int64x2_t, int32x2_t] + compose: + - LLVMLink: + name: "vrsubhn_{neon_type[0]}" + links: + - link: "llvm.arm.neon.vrsubhn.{neon_type[2]}" + arch: arm + - link: "llvm.aarch64.neon.rsubhn.{neon_type[2]}" + arch: aarch64,arm64ec + + - name: "vrsubhn_{neon_type[0]}" + doc: "Rounding subtract returning high narrow" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsubhn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [rsubhn]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint16x8_t, uint8x8_t, s16] + - [uint32x4_t, uint32x4_t, uint16x4_t, s32] + - [uint64x2_t, uint64x2_t, uint32x2_t, s64] + compose: + - FnCall: + - transmute + - - FnCall: + - "vrsubhn_{type[3]}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vcreate_{neon_type[1]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["u64", int8x8_t] + - ["u64", int16x4_t] + - ["u64", int32x2_t] + - ["u64", int64x1_t] + - ["u64", uint8x8_t] + - ["u64", uint16x4_t] + - ["u64", uint32x2_t] + - ["u64", uint64x1_t] + - ["u64", poly8x8_t] + - ["u64", poly16x4_t] + - ["u64", float32x2_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vcreate_p64" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["u64", poly64x1_t] + compose: + - FnCall: [transmute, [a]] + + - name: "vset{neon_type[1].lane_nox}" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop, LANE = 0]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i8", int8x8_t, '3'] + - ["i16", int16x4_t, '2'] + - ["i32", int32x2_t, '1'] + - ["u8", uint8x8_t, '3'] + - ["u16", uint16x4_t, '2'] + - ["u32", uint32x2_t, '1'] + - ["p8", poly8x8_t, '3'] + - ["p16", poly16x4_t, '2'] + - ["i8", int8x16_t, '4'] + - ["i16", int16x8_t, '3'] + - ["i32", int32x4_t, '2'] + - ["i64", int64x2_t, '1'] + - ["u8", uint8x16_t, '4'] + - ["u16", uint16x8_t, '3'] + - ["u32", uint32x4_t, '2'] + - ["u64", uint64x2_t, '1'] + - ["p8", poly8x16_t, '4'] + - ["p16", poly16x8_t, '3'] + - ["f32", float32x2_t, '1'] + - ["f32", float32x4_t, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vset_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["i64", int64x1_t, int64x1_t] + - ["u64", uint64x1_t, uint64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vset_lane_{neon_type[0]}" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["p64", poly64x1_t, poly64x1_t] + compose: + - FnCall: [static_assert!, ['LANE == 0']] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vsetq_lane_p64" + doc: "Insert vector element from another vector element" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [nop, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - ["p64", poly64x2_t, poly64x2_t] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '1']] + - FnCall: [simd_insert!, [b, 'LANE as u32', a]] + + - name: "vshl{neon_type.no}" + doc: "Signed Shift left" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + - int64x1_t + - int64x2_t + compose: + - LLVMLink: + name: "vshl{neon_type.no}" + links: + - link: "llvm.arm.neon.vshifts.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.sshl.{neon_type}" + arch: aarch64,arm64ec + + - name: "vshl{neon_type[0].no}" + doc: "Unsigned Shift left" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vshl]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, int8x8_t] + - [uint8x16_t, int8x16_t] + - [uint16x4_t, int16x4_t] + - [uint16x8_t, int16x8_t] + - [uint32x2_t, int32x2_t] + - [uint32x4_t, int32x4_t] + - [uint64x1_t, int64x1_t] + - [uint64x2_t, int64x2_t] + compose: + - LLVMLink: + name: "vshl{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vshiftu.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.ushl.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vshll_n_s8" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.s8"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, int16x8_t, 'N >= 0 && N <= 8'] + compose: + - FnCall: [static_assert!, ["{type[2]}"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_s16, ['N as _']] + + - name: "vshll_n_s16" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.s16"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, int32x4_t] + compose: + - FnCall: [static_assert!, ["N >= 0 && N <= 16"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_s32, ['N as _']] + + - name: "vshll_n_s32" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.s32"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int32x2_t, int64x2_t] + compose: + - FnCall: [static_assert!, ["N >= 0 && N <= 32"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_s64, ['N as _']] + + - name: "vshll_n_u8" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.u8"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint16x8_t] + compose: + - FnCall: [static_assert!, ["N >= 0 && N <= 8"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_u16, ['N as _']] + + - name: "vshll_n_u16" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.u16"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x4_t, uint32x4_t] + compose: + - FnCall: [static_assert!, ["N >= 0 && N <= 16"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_u32, ['N as _']] + + - name: "vshll_n_u32" + doc: "Signed shift left long" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshll.u32"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushll, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint32x2_t, uint64x2_t] + compose: + - FnCall: [static_assert!, ["N >= 0 && N <= 32"]] + - FnCall: + - simd_shl + - - FnCall: [simd_cast, [a]] + - FnCall: [vdupq_n_u64, ['N as _']] + + - name: "vshr{neon_type[0].N}" + doc: "Shift right" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshr.{neon_type[0]}"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sshr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { 7 }', 'else { N };'] + - [int8x16_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { 7 }', 'else { N };'] + - [int16x4_t, 'N >= 1 && N <= 16', 'let n: i32 = if N == 16 { 15 }', 'else { N };'] + - [int16x8_t, 'N >= 1 && N <= 16', 'let n: i32 = if N == 16 { 15 }', 'else { N };'] + - [int32x2_t, 'N >= 1 && N <= 32', 'let n: i32 = if N == 32 { 31 }', 'else { N };'] + - [int32x4_t, 'N >= 1 && N <= 32', 'let n: i32 = if N == 32 { 31 }', 'else { N };'] + - [int64x1_t, 'N >= 1 && N <= 64', 'let n: i32 = if N == 64 { 63 }', 'else { N };'] + - [int64x2_t, 'N >= 1 && N <= 64', 'let n: i32 = if N == 64 { 63 }', 'else { N };'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - Identifier: ["{type[2]}{type[3]}", Symbol] + - FnCall: + - simd_shr + - - a + - FnCall: ["vdup{neon_type[0].N}", ['n as _']] + + - name: "vshr{neon_type[0].N}" + doc: "Shift right" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshr.{neon_type[0]}"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ushr, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { return vdup_n_u8(0); }', 'else { N };'] + - [uint8x16_t, 'N >= 1 && N <= 8', 'let n: i32 = if N == 8 { return vdupq_n_u8(0); }', 'else { N };'] + - [uint16x4_t, 'N >= 1 && N <= 16', 'let n: i32 = if N == 16 { return vdup_n_u16(0); }', 'else { N };'] + - [uint16x8_t, 'N >= 1 && N <= 16', 'let n: i32 = if N == 16 { return vdupq_n_u16(0); }', 'else { N };'] + - [uint32x2_t, 'N >= 1 && N <= 32', 'let n: i32 = if N == 32 { return vdup_n_u32(0); }', 'else { N };'] + - [uint32x4_t, 'N >= 1 && N <= 32', 'let n: i32 = if N == 32 { return vdupq_n_u32(0); }', 'else { N };'] + - [uint64x1_t, 'N >= 1 && N <= 64', 'let n: i32 = if N == 64 { return vdup_n_u64(0); }', 'else { N };'] + - [uint64x2_t, 'N >= 1 && N <= 64', 'let n: i32 = if N == 64 { return vdupq_n_u64(0); }', 'else { N };'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - Identifier: ['{type[2]}{type[3]}', Symbol] + - FnCall: + - simd_shr + - - a + - FnCall: ["vdup{neon_type[0].N}", ['n as _']] + + - name: "vshrn_n_{neon_type[0]}" + doc: "Shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vshrn{type[2]}"', 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [shrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, '.i16', 'N >= 1 && N <= 8'] + - [uint16x8_t, uint8x8_t, '.i16', 'N >= 1 && N <= 8'] + - [int32x4_t, int16x4_t, '.i32', 'N >= 1 && N <= 16'] + - [uint32x4_t, uint16x4_t, '.i32', 'N >= 1 && N <= 16'] + - [int64x2_t, int32x2_t, '.i64', 'N >= 1 && N <= 32'] + - [uint64x2_t, uint32x2_t, '.i64', 'N >= 1 && N <= 32'] + compose: + - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: + - simd_cast + - - FnCall: + - simd_shr + - - a + - FnCall: ["vdupq_n_{neon_type[0]}", ['N as _']] + + - name: "vsra{neon_type[0].N}" + doc: "Signed shift right and accumulate" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vsra, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ssra, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, 'N >= 1 && N <= 8'] + - [int8x16_t, 'N >= 1 && N <= 8'] + - [int16x4_t, 'N >= 1 && N <= 16'] + - [int16x8_t, 'N >= 1 && N <= 16'] + - [int32x2_t, 'N >= 1 && N <= 32'] + - [int32x4_t, 'N >= 1 && N <= 32'] + - [int64x1_t, 'N >= 1 && N <= 64'] + - [int64x2_t, 'N >= 1 && N <= 64'] + compose: + - FnCall: [static_assert!, ["{type[1]}"]] + - FnCall: + - simd_add + - - a + - FnCall: ["vshr{neon_type[0].N}::", [b]] + + - name: "vtrn{neon_type[0].no}" + doc: "Transpose elements" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vtrn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [trn]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int8x8_t, int8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [int16x4_t, int16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + - [int8x16_t, int8x16x2_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]', '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [int16x8_t, int16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [int32x4_t, int32x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + - [uint8x8_t, uint8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [uint16x4_t, uint16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + - [uint8x16_t, uint8x16x2_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]', '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [uint16x8_t, uint16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [uint32x4_t, uint32x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + - [poly8x8_t, poly8x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [poly16x4_t, poly16x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + - [poly8x16_t, poly8x16x2_t, '[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]', '[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]'] + - [poly16x8_t, poly16x8x2_t, '[0, 8, 2, 10, 4, 12, 6, 14]', '[1, 9, 3, 11, 5, 13, 7, 15]'] + - [float32x4_t, float32x4x2_t, '[0, 4, 2, 6]', '[1, 5, 3, 7]'] + compose: + - Let: + - a1 + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [a, b, "{type[2]}"]] + - Let: + - b1 + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - Identifier: ['(a1, b1)', Symbol] + + - name: "vtrn{neon_type[0].no}" + doc: "Transpose elements" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vtrn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [zip]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] + - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] + - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] + compose: + - Let: + - a1 + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [a, b, "{type[2]}"]] + - Let: + - b1 + - "{neon_type[0]}" + - FnCall: [simd_shuffle!, [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - Identifier: ['(a1, b1)', Symbol] + + - name: "vzip{neon_type[0].no}" + doc: Zip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vorr]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x16_t, int8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [int16x8_t, int16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [int32x4_t, int32x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + - [uint8x16_t, uint8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [uint16x8_t, uint16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [uint32x4_t, uint32x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + - [poly8x16_t, poly8x16x2_t, '[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]', '[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]'] + - [poly16x8_t, poly16x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [float32x4_t, float32x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + compose: + - Let: + - a0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[2]}"]] + - Let: + - b0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - '(a0, b0)' + + - name: "vzip{neon_type[0].no}" + doc: Zip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] + - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] + - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] + compose: + - Let: + - a0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[2]}"]] + - Let: + - b0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - '(a0, b0)' + + - name: "vzip{neon_type[0].no}" + doc: Zip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vzip]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, int8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [int16x4_t, int16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + - [uint8x8_t, uint8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [uint16x4_t, uint16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + - [poly8x8_t, poly8x8x2_t, '[0, 8, 1, 9, 2, 10, 3, 11]', '[4, 12, 5, 13, 6, 14, 7, 15]'] + - [poly16x4_t, poly16x4x2_t, '[0, 4, 1, 5]', '[2, 6, 3, 7]'] + compose: + - Let: + - a0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[2]}"]] + - Let: + - b0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - '(a0, b0)' + + - name: "vuzp{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vuzp]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [uzp]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [int8x8_t, int8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [int16x4_t, int16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + - [int8x16_t, int8x16x2_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]', '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [int16x8_t, int16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [int32x4_t, int32x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + - [uint8x8_t, uint8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [uint16x4_t, uint16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + - [uint8x16_t, uint8x16x2_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]', '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [uint16x8_t, uint16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [uint32x4_t, uint32x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + - [poly8x8_t, poly8x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [poly16x4_t, poly16x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + - [poly8x16_t, poly8x16x2_t, '[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]', '[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]'] + - [poly16x8_t, poly16x8x2_t, '[0, 2, 4, 6, 8, 10, 12, 14]', '[1, 3, 5, 7, 9, 11, 13, 15]'] + - [float32x4_t, float32x4x2_t, '[0, 2, 4, 6]', '[1, 3, 5, 7]'] + compose: + - Let: + - a0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[2]}"]] + - Let: + - b0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - '(a0, b0)' + + - name: "vuzp{neon_type[0].no}" + doc: Unzip vectors + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, [vtrn]]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [zip]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2x2_t, '[0, 2]', '[1, 3]'] + - [int32x2_t, int32x2x2_t, '[0, 2]', '[1, 3]'] + - [uint32x2_t, uint32x2x2_t, '[0, 2]', '[1, 3]'] + compose: + - Let: + - a0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[2]}"]] + - Let: + - b0 + - "{neon_type[0]}" + - FnCall: ["simd_shuffle!", [a, b, "{type[3]}"]] + - FnCall: + - transmute + - - '(a0, b0)' + + - name: "vabal_{neon_type[1]}" + doc: "Unsigned Absolute difference and Accumulate Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vabal.{type[2]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uabal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, "u8"] + - [uint32x4_t, uint16x4_t, "u16"] + - [uint64x2_t, uint32x2_t, "u32"] + compose: + - Let: [d, "{neon_type[1]}", {FnCall: ["vabd_{type[2]}", [b, c]]}] + - FnCall: [simd_add, [a, {FnCall: [simd_cast, [d]]}]] + + - name: "vabal_{neon_type[1]}" + doc: "Signed Absolute difference and Accumulate Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}", "c: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vabal.{neon_type[1]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sabal]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x8_t, int8x8_t, uint8x8_t] + - [int32x4_t, int16x4_t, uint16x4_t] + - [int64x2_t, int32x2_t, uint32x2_t] + compose: + - Let: [d, "{type[1]}", {FnCall: ["vabd_{neon_type[1]}", [b, c]]}] + - Let: [e, "{type[2]}", {FnCall: ["simd_cast", [d]]}] + - FnCall: [simd_add, [a, {FnCall: [simd_cast, [e]]}]] + + - name: "vqabs{neon_type.no}" + doc: Signed saturating Absolute value + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - *neon-v7 + - FnCall: [cfg_attr, [*test-is-arm, {FnCall: [assert_instr, ['"vqabs.{neon_type}"']]}]] + - FnCall: [cfg_attr, [*neon-target-aarch64-arm64ec, {FnCall: [assert_instr, [sqabs]]}]] + - *neon-stable-not-arm + - *neon-unstable-is-arm + safety: + unsafe: [neon] + types: + - int8x8_t + - int8x16_t + - int16x4_t + - int16x8_t + - int32x2_t + - int32x4_t + compose: + - LLVMLink: + name: "sqabs.{neon_type}" + links: + - link: "llvm.aarch64.neon.sqabs.{neon_type}" + arch: aarch64,arm64ec + - link: "llvm.arm.neon.vqabs.{neon_type}" + arch: arm + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vst1]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*mut u8", uint8x8x2_t, int8x8x2_t] + - ["*mut u16", uint16x4x2_t, int16x4x2_t] + - ["*mut u32", uint32x2x2_t, int32x2x2_t] + - ["*mut u64", uint64x1x2_t, int64x1x2_t] + - ["*mut u8", uint8x16x2_t, int8x16x2_t] + - ["*mut u16", uint16x8x2_t, int16x8x2_t] + - ["*mut u32", uint32x4x2_t, int32x4x2_t] + - ["*mut u64", uint64x2x2_t, int64x2x2_t] + - ["*mut u8", uint8x8x3_t, int8x8x3_t] + - ["*mut u16", uint16x4x3_t, int16x4x3_t] + - ["*mut u32", uint32x2x3_t, int32x2x3_t] + - ["*mut u64", uint64x1x3_t, int64x1x3_t] + - ["*mut u8", uint8x16x3_t, int8x16x3_t] + - ["*mut u16", uint16x8x3_t, int16x8x3_t] + - ["*mut u32", uint32x4x3_t, int32x4x3_t] + - ["*mut u64", uint64x2x3_t, int64x2x3_t] + - ["*mut u8", uint8x8x4_t, int8x8x4_t] + - ["*mut u16", uint16x4x4_t, int16x4x4_t] + - ["*mut u32", uint32x2x4_t, int32x2x4_t] + - ["*mut u64", uint64x1x4_t, int64x1x4_t] + - ["*mut u8", uint8x16x4_t, int8x16x4_t] + - ["*mut u16", uint16x8x4_t, int16x8x4_t] + - ["*mut u32", uint32x4x4_t, int32x4x4_t] + - ["*mut u64", uint64x2x4_t, int64x2x4_t] + - ["*mut p8", poly8x8x2_t, int8x8x2_t] + - ["*mut p8", poly8x8x3_t, int8x8x3_t] + - ["*mut p8", poly8x8x4_t, int8x8x4_t] + - ["*mut p8", poly8x16x2_t, int8x16x2_t] + - ["*mut p8", poly8x16x3_t, int8x16x3_t] + - ["*mut p8", poly8x16x4_t, int8x16x4_t] + - ["*mut p16", poly16x4x2_t, int16x4x2_t] + - ["*mut p16", poly16x4x3_t, int16x4x3_t] + - ["*mut p16", poly16x4x4_t, int16x4x4_t] + - ["*mut p16", poly16x8x2_t, int16x8x2_t] + - ["*mut p16", poly16x8x3_t, int16x8x3_t] + - ["*mut p16", poly16x8x4_t, int16x8x4_t] + compose: + - FnCall: + - "vst1{neon_type[2].no}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vst1]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*mut p64", poly64x1x2_t, int64x1x2_t] + compose: + - FnCall: + - "vst1{neon_type[2].no}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*mut p64", poly64x1x3_t, int64x1x3_t] + - ["*mut p64", poly64x1x4_t, int64x1x4_t] + - ["*mut p64", poly64x2x2_t, int64x2x2_t] + - ["*mut p64", poly64x2x3_t, int64x2x3_t] + - ["*mut p64", poly64x2x4_t, int64x2x4_t] + compose: + - FnCall: + - "vst1{neon_type[2].no}" + - - FnCall: [transmute, [a]] + - FnCall: [transmute, [b]] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst1]]}]] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + safety: + unsafe: [neon] + types: + - ['*mut f32', float32x2x2_t, float32x2_t] + - ['*mut f32', float32x4x2_t, float32x4_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "ptr: {type[0]}" + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + links: + - link: "llvm.arm.neon.vst1x{neon_type[1].tuple}.p0f32.{neon_type[2]}" + arch: arm + - FnCall: ["_vst1{neon_type[1].no}", ['a', 'b.0', 'b.1']] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vst1]]}]] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + safety: + unsafe: [neon] + types: + - ['*mut f32', float32x2x3_t, float32x2_t] + - ['*mut f32', float32x4x3_t, float32x4_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "ptr: {type[0]}" + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "c: {neon_type[2]}" + links: + - link: "llvm.arm.neon.vst1x{neon_type[1].tuple}.p0f32.{neon_type[2]}" + arch: arm + - FnCall: ["_vst1{neon_type[1].no}", ['a', 'b.0', 'b.1', 'b.2']] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*mut f32", float32x2x2_t, float32x2_t] + - ["*mut f32", float32x4x2_t, float32x4_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x2.{neon_type[2]}.p0f32" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', a]] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*mut f32", float32x2x3_t, float32x2_t] + - ["*mut f32", float32x4x3_t, float32x4_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "c: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x3.{neon_type[2]}.p0f32" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', 'b.2', a]] + + - name: "vst1{neon_type[1].no}" + doc: "Store multiple single-element structures to one, two, three, or four registers" + arguments: ["a: {type[0]}", "b: {neon_type[1]}"] + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [st1]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*mut f32", float32x2x4_t, float32x2_t] + - ["*mut f32", float32x4x4_t, float32x4_t] + compose: + - LLVMLink: + name: "vst1{neon_type[1].no}" + arguments: + - "a: {neon_type[2]}" + - "b: {neon_type[2]}" + - "c: {neon_type[2]}" + - "d: {neon_type[2]}" + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.st1x4.{neon_type[2]}.p0f32" + arch: aarch64,arm64ec + - FnCall: ["_vst1{neon_type[1].no}", ['b.0', 'b.1', 'b.2', 'b.3', a]] + + - name: "vfms{neon_type.no}" + doc: "Floating-point fused multiply-subtract from accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "vfp4"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vfms]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - Let: [b, "{neon_type}", {FnCall: [simd_neg, [b]]}] + - FnCall: ["vfma{neon_type.no}", [a, b, c]] + + - name: "vmul{neon_type[0].no}" + doc: "Polynomial multiply" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [pmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [poly8x8_t, int8x8_t] + - [poly8x16_t, int8x16_t] + compose: + - LLVMLink: + name: "vmul{neon_type[0].no}" + links: + - link: "llvm.arm.neon.vmulp.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.pmul.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vmls{neon_type.no}" + doc: "Floating-point multiply-subtract from accumulator" + arguments: ["a: {neon_type}", "b: {neon_type}", "c: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - FnCall: [simd_sub, [a, {FnCall: [simd_mul, [b, c]]}]] + + - name: "vcge{neon_type.no}" + doc: "Compare unsigned greater than or equal" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.{neon_type}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhs]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vcge{neon_type[0].no}" + doc: "Floating-point compare greater than or equal" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmge]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: [simd_ge, [a, b]] + + - name: "vclt{neon_type.no}" + doc: "Compare unsigned less than" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.{neon_type}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhi]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vtst{neon_type[0].no}" + doc: "Unsigned compare bitwise Test bits nonzero" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vtst]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmtst]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, u8x8, 'u8x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint8x16_t, u8x16, 'u8x16::new(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint16x4_t, u16x4, 'u16x4::new(0, 0, 0, 0)'] + - [uint16x8_t, u16x8, 'u16x8::new(0, 0, 0, 0, 0, 0, 0, 0)'] + - [uint32x2_t, u32x2, 'u32x2::new(0, 0)'] + - [uint32x4_t, u32x4, 'u32x4::new(0, 0, 0, 0)'] + compose: + - Let: [c, "{neon_type[0]}", {FnCall: [simd_and, [a, b]]}] + - Let: [d, "{type[1]}", "{type[2]}"] + - FnCall: [simd_ne, [c, {FnCall: [transmute, [d]]}]] + + - name: "vshl{neon_type[0].N}" + doc: "Shift left" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vshl, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [shl, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, '3'] + - [int8x16_t, '3'] + - [int16x4_t, '4'] + - [int16x8_t, '4'] + - [int32x2_t, '5'] + - [int32x4_t, '5'] + - [uint8x8_t, '3'] + - [uint8x16_t, '3'] + - [uint16x4_t, '4'] + - [uint16x8_t, '4'] + - [uint32x2_t, '5'] + - [uint32x4_t, '5'] + - [int64x1_t, '6'] + - [int64x2_t, '6'] + - [uint64x1_t, '6'] + - [uint64x2_t, '6'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[1]}"]] + - FnCall: + - simd_shl + - - a + - FnCall: ["vdup{neon_type[0].N}", ['N as _']] + + - name: "vsra{neon_type[0].N}" + doc: "Unsigned shift right and accumulate" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vsra, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [usra, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, '8'] + - [uint8x16_t, '8'] + - [uint16x4_t, '16'] + - [uint16x8_t, '16'] + - [uint32x2_t, '32'] + - [uint32x4_t, '32'] + - [uint64x1_t, '64'] + - [uint64x2_t, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[1]}']] + - FnCall: + - simd_add + - - a + - FnCall: ["vshr{neon_type[0].N}::", [b]] + + - name: "vrsra{neon_type[0].N}" + doc: "Unsigned rounding shift right and accumulate" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsra, 'N = 2']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ursra, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint8x8_t, '8'] + - [uint8x16_t, '8'] + - [uint16x4_t, '16'] + - [uint16x8_t, '16'] + - [uint32x2_t, '32'] + - [uint32x4_t, '32'] + - [uint64x1_t, '64'] + - [uint64x2_t, '64'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[1]}']] + - FnCall: + - simd_add + - - a + - FnCall: ["vrshr{neon_type[0].N}::", [b]] + + - name: "vqrshrn_n_{neon_type[0]}" + doc: "Unsigned signed saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] + - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] + - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']] + - LLVMLink: + name: "vqrshrn{neon_type[0].N}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqrshiftnu.{neon_type[1]}" + arch: arm + - FnCall: ["_vqrshrn{neon_type[0].N}", ["a.as_signed()", "{type[3]}"]] + + - name: "vqrshrn_n_{neon_type[0]}" + doc: "Unsigned signed saturating rounded shift right narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-not-arm + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [uqrshrn, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t, '8'] + - [uint32x4_t, uint16x4_t, '16'] + - [uint64x2_t, uint32x2_t, '32'] + compose: + - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']] + - LLVMLink: + name: "vqrshrn_n_{neon_type[0]}" + arguments: + - "a: {neon_type[0]}" + - "n: i32" + links: + - link: "llvm.aarch64.neon.uqrshrn.{neon_type[1]}" + arch: aarch64,arm64ec + - FnCall: ["_vqrshrn_n_{neon_type[0]}", ["a.as_signed()", N]] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to unsigned fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vcvt]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzu]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - LLVMLink: + name: "vcvt{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.fptoui.sat.{neon_type[1]}.{neon_type[0]}" + arch: arm + - link: "llvm.fptoui.sat.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vmla{neon_type[0].N}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.i16"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", int16x4_t] + - [int16x8_t, "i16", int16x8_t] + - [uint16x4_t, "u16", uint16x4_t] + - [uint16x8_t, "u16", uint16x8_t] + compose: + - FnCall: + - "vmla{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [c]] + + - name: "vmla{neon_type[0].N}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.i32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, "i32", int32x2_t] + - [int32x4_t, "i32", int32x4_t] + - [uint32x2_t, "u32", uint32x2_t] + - [uint32x4_t, "u32", uint32x4_t] + compose: + - FnCall: + - "vmla{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [c]] + + - name: "vmla{neon_type[0].N}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, "f32", float32x2_t] + - [float32x4_t, "f32", float32x4_t] + compose: + - FnCall: ["vmla{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [c]]}]] + + - name: "vmla{type[0]}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.i16"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmla{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmla{type[0]}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.i32"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mla, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmla{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmla{type[0]}" + doc: "Vector multiply accumulate with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmla.f32"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmla{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmls{neon_type[0].N}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.i16"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16", int16x4_t] + - [int16x8_t, "i16", int16x8_t] + - [uint16x4_t, "u16", uint16x4_t] + - [uint16x8_t, "u16", uint16x8_t] + compose: + - FnCall: + - "vmls{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [c]] + + - name: "vmls{neon_type[0].N}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.i32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int32x2_t, "i32", int32x2_t] + - [int32x4_t, "i32", int32x4_t] + - [uint32x2_t, "u32", uint32x2_t] + - [uint32x4_t, "u32", uint32x4_t] + compose: + - FnCall: + - "vmls{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}", [c]] + + - name: "vmls{neon_type[0].N}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, "f32", float32x2_t] + - [float32x4_t, "f32", float32x4_t] + compose: + - FnCall: ["vmls{neon_type[0].no}", [a, b, {FnCall: ["vdup{neon_type[0].N}", [c]]}]] + + - name: "vmls{type[0]}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.i16"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_u16, uint16x4_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_u16, uint16x4_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_u16, uint16x8_t, uint16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_u16, uint16x8_t, uint16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmls{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmls{type[0]}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.i32"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mls, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_u32, uint32x2_t, uint32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_u32, uint32x2_t, uint32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_u32, uint32x4_t, uint32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_u32, uint32x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmls{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmls{type[0]}" + doc: "Vector multiply subtract with scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[1]}", "c: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vmls.f32"', 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['3']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_f32, float32x2_t, float32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_f32, float32x2_t, float32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_f32, float32x4_t, float32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_f32, float32x4_t, float32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - "vmls{neon_type[1].no}" + - - a + - b + - FnCall: [simd_shuffle!, [c, c, "{type[4]}"]] + + - name: "vmul{neon_type[0].N}" + doc: "Vector multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [mul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16"] + - [int16x8_t, "i16"] + - [int32x2_t, "i32"] + - [int32x4_t, "i32"] + - [uint16x4_t, "u16"] + - [uint16x8_t, "u16"] + - [uint32x2_t, "u32"] + - [uint32x4_t, "u32"] + compose: + - FnCall: + - simd_mul + - - a + - FnCall: ["vdup{neon_type[0].N}", [b]] + + - name: "vmul{neon_type[0].N}" + doc: "Vector multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, "f32"] + - [float32x4_t, "f32"] + compose: + - FnCall: + - simd_mul + - - a + - FnCall: ["vdup{neon_type[0].N}", [b]] + + - name: "vmul{type[2]}" + doc: "Floating-point multiply" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmul, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmul, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [float32x2_t, float32x2_t, '_lane_f32', '1', '[LANE as u32, LANE as u32]'] + - [float32x2_t, float32x4_t, '_laneq_f32', '2', '[LANE as u32, LANE as u32]'] + - [float32x4_t, float32x2_t, 'q_lane_f32', '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [float32x4_t, float32x4_t, 'q_laneq_f32', '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, '{type[3]}']] + - FnCall: + - simd_mul + - - a + - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + + - name: "vqrdmulh{type[0]}" + doc: "Vector rounding saturating doubling multiply high by scalar" + arguments: ["a: {neon_type[1]}", "b: {neon_type[2]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqrdmulh, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrdmulh, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [_lane_s16, int16x4_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_laneq_s16, int16x4_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_lane_s16, int16x8_t, int16x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s16, int16x8_t, int16x8_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [_lane_s32, int32x2_t, int32x2_t, '1', '[LANE as u32, LANE as u32]'] + - [_laneq_s32, int32x2_t, int32x4_t, '2', '[LANE as u32, LANE as u32]'] + - [q_lane_s32, int32x4_t, int32x2_t, '1', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [q_laneq_s32, int32x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - Let: [b, "{neon_type[1]}", {FnCall: [simd_shuffle!, [b, b, '{type[4]}']]}] + - FnCall: ["vqrdmulh{neon_type[1].no}", [a, b]] + + - name: "vqrdmulh{neon_type[0].N}" + doc: "Vector saturating rounding doubling multiply high with scalar" + arguments: ["a: {neon_type[0]}", "b: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqrdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqrdmulh]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [int16x4_t, "i16"] + - [int16x8_t, "i16"] + - [int32x2_t, "i32"] + - [int32x4_t, "i32"] + compose: + - FnCall: + - "vqrdmulh{neon_type[0].no}" + - - a + - FnCall: ["vdup{neon_type[0].N}", [b]] + + - name: "vclt{neon_type[0].no}" + doc: "Floating-point compare less than" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcgt.f32"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcmgt]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, uint32x2_t] + - [float32x4_t, uint32x4_t] + compose: + - FnCall: [simd_lt, [a, b]] + + - name: "vabdl_{neon_type[0]}" + doc: "Unsigned Absolute difference Long" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vabdl.{neon_type[0]}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uabdl]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint8x8_t, uint16x8_t] + - [uint16x4_t, uint32x4_t] + - [uint32x2_t, uint64x2_t] + compose: + - FnCall: [simd_cast, [{FnCall: ["vabd_{neon_type[0]}", [a, b]]}]] + + - name: "vmull_lane{neon_type[1].no}" + doc: "Vector long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmull, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [smull, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int16x4_t, int16x4_t, int32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int16x4_t, int16x8_t, int32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [int32x2_t, int32x2_t, int64x2_t, '1', '[LANE as u32, LANE as u32]'] + - [int32x2_t, int32x4_t, int64x2_t, '2', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmull_{neon_type[0]}" + - - a + - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + + - name: "vmull_lane{neon_type[1].no}" + doc: "Vector long multiply by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[2]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vmull, 'LANE = 1']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [umull, 'LANE = 1']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [uint16x4_t, uint16x4_t, uint32x4_t, '2', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint16x4_t, uint16x8_t, uint32x4_t, '3', '[LANE as u32, LANE as u32, LANE as u32, LANE as u32]'] + - [uint32x2_t, uint32x2_t, uint64x2_t, '1', '[LANE as u32, LANE as u32]'] + - [uint32x2_t, uint32x4_t, uint64x2_t, '2', '[LANE as u32, LANE as u32]'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[3]}"]] + - FnCall: + - "vmull_{neon_type[0]}" + - - a + - FnCall: [simd_shuffle!, [b, b, "{type[4]}"]] + + - name: "vfms{neon_type[0].N}" + doc: "Floating-point fused Multiply-subtract to accumulator(vector)" + arguments: ["a: {neon_type[0]}", "b: {neon_type[0]}", "c: {type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "vfp4"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vfms]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fmls]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, "f32"] + - [float32x4_t, "f32"] + compose: + - FnCall: + - "vfms{neon_type[0].no}" + - - a + - b + - FnCall: ["vdup{neon_type[0].N}_vfp4", [c]] + + - name: "vqdmulh{neon_type[0].laneq_nox}" + doc: "Vector saturating doubling multiply high by scalar" + arguments: ["a: {neon_type[0]}", "b: {neon_type[1]}"] + return_type: "{neon_type[0]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqdmulh, 'LANE = 0']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [sqdmulh, 'LANE = 0']]}]] + - FnCall: [rustc_legacy_const_generics, ['2']] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + static_defs: ['const LANE: i32'] + safety: + unsafe: [neon] + types: + - [int16x8_t, int16x8_t, '3'] + - [int16x4_t, int16x8_t, '3'] + - [int32x4_t, int32x4_t, '2'] + - [int32x2_t, int32x4_t, '2'] + compose: + - FnCall: [static_assert_uimm_bits!, [LANE, "{type[2]}"]] + - FnCall: + - "vqdmulh{neon_type[0].no}" + - - a + - FnCall: + - "vdup{neon_type[0].N}" + - - FnCall: [simd_extract!, [b, 'LANE as u32']] + + - name: "vrecpe{neon_type.no}" + doc: "Unsigned reciprocal estimate" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrecpe]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [urecpe]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "vrecpe{neon_type.no}" + links: + - link: "llvm.arm.neon.vrecpe.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.urecpe.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrsqrte{neon_type.no}" + doc: "Unsigned reciprocal square root estimate" + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsqrte]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ursqrte]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint32x2_t + - uint32x4_t + compose: + - LLVMLink: + name: "vrsqrte{neon_type.no}" + links: + - link: "llvm.arm.neon.vrsqrte.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.ursqrte.{neon_type}" + arch: aarch64,arm64ec + + - name: "vrsqrte{neon_type.no}" + doc: "Reciprocal square-root estimate." + arguments: ["a: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vrsqrte]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [frsqrte]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - float32x2_t + - float32x4_t + compose: + - LLVMLink: + name: "vrsqrte{neon_type.no}" + links: + - link: "llvm.arm.neon.vrsqrte.{neon_type}" + arch: arm + - link: "llvm.aarch64.neon.frsqrte.{neon_type}" + arch: aarch64,arm64ec + + - name: "vqshlu{neon_type[0].N}" + doc: "Signed saturating shift left unsigned" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - *target-is-arm + - *enable-v7 + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vqshlu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] + - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] + - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }'] + - [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }'] + - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] + - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }'] + - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }'] + - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] + - LLVMLink: + name: "vqshlu{neon_type[0].N}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.arm.neon.vqshiftsu.{neon_type[0]}" + arch: arm + - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"]] + + - name: "vqshlu{neon_type[0].N}" + doc: "Signed saturating shift left unsigned" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [sqshlu, 'N = 2']]}]] + - FnCall: [rustc_legacy_const_generics, ['1']] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + static_defs: ['const N: i32'] + safety: + unsafe: [neon] + types: + - [int8x8_t, uint8x8_t, '3', 'const { int8x8_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] + - [int16x4_t, uint16x4_t, '4', 'const { int16x4_t([N as i16, N as i16, N as i16, N as i16]) }'] + - [int32x2_t, uint32x2_t, '5', 'const { int32x2_t([N as i32, N as i32]) }'] + - [int64x1_t, uint64x1_t, '6', 'const { int64x1_t([N as i64]) }'] + - [int8x16_t, uint8x16_t, '3', 'const { int8x16_t([N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8, N as i8]) }'] + - [int16x8_t, uint16x8_t, '4', 'const { int16x8_t([N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16, N as i16]) }'] + - [int32x4_t, uint32x4_t, '5', 'const { int32x4_t([N as i32, N as i32, N as i32, N as i32]) }'] + - [int64x2_t, uint64x2_t, '6', 'const { int64x2_t([N as i64, N as i64]) }'] + compose: + - FnCall: [static_assert_uimm_bits!, [N, "{type[2]}"]] + - LLVMLink: + name: "vqshlu{neon_type[0].N}" + arguments: + - "a: {neon_type[0]}" + - "n: {neon_type[0]}" + links: + - link: "llvm.aarch64.neon.sqshlu.{neon_type[0]}" + arch: aarch64,arm64ec + - FnCall: ["_vqshlu{neon_type[0].N}", [a, "{type[3]}"]] + + - name: "vcvt{neon_type[1].no}_{neon_type[0]}" + doc: "Floating-point convert to signed fixed-point, rounding toward zero" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vcvt]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [fcvtzs]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [float32x2_t, int32x2_t] + - [float32x4_t, int32x4_t] + compose: + - LLVMLink: + name: "vcvt{neon_type[1].no}_{neon_type[0]}" + links: + - link: "llvm.fptosi.sat.{neon_type[1]}.{neon_type[0]}" + arch: arm + - link: "llvm.fptosi.sat.{neon_type[1]}.{neon_type[0]}" + arch: aarch64,arm64ec + + - name: "vqmovn_{neon_type[0]}" + doc: "Unsigned saturating extract narrow" + arguments: ["a: {neon_type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vqmovn]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [uqxtn]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - [uint16x8_t, uint8x8_t] + - [uint32x4_t, uint16x4_t] + - [uint64x2_t, uint32x2_t] + compose: + - LLVMLink: + name: "vqmovn_{neon_type[1]}" + links: + - link: "llvm.arm.neon.vqmovnu.{neon_type[1]}" + arch: arm + - link: "llvm.aarch64.neon.uqxtn.{neon_type[1]}" + arch: aarch64,arm64ec + + - name: "vcle{neon_type.no}" + doc: "Compare unsigned less than or equal" + arguments: ["a: {neon_type}", "b: {neon_type}"] + return_type: "{neon_type}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, ['"vcge.{neon_type}"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [cmhs]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - uint8x8_t + - uint8x16_t + - uint16x4_t + - uint16x8_t + - uint32x2_t + - uint32x4_t + compose: + - FnCall: [simd_le, [a, b]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [vld4]]}]] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x4_t, int8x8_t, '1'] + - ["*const i16", int16x4x4_t, int16x4_t, '2'] + - ["*const i32", int32x2x4_t, int32x2_t, '4'] + - ["*const i8", int8x16x4_t, int8x16_t, '1'] + - ["*const i16", int16x8x4_t, int16x8_t, '2'] + - ["*const i32", int32x4x4_t, int32x4_t, '4'] + - ["*const f32", float32x2x4_t, float32x2_t, '4'] + - ["*const f32", float32x4x4_t, float32x4_t, '4'] + compose: + - LLVMLink: + name: "vld4{neon_type[1].dup_nox}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld4dup.{neon_type[2]}.p0i8" + arch: arm + - FnCall: ["_vld4{neon_type[1].dup_nox}", ['a as *const i8', "{type[3]}"]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, [{FnCall: [not, ['target_arch = "arm"']]}]] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']] + safety: + unsafe: [neon] + types: + - ["*const i8", int8x8x4_t, int8x8_t, 'p0i8'] + - ["*const i16", int16x4x4_t, int16x4_t, 'p0i16'] + - ["*const i32", int32x2x4_t, int32x2_t, 'p0i32'] + - ["*const i8", int8x16x4_t, int8x16_t, 'p0i8'] + - ["*const i16", int16x8x4_t, int16x8_t, 'p0i16'] + - ["*const i32", int32x4x4_t, int32x4_t, 'p0i32'] + - ["*const i64", int64x1x4_t, int64x1_t, 'p0i64'] + - ["*const f32", float32x2x4_t, float32x2_t, 'p0f32'] + - ["*const f32", float32x4x4_t, float32x4_t, 'p0f32'] + compose: + - LLVMLink: + name: "vld4{neon_type[1].dup_nox}" + arguments: + - "ptr: {type[0]}" + links: + - link: "llvm.aarch64.neon.ld4r.{neon_type[2]}.{type[3]}" + arch: aarch64,arm64ec + - FnCall: ["_vld4{neon_type[1].dup_nox}", ['a as _']] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg, ['target_arch = "arm"']] + - FnCall: [target_feature, ['enable = "neon,v7"']] + - FnCall: [cfg_attr, [test, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']] + safety: + unsafe: [neon] + types: + - ["*const i64", int64x1x4_t] + compose: + - LLVMLink: + name: "vld4{neon_type[1].dup_nox}" + arguments: + - "ptr: *const i8" + - "size: i32" + links: + - link: "llvm.arm.neon.vld4dup.v1i64.p0i8" + arch: arm + - FnCall: ["_vld4{neon_type[1].dup_nox}", ['a as *const i8', '8']] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [vld4]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*const u8", uint8x8x4_t, int8x8x4_t] + - ["*const u16", uint16x4x4_t, int16x4x4_t] + - ["*const u32", uint32x2x4_t, int32x2x4_t] + - ["*const u8", uint8x16x4_t, int8x16x4_t] + - ["*const u16", uint16x8x4_t, int16x8x4_t] + - ["*const u32", uint32x4x4_t, int32x4x4_t] + - ["*const p8", poly8x8x4_t, int8x8x4_t] + - ["*const p16", poly16x4x4_t, int16x4x4_t] + - ["*const p8", poly8x16x4_t, int8x16x4_t] + - ["*const p16", poly16x8x4_t, int16x8x4_t] + compose: + - FnCall: + - "transmute" + - - FnCall: ["vld4{neon_type[2].dup_nox}", [{FnCall: [transmute, [a]]}]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v7"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*const u64", uint64x1x4_t, int64x1x4_t] + compose: + - FnCall: + - "transmute" + - - FnCall: ["vld4{neon_type[2].dup_nox}", [{FnCall: [transmute, [a]]}]] + + - name: "vld4{neon_type[1].dup_nox}" + doc: "Load single 4-element structure and replicate to all lanes of four registers" + arguments: ["a: {type[0]}"] + return_type: "{neon_type[1]}" + attr: + - FnCall: [target_feature, ['enable = "neon,aes"']] + - FnCall: [cfg_attr, [target_arch = "arm", {FnCall: [target_feature, ['enable = "v8"']]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, 'target_arch = "arm"']]}, {FnCall: [assert_instr, [nop]]}]] + - FnCall: [cfg_attr, [{FnCall: [all, [test, {FnCall: [any, ['target_arch = "aarch64"', 'target_arch = "arm64ec"']]}]]}, {FnCall: [assert_instr, [ld4r]]}]] + - FnCall: [cfg_attr, [{FnCall: [not, ['target_arch = "arm"']]}, {FnCall: [stable, ['feature = "neon_intrinsics"', 'since = "1.59.0"']]}]] + - FnCall: [cfg_attr, ['target_arch = "arm"', {FnCall: [unstable, ['feature = "stdarch_arm_neon_intrinsics"', 'issue = "111800"']]}]] + safety: + unsafe: [neon] + types: + - ["*const p64", poly64x1x4_t, int64x1x4_t] + compose: + - FnCall: + - "transmute" + - - FnCall: ["vld4{neon_type[2].dup_nox}", [{FnCall: [transmute, [a]]}]] + diff --git a/crates/stdarch-gen2/src/context.rs b/crates/stdarch-gen2/src/context.rs index 108f7ab706..8405428b7a 100644 --- a/crates/stdarch-gen2/src/context.rs +++ b/crates/stdarch-gen2/src/context.rs @@ -1,6 +1,6 @@ use itertools::Itertools; use serde::{Deserialize, Serialize}; -use std::collections::HashMap; +use std::{collections::HashMap, usize}; use crate::{ expression::Expression, @@ -71,17 +71,31 @@ impl LocalContext { } pub fn provide_type_wildcard(&self, wildcard: &Wildcard) -> Result { - let err = || format!("wildcard {{{wildcard}}} not found"); + let err = || { + format!( + "provide_type_wildcard() wildcard {{{wildcard}}} not found for {}", + &self.signature.name.to_string() + ) + }; - let make_neon = |tuple_size| move |ty| TypeKind::make_vector(ty, false, tuple_size); + /* If the type is already a vector then we can just return the vector */ + let make_neon = |tuple_size| { + move |ty| match ty { + TypeKind::Vector(_) => Ok(ty), + _ => TypeKind::make_vector(ty, false, tuple_size), + } + }; let make_sve = |tuple_size| move |ty| TypeKind::make_vector(ty, true, tuple_size); match wildcard { Wildcard::Type(idx) => self.input.typekind(*idx).ok_or_else(err), - Wildcard::NEONType(idx, tuple_size) => self + Wildcard::NEONType(idx, tuple_size, _) => self .input .typekind(*idx) - .ok_or_else(err) + .ok_or_else(|| { + dbg!("{:?}", &self); + err() + }) .and_then(make_neon(*tuple_size)), Wildcard::SVEType(idx, tuple_size) => self .input diff --git a/crates/stdarch-gen2/src/expression.rs b/crates/stdarch-gen2/src/expression.rs index 4434ae276e..8398467958 100644 --- a/crates/stdarch-gen2/src/expression.rs +++ b/crates/stdarch-gen2/src/expression.rs @@ -1,6 +1,6 @@ use itertools::Itertools; use lazy_static::lazy_static; -use proc_macro2::{Literal, TokenStream}; +use proc_macro2::{Literal, Punct, Spacing, TokenStream}; use quote::{format_ident, quote, ToTokens, TokenStreamExt}; use regex::Regex; use serde::de::{self, MapAccess, Visitor}; @@ -48,8 +48,16 @@ impl FnCall { } pub fn is_llvm_link_call(&self, llvm_link_name: &String) -> bool { + self.is_expected_call(llvm_link_name) + } + + pub fn is_target_feature_call(&self) -> bool { + self.is_expected_call("target_feature") + } + + pub fn is_expected_call(&self, fn_call_name: &str) -> bool { if let Expression::Identifier(fn_name, IdentifierType::Symbol) = self.0.as_ref() { - &fn_name.to_string() == llvm_link_name + &fn_name.to_string() == fn_call_name } else { false } @@ -128,6 +136,8 @@ pub enum Expression { SvUndef, /// Multiplication Multiply(Box, Box), + /// Xor + Xor(Box, Box), /// Converts the specified constant to the specified type's kind ConvertConst(TypeKind, i32), /// Yields the given type in the Rust representation @@ -149,7 +159,7 @@ impl Expression { ex.pre_build(ctx) } Self::CastAs(ex, _) => ex.pre_build(ctx), - Self::Multiply(lhs, rhs) => { + Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => { lhs.pre_build(ctx)?; rhs.pre_build(ctx) } @@ -223,7 +233,7 @@ impl Expression { ex.build(intrinsic, ctx) } Self::CastAs(ex, _) => ex.build(intrinsic, ctx), - Self::Multiply(lhs, rhs) => { + Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => { lhs.build(intrinsic, ctx)?; rhs.build(intrinsic, ctx) } @@ -279,7 +289,7 @@ impl Expression { exp.requires_unsafe_wrapper(ctx_fn) } Self::Array(exps) => exps.iter().any(|exp| exp.requires_unsafe_wrapper(ctx_fn)), - Self::Multiply(lhs, rhs) => { + Self::Multiply(lhs, rhs) | Self::Xor(lhs, rhs) => { lhs.requires_unsafe_wrapper(ctx_fn) || rhs.requires_unsafe_wrapper(ctx_fn) } Self::CastAs(exp, _ty) => exp.requires_unsafe_wrapper(ctx_fn), @@ -413,7 +423,26 @@ impl ToTokens for Expression { tokens.append_all(quote! { let #var_ident: #ty = #exp }) } Self::Assign(var_name, exp) => { - let var_ident = format_ident!("{}", var_name); + /* If we are dereferencing a variable to assign a value \ + * the 'format_ident!' macro does not like the asterix */ + let var_name_str: &str; + + if let Some(ch) = var_name.chars().nth(0) { + /* Manually append the asterix and split out the rest of + * the variable name */ + if ch == '*' { + tokens.append(Punct::new('*', Spacing::Alone)); + var_name_str = &var_name[1..var_name.len()]; + } else { + var_name_str = var_name.as_str(); + } + } else { + /* Should not be reached as you cannot have a variable + * without a name */ + panic!("Invalid variable name, must be at least one character") + } + + let var_ident = format_ident!("{}", var_name_str); tokens.append_all(quote! { #var_ident = #exp }) } Self::MacroCall(name, ex) => { @@ -434,7 +463,7 @@ impl ToTokens for Expression { identifier .to_string() .parse::() - .expect("invalid syntax") + .expect(format!("invalid syntax: {:?}", self).as_str()) .to_tokens(tokens); } Self::IntConstant(n) => tokens.append(Literal::i32_unsuffixed(*n)), @@ -449,6 +478,7 @@ impl ToTokens for Expression { } Self::SvUndef => tokens.append_all(quote! { simd_reinterpret(()) }), Self::Multiply(lhs, rhs) => tokens.append_all(quote! { #lhs * #rhs }), + Self::Xor(lhs, rhs) => tokens.append_all(quote! { #lhs ^ #rhs }), Self::Type(ty) => ty.to_tokens(tokens), _ => unreachable!("{self:?} cannot be converted to tokens."), } diff --git a/crates/stdarch-gen2/src/fn_suffix.rs b/crates/stdarch-gen2/src/fn_suffix.rs new file mode 100644 index 0000000000..9f7827776e --- /dev/null +++ b/crates/stdarch-gen2/src/fn_suffix.rs @@ -0,0 +1,308 @@ +use std::fmt::{self}; + +/* This file is acting as a bridge between the old neon types and how they + * have a fairly complex way of picking suffixes and the new world. If possible + * it would be good to clean this up. At least it is self contained and the + * logic simple */ +use crate::typekinds::{BaseType, BaseTypeKind, TypeKind, VectorType}; +use serde::{Deserialize, Serialize}; + +use std::str::FromStr; + +#[allow(clippy::enum_variant_names)] +#[derive(Debug, Clone, Copy, Hash, PartialEq, Eq, Deserialize, Serialize)] +pub enum SuffixKind { + Normal, + Base, + NoQ, + NSuffix, + NoQNSuffix, + DupNox, + Dup, + /* Get the number of lanes or panic if there are not any Lanes */ + Lane, + Rot270, + Rot270Lane, + Rot270LaneQ, + Rot180, + Rot180Lane, + Rot180LaneQ, + Rot90, + Rot90Lane, + Rot90LaneQ, + /* Force the type to be unsigned */ + Unsigned, + Tuple, + NoX, + BaseByteSize, + LaneNoX, + LaneQNoX, +} + +pub fn type_to_size(str_type: &str) -> i32 { + match str_type { + "int8x8_t" | "int8x16_t" | "i8" | "s8" | "uint8x8_t" | "uint8x16_t" | "u8" + | "poly8x8_t" | "poly8x16_t" => 8, + "int16x4_t" | "int16x8_t" | "i16" | "s16" | "uint16x4_t" | "uint16x8_t" | "u16" + | "float16x4_t" | "float16x8_t" | "_f16" | "poly16x4_t" | "poly16x8_t" => 16, + "int32x2_t" | "int32x4_t" | "i32" | "s32" | "uint32x2_t" | "uint32x4_t" | "u32" + | "float32x2_t" | "float32x4_t" | "f32" => 32, + "int64x1_t" | "int64x2_t" | "i64" | "s64" | "uint64x1_t" | "uint64x2_t" | "u64" + | "float64x1_t" | "float64x2_t" | "f64" | "poly64x1_t" | "poly64x2_t" | "p64" => 64, + "p128" => 128, + _ => panic!("unknown type: {str_type}"), + } +} + +fn neon_get_base_and_char(ty: &VectorType) -> (u32, char, bool) { + let lanes = ty.lanes(); + match ty.base_type() { + BaseType::Sized(BaseTypeKind::Float, size) => (*size, 'f', *size * lanes == 128), + BaseType::Sized(BaseTypeKind::Int, size) => (*size, 's', *size * lanes == 128), + BaseType::Sized(BaseTypeKind::UInt, size) => (*size, 'u', *size * lanes == 128), + BaseType::Sized(BaseTypeKind::Poly, size) => (*size, 'p', *size * lanes == 128), + _ => panic!("Unhandled {:?}", ty), + } +} + +/* @TODO + * for the chained enum types we can safely delete them as we can index the + * types array */ +pub fn make_neon_suffix(type_kind: TypeKind, suffix_kind: SuffixKind) -> String { + match type_kind { + TypeKind::Vector(ty) => { + let tuple_size = ty.tuple_size().map_or(0, |t| t.to_int()); + let (base_size, prefix_char, requires_q) = neon_get_base_and_char(&ty); + let lanes = ty.lanes(); + match suffix_kind { + SuffixKind::Normal => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + if tuple_size > 0 { + str_suffix.push_str("_x"); + str_suffix.push_str(tuple_size.to_string().as_str()); + } + return str_suffix; + } + SuffixKind::NSuffix => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push_str("_n_"); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + return str_suffix; + } + + SuffixKind::NoQ => format!("_{}{}", prefix_char, base_size), + SuffixKind::NoQNSuffix => format!("_n{}{}", prefix_char, base_size), + + SuffixKind::Unsigned => { + let t = type_kind.to_string(); + if t.starts_with("u") { + return t; + } + return format!("u{}", t); + } + SuffixKind::Lane => { + if lanes == 0 { + panic!("type {} has no lanes!", type_kind.to_string()) + } else { + format!("{}", lanes) + } + } + SuffixKind::Tuple => { + if tuple_size == 0 { + panic!("type {} has no lanes!", type_kind.to_string()) + } else { + format!("{}", tuple_size) + } + } + SuffixKind::Base => base_size.to_string(), + SuffixKind::NoX => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + return str_suffix; + } + SuffixKind::Dup => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push_str("dup_"); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + if tuple_size > 0 { + str_suffix.push_str("_x"); + str_suffix.push_str(tuple_size.to_string().as_str()); + } + return str_suffix; + } + SuffixKind::DupNox => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push_str("dup_"); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + return str_suffix; + } + SuffixKind::LaneNoX => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push_str("lane_"); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + return str_suffix; + } + SuffixKind::LaneQNoX => { + let mut str_suffix: String = String::new(); + if requires_q { + str_suffix.push('q'); + } + str_suffix.push('_'); + str_suffix.push_str("laneq_"); + str_suffix.push(prefix_char); + str_suffix.push_str(base_size.to_string().as_str()); + return str_suffix; + } + SuffixKind::Rot270 => { + if requires_q { + return format!("q_rot270_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot270_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot270Lane => { + if requires_q { + return format!("q_rot270_lane_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot270_lane_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot270LaneQ => { + if requires_q { + return format!("q_rot270_laneq_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot270_laneq_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot180 => { + if requires_q { + return format!("q_rot180_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot180_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot180Lane => { + if requires_q { + return format!("q_rot180_lane_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot180_lane_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot180LaneQ => { + if requires_q { + return format!("q_rot180_laneq_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot180_laneq_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot90 => { + if requires_q { + return format!("q_rot90_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot90_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot90Lane => { + if requires_q { + return format!("q_rot90_lane_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot90_lane_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::Rot90LaneQ => { + if requires_q { + return format!("q_rot90_laneq_{}{}", prefix_char, base_size.to_string()); + } + return format!("_rot90_laneq_{}{}", prefix_char, base_size.to_string()); + } + SuffixKind::BaseByteSize => format!("{}", base_size / 8), + } + } + _ => panic!("Cannot only make neon vector types suffixed"), + } +} + +impl FromStr for SuffixKind { + type Err = String; + + fn from_str(s: &str) -> Result { + match s { + "no" => Ok(SuffixKind::Normal), + "noq" => Ok(SuffixKind::NoQ), + "N" => Ok(SuffixKind::NSuffix), + "noq_N" => Ok(SuffixKind::NoQNSuffix), + "dup_nox" => Ok(SuffixKind::DupNox), + "dup" => Ok(SuffixKind::Dup), + "lane" => Ok(SuffixKind::Lane), + "base" => Ok(SuffixKind::Base), + "tuple" => Ok(SuffixKind::Tuple), + "rot270" => Ok(SuffixKind::Rot270), + "rot270_lane" => Ok(SuffixKind::Rot270Lane), + "rot270_laneq" => Ok(SuffixKind::Rot270LaneQ), + "rot90" => Ok(SuffixKind::Rot90), + "rot90_lane" => Ok(SuffixKind::Rot90Lane), + "rot90_laneq" => Ok(SuffixKind::Rot90LaneQ), + "rot180" => Ok(SuffixKind::Rot180), + "rot180_lane" => Ok(SuffixKind::Rot180LaneQ), + "rot180_laneq" => Ok(SuffixKind::Rot180LaneQ), + "u" => Ok(SuffixKind::Unsigned), + "nox" => Ok(SuffixKind::NoX), + "base_byte_size" => Ok(SuffixKind::BaseByteSize), + "lane_nox" => Ok(SuffixKind::LaneNoX), + "laneq_nox" => Ok(SuffixKind::LaneQNoX), + _ => Err(format!("unknown suffix type: {}", s)), + } + } +} + +impl fmt::Display for SuffixKind { + fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result { + match self { + SuffixKind::Normal => write!(f, "normal"), + SuffixKind::NoQ => write!(f, "NoQ"), + SuffixKind::NSuffix => write!(f, "NSuffix"), + SuffixKind::NoQNSuffix => write!(f, "NoQNSuffix"), + SuffixKind::DupNox => write!(f, "DupNox"), + SuffixKind::Dup => write!(f, "Dup",), + SuffixKind::Lane => write!(f, "Lane"), + SuffixKind::LaneNoX => write!(f, "LaneNoX"), + SuffixKind::LaneQNoX => write!(f, "LaneQNoX"), + SuffixKind::Base => write!(f, "Base"), + SuffixKind::Rot270 => write!(f, "Rot270",), + SuffixKind::Rot270Lane => write!(f, "Rot270Lane"), + SuffixKind::Rot270LaneQ => write!(f, "Rot270LaneQ"), + SuffixKind::Rot90 => write!(f, "Rot90",), + SuffixKind::Rot90Lane => write!(f, "Rot90Lane"), + SuffixKind::Rot90LaneQ => write!(f, "Rot90LaneQ"), + SuffixKind::Rot180 => write!(f, "Rot180",), + SuffixKind::Rot180Lane => write!(f, "Rot180Lane"), + SuffixKind::Rot180LaneQ => write!(f, "Rot180LaneQ"), + SuffixKind::Unsigned => write!(f, "Unsigned"), + SuffixKind::Tuple => write!(f, "Tuple"), + SuffixKind::NoX => write!(f, "NoX"), + SuffixKind::BaseByteSize => write!(f, "BaseByteSize"), + } + } +} diff --git a/crates/stdarch-gen2/src/intrinsic.rs b/crates/stdarch-gen2/src/intrinsic.rs index d05b71e44d..4a973691b1 100644 --- a/crates/stdarch-gen2/src/intrinsic.rs +++ b/crates/stdarch-gen2/src/intrinsic.rs @@ -4,7 +4,8 @@ use quote::{format_ident, quote, ToTokens, TokenStreamExt}; use serde::{Deserialize, Serialize}; use serde_with::{DeserializeFromStr, SerializeDisplay}; use std::collections::{HashMap, HashSet}; -use std::fmt; +use std::fmt::{self}; +use std::num::ParseIntError; use std::ops::RangeInclusive; use std::str::FromStr; @@ -16,6 +17,7 @@ use crate::{ assert_instr::InstructionAssertionMethod, context::{self, ArchitectureSettings, Context, LocalContext, VariableType}, expression::{Expression, FnCall, IdentifierType}, + fn_suffix::{type_to_size, SuffixKind}, input::IntrinsicInput, matching::{KindMatchable, SizeMatchable}, typekinds::*, @@ -238,7 +240,10 @@ impl Constraint { .map_err(|_| format!("the minimum value `{min}` is not a valid number"))?; let max: i32 = max .parse() - .map_err(|_| format!("the maximum value `{max}` is not a valid number"))?; + .or_else(|_| Ok(type_to_size(max.as_str()))) + .map_err(|_: ParseIntError| { + format!("the maximum value `{max}` is not a valid number") + })?; *self = Self::RangeI32 { variable: variable.to_owned(), range: SizeMatchable::Matched(RangeInclusive::new(min, max)), @@ -282,6 +287,9 @@ pub struct Signature { /// Function return type, leave unset for void pub return_type: Option, + /// For some neon intrinsics we want to modify the suffix of the function name + pub suffix_type: Option, + /// List of static definitions, leave unset of empty if not required #[serde(default)] pub static_defs: Vec, @@ -312,7 +320,11 @@ impl Signature { } pub fn build(&mut self, ctx: &LocalContext) -> context::Result { - self.name.build_acle(ctx)?; + if self.name_has_neon_suffix() { + self.name.build_neon_intrinsic_signature(ctx)?; + } else { + self.name.build_acle(ctx)?; + } if let Some(ref mut return_type) = self.return_type { if let Some(w) = return_type.clone().wildcard() { @@ -342,6 +354,20 @@ impl Signature { pub fn doc_name(&self) -> String { self.name.to_string() } + + fn name_has_neon_suffix(&self) -> bool { + for part in self.name.wildcards() { + let has_suffix = match part { + Wildcard::NEONType(_, _, suffix_type) => suffix_type.is_some(), + _ => false, + }; + + if has_suffix { + return true; + } + } + false + } } impl ToTokens for Signature { @@ -380,18 +406,46 @@ impl ToTokens for Signature { } } -#[derive(Debug, Clone)] +#[derive(Debug, Clone, Serialize, Deserialize)] pub struct LLVMLinkAttribute { + /// Either one architecture or a comma separated list of architectures with NO spaces pub arch: String, - pub link: String, + pub link: WildString, } impl ToTokens for LLVMLinkAttribute { fn to_tokens(&self, tokens: &mut TokenStream) { let LLVMLinkAttribute { arch, link } = self; - tokens.append_all(quote! { - #[cfg_attr(target_arch = #arch, link_name = #link)] - }) + let link = link.to_string(); + let archs: Vec<&str> = arch.split(',').collect(); + let arch_len = archs.len(); + + if arch_len == 1 { + tokens.append_all(quote! { + #[cfg_attr(target_arch = #arch, link_name = #link)] + }) + } else { + tokens.append(Punct::new('#', Spacing::Alone)); + tokens.append(Punct::new('[', Spacing::Alone)); + tokens.append_all(quote! { cfg_attr }); + tokens.append(Punct::new('(', Spacing::Alone)); + tokens.append_all(quote! { any }); + tokens.append(Punct::new('(', Spacing::Alone)); + let mut i = 0; + while i < arch_len { + let arch = archs[i].to_string(); + tokens.append_all(quote! { target_arch = #arch }); + if i + 1 != arch_len { + tokens.append(Punct::new(',', Spacing::Alone)); + } + i += 1; + } + tokens.append(Punct::new(')', Spacing::Alone)); + tokens.append(Punct::new(',', Spacing::Alone)); + tokens.append_all(quote! { link_name = #link }); + tokens.append(Punct::new(')', Spacing::Alone)); + tokens.append(Punct::new(']', Spacing::Alone)); + } } } @@ -406,10 +460,9 @@ pub struct LLVMLink { /// LLVM link signature return type, leave unset if it inherits from intrinsic's signature pub return_type: Option, - /// **Internal use only. Do not set.** + /// **This will be set automatically if not set** /// Attribute LLVM links for the function. First element is the architecture it targets, /// second element is the LLVM link itself. - #[serde(skip)] pub links: Option>, /// **Internal use only. Do not set.** @@ -453,6 +506,7 @@ impl LLVMLink { .return_type .clone() .or_else(|| ctx.local.signature.return_type.clone()), + suffix_type: None, static_defs: vec![], is_predicate_specific: ctx.local.signature.is_predicate_specific, predicate_needs_conversion: false, @@ -467,16 +521,25 @@ impl LLVMLink { .insert(Wildcard::LLVMLink, sig.fn_name().to_string()); self.signature = Some(Box::new(sig)); - self.links = Some( - ctx.global - .arch_cfgs - .iter() - .map(|cfg| LLVMLinkAttribute { - arch: cfg.arch_name.to_owned(), - link: self.resolve(cfg), - }) - .collect_vec(), - ); + + if let Some(ref mut links) = self.links { + links.iter_mut().for_each(|ele| { + ele.link + .build(&ctx.local, TypeRepr::LLVMMachine) + .expect("Failed to transform to LLVMMachine representation"); + }); + } else { + self.links = Some( + ctx.global + .arch_cfgs + .iter() + .map(|cfg| LLVMLinkAttribute { + arch: cfg.arch_name.to_owned(), + link: self.resolve(cfg).into(), + }) + .collect_vec(), + ); + } Ok(()) } @@ -603,8 +666,8 @@ impl ToTokens for LLVMLink { let signature = self.signature.as_ref().unwrap(); let links = self.links.as_ref().unwrap(); tokens.append_all(quote! { - extern "C" { - #(#links),* + extern "unadjusted" { + #(#links)* #signature; } }) @@ -725,6 +788,7 @@ pub enum UnsafetyComment { Dereference(GovernedBy), UnpredictableOnFault, NonTemporal, + Neon, NoProvenance(String), } @@ -759,6 +823,7 @@ impl fmt::Display for UnsafetyComment { fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { match self { Self::Custom(s) => s.fmt(f), + Self::Neon => write!(f, "Neon instrinsic unsafe"), Self::Uninitialized => write!( f, "This creates an uninitialized value, and may be unsound (like \ @@ -834,13 +899,15 @@ pub struct Intrinsic { /// behaviour is all unsigned types are converted to signed) #[serde(default)] pub defer_to_signed_only_indices: HashSet, - pub assert_instr: Vec, + pub assert_instr: Option>, /// Whether we should generate a test for this intrinsic #[serde(default)] pub test: Test, /// Primary base type, used for instruction assertion. #[serde(skip)] pub base_type: Option, + /// Attributes for the function + pub attr: Option>, } impl Intrinsic { @@ -930,6 +997,21 @@ impl Intrinsic { } }; + if variant.attr.is_none() && variant.assert_instr.is_none() { + panic!("Error: {} is missing both 'attr' and 'assert_instr' fields. You must either manually declare the attributes using the 'attr' field or use 'assert_instr'!", variant.signature.name.to_string()); + } + + if variant.attr.is_some() { + let attr: &Vec = &variant.attr.clone().unwrap(); + let mut expanded_attr: Vec = Vec::new(); + for idx in 0..attr.len() { + let mut ex = attr[idx].clone(); + ex.build(&variant, &mut ctx)?; + expanded_attr.push(ex); + } + variant.attr = Some(expanded_attr); + } + variant.post_build(&mut ctx)?; if let Some(n_variant_op) = ctx.local.n_variant_op().cloned() { @@ -1238,9 +1320,9 @@ impl Intrinsic { } } - self.assert_instr - .iter_mut() - .try_for_each(|ai| ai.build(ctx))?; + if let Some(ref mut assert_instr) = self.assert_instr { + assert_instr.iter_mut().try_for_each(|ai| ai.build(ctx))?; + } // Prepend constraint assertions self.constraints.iter_mut().try_for_each(|c| c.build(ctx))?; @@ -1347,8 +1429,13 @@ impl Intrinsic { match (from_base_type, to_base_type) { // Use AsSigned for uint -> int (Some(BaseTypeKind::UInt), Some(BaseTypeKind::Int)) => as_signed(ex), + (Some(BaseTypeKind::Int), Some(BaseTypeKind::Int)) => ex, // Use AsUnsigned for int -> uint (Some(BaseTypeKind::Int), Some(BaseTypeKind::UInt)) => as_unsigned(ex), + (Some(BaseTypeKind::Float), Some(BaseTypeKind::Float)) => ex, + (Some(BaseTypeKind::UInt), Some(BaseTypeKind::UInt)) => ex, + (Some(BaseTypeKind::Poly), Some(BaseTypeKind::Poly)) => ex, + (None, None) => ex, _ => unreachable!("unsupported conversion case from {from_base_type:?} to {to_base_type:?} hit"), } @@ -1426,11 +1513,9 @@ impl ToTokens for Intrinsic { if let Some(doc) = &self.doc { let mut doc = vec![doc.to_string()]; - doc.push(String::new()); doc.push(format!("[Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/{})", &signature.doc_name())); if safety.has_doc_comments() { - doc.push(String::new()); doc.push("## Safety".to_string()); for comment in safety.doc_comments() { doc.push(format!(" * {comment}")); @@ -1454,14 +1539,43 @@ impl ToTokens for Intrinsic { ); } - tokens.append_all(quote! { - #[inline] - #[target_feature(enable = #target_feature)] - }); + tokens.append_all(quote! { #[inline] }); + + /* If we have manually defined attributes on the block of yaml with + * 'attr:' we want to add them */ + if let Some(attr) = &self.attr { + /* Scan to see if we have defined `FnCall: [target_feature, ['']]`*/ + if !has_target_feature_attr(attr) { + /* If not add the default one that is defined at the top of + * the yaml file. This does mean we scan the attributes vector + * twice, once to see if the `target_feature` exists and again + * to actually append the tokens. We could impose that the + * `target_feature` call has to be the first argument of the + * `attr` block */ + tokens.append_all(quote! { + #[target_feature(enable = #target_feature)] + }); + } - if !self.assert_instr.is_empty() { - InstructionAssertionsForBaseType(&self.assert_instr, &self.base_type.as_ref()) - .to_tokens(tokens) + /* Target feature will get added here */ + let attr_expressions = &mut attr.iter().peekable(); + while let Some(ex) = attr_expressions.next() { + tokens.append(Punct::new('#', Spacing::Alone)); + tokens.append(Punct::new('[', Spacing::Alone)); + ex.to_tokens(tokens); + tokens.append(Punct::new(']', Spacing::Alone)); + } + } else { + tokens.append_all(quote! { + #[target_feature(enable = #target_feature)] + }); + } + + if let Some(assert_instr) = &self.assert_instr { + if !assert_instr.is_empty() { + InstructionAssertionsForBaseType(&assert_instr, &self.base_type.as_ref()) + .to_tokens(tokens) + } } match &self.visibility { @@ -1494,5 +1608,17 @@ impl ToTokens for Intrinsic { } tokens.append(Punct::new('}', Spacing::Alone)); + tokens.append(Punct::new('\n', Spacing::Alone)); + tokens.append(Punct::new('\n', Spacing::Alone)); } } + +fn has_target_feature_attr(attrs: &[Expression]) -> bool { + attrs.iter().any(|attr| { + if let Expression::FnCall(fn_call) = attr { + fn_call.is_target_feature_call() + } else { + false + } + }) +} diff --git a/crates/stdarch-gen2/src/main.rs b/crates/stdarch-gen2/src/main.rs index 5379d18404..22bf6724b0 100644 --- a/crates/stdarch-gen2/src/main.rs +++ b/crates/stdarch-gen2/src/main.rs @@ -3,6 +3,7 @@ mod assert_instr; mod context; mod expression; +mod fn_suffix; mod input; mod intrinsic; mod load_store_tests; @@ -39,7 +40,9 @@ fn main() -> Result<(), String> { .into_iter() .map(|(input, filepath, out)| { let intrinsics = input.intrinsics.into_iter() - .map(|intrinsic| intrinsic.generate_variants(&input.ctx)) + .map(|intrinsic| { + intrinsic.generate_variants(&input.ctx) + }) .try_collect() .map(|mut vv: Vec<_>| { vv.sort_by_cached_key(|variants| { @@ -50,23 +53,26 @@ fn main() -> Result<(), String> { vv.into_iter().flatten().collect_vec() })?; - let loads = intrinsics.iter() - .filter_map(|i| { - if matches!(i.test, Test::Load(..)) { - Some(i.clone()) - } else { - None - } - }).collect(); - let stores = intrinsics.iter() - .filter_map(|i| { - if matches!(i.test, Test::Store(..)) { - Some(i.clone()) - } else { - None - } - }).collect(); - load_store_tests::generate_load_store_tests(loads, stores, out.as_ref().map(|o| make_tests_filepath(&filepath, o)).as_ref())?; + if filepath.ends_with("sve.spec.yml") || filepath.ends_with("sve2.spec.yml") { + let loads = intrinsics.iter() + .filter_map(|i| { + if matches!(i.test, Test::Load(..)) { + Some(i.clone()) + } else { + None + } + }).collect(); + let stores = intrinsics.iter() + .filter_map(|i| { + if matches!(i.test, Test::Store(..)) { + Some(i.clone()) + } else { + None + } + }).collect(); + load_store_tests::generate_load_store_tests(loads, stores, out.as_ref().map(|o| make_tests_filepath(&filepath, o)).as_ref())?; + } + Ok(( input::GeneratorInput { intrinsics, diff --git a/crates/stdarch-gen2/src/typekinds.rs b/crates/stdarch-gen2/src/typekinds.rs index 71f6297d94..7a4fed85ce 100644 --- a/crates/stdarch-gen2/src/typekinds.rs +++ b/crates/stdarch-gen2/src/typekinds.rs @@ -67,6 +67,7 @@ pub struct TypeKindOptions { f: bool, s: bool, u: bool, + p: bool, } impl TypeKindOptions { @@ -75,6 +76,7 @@ impl TypeKindOptions { BaseTypeKind::Float => self.f, BaseTypeKind::Int => self.s, BaseTypeKind::UInt => self.u, + BaseTypeKind::Poly => self.p, BaseTypeKind::Bool => false, } } @@ -90,6 +92,7 @@ impl FromStr for TypeKindOptions { b'f' => result.f = true, b's' => result.s = true, b'u' => result.u = true, + b'p' => result.p = true, _ => { return Err(format!("unknown type kind: {}", char::from(kind))); } @@ -113,6 +116,7 @@ pub enum BaseTypeKind { Int, UInt, Bool, + Poly, } #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] @@ -130,6 +134,16 @@ pub enum VectorTupleSize { Four, } +impl VectorTupleSize { + pub fn to_int(&self) -> u32 { + match self { + Self::Two => 2, + Self::Three => 3, + Self::Four => 4, + } + } +} + #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)] pub struct VectorType { base_type: BaseType, @@ -181,6 +195,7 @@ impl TypeKind { match self { Self::Base(ty) => Some(ty), Self::Pointer(tk, _) => tk.base(), + Self::Vector(ty) => Some(&ty.base_type), _ => None, } } @@ -366,22 +381,22 @@ impl PartialOrd for TypeKind { } } +impl From<&TypeKind> for usize { + fn from(ty: &TypeKind) -> Self { + match ty { + TypeKind::Base(_) => 1, + TypeKind::Pointer(_, _) => 2, + TypeKind::Vector(_) => 3, + TypeKind::Custom(_) => 4, + TypeKind::Wildcard(_) => 5, + } + } +} + impl Ord for TypeKind { fn cmp(&self, other: &Self) -> std::cmp::Ordering { use std::cmp::Ordering::*; - impl From<&TypeKind> for usize { - fn from(ty: &TypeKind) -> Self { - match ty { - TypeKind::Base(_) => 1, - TypeKind::Pointer(_, _) => 2, - TypeKind::Vector(_) => 3, - TypeKind::Custom(_) => 4, - TypeKind::Wildcard(_) => 5, - } - } - } - let self_int: usize = self.into(); let other_int: usize = other.into(); @@ -466,6 +481,14 @@ impl VectorType { pub fn cast_base_type_as(&mut self, ty: BaseType) { self.base_type = ty } + + pub fn lanes(&self) -> u32 { + self.lanes + } + + pub fn tuple_size(&self) -> Option { + self.tuple_size + } } impl FromStr for VectorType { @@ -473,7 +496,7 @@ impl FromStr for VectorType { fn from_str(s: &str) -> Result { lazy_static! { - static ref RE: Regex = Regex::new(r"^(?:(?:sv(?P(?:uint|int|bool|float)(?:\d+)?))|(?:(?P(?:uint|int|bool|float)(?:\d+)?)x(?P[0-9])))(?:x(?P2|3|4))?_t$").unwrap(); + static ref RE: Regex = Regex::new(r"^(?:(?:sv(?P(?:uint|int|bool|float)(?:\d+)?))|(?:(?P(?:uint|int|bool|poly|float)(?:\d+)?)x(?P(?:\d+)?)))(?:x(?P2|3|4))?_t$").unwrap(); } if let Some(c) = RE.captures(s) { @@ -498,12 +521,13 @@ impl FromStr for VectorType { .transpose() .unwrap(); - Ok(VectorType { + let v = Ok(VectorType { base_type, is_scalable: c.name("sv_ty").is_some(), lanes, tuple_size, - }) + }); + return v; } else { Err(format!("invalid vector type {s:#?} given")) } @@ -612,6 +636,7 @@ impl FromStr for BaseTypeKind { "float" | "f" => Ok(Self::Float), "int" | "i" => Ok(Self::Int), "uint" | "u" => Ok(Self::UInt), + "poly" | "p" => Ok(Self::Poly), "bool" | "b" => Ok(Self::Bool), _ => Err(format!("no match for {s}")), } @@ -624,9 +649,11 @@ impl ToRepr for BaseTypeKind { (TypeRepr::C, Self::Float) => "float", (TypeRepr::C, Self::Int) => "int", (TypeRepr::C, Self::UInt) => "uint", + (TypeRepr::C, Self::Poly) => "poly", (TypeRepr::Rust | TypeRepr::LLVMMachine | TypeRepr::ACLENotation, Self::Float) => "f", (TypeRepr::Rust, Self::Int) | (TypeRepr::LLVMMachine, Self::Int | Self::UInt) => "i", (TypeRepr::Rust | TypeRepr::ACLENotation, Self::UInt) => "u", + (TypeRepr::Rust | TypeRepr::LLVMMachine | TypeRepr::ACLENotation, Self::Poly) => "p", (TypeRepr::ACLENotation, Self::Int) => "s", (TypeRepr::ACLENotation, Self::Bool) => "b", (_, Self::Bool) => "bool", @@ -683,7 +710,6 @@ impl FromStr for BaseType { .map(u32::from_str) .transpose() .unwrap(); - match size { Some(size) => Ok(Self::Sized(kind, size)), None => Ok(Self::Unsized(kind)), @@ -705,6 +731,7 @@ impl ToRepr for BaseType { (Sized(_, size), SizeLiteral) if *size == 16 => "h".to_string(), (Sized(_, size), SizeLiteral) if *size == 32 => "w".to_string(), (Sized(_, size), SizeLiteral) if *size == 64 => "d".to_string(), + (Sized(_, size), SizeLiteral) if *size == 128 => "q".to_string(), (_, SizeLiteral) => unreachable!("cannot represent {self:#?} as size literal"), (Sized(Float, _) | Unsized(Float), TypeKind) => "f".to_string(), (Sized(Int, _) | Unsized(Int), TypeKind) => "s".to_string(), diff --git a/crates/stdarch-gen2/src/wildcards.rs b/crates/stdarch-gen2/src/wildcards.rs index 9d6194d517..25aa803489 100644 --- a/crates/stdarch-gen2/src/wildcards.rs +++ b/crates/stdarch-gen2/src/wildcards.rs @@ -5,6 +5,7 @@ use std::fmt; use std::str::FromStr; use crate::{ + fn_suffix::SuffixKind, predicate_forms::PredicationMask, typekinds::{ToRepr, TypeKind, TypeKindOptions, VectorTupleSize}, }; @@ -13,7 +14,7 @@ use crate::{ pub enum Wildcard { Type(Option), /// NEON type derivated by a base type - NEONType(Option, Option), + NEONType(Option, Option, Option), /// SVE type derivated by a base type SVEType(Option, Option), /// Integer representation of bitsize @@ -87,7 +88,14 @@ impl FromStr for Wildcard { let wildcard = match (wildcard_name, inputset_index, tuple_size, modifiers) { ("type", index, None, None) => Ok(Wildcard::Type(index)), - ("neon_type", index, tuple, None) => Ok(Wildcard::NEONType(index, tuple)), + ("neon_type", index, tuple, modifier) => { + if let Some(str_suffix) = modifier { + let suffix_kind = SuffixKind::from_str(str_suffix); + return Ok(Wildcard::NEONType(index, tuple, Some(suffix_kind.unwrap()))); + } else { + Ok(Wildcard::NEONType(index, tuple, None)) + } + } ("sve_type", index, tuple, None) => Ok(Wildcard::SVEType(index, tuple)), ("size", index, None, None) => Ok(Wildcard::Size(index)), ("size_minus_one", index, None, None) => Ok(Wildcard::SizeMinusOne(index)), @@ -131,7 +139,7 @@ impl FromStr for Wildcard { Ok(wildcard) } } else { - Err(format!("invalid wildcard `{s:#?}`")) + Err(format!("## invalid wildcard `{s:#?}`")) } } } @@ -141,12 +149,22 @@ impl fmt::Display for Wildcard { match self { Self::Type(None) => write!(f, "type"), Self::Type(Some(index)) => write!(f, "type[{index}]"), - Self::NEONType(None, None) => write!(f, "neon_type"), - Self::NEONType(Some(index), None) => write!(f, "neon_type[{index}]"), - Self::NEONType(None, Some(tuple_size)) => write!(f, "neon_type_x{tuple_size}"), - Self::NEONType(Some(index), Some(tuple_size)) => { + Self::NEONType(None, None, None) => write!(f, "neon_type"), + Self::NEONType(None, None, Some(suffix_kind)) => write!(f, "neon_type.{suffix_kind}"), + Self::NEONType(Some(index), None, None) => write!(f, "neon_type[{index}]"), + Self::NEONType(Some(index), None, Some(suffix_kind)) => { + write!(f, "neon_type[{index}].{suffix_kind}") + } + Self::NEONType(None, Some(tuple_size), Some(suffix_kind)) => { + write!(f, "neon_type_x{tuple_size}.{suffix_kind}") + } + Self::NEONType(None, Some(tuple_size), None) => write!(f, "neon_type_x{tuple_size}"), + Self::NEONType(Some(index), Some(tuple_size), None) => { write!(f, "neon_type_x{tuple_size}[{index}]") } + Self::NEONType(Some(index), Some(tuple_size), Some(suffix_kind)) => { + write!(f, "neon_type_x{tuple_size}[{index}].{suffix_kind}") + } Self::SVEType(None, None) => write!(f, "sve_type"), Self::SVEType(Some(index), None) => write!(f, "sve_type[{index}]"), Self::SVEType(None, Some(tuple_size)) => write!(f, "sve_type_x{tuple_size}"), diff --git a/crates/stdarch-gen2/src/wildstring.rs b/crates/stdarch-gen2/src/wildstring.rs index 1f9e6c9ada..2eb467b962 100644 --- a/crates/stdarch-gen2/src/wildstring.rs +++ b/crates/stdarch-gen2/src/wildstring.rs @@ -6,6 +6,7 @@ use std::str::pattern::Pattern; use std::{fmt, str::FromStr}; use crate::context::LocalContext; +use crate::fn_suffix::make_neon_suffix; use crate::typekinds::{ToRepr, TypeRepr}; use crate::wildcards::Wildcard; @@ -17,7 +18,7 @@ pub enum WildStringPart { /// Wildcard-able string #[derive(Debug, Clone, PartialEq, Eq, Default, SerializeDisplay, DeserializeFromStr)] -pub struct WildString(Vec); +pub struct WildString(pub Vec); impl WildString { pub fn has_wildcards(&self) -> bool { @@ -67,7 +68,7 @@ impl WildString { pub fn replace<'a, P>(&'a self, from: P, to: &str) -> WildString where - P: Pattern<'a> + Copy, + P: Pattern + Copy, { WildString( self.0 @@ -84,17 +85,62 @@ impl WildString { self.build(ctx, TypeRepr::ACLENotation) } - pub fn build(&mut self, ctx: &LocalContext, repr: TypeRepr) -> Result<(), String> { + pub fn build_neon_intrinsic_signature(&mut self, ctx: &LocalContext) -> Result<(), String> { + let repr = TypeRepr::ACLENotation; self.iter_mut().try_for_each(|wp| -> Result<(), String> { if let WildStringPart::Wildcard(w) = wp { - let value = ctx - .provide_substitution_wildcard(w) - .or_else(|_| ctx.provide_type_wildcard(w).map(|ty| ty.repr(repr)))?; - *wp = WildStringPart::String(value); + match w { + Wildcard::NEONType(_, _, ref maybe_suffix_kind) => { + if let Some(suffix_kind) = maybe_suffix_kind { + let x = ctx.provide_type_wildcard(w).unwrap(); + *wp = WildStringPart::String(make_neon_suffix(x, *suffix_kind)) + } else { + *wp = WildString::make_default_build(ctx, repr, w) + } + } + _ => *wp = WildString::make_default_build(ctx, repr, w), + } } Ok(()) }) } + + pub fn build(&mut self, ctx: &LocalContext, repr: TypeRepr) -> Result<(), String> { + match repr { + TypeRepr::ACLENotation | TypeRepr::LLVMMachine => { + self.iter_mut().try_for_each(|wp| -> Result<(), String> { + if let WildStringPart::Wildcard(w) = wp { + match w { + Wildcard::NEONType(_, _, ref maybe_suffix_kind) => { + if let Some(suffix_kind) = maybe_suffix_kind { + let x = ctx.provide_type_wildcard(w).unwrap(); + *wp = WildStringPart::String(make_neon_suffix(x, *suffix_kind)) + } else { + *wp = WildString::make_default_build(ctx, repr, w) + } + } + _ => *wp = WildString::make_default_build(ctx, repr, w), + } + } + Ok(()) + }) + } + _ => self.iter_mut().try_for_each(|wp| -> Result<(), String> { + if let WildStringPart::Wildcard(w) = wp { + *wp = WildString::make_default_build(ctx, repr, w); + } + Ok(()) + }), + } + } + + fn make_default_build(ctx: &LocalContext, repr: TypeRepr, w: &mut Wildcard) -> WildStringPart { + WildStringPart::String( + ctx.provide_substitution_wildcard(w) + .or_else(|_| ctx.provide_type_wildcard(w).map(|ty| ty.repr(repr))) + .unwrap(), + ) + } } impl From for WildString { From 067d701dfb61ad7ebf53e326042df943e2404a18 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Mon, 16 Dec 2024 14:12:00 +0000 Subject: [PATCH 4/8] Remove old ARM intrinsic generator --- Cargo.toml | 1 - crates/core_arch/src/arm_shared/neon/mod.rs | 56 +- crates/stdarch-gen-arm/Cargo.toml | 9 - crates/stdarch-gen-arm/README.md | 11 - crates/stdarch-gen-arm/neon.spec | 7852 ------------------- crates/stdarch-gen-arm/src/main.rs | 3499 --------- 6 files changed, 4 insertions(+), 11424 deletions(-) delete mode 100644 crates/stdarch-gen-arm/Cargo.toml delete mode 100644 crates/stdarch-gen-arm/README.md delete mode 100644 crates/stdarch-gen-arm/neon.spec delete mode 100644 crates/stdarch-gen-arm/src/main.rs diff --git a/Cargo.toml b/Cargo.toml index 43b6dc1ea5..d4864a24c4 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -6,7 +6,6 @@ members = [ "crates/stdarch-verify", "crates/core_arch", "crates/std_detect", - "crates/stdarch-gen-arm", "crates/stdarch-gen-loongarch", "crates/stdarch-gen2", "crates/intrinsic-test", diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index 33065b0b9d..52707f527d 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -11,63 +11,15 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::* #[cfg(test)] use stdarch_test::assert_instr; -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub trait AsUnsigned { - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] +#[unstable(feature = "stdarch_internal", issue = "none")] +pub(crate) trait AsUnsigned { type Unsigned: ?Sized; - - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] unsafe fn as_unsigned(self) -> Self::Unsigned; } -#[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") -)] -#[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") -)] -pub trait AsSigned { - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] +#[unstable(feature = "stdarch_internal", issue = "none")] +pub(crate) trait AsSigned { type Signed: ?Sized; - - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] unsafe fn as_signed(self) -> Self::Signed; } diff --git a/crates/stdarch-gen-arm/Cargo.toml b/crates/stdarch-gen-arm/Cargo.toml deleted file mode 100644 index fcbebe47a5..0000000000 --- a/crates/stdarch-gen-arm/Cargo.toml +++ /dev/null @@ -1,9 +0,0 @@ -[package] -name = "stdarch-gen-arm" -version = "0.1.0" -authors = ["Heinz Gies "] -edition = "2021" - -# See more keys and their definitions at https://doc.rust-lang.org/cargo/reference/manifest.html - -[dependencies] diff --git a/crates/stdarch-gen-arm/README.md b/crates/stdarch-gen-arm/README.md deleted file mode 100644 index fa8a7d0d2d..0000000000 --- a/crates/stdarch-gen-arm/README.md +++ /dev/null @@ -1,11 +0,0 @@ -# Neon intrinsic code generator - -A small tool that allows to quickly generate intrinsics for the NEON architecture. - -The specification for the intrinsics can be found in `neon.spec`. - -To run and re-generate the code run the following from the root of the `stdarch` crate. - -``` -OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-arm -- crates/stdarch-gen-arm/neon.spec -``` \ No newline at end of file diff --git a/crates/stdarch-gen-arm/neon.spec b/crates/stdarch-gen-arm/neon.spec deleted file mode 100644 index 8e929c7773..0000000000 --- a/crates/stdarch-gen-arm/neon.spec +++ /dev/null @@ -1,7852 +0,0 @@ -// ARM Neon intrinsic specification. -// -// This file contains the specification for a number of -// intrinsics that allows us to generate them along with -// their test cases. -// -// To the syntax of the file - it's not very intelligently parsed! -// -// # Comments -// start with AT LEAST two, or four or more slashes so // is a -// comment /////// is too. -// -// # Sections -// Sections start with EXACTLY three slashes followed -// by AT LEAST one space. Sections are used for two things: -// -// 1) they serve as the doc comment for the given intrinsics. -// 2) they reset all variables (name, fn, etc.) -// -// # Variables -// -// name - The prefix of the function, suffixes are auto -// generated by the type they get passed. -// -// fn - The function to call in rust-land. -// -// aarch64 - The intrinsic to check on aarch64 architecture. -// If this is given but no arm intrinsic is provided, -// the function will exclusively be generated for -// aarch64. -// This is used to generate both aarch64 specific and -// shared intrinsics by first only specifying th aarch64 -// variant then the arm variant. -// -// arm - The arm v7 intrinsics used to checked for arm code -// generation. All neon functions available in arm are -// also available in aarch64. If no aarch64 intrinsic was -// set they are assumed to be the same. -// Intrinsics ending with a `.` will have a size suffixes -// added (such as `i8` or `i64`) that is not sign specific -// Intrinsics ending with a `.s` will have a size suffixes -// added (such as `s8` or `u64`) that is sign specific -// -// a - First input for tests, it gets scaled to the size of -// the type. -// -// b - Second input for tests, it gets scaled to the size of -// the type. -// -// # special values -// -// TRUE - 'true' all bits are set to 1 -// FALSE - 'false' all bits are set to 0 -// FF - same as 'true' -// MIN - minimal value (either 0 or the lowest negative number) -// MAX - maximal value proper to overflow -// -// # validate -// Validates a and b against the expected result of the test. -// The special values 'TRUE' and 'FALSE' can be used to -// represent the correct NEON representation of true or -// false values. It too gets scaled to the type. -// -// Validate needs to be called before generate as it sets -// up the rules for validation that get generated for each -// type. -// # generate -// The generate command generates the intrinsics, it uses the -// Variables set and can be called multiple times while overwriting -// some of the variables. - -/// Vector bitwise and -name = vand -fn = simd_and -arm = vand -aarch64 = and -a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00 -b = 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F -validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x00 -b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -validate 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -generate int*_t, uint*_t, int64x*_t, uint64x*_t - -/// Vector bitwise or (immediate, inclusive) -name = vorr -fn = simd_or -arm = vorr -aarch64 = orr -a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -generate int*_t, uint*_t, int64x*_t, uint64x*_t - - -/// Vector bitwise exclusive or (vector) -name = veor -fn = simd_xor -arm = veor -aarch64 = eor -a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -generate int*_t, uint*_t, int64x*_t, uint64x*_t - -/// Three-way exclusive OR -name = veor3 -a = 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -b = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -c = 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -validate 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F -target = sha3 - -aarch64 = eor3 -link-aarch64 = llvm.aarch64.crypto.eor3s._EXT_ -generate int8x16_t, int16x8_t, int32x4_t, int64x2_t -link-aarch64 = llvm.aarch64.crypto.eor3u._EXT_ -generate uint8x16_t, uint16x8_t, uint32x4_t, uint64x2_t - -//////////////////// -// Absolute difference between the arguments -//////////////////// - -/// Absolute difference between the arguments -name = vabd -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 -validate 15, 13, 11, 9, 7, 5, 3, 1, 1, 3, 5, 7, 9, 11, 13, 15 - -arm = vabd.s -aarch64 = sabd -link-arm = vabds._EXT_ -link-aarch64 = sabd._EXT_ -generate int*_t - -arm = vabd.s -aarch64 = uabd -link-arm = vabdu._EXT_ -link-aarch64 = uabd._EXT_ -generate uint*_t - -/// Absolute difference between the arguments of Floating -name = vabd -a = 1.0, 2.0, 5.0, -4.0 -b = 9.0, 3.0, 2.0, 8.0 -validate 8.0, 1.0, 3.0, 12.0 - -aarch64 = fabd -link-aarch64 = fabd._EXT_ -generate float64x*_t - -arm = vabd.s -aarch64 = fabd -link-arm = vabds._EXT_ -link-aarch64 = fabd._EXT_ -generate float*_t - -/// Floating-point absolute difference -name = vabd -multi_fn = simd_extract!, {vabd-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1.0 -b = 9.0 -validate 8.0 - -aarch64 = fabd -generate f32, f64 - -//////////////////// -// Absolute difference Long -//////////////////// - -/// Unsigned Absolute difference Long -name = vabdl -multi_fn = simd_cast, {vabd-unsigned-noext, a, b} -a = 1, 2, 3, 4, 4, 3, 2, 1 -b = 10, 10, 10, 10, 10, 10, 10, 10 -validate 9, 8, 7, 6, 6, 7, 8, 9 - -arm = vabdl.s -aarch64 = uabdl -generate uint8x8_t:uint8x8_t:uint16x8_t, uint16x4_t:uint16x4_t:uint32x4_t, uint32x2_t:uint32x2_t:uint64x2_t - -/// Signed Absolute difference Long -name = vabdl -multi_fn = simd_cast, c:uint8x8_t, {vabd-signed-noext, a, b} -multi_fn = simd_cast, c -a = 1, 2, 3, 4, 4, 3, 2, 1 -b = 10, 10, 10, 10, 10, 10, 10, 10 -validate 9, 8, 7, 6, 6, 7, 8, 9 - -arm = vabdl.s -aarch64 = sabdl -generate int8x8_t:int8x8_t:int16x8_t - -/// Signed Absolute difference Long -name = vabdl -multi_fn = simd_cast, c:uint16x4_t, {vabd-signed-noext, a, b} -multi_fn = simd_cast, c -a = 1, 2, 11, 12 -b = 10, 10, 10, 10 -validate 9, 8, 1, 2 - -arm = vabdl.s -aarch64 = sabdl -generate int16x4_t:int16x4_t:int32x4_t - -/// Signed Absolute difference Long -name = vabdl -multi_fn = simd_cast, c:uint32x2_t, {vabd-signed-noext, a, b} -multi_fn = simd_cast, c -a = 1, 11 -b = 10, 10 -validate 9, 1 - -arm = vabdl.s -aarch64 = sabdl -generate int32x2_t:int32x2_t:int64x2_t - -/// Unsigned Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:uint8x8_t, a, a, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_shuffle!, d:uint8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, {vabd_u8, c, d} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 -validate 1, 0, 1, 2, 3, 4, 5, 6 - -aarch64 = uabdl -generate uint8x16_t:uint8x16_t:uint16x8_t - -/// Unsigned Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:uint16x4_t, a, a, [4, 5, 6, 7] -multi_fn = simd_shuffle!, d:uint16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_cast, {vabd_u16, c, d} -a = 1, 2, 3, 4, 8, 9, 11, 12 -b = 10, 10, 10, 10, 10, 10, 10, 10 -validate 2, 1, 1, 2 - -aarch64 = uabdl -generate uint16x8_t:uint16x8_t:uint32x4_t - -/// Unsigned Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:uint32x2_t, a, a, [2, 3] -multi_fn = simd_shuffle!, d:uint32x2_t, b, b, [2, 3] -multi_fn = simd_cast, {vabd_u32, c, d} -a = 1, 2, 3, 4 -b = 10, 10, 10, 10 -validate 7, 6 - -aarch64 = uabdl -generate uint32x4_t:uint32x4_t:uint64x2_t - -/// Signed Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:int8x8_t, a, a, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_shuffle!, d:int8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, e:uint8x8_t, {vabd_s8, c, d} -multi_fn = simd_cast, e -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10 -validate 1, 0, 1, 2, 3, 4, 5, 6 - -aarch64 = sabdl -generate int8x16_t:int8x16_t:int16x8_t - -/// Signed Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:int16x4_t, a, a, [4, 5, 6, 7] -multi_fn = simd_shuffle!, d:int16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_cast, e:uint16x4_t, {vabd_s16, c, d} -multi_fn = simd_cast, e -a = 1, 2, 3, 4, 9, 10, 11, 12 -b = 10, 10, 10, 10, 10, 10, 10, 10 -validate 1, 0, 1, 2 - -aarch64 = sabdl -generate int16x8_t:int16x8_t:int32x4_t - -/// Signed Absolute difference Long -name = vabdl_high -no-q -multi_fn = simd_shuffle!, c:int32x2_t, a, a, [2, 3] -multi_fn = simd_shuffle!, d:int32x2_t, b, b, [2, 3] -multi_fn = simd_cast, e:uint32x2_t, {vabd_s32, c, d} -multi_fn = simd_cast, e -a = 1, 2, 3, 4 -b = 10, 10, 10, 10 -validate 7, 6 - -aarch64 = sabdl -generate int32x4_t:int32x4_t:int64x2_t - -//////////////////// -// equality -//////////////////// - -/// Compare bitwise Equal (vector) -name = vceq -fn = simd_eq -a = MIN, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, MAX -b = MIN, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, MAX -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE -a = MIN, MIN, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0xCC, 0x0D, 0xEE, MAX -b = MIN, MAX, 0x02, 0x04, 0x04, 0x00, 0x06, 0x08, 0x08, 0x00, 0x0A, 0x0A, 0xCC, 0xD0, 0xEE, MIN -validate TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE - -aarch64 = cmeq -generate uint64x*_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t, poly64x1_t:uint64x1_t, poly64x2_t:uint64x2_t - -arm = vceq. -generate uint*_t, int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, poly8x8_t:uint8x8_t, poly8x16_t:uint8x16_t - -/// Floating-point compare equal -name = vceq -fn = simd_eq -a = 1.2, 3.4, 5.6, 7.8 -b = 1.2, 3.4, 5.6, 7.8 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmeq -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -arm = vceq. -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Compare bitwise equal -name = vceq -multi_fn = transmute, {vceq-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 1 -b = 2 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare equal -name = vceq -multi_fn = simd_extract!, {vceq-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1. -b = 2. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Signed compare bitwise equal to zero -name = vceqz -fn = simd_eq -a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate FALSE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = cmeq -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t, poly8x8_t:uint8x8_t, poly8x16_t:uint8x16_t, poly64x1_t:uint64x1_t, poly64x2_t:uint64x2_t - -/// Unsigned compare bitwise equal to zero -name = vceqz -fn = simd_eq -a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = cmeq -generate uint*_t, uint64x*_t - -/// Floating-point compare bitwise equal to zero -name = vceqz -fn = simd_eq -a = 0.0, 1.2, 3.4, 5.6 -fixed = 0.0, 0.0, 0.0, 0.0 -validate TRUE, FALSE, FALSE, FALSE - -aarch64 = fcmeq -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Compare bitwise equal to zero -name = vceqz -multi_fn = transmute, {vceqz-in_ntt-noext, {transmute, a}} -a = 1 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare bitwise equal to zero -name = vceqz -multi_fn = simd_extract!, {vceqz-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = 1. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Signed compare bitwise Test bits nonzero -name = vtst -multi_fn = simd_and, c:in_t, a, b -multi_fn = fixed, d:in_t -multi_fn = simd_ne, c, transmute(d) -a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -b = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate TRUE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmtst -generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t, poly64x1_t:uint64x1_t, poly64x2_t:uint64x2_t - -arm = vtst -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, poly8x8_t:uint8x8_t, poly8x16_t:uint8x16_t, poly16x4_t:uint16x4_t, poly16x8_t:uint16x8_t - -/// Unsigned compare bitwise Test bits nonzero -name = vtst -multi_fn = simd_and, c:in_t, a, b -multi_fn = fixed, d:in_t -multi_fn = simd_ne, c, transmute(d) -a = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -b = MIN, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmtst -generate uint64x*_t - -arm = vtst -generate uint*_t - -/// Compare bitwise test bits nonzero -name = vtst -multi_fn = transmute, {vtst-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 0 -b = 0 -validate 0 - -aarch64 = tst -generate i64:i64:u64, u64 - -/// Signed saturating accumulate of unsigned value -name = vuqadd -out-suffix -a = 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 -b = 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4 -validate 2, 4, 6, 8, 2, 4, 6, 8, 2, 4, 6, 8, 2, 4, 6, 8 - -aarch64 = suqadd -link-aarch64 = suqadd._EXT_ -generate i32:u32:i32, i64:u64:i64 - -/// Signed saturating accumulate of unsigned value -name = vuqadd -out-suffix -multi_fn = simd_extract!, {vuqadd-out_ntt-noext, {vdup_n-out_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1 -b = 2 -validate 3 - -aarch64 = suqadd -generate i8:u8:i8, i16:u16:i16 - -//////////////////// -// Floating-point absolute value -//////////////////// - -/// Floating-point absolute value -name = vabs -fn = simd_fabs -a = -0.1, -2.2, -3.3, -6.6 -validate 0.1, 2.2, 3.3, 6.6 -aarch64 = fabs -generate float64x1_t:float64x1_t, float64x2_t:float64x2_t - -arm = vabs -generate float32x2_t:float32x2_t, float32x4_t:float32x4_t - -//////////////////// -// greater then -//////////////////// - -/// Compare signed greater than -name = vcgt -fn = simd_gt -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE -aarch64 = cmgt -generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -arm = vcgt.s -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t - -/// Compare unsigned greater than -name = vcgt -fn = simd_gt -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmhi -generate uint64x*_t - -arm = vcgt.s -generate uint*_t - -/// Floating-point compare greater than -name = vcgt -fn = simd_gt -a = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 -b = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmgt -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -arm = vcgt.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Compare greater than -name = vcgt -multi_fn = transmute, {vcgt-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 1 -b = 2 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare greater than -name = vcgt -multi_fn = simd_extract!, {vcgt-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1. -b = 2. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -//////////////////// -// lesser then -//////////////////// - -/// Compare signed less than -name = vclt -fn = simd_lt -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE -aarch64 = cmgt -generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -arm = vcgt.s -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t - -/// Compare unsigned less than -name = vclt -fn = simd_lt -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmhi -generate uint64x*_t - -arm = vcgt.s -generate uint*_t - -/// Floating-point compare less than -name = vclt -fn = simd_lt -a = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8 -b = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmgt -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -arm = vcgt.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Compare less than -name = vclt -multi_fn = transmute, {vclt-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 2 -b = 1 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare less than -name = vclt -multi_fn = simd_extract!, {vclt-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 2. -b = 1. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -//////////////////// -// lesser then equals -//////////////////// - -/// Compare signed less than or equal -name = vcle -fn = simd_le -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmge -generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -arm = vcge.s -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t - -/// Compare greater than or equal -name = vcge -multi_fn = transmute, {vcge-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 1 -b = 2 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare greater than or equal -name = vcge -multi_fn = simd_extract!, {vcge-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1. -b = 2. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Compare unsigned less than or equal -name = vcle -fn = simd_le -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmhs -generate uint64x*_t - -arm = vcge.s -generate uint*_t - -/// Floating-point compare less than or equal -name = vcle -fn = simd_le -a = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8 -b = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE -aarch64 = fcmge -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -arm = vcge.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Compare less than or equal -name = vcle -multi_fn = transmute, {vcle-in_ntt-noext, {transmute, a}, {transmute, b}} -a = 2 -b = 1 -validate 0 - -aarch64 = cmp -generate i64:u64, u64 - -/// Floating-point compare less than or equal -name = vcle -multi_fn = simd_extract!, {vcle-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 2. -b = 1. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -//////////////////// -// greater then equals -//////////////////// - -/// Compare signed greater than or equal -name = vcge -fn = simd_ge -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmge -generate int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -arm = vcge.s -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t - -/// Compare unsigned greater than or equal -name = vcge -fn = simd_ge -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmhs -generate uint64x*_t - -arm = vcge.s -generate uint*_t - -/// Floating-point compare greater than or equal -name = vcge -fn = simd_ge -a = 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8, 8.9 -b = 0.1, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7, 7.8 -validate TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmge -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -arm = vcge.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Compare signed greater than or equal to zero -name = vcgez -fn = simd_ge -a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmge -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -/// Floating-point compare greater than or equal to zero -name = vcgez -fn = simd_ge -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -fixed = 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 -validate FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmge -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Compare signed greater than or equal to zero -name = vcgez -multi_fn = transmute, {vcgez-in_ntt-noext, {transmute, a}} -a = -1 -validate 0 - -aarch64 = nop -generate i64:u64 - -/// Floating-point compare greater than or equal to zero -name = vcgez -multi_fn = simd_extract!, {vcgez-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = -1. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Compare signed greater than zero -name = vcgtz -fn = simd_gt -a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate FALSE, FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = cmgt -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -/// Floating-point compare greater than zero -name = vcgtz -fn = simd_gt -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -fixed = 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 -validate FALSE, FALSE, TRUE, TRUE, TRUE, TRUE, TRUE, TRUE - -aarch64 = fcmgt -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Compare signed greater than zero -name = vcgtz -multi_fn = transmute, {vcgtz-in_ntt-noext, {transmute, a}} -a = -1 -validate 0 - -aarch64 = cmp -generate i64:u64 - -/// Floating-point compare greater than zero -name = vcgtz -multi_fn = simd_extract!, {vcgtz-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = -1. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Compare signed less than or equal to zero -name = vclez -fn = simd_le -a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate TRUE, TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = cmle -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -/// Floating-point compare less than or equal to zero -name = vclez -fn = simd_le -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -fixed = 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 -validate TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = fcmle -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Compare less than or equal to zero -name = vclez -multi_fn = transmute, {vclez-in_ntt-noext, {transmute, a}} -a = 2 -validate 0 - -aarch64 = cmp -generate i64:u64 - -/// Floating-point compare less than or equal to zero -name = vclez -multi_fn = simd_extract!, {vclez-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = 2. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Compare signed less than zero -name = vcltz -fn = simd_lt -a = MIN, -1, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x08, 0x09, 0x0A, 0x0B, 0x0C, MAX -fixed = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate TRUE, TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = cmlt -generate int8x8_t:uint8x8_t, int8x16_t:uint8x16_t, int16x4_t:uint16x4_t, int16x8_t:uint16x8_t, int32x2_t:uint32x2_t, int32x4_t:uint32x4_t, int64x1_t:uint64x1_t, int64x2_t:uint64x2_t - -/// Floating-point compare less than zero -name = vcltz -fn = simd_lt -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -fixed = 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0, 0.0 -validate TRUE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE - -aarch64 = fcmlt -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Compare less than zero -name = vcltz -multi_fn = transmute, {vcltz-in_ntt-noext, {transmute, a}} -a = 2 -validate 0 - -aarch64 = asr -generate i64:u64 - -/// Floating-point compare less than zero -name = vcltz -multi_fn = simd_extract!, {vcltz-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = 2. -validate 0 - -aarch64 = fcmp -generate f32:u32, f64:u64 - -/// Count leading sign bits -name = vcls -a = MIN, -1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, MAX -validate 0, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, 0 - -arm = vcls.s -aarch64 = cls -link-arm = vcls._EXT_ -link-aarch64 = cls._EXT_ -generate int*_t - -/// Count leading sign bits -name = vcls -multi_fn = vcls-signed-noext, {transmute, a} -a = MIN, MAX, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, MAX -validate BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1 - -arm = vcls -aarch64 = cls -generate uint8x8_t:int8x8_t, uint8x16_t:int8x16_t, uint16x4_t:int16x4_t, uint16x8_t:int16x8_t, uint32x2_t:int32x2_t, uint32x4_t:int32x4_t - -/// Count leading zero bits -name = vclz -multi_fn = self-signed-ext, a -a = MIN, -1, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, MAX -validate 0, 0, BITS, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, 1 - -arm = vclz. -aarch64 = clz -generate int*_t - -/// Count leading zero bits -name = vclz -multi_fn = transmute, {self-signed-ext, transmute(a)} -a = MIN, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, MAX -validate BITS, BITS, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, BITS_M1, 0 - -arm = vclz. -aarch64 = clz -generate uint*_t - -/// Floating-point absolute compare greater than -name = vcagt -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -b = -1.1, 0.0, 1.1, 2.4, 3.3, 4.6, 5.5, 6.8 -validate !0, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE - -aarch64 = facgt -link-aarch64 = facgt._EXT2_._EXT_ -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -arm = vacgt.s -link-arm = vacgt._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Floating-point absolute compare greater than or equal -name = vcage -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -b = -1.1, 0.0, 1.1, 2.4, 3.3, 4.6, 5.5, 6.8 -validate !0, TRUE, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE - -aarch64 = facge -link-aarch64 = facge._EXT2_._EXT_ -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -arm = vacge.s -link-arm = vacge._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Floating-point absolute compare less than -name = vcalt -multi_fn = vcagt-self-noext, b, a -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -b = -1.1, 0.0, 1.1, 2.4, 3.3, 4.6, 5.5, 6.8 -validate 0, FALSE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE - -aarch64 = facgt -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -arm = vacgt.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Floating-point absolute compare less than or equal -name = vcale -multi_fn = vcage-self-noext , b, a -a = -1.2, 0.0, 1.2, 2.3, 3.4, 4.5, 5.6, 6.7 -b = -1.1, 0.0, 1.1, 2.4, 3.3, 4.6, 5.5, 6.8 -validate 0, TRUE, FALSE, TRUE, FALSE, TRUE, FALSE, TRUE - -aarch64 = facge -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -arm = vacge.s -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in0_len-LANE2} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, MAX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 0:1 -validate MAX, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = mov -generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x2_t, int32x4_t, int64x2_t -generate uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x2_t, uint32x4_t, uint64x2_t -generate poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t, poly64x2_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in0_len-LANE2} -a = 1., 2., 3., 4. -b = 0., 0.5, 0., 0. -n = 0:1 -validate 0.5, 2., 3., 4. - -aarch64 = mov -generate float32x2_t, float32x4_t, float64x2_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = simd_shuffle!, a:in_t, a, a, {asc-0-in_len} -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in_len-LANE2} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, MAX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 0:1 -validate MAX, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = mov -generate int8x8_t:int8x16_t:int8x8_t, int16x4_t:int16x8_t:int16x4_t, int32x2_t:int32x4_t:int32x2_t -generate uint8x8_t:uint8x16_t:uint8x8_t, uint16x4_t:uint16x8_t:uint16x4_t, uint32x2_t:uint32x4_t:uint32x2_t -generate poly8x8_t:poly8x16_t:poly8x8_t, poly16x4_t:poly16x8_t:poly16x4_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = simd_shuffle!, a:in_t, a, a, {asc-0-in_len} -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in_len-LANE2} -a = 1., 2., 3., 4. -b = 0., 0.5, 0., 0. -n = 0:1 -validate 0.5, 2., 3., 4. - -aarch64 = mov -generate float32x2_t:float32x4_t:float32x2_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = simd_shuffle!, b:in_t0, b, b, {asc-0-in0_len} -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in0_len-LANE2} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, MAX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 0:1 -validate MAX, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = mov -generate int8x16_t:int8x8_t:int8x16_t, int16x8_t:int16x4_t:int16x8_t, int32x4_t:int32x2_t:int32x4_t -generate uint8x16_t:uint8x8_t:uint8x16_t, uint16x8_t:uint16x4_t:uint16x8_t, uint32x4_t:uint32x2_t:uint32x4_t -generate poly8x16_t:poly8x8_t:poly8x16_t, poly16x8_t:poly16x4_t:poly16x8_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = simd_shuffle!, b:in_t0, b, b, {asc-0-in0_len} -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in0_len-LANE2} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = MAX, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1:0 -validate 1, MAX - -aarch64 = mov -generate int64x2_t:int64x1_t:int64x2_t, uint64x2_t:uint64x1_t:uint64x2_t, poly64x2_t:poly64x1_t:poly64x2_t - -/// Insert vector element from another vector element -name = vcopy -lane-suffixes -constn = LANE1:LANE2 -multi_fn = static_assert_imm-in0_exp_len-LANE1 -multi_fn = static_assert_imm-in_exp_len-LANE2 -multi_fn = simd_shuffle!, b:in_t0, b, b, {asc-0-in0_len} -multi_fn = matchn-in0_exp_len-LANE1, simd_shuffle!, a, b, {ins-in0_len-in0_len-LANE2} -a = 1., 2., 3., 4. -b = 0.5, 0., 0., 0. -n = 1:0 -validate 1., 0.5, 3., 4. - -aarch64 = mov -generate float32x4_t:float32x2_t:float32x4_t -aarch64 = mov -generate float64x2_t:float64x1_t:float64x2_t - -/// Insert vector element from another vector element -name = vcreate -out-suffix -multi_fn = transmute, a -a = 1 -validate 1, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = nop -arm = nop -generate u64:int8x8_t, u64:int16x4_t, u64:int32x2_t, u64:int64x1_t -generate u64:uint8x8_t, u64:uint16x4_t, u64:uint32x2_t, u64:uint64x1_t -generate u64:poly8x8_t, u64:poly16x4_t -target = aes -generate u64:poly64x1_t - -/// Insert vector element from another vector element -name = vcreate -out-suffix -multi_fn = transmute, a -a = 0 -validate 0., 0. - -aarch64 = nop -generate u64:float64x1_t -arm = nop -generate u64:float32x2_t - -/// Fixed-point convert to floating-point -name = vcvt -double-suffixes -fn = simd_cast -a = 1, 2, 3, 4 -validate 1., 2., 3., 4. - -aarch64 = scvtf -generate int64x1_t:float64x1_t, int64x2_t:float64x2_t -aarch64 = ucvtf -generate uint64x1_t:float64x1_t, uint64x2_t:float64x2_t - -arm = vcvt -aarch64 = scvtf -generate int32x2_t:float32x2_t, int32x4_t:float32x4_t -aarch64 = ucvtf -generate uint32x2_t:float32x2_t, uint32x4_t:float32x4_t - -/// Floating-point convert to higher precision long -name = vcvt -double-suffixes -fn = simd_cast -a = -1.2, 1.2 -validate -1.2f32 as f64, 1.2f32 as f64 - -aarch64 = fcvtl -generate float32x2_t:float64x2_t - -/// Floating-point convert to higher precision long -name = vcvt_high -noq-double-suffixes -multi_fn = simd_shuffle!, b:float32x2_t, a, a, [2, 3] -multi_fn = simd_cast, b -a = -1.2, 1.2, 2.3, 3.4 -validate 2.3f32 as f64, 3.4f32 as f64 - -aarch64 = fcvtl -generate float32x4_t:float64x2_t - -/// Floating-point convert to lower precision narrow -name = vcvt -double-suffixes -fn = simd_cast -a = -1.2, 1.2 -validate -1.2f64 as f32, 1.2f64 as f32 - -aarch64 = fcvtn -generate float64x2_t:float32x2_t - -/// Floating-point convert to lower precision narrow -name = vcvt_high -noq-double-suffixes -multi_fn = simd_shuffle!, a, {simd_cast, b}, [0, 1, 2, 3] -a = -1.2, 1.2 -b = -2.3, 3.4 -validate -1.2, 1.2, -2.3f64 as f32, 3.4f64 as f32 - -aarch64 = fcvtn -generate float32x2_t:float64x2_t:float32x4_t - -/// Floating-point convert to lower precision narrow, rounding to odd -name = vcvtx -double-suffixes -a = -1.0, 2.0 -validate -1.0, 2.0 - -aarch64 = fcvtxn -link-aarch64 = fcvtxn._EXT2_._EXT_ -generate float64x2_t:float32x2_t - -/// Floating-point convert to lower precision narrow, rounding to odd -name = vcvtx -double-suffixes -multi_fn = simd_extract!, {vcvtx-_f32_f64-noext, {vdupq_n-in_ntt-noext, a}}, 0 -a = -1.0 -validate -1.0 - -aarch64 = fcvtxn -generate f64:f32 - -/// Floating-point convert to lower precision narrow, rounding to odd -name = vcvtx_high -noq-double-suffixes -multi_fn = simd_shuffle!, a, {vcvtx-noq_doubleself-noext, b}, [0, 1, 2, 3] -a = -1.0, 2.0 -b = -3.0, 4.0 -validate -1.0, 2.0, -3.0, 4.0 - -aarch64 = fcvtxn -generate float32x2_t:float64x2_t:float32x4_t - -/// Fixed-point convert to floating-point -name = vcvt -double-n-suffixes -constn = N -multi_fn = static_assert-N-1-bits -a = 1, 2, 3, 4 -n = 2 -validate 0.25, 0.5, 0.75, 1. -arm-aarch64-separate - -aarch64 = scvtf -link-aarch64 = vcvtfxs2fp._EXT2_._EXT_ -const-aarch64 = N -generate int64x1_t:float64x1_t, int64x2_t:float64x2_t, i32:f32, i64:f64 - -aarch64 = ucvtf -link-aarch64 = vcvtfxu2fp._EXT2_._EXT_ -const-aarch64 = N -generate uint64x1_t:float64x1_t, uint64x2_t:float64x2_t, u32:f32, u64:f64 - -aarch64 = scvtf -link-aarch64 = vcvtfxs2fp._EXT2_._EXT_ -arm = vcvt -link-arm = vcvtfxs2fp._EXT2_._EXT_ -const-arm = N:i32 - -generate int32x2_t:float32x2_t, int32x4_t:float32x4_t - -aarch64 = ucvtf -link-aarch64 = vcvtfxu2fp._EXT2_._EXT_ -arm = vcvt -link-arm = vcvtfxu2fp._EXT2_._EXT_ -const-arm = N:i32 -generate uint32x2_t:float32x2_t, uint32x4_t:float32x4_t - -/// Floating-point convert to fixed-point, rounding toward zero -name = vcvt -double-n-suffixes -constn = N -multi_fn = static_assert-N-1-bits -a = 0.25, 0.5, 0.75, 1. -n = 2 -validate 1, 2, 3, 4 -arm-aarch64-separate - -aarch64 = fcvtzs -link-aarch64 = vcvtfp2fxs._EXT2_._EXT_ -const-aarch64 = N -generate float64x1_t:int64x1_t, float64x2_t:int64x2_t, f32:i32, f64:i64 - -aarch64 = fcvtzu -link-aarch64 = vcvtfp2fxu._EXT2_._EXT_ -const-aarch64 = N -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -aarch64 = fcvtzs -link-aarch64 = vcvtfp2fxs._EXT2_._EXT_ -arm = vcvt -link-arm = vcvtfp2fxs._EXT2_._EXT_ -const-arm = N:i32 -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t - -aarch64 = fcvtzu -link-aarch64 = vcvtfp2fxu._EXT2_._EXT_ -arm = vcvt -link-arm = vcvtfp2fxu._EXT2_._EXT_ -const-arm = N:i32 -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Fixed-point convert to floating-point -name = vcvt -double-suffixes -multi_fn = a as out_t -a = 1 -validate 1. - -aarch64 = scvtf -generate i32:f32, i64:f64 -aarch64 = ucvtf -generate u32:f32, u64:f64 - -/// Fixed-point convert to floating-point -name = vcvt -double-suffixes -multi_fn = a as out_t -a = 1. -validate 1 - -aarch64 = fcvtzs -generate f32:i32, f64:i64 -aarch64 = fcvtzu -generate f32:u32, f64:u64 - -/// Floating-point convert to signed fixed-point, rounding toward zero -name = vcvt -double-suffixes -link-aarch64 = llvm.fptosi.sat._EXT2_._EXT_ -a = -1.1, 2.1, -2.9, 3.9 -validate -1, 2, -2, 3 - -aarch64 = fcvtzs -generate float64x1_t:int64x1_t, float64x2_t:int64x2_t - -link-arm = llvm.fptosi.sat._EXT2_._EXT_ -arm = vcvt -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t - -/// Floating-point convert to unsigned fixed-point, rounding toward zero -name = vcvt -double-suffixes -link-aarch64 = llvm.fptoui.sat._EXT2_._EXT_ -a = 1.1, 2.1, 2.9, 3.9 -validate 1, 2, 2, 3 - -aarch64 = fcvtzu -generate float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -link-arm = llvm.fptoui.sat._EXT2_._EXT_ -arm = vcvt -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t - -/// Floating-point convert to signed integer, rounding to nearest with ties to away -name = vcvta -double-suffixes -a = -1.1, 2.1, -2.9, 3.9 -validate -1, 2, -3, 4 - -aarch64 = fcvtas -link-aarch64 = fcvtas._EXT2_._EXT_ -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t, float64x1_t:int64x1_t, float64x2_t:int64x2_t - -/// Floating-point convert to integer, rounding to nearest with ties to away -name = vcvta -double-suffixes -a = 2.9 -validate 3 - -aarch64 = fcvtas -link-aarch64 = fcvtas._EXT2_._EXT_ -generate f32:i32, f64:i64 - -aarch64 = fcvtau -link-aarch64 = fcvtau._EXT2_._EXT_ -generate f32:u32, f64:u64 - -/// Floating-point convert to signed integer, rounding to nearest with ties to even -name = vcvtn -double-suffixes -a = -1.5, 2.1, -2.9, 3.9 -validate -2, 2, -3, 4 - -aarch64 = fcvtns -link-aarch64 = fcvtns._EXT2_._EXT_ -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t, float64x1_t:int64x1_t, float64x2_t:int64x2_t, f32:i32, f64:i64 - -/// Floating-point convert to signed integer, rounding toward minus infinity -name = vcvtm -double-suffixes -a = -1.1, 2.1, -2.9, 3.9 -validate -2, 2, -3, 3 - -aarch64 = fcvtms -link-aarch64 = fcvtms._EXT2_._EXT_ -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t, float64x1_t:int64x1_t, float64x2_t:int64x2_t, f32:i32, f64:i64 - -/// Floating-point convert to signed integer, rounding toward plus infinity -name = vcvtp -double-suffixes -a = -1.1, 2.1, -2.9, 3.9 -validate -1, 3, -2, 4 - -aarch64 = fcvtps -link-aarch64 = fcvtps._EXT2_._EXT_ -generate float32x2_t:int32x2_t, float32x4_t:int32x4_t, float64x1_t:int64x1_t, float64x2_t:int64x2_t, f32:i32, f64:i64 - -/// Floating-point convert to unsigned integer, rounding to nearest with ties to away -name = vcvta -double-suffixes -a = 1.1, 2.1, 2.9, 3.9 -validate 1, 2, 3, 4 - -aarch64 = fcvtau -link-aarch64 = fcvtau._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t - -/// Floating-point convert to unsigned integer, rounding to nearest with ties to even -name = vcvtn -double-suffixes -a = 1.5, 2.1, 2.9, 3.9 -validate 2, 2, 3, 4 - -aarch64 = fcvtnu -link-aarch64 = fcvtnu._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -/// Floating-point convert to unsigned integer, rounding toward minus infinity -name = vcvtm -double-suffixes -a = 1.1, 2.1, 2.9, 3.9 -validate 1, 2, 2, 3 - -aarch64 = fcvtmu -link-aarch64 = fcvtmu._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -/// Floating-point convert to unsigned integer, rounding toward plus infinity -name = vcvtp -double-suffixes -a = 1.1, 2.1, 2.9, 3.9 -validate 2, 3, 3, 4 - -aarch64 = fcvtpu -link-aarch64 = fcvtpu._EXT2_._EXT_ -generate float32x2_t:uint32x2_t, float32x4_t:uint32x4_t, float64x1_t:uint64x1_t, float64x2_t:uint64x2_t, f32:u32, f64:u64 - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, a, a, {dup-out_len-N as u32} -a = 1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16 -n = HFLEN -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 - -aarch64 = dup -generate poly64x2_t, poly64x1_t:poly64x2_t - -arm = vdup.l -generate int*_t -generate int8x16_t:int8x8_t, int16x8_t:int16x4_t, int32x4_t:int32x2_t -generate int8x8_t:int8x16_t, int16x4_t:int16x8_t, int32x2_t:int32x4_t - -generate uint*_t -generate uint8x16_t:uint8x8_t, uint16x8_t:uint16x4_t, uint32x4_t:uint32x2_t -generate uint8x8_t:uint8x16_t, uint16x4_t:uint16x8_t, uint32x2_t:uint32x4_t - -generate poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t -generate poly8x16_t:poly8x8_t, poly16x8_t:poly16x4_t -generate poly8x8_t:poly8x16_t, poly16x4_t:poly16x8_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, a, a, {dup-out_len-N as u32} -a = 1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16 -n = HFLEN -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 - -aarch64 = dup -arm = vmov -generate int64x2_t, int64x1_t:int64x2_t, uint64x2_t, uint64x1_t:uint64x2_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, a, a, {dup-out_len-N as u32} -a = 1., 1., 1., 4. -n = HFLEN -validate 1., 1., 1., 1. - -aarch64 = dup -generate float64x2_t, float64x1_t:float64x2_t - -arm = vdup.l -generate float*_t, float32x4_t:float32x2_t, float32x2_t:float32x4_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = a -a = 0 -n = HFLEN -validate 0 - -aarch64 = nop -generate poly64x1_t - -arm = nop -generate int64x1_t, uint64x1_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = a -a = 0. -n = HFLEN -validate 0. - -aarch64 = nop -generate float64x1_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = transmute--, {simd_extract!, a, N as u32} -a = 0, 1 -n = HFLEN -validate 1 - -aarch64 = nop -generate poly64x2_t:poly64x1_t - -arm = vmov -generate int64x2_t:int64x1_t, uint64x2_t:uint64x1_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = transmute--, {simd_extract!, a, N as u32} -a = 0., 1. -n = HFLEN -validate 1. - -aarch64 = nop -generate float64x2_t:float64x1_t - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, a, N as u32 -a = 1, 1, 1, 4, 1, 6, 7, 8, 1, 10, 11, 12, 13, 14, 15, 16 -n = HFLEN -validate 1 - -aarch64 = nop -generate int8x8_t:i8, int8x16_t:i8, int16x4_t:i16, int16x8_t:i16, int32x2_t:i32, int32x4_t:i32, int64x1_t:i64, int64x2_t:i64 -generate uint8x8_t:u8, uint8x16_t:u8, uint16x4_t:u16, uint16x8_t:u16, uint32x2_t:u32, uint32x4_t:u32, uint64x1_t:u64, uint64x2_t:u64 -generate poly8x8_t:p8, poly8x16_t:p8, poly16x4_t:p16, poly16x8_t:p16 - -/// Set all vector lanes to the same value -name = vdup -lane-suffixes -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, a, N as u32 -a = 1., 1., 1., 4. -n = HFLEN -validate 1. - -aarch64 = nop -generate float32x2_t:f32, float32x4_t:f32, float64x1_t:f64, float64x2_t:f64 - -/// Extract vector from pair of vectors -name = vext -constn = N -multi_fn = static_assert_imm-out_exp_len-N -multi_fn = matchn-out_exp_len-N, simd_shuffle!, a, b, {asc-n-out_len} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -n = LEN_M1 -validate 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 - -arm = "vext.8" -aarch64 = ext -generate int*_t, uint*_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t - -/// Extract vector from pair of vectors -name = vext -constn = N -multi_fn = static_assert_imm-out_exp_len-N -multi_fn = matchn-out_exp_len-N, simd_shuffle!, a, b, {asc-n-out_len} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -n = LEN_M1 -validate 1, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 - -aarch64 = ext -generate poly64x2_t - -arm = vmov -generate int64x2_t, uint64x2_t - -/// Extract vector from pair of vectors -name = vext -constn = N -multi_fn = static_assert_imm-out_exp_len-N -multi_fn = matchn-out_exp_len-N, simd_shuffle!, a, b, {asc-n-out_len} -a = 1., 1., 1., 1. -b = 2., 2., 2., 2., -n = LEN_M1 -validate 1., 2., 2., 2. - -aarch64 = ext -generate float64x2_t - -arm = "vext.8" -generate float*_t - -/// Multiply-add to accumulator -name = vmla -multi_fn = simd_add, a, {simd_mul, b, c} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -arm = vmla. -aarch64 = mla -generate int*_t, uint*_t - -/// Floating-point multiply-add to accumulator -name = vmla -multi_fn = simd_add, a, {simd_mul, b, c} -a = 0., 1., 2., 3. -b = 2., 2., 2., 2. -c = 3., 3., 3., 3. -validate 6., 7., 8., 9. - -aarch64 = fmul -generate float64x*_t - -arm = vmla. -generate float*_t - -/// Vector multiply accumulate with scalar -name = vmla -n-suffix -multi_fn = vmla-self-noext, a, b, {vdup-nself-noext, c} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -aarch64 = mla -arm = vmla. -generate int16x4_t:int16x4_t:i16:int16x4_t, int16x8_t:int16x8_t:i16:int16x8_t, int32x2_t:int32x2_t:i32:int32x2_t, int32x4_t:int32x4_t:i32:int32x4_t -generate uint16x4_t:uint16x4_t:u16:uint16x4_t, uint16x8_t:uint16x8_t:u16:uint16x8_t, uint32x2_t:uint32x2_t:u32:uint32x2_t, uint32x4_t:uint32x4_t:u32:uint32x4_t - -/// Vector multiply accumulate with scalar -name = vmla -n-suffix -multi_fn = vmla-self-noext, a, b, {vdup-nself-noext, c} -a = 0., 1., 2., 3. -b = 2., 2., 2., 2. -c = 3. -validate 6., 7., 8., 9. - -aarch64 = fmul -arm = vmla. -generate float32x2_t:float32x2_t:f32:float32x2_t, float32x4_t:float32x4_t:f32:float32x4_t - -/// Vector multiply accumulate with scalar -name = vmla -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmla-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -aarch64 = mla -arm = vmla. -generate int16x4_t, int16x4_t:int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x4_t:int32x2_t:int32x4_t, int32x4_t -generate uint16x4_t, uint16x4_t:uint16x4_t:uint16x8_t:uint16x4_t, uint16x8_t:uint16x8_t:uint16x4_t:uint16x8_t, uint16x8_t -generate uint32x2_t, uint32x2_t:uint32x2_t:uint32x4_t:uint32x2_t, uint32x4_t:uint32x4_t:uint32x2_t:uint32x4_t, uint32x4_t - -/// Vector multiply accumulate with scalar -name = vmla -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmla-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 0., 1., 2., 3. -b = 2., 2., 2., 2. -c = 0., 3., 0., 0. -n = 1 -validate 6., 7., 8., 9. - -aarch64 = fmul -arm = vmla. -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Signed multiply-add long -name = vmlal -multi_fn = simd_add, a, {vmull-self-noext, b, c} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -arm = vmlal.s -aarch64 = smlal -generate int16x8_t:int8x8_t:int8x8_t:int16x8_t, int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Unsigned multiply-add long -name = vmlal -multi_fn = simd_add, a, {vmull-self-noext, b, c} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -arm = vmlal.s -aarch64 = umlal -generate uint16x8_t:uint8x8_t:uint8x8_t:uint16x8_t, uint32x4_t:uint16x4_t:uint16x4_t:uint32x4_t, uint64x2_t:uint32x2_t:uint32x2_t:uint64x2_t - -/// Vector widening multiply accumulate with scalar -name = vmlal -n-suffix -multi_fn = vmlal-self-noext, a, b, {vdup-nself-noext, c} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -arm = vmlal.s -aarch64 = smlal -generate int32x4_t:int16x4_t:i16:int32x4_t, int64x2_t:int32x2_t:i32:int64x2_t -aarch64 = umlal -generate uint32x4_t:uint16x4_t:u16:uint32x4_t, uint64x2_t:uint32x2_t:u32:uint64x2_t - -/// Vector widening multiply accumulate with scalar -name = vmlal_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmlal-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 - -arm = vmlal.s -aarch64 = smlal -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int32x4_t:int16x4_t:int16x8_t:int32x4_t -generate int64x2_t:int32x2_t:int32x2_t:int64x2_t, int64x2_t:int32x2_t:int32x4_t:int64x2_t -aarch64 = umlal -generate uint32x4_t:uint16x4_t:uint16x4_t:uint32x4_t, uint32x4_t:uint16x4_t:uint16x8_t:uint32x4_t -generate uint64x2_t:uint32x2_t:uint32x2_t:uint64x2_t, uint64x2_t:uint32x2_t:uint32x4_t:uint64x2_t - -/// Signed multiply-add long -name = vmlal_high -no-q -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = simd_shuffle!, c:half, c, c, {fixed-half-right} -multi_fn = vmlal-noqself-noext, a, b, c -a = 8, 7, 6, 5, 4, 3, 2, 1 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = smlal2 -generate int16x8_t:int8x16_t:int8x16_t:int16x8_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Unsigned multiply-add long -name = vmlal_high -no-q -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = simd_shuffle!, c:half, c, c, {fixed-half-right} -multi_fn = vmlal-noqself-noext, a, b, c -a = 8, 7, 6, 5, 4, 3, 2, 1 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = umlal2 -generate uint16x8_t:uint8x16_t:uint8x16_t:uint16x8_t, uint32x4_t:uint16x8_t:uint16x8_t:uint32x4_t, uint64x2_t:uint32x4_t:uint32x4_t:uint64x2_t - -/// Multiply-add long -name = vmlal_high_n -no-q -multi_fn = vmlal_high-noqself-noext, a, b, {vdupq_n-noqself-noext, c} -a = 8, 7, 6, 5, 4, 3, 2, 1 -b = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -c = 2 -validate 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = smlal2 -generate int32x4_t:int16x8_t:i16:int32x4_t, int64x2_t:int32x4_t:i32:int64x2_t -aarch64 = umlal2 -generate uint32x4_t:uint16x8_t:u16:uint32x4_t, uint64x2_t:uint32x4_t:u32:uint64x2_t - -/// Multiply-add long -name = vmlal_high_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmlal_high-noqself-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 8, 7, 6, 5, 4, 3, 2, 1 -b = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -c = 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = smlal2 -generate int32x4_t:int16x8_t:int16x4_t:int32x4_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t -generate int64x2_t:int32x4_t:int32x2_t:int64x2_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t -aarch64 = umlal2 -generate uint32x4_t:uint16x8_t:uint16x4_t:uint32x4_t, uint32x4_t:uint16x8_t:uint16x8_t:uint32x4_t -generate uint64x2_t:uint32x4_t:uint32x2_t:uint64x2_t, uint64x2_t:uint32x4_t:uint32x4_t:uint64x2_t - -/// Multiply-subtract from accumulator -name = vmls -multi_fn = simd_sub, a, {simd_mul, b, c} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -arm = vmls. -aarch64 = mls -generate int*_t, uint*_t - -/// Floating-point multiply-subtract from accumulator -name = vmls -multi_fn = simd_sub, a, {simd_mul, b, c} -a = 6., 7., 8., 9. -b = 2., 2., 2., 2. -c = 3., 3., 3., 3. -validate 0., 1., 2., 3. - -aarch64 = fmul -generate float64x*_t - -arm = vmls. -generate float*_t - -/// Vector multiply subtract with scalar -name = vmls -n-suffix -multi_fn = vmls-self-noext, a, b, {vdup-nself-noext, c} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = mls -arm = vmls. -generate int16x4_t:int16x4_t:i16:int16x4_t, int16x8_t:int16x8_t:i16:int16x8_t, int32x2_t:int32x2_t:i32:int32x2_t, int32x4_t:int32x4_t:i32:int32x4_t -generate uint16x4_t:uint16x4_t:u16:uint16x4_t, uint16x8_t:uint16x8_t:u16:uint16x8_t, uint32x2_t:uint32x2_t:u32:uint32x2_t, uint32x4_t:uint32x4_t:u32:uint32x4_t - -/// Vector multiply subtract with scalar -name = vmls -n-suffix -multi_fn = vmls-self-noext, a, b, {vdup-nself-noext, c} -a = 6., 7., 8., 9. -b = 2., 2., 2., 2. -c = 3. -validate 0., 1., 2., 3. - -aarch64 = fmul -arm = vmls. -generate float32x2_t:float32x2_t:f32:float32x2_t, float32x4_t:float32x4_t:f32:float32x4_t - -/// Vector multiply subtract with scalar -name = vmls -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmls-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = mls -arm = vmls. -generate int16x4_t, int16x4_t:int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x4_t:int32x2_t:int32x4_t, int32x4_t -generate uint16x4_t, uint16x4_t:uint16x4_t:uint16x8_t:uint16x4_t, uint16x8_t:uint16x8_t:uint16x4_t:uint16x8_t, uint16x8_t -generate uint32x2_t, uint32x2_t:uint32x2_t:uint32x4_t:uint32x2_t, uint32x4_t:uint32x4_t:uint32x2_t:uint32x4_t, uint32x4_t - -/// Vector multiply subtract with scalar -name = vmls -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmls-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 6., 7., 8., 9. -b = 2., 2., 2., 2. -c = 0., 3., 0., 0. -n = 1 -validate 0., 1., 2., 3. - -aarch64 = fmul -arm = vmls. -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Signed multiply-subtract long -name = vmlsl -multi_fn = simd_sub, a, {vmull-self-noext, b, c} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -arm = vmlsl.s -aarch64 = smlsl -generate int16x8_t:int8x8_t:int8x8_t:int16x8_t, int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Unsigned multiply-subtract long -name = vmlsl -multi_fn = simd_sub, a, {vmull-self-noext, b, c} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -arm = vmlsl.s -aarch64 = umlsl -generate uint16x8_t:uint8x8_t:uint8x8_t:uint16x8_t, uint32x4_t:uint16x4_t:uint16x4_t:uint32x4_t, uint64x2_t:uint32x2_t:uint32x2_t:uint64x2_t - -/// Vector widening multiply subtract with scalar -name = vmlsl -n-suffix -multi_fn = vmlsl-self-noext, a, b, {vdup-nself-noext, c} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -arm = vmlsl.s -aarch64 = smlsl -generate int32x4_t:int16x4_t:i16:int32x4_t, int64x2_t:int32x2_t:i32:int64x2_t -aarch64 = umlsl -generate uint32x4_t:uint16x4_t:u16:uint32x4_t, uint64x2_t:uint32x2_t:u32:uint64x2_t - -/// Vector widening multiply subtract with scalar -name = vmlsl_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmlsl-self-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 0, 3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -arm = vmlsl.s -aarch64 = smlsl -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int32x4_t:int16x4_t:int16x8_t:int32x4_t -generate int64x2_t:int32x2_t:int32x2_t:int64x2_t, int64x2_t:int32x2_t:int32x4_t:int64x2_t -aarch64 = umlsl -generate uint32x4_t:uint16x4_t:uint16x4_t:uint32x4_t, uint32x4_t:uint16x4_t:uint16x8_t:uint32x4_t -generate uint64x2_t:uint32x2_t:uint32x2_t:uint64x2_t, uint64x2_t:uint32x2_t:uint32x4_t:uint64x2_t - -/// Signed multiply-subtract long -name = vmlsl_high -no-q -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = simd_shuffle!, c:half, c, c, {fixed-half-right} -multi_fn = vmlsl-noqself-noext, a, b, c -a = 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 14, 13, 12, 11, 10, 9, 8, 7 - -aarch64 = smlsl2 -generate int16x8_t:int8x16_t:int8x16_t:int16x8_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Unsigned multiply-subtract long -name = vmlsl_high -no-q -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = simd_shuffle!, c:half, c, c, {fixed-half-right} -multi_fn = vmlsl-noqself-noext, a, b, c -a = 14, 15, 16, 17, 18, 19, 20, 21 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -c = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 14, 13, 12, 11, 10, 9, 8, 7 - -aarch64 = umlsl2 -generate uint16x8_t:uint8x16_t:uint8x16_t:uint16x8_t, uint32x4_t:uint16x8_t:uint16x8_t:uint32x4_t, uint64x2_t:uint32x4_t:uint32x4_t:uint64x2_t - -/// Multiply-subtract long -name = vmlsl_high_n -no-q -multi_fn = vmlsl_high-noqself-noext, a, b, {vdupq_n-noqself-noext, c} -a = 14, 15, 16, 17, 18, 19, 20, 21 -b = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -c = 2 -validate 14, 13, 12, 11, 10, 9, 8, 7 - -aarch64 = smlsl2 -generate int32x4_t:int16x8_t:i16:int32x4_t, int64x2_t:int32x4_t:i32:int64x2_t -aarch64 = umlsl2 -generate uint32x4_t:uint16x8_t:u16:uint32x4_t, uint64x2_t:uint32x4_t:u32:uint64x2_t - -/// Multiply-subtract long -name = vmlsl_high_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vmlsl_high-noqself-noext, a, b, {simd_shuffle!, c, c, {dup-in_len-LANE as u32}} -a = 14, 15, 16, 17, 18, 19, 20, 21 -b = 3, 3, 0, 1, 0, 1, 2, 3, 0, 1, 2, 3, 4, 5, 6, 7 -c = 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 14, 13, 12, 11, 10, 9, 8, 7 - -aarch64 = smlsl2 -generate int32x4_t:int16x8_t:int16x4_t:int32x4_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t -generate int64x2_t:int32x4_t:int32x2_t:int64x2_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t -aarch64 = umlsl2 -generate uint32x4_t:uint16x8_t:uint16x4_t:uint32x4_t, uint32x4_t:uint16x8_t:uint16x8_t:uint32x4_t -generate uint64x2_t:uint32x4_t:uint32x2_t:uint64x2_t, uint64x2_t:uint32x4_t:uint32x4_t:uint64x2_t - -/// Extract narrow -name = vmovn_high -no-q -multi_fn = simd_cast, c:in_t0, b -multi_fn = simd_shuffle!, a, c, {asc-0-out_len} -a = 0, 1, 2, 3, 2, 3, 4, 5 -b = 2, 3, 4, 5, 12, 13, 14, 15 -validate 0, 1, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 12, 13, 14, 15 - -aarch64 = xtn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Negate -name = vneg -fn = simd_neg -a = 0, 1, -1, 2, -2, 3, -3, 4, -4, 5, -5, 6, -6, 7, -7, 8 -validate 0, -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7, -8 - -aarch64 = neg -generate int64x*_t - -arm = vneg.s -generate int*_t - -/// Negate -name = vneg -multi_fn = a.wrapping_neg() -a = 1 -validate -1 - -aarch64 = neg -generate i64 - -/// Negate -name = vneg -fn = simd_neg -a = 0., 1., -1., 2., -2., 3., -3., 4. -validate 0., -1., 1., -2., 2., -3., 3., -4. - -aarch64 = fneg -generate float64x*_t - -arm = vneg.s -generate float*_t - -/// Signed saturating negate -name = vqneg -a = MIN, 0, 1, -1, 2, -2, 3, -3, 4, -4, 5, -5, 6, -6, 7, -7 -validate MAX, 0, -1, 1, -2, 2, -3, 3, -4, 4, -5, 5, -6, 6, -7, 7 -link-arm = vqneg._EXT_ -link-aarch64 = sqneg._EXT_ - -aarch64 = sqneg -generate int64x*_t - -arm = vqneg.s -generate int*_t - -/// Signed saturating negate -name = vqneg -multi_fn = simd_extract!, {vqneg-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = 1 -validate -1 - -aarch64 = sqneg -generate i8, i16, i32, i64 - -/// Saturating subtract -name = vqsub -a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 41, 40, 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, 29, 28, 27, 26 - -arm = vqsub.s -aarch64 = uqsub -link-arm = llvm.usub.sat._EXT_ -link-aarch64 = uqsub._EXT_ -generate uint*_t, uint64x*_t - -arm = vqsub.s -aarch64 = sqsub -link-arm = llvm.ssub.sat._EXT_ -link-aarch64 = sqsub._EXT_ -generate int*_t, int64x*_t - -/// Saturating subtract -name = vqsub -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqsub-in_ntt-noext, a, b}, 0 -a = 42 -b = 1 -validate 41 - -aarch64 = sqsub -generate i8, i16 -aarch64 = uqsub -generate u8, u16 - -/// Saturating subtract -name = vqsub -a = 42 -b = 1 -validate 41 - -aarch64 = uqsub -link-aarch64 = uqsub._EXT_ -generate u32, u64 - -aarch64 = sqsub -link-aarch64 = sqsub._EXT_ -generate i32, i64 - -/// Halving add -name = vhadd -a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29 - -arm = vhadd.s -aarch64 = uhadd -link-aarch64 = uhadd._EXT_ -link-arm = vhaddu._EXT_ -generate uint*_t - -arm = vhadd.s -aarch64 = shadd -link-aarch64 = shadd._EXT_ -link-arm = vhadds._EXT_ -generate int*_t - -/// Reverse bit order -name = vrbit -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -validate 0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120 - -aarch64 = rbit -link-aarch64 = rbit._EXT_ - -generate int8x8_t, int8x16_t - -/// Reverse bit order -name = vrbit -multi_fn = transmute, {vrbit-signed-noext, transmute(a)} -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -validate 0, 64, 32, 96, 16, 80, 48, 112, 8, 72, 40, 104, 24, 88, 56, 120 - -aarch64 = rbit - -generate uint8x8_t, uint8x16_t, poly8x8_t, poly8x16_t - -/// Rounding halving add -name = vrhadd -a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 22, 22, 23, 23, 24, 24, 25, 25, 26, 26, 27, 27, 28, 28, 29, 29 - -arm = vrhadd.s -aarch64 = urhadd -link-arm = vrhaddu._EXT_ -link-aarch64 = urhadd._EXT_ -generate uint*_t - -arm = vrhadd.s -aarch64 = srhadd -link-arm = vrhadds._EXT_ -link-aarch64 = srhadd._EXT_ -generate int*_t - -/// Floating-point round to integral exact, using current rounding mode -name = vrndx -a = -1.5, 0.5, 1.5, 2.5 -validate -2.0, 0.0, 2.0, 2.0 - -aarch64 = frintx -link-aarch64 = llvm.rint._EXT_ -generate float*_t, float64x*_t - -/// Floating-point round to integral, to nearest with ties to away -name = vrnda -a = -1.5, 0.5, 1.5, 2.5 -validate -2.0, 1.0, 2.0, 3.0 - -aarch64 = frinta -link-aarch64 = llvm.round._EXT_ -generate float*_t, float64x*_t - -/// Floating-point round to integral, to nearest with ties to even -name = vrndn -a = -1.5, 0.5, 1.5, 2.5 -validate -2.0, 0.0, 2.0, 2.0 - -link-aarch64 = frintn._EXT_ -aarch64 = frintn -generate float64x*_t - -target = fp-armv8 -arm = vrintn -link-arm = vrintn._EXT_ -generate float*_t - -/// Floating-point round to integral, to nearest with ties to even -name = vrndn -a = -1.5 -validate -2.0 - -aarch64 = frintn -link-aarch64 = llvm.roundeven._EXT_ -generate f32 - -/// Floating-point round to integral, toward minus infinity -name = vrndm -a = -1.5, 0.5, 1.5, 2.5 -validate -2.0, 0.0, 1.0, 2.0 - -aarch64 = frintm -link-aarch64 = llvm.floor._EXT_ -generate float*_t, float64x*_t - -/// Floating-point round to integral, toward plus infinity -name = vrndp -a = -1.5, 0.5, 1.5, 2.5 -validate -1.0, 1.0, 2.0, 3.0 - -aarch64 = frintp -link-aarch64 = llvm.ceil._EXT_ -generate float*_t, float64x*_t - -/// Floating-point round to integral, toward zero -name = vrnd -a = -1.5, 0.5, 1.5, 2.5 -validate -1.0, 0.0, 1.0, 2.0 - -aarch64 = frintz -link-aarch64 = llvm.trunc._EXT_ -generate float*_t, float64x*_t - -/// Floating-point round to integral, using current rounding mode -name = vrndi -a = -1.5, 0.5, 1.5, 2.5 -validate -2.0, 0.0, 2.0, 2.0 - -aarch64 = frinti -link-aarch64 = llvm.nearbyint._EXT_ -generate float*_t, float64x*_t - -/// Saturating add -name = vqadd -a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 - -arm = vqadd.s -aarch64 = uqadd -link-arm = llvm.uadd.sat._EXT_ -link-aarch64 = uqadd._EXT_ -generate uint*_t, uint64x*_t - -arm = vqadd.s -aarch64 = sqadd -link-arm = llvm.sadd.sat._EXT_ -link-aarch64 = sqadd._EXT_ -generate int*_t, int64x*_t - -/// Saturating add -name = vqadd -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqadd-in_ntt-noext, a, b}, 0 -a = 42 -b = 1 -validate 43 - -aarch64 = sqadd -generate i8, i16 -aarch64 = uqadd -generate u8, u16 - -/// Saturating add -name = vqadd -a = 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42, 42 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58 - -aarch64 = uqadd -link-aarch64 = uqadd._EXT_ -generate u32, u64 - -aarch64 = sqadd -link-aarch64 = sqadd._EXT_ -generate i32, i64 - -/// Load multiple single-element structures to one, two, three, or four registers -name = vld1 -out-suffix -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -load_fn - -aarch64 = ld1 -link-aarch64 = ld1x2._EXT2_ -arm = vld1 -link-arm = vld1x2._EXT2_ -generate *const i8:int8x8x2_t, *const i16:int16x4x2_t, *const i32:int32x2x2_t, *const i64:int64x1x2_t -generate *const i8:int8x16x2_t, *const i16:int16x8x2_t, *const i32:int32x4x2_t, *const i64:int64x2x2_t - -link-aarch64 = ld1x3._EXT2_ -link-arm = vld1x3._EXT2_ -generate *const i8:int8x8x3_t, *const i16:int16x4x3_t, *const i32:int32x2x3_t, *const i64:int64x1x3_t -generate *const i8:int8x16x3_t, *const i16:int16x8x3_t, *const i32:int32x4x3_t, *const i64:int64x2x3_t - -link-aarch64 = ld1x4._EXT2_ -link-arm = vld1x4._EXT2_ -generate *const i8:int8x8x4_t, *const i16:int16x4x4_t, *const i32:int32x2x4_t, *const i64:int64x1x4_t -generate *const i8:int8x16x4_t, *const i16:int16x8x4_t, *const i32:int32x4x4_t, *const i64:int64x2x4_t - -/// Load multiple single-element structures to one, two, three, or four registers -name = vld1 -out-suffix -multi_fn = transmute, {vld1-outsigned-noext, transmute(a)} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 - -load_fn -aarch64 = ld1 -arm = vld1 -generate *const u8:uint8x8x2_t, *const u16:uint16x4x2_t, *const u32:uint32x2x2_t, *const u64:uint64x1x2_t -generate *const u8:uint8x16x2_t, *const u16:uint16x8x2_t, *const u32:uint32x4x2_t, *const u64:uint64x2x2_t -generate *const u8:uint8x8x3_t, *const u16:uint16x4x3_t, *const u32:uint32x2x3_t, *const u64:uint64x1x3_t -generate *const u8:uint8x16x3_t, *const u16:uint16x8x3_t, *const u32:uint32x4x3_t, *const u64:uint64x2x3_t -generate *const u8:uint8x8x4_t, *const u16:uint16x4x4_t, *const u32:uint32x2x4_t, *const u64:uint64x1x4_t -generate *const u8:uint8x16x4_t, *const u16:uint16x8x4_t, *const u32:uint32x4x4_t, *const u64:uint64x2x4_t -generate *const p8:poly8x8x2_t, *const p8:poly8x8x3_t, *const p8:poly8x8x4_t -generate *const p8:poly8x16x2_t, *const p8:poly8x16x3_t, *const p8:poly8x16x4_t -generate *const p16:poly16x4x2_t, *const p16:poly16x4x3_t, *const p16:poly16x4x4_t -generate *const p16:poly16x8x2_t, *const p16:poly16x8x3_t, *const p16:poly16x8x4_t -target = aes -generate *const p64:poly64x1x2_t -arm = nop -generate *const p64:poly64x1x3_t, *const p64:poly64x1x4_t -generate *const p64:poly64x2x2_t, *const p64:poly64x2x3_t, *const p64:poly64x2x4_t -/// Load multiple single-element structures to one, two, three, or four registers -name = vld1 -out-suffix -a = 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16. -validate 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16. -load_fn - -aarch64 = ld1 -link-aarch64 = ld1x2._EXT2_ -generate *const f64:float64x1x2_t, *const f64:float64x2x2_t - -link-aarch64 = ld1x3._EXT2_ -generate *const f64:float64x1x3_t, *const f64:float64x2x3_t - -link-aarch64 = ld1x4._EXT2_ -generate *const f64:float64x1x4_t, *const f64:float64x2x4_t - -arm = vld1 -link-aarch64 = ld1x2._EXT2_ -link-arm = vld1x2._EXT2_ -generate *const f32:float32x2x2_t, *const f32:float32x4x2_t - -link-aarch64 = ld1x3._EXT2_ -link-arm = vld1x3._EXT2_ -generate *const f32:float32x2x3_t, *const f32:float32x4x3_t - -link-aarch64 = ld1x4._EXT2_ -link-arm = vld1x4._EXT2_ -generate *const f32:float32x2x4_t, *const f32:float32x4x4_t - -/// Load multiple 2-element structures to two registers -name = vld2 -out-nox -a = 0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -load_fn -arm-aarch64-separate - -aarch64 = ld2 -link-aarch64 = ld2._EXTv2_ -generate *const i64:int64x2x2_t - -arm = vld2 -link-arm = vld2._EXTpi82_ -generate *const i8:int8x8x2_t, *const i16:int16x4x2_t, *const i32:int32x2x2_t -generate *const i8:int8x16x2_t, *const i16:int16x8x2_t, *const i32:int32x4x2_t -arm = nop -aarch64 = nop -generate *const i64:int64x1x2_t - -/// Load multiple 2-element structures to two registers -name = vld2 -out-nox -multi_fn = transmute, {vld2-outsignednox-noext, transmute(a)} -a = 0, 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -load_fn - -aarch64 = ld2 -generate *const u64:uint64x2x2_t -target = aes -generate *const p64:poly64x2x2_t - -target = default -arm = vld2 -generate *const u8:uint8x8x2_t, *const u16:uint16x4x2_t, *const u32:uint32x2x2_t -generate *const u8:uint8x16x2_t, *const u16:uint16x8x2_t, *const u32:uint32x4x2_t -generate *const p8:poly8x8x2_t, *const p16:poly16x4x2_t, *const p8:poly8x16x2_t, *const p16:poly16x8x2_t -arm = nop -aarch64 = nop -generate *const u64:uint64x1x2_t -target = aes -generate *const p64:poly64x1x2_t - - -/// Load multiple 2-element structures to two registers -name = vld2 -out-nox -a = 0., 1., 2., 2., 3., 2., 4., 3., 5., 2., 6., 3., 7., 4., 8., 5., 9. -validate 1., 2., 2., 3., 2., 3., 4., 5., 2., 3., 4., 5., 6., 7., 8., 9. -load_fn -arm-aarch64-separate - -aarch64 = nop -link-aarch64 = ld2._EXTv2_ -generate *const f64:float64x1x2_t -aarch64 = ld2 -generate *const f64:float64x2x2_t - -arm = vld2 -link-arm = vld2._EXTpi82_ -generate *const f32:float32x2x2_t, *const f32:float32x4x2_t - -/// Load single 2-element structure and replicate to all lanes of two registers -name = vld2 -out-dup-nox -a = 0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn -arm-aarch64-separate - -aarch64 = ld2r -link-aarch64 = ld2r._EXT2_ -generate *const i64:int64x2x2_t - -arm = vld2 -link-arm = vld2dup._EXTpi82_ -generate *const i8:int8x8x2_t, *const i16:int16x4x2_t, *const i32:int32x2x2_t -generate *const i8:int8x16x2_t, *const i16:int16x8x2_t, *const i32:int32x4x2_t -arm = nop -generate *const i64:int64x1x2_t - -/// Load single 2-element structure and replicate to all lanes of two registers -name = vld2 -out-dup-nox -multi_fn = transmute, {vld2-outsigneddupnox-noext, transmute(a)} -a = 0, 1, 1, 2, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn - -aarch64 = ld2r -generate *const u64:uint64x2x2_t -target = aes -generate *const p64:poly64x2x2_t - -target = default -arm = vld2 -generate *const u8:uint8x8x2_t, *const u16:uint16x4x2_t, *const u32:uint32x2x2_t -generate *const u8:uint8x16x2_t, *const u16:uint16x8x2_t, *const u32:uint32x4x2_t -generate *const p8:poly8x8x2_t, *const p16:poly16x4x2_t, *const p8:poly8x16x2_t, *const p16:poly16x8x2_t -arm = nop -generate *const u64:uint64x1x2_t -target = aes -generate *const p64:poly64x1x2_t - -/// Load single 2-element structure and replicate to all lanes of two registers -name = vld2 -out-dup-nox -a = 0., 1., 1., 2., 3., 1., 4., 3., 5. -validate 1., 1., 1., 1., 1., 1., 1., 1. -load_fn -arm-aarch64-separate - -aarch64 = ld2r -link-aarch64 = ld2r._EXT2_ -generate *const f64:float64x1x2_t, *const f64:float64x2x2_t - -arm = vld2 -link-arm = vld2dup._EXTpi82_ -generate *const f32:float32x2x2_t, *const f32:float32x4x2_t - -/// Load multiple 2-element structures to two registers -name = vld2 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -b = 0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 -n = 0 -validate 1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 -load_fn -arm-aarch64-separate - -aarch64 = ld2 -const-aarch64 = LANE -link-aarch64 = ld2lane._EXTpi82_ -generate *const i8:int8x16x2_t:int8x16x2_t, *const i64:int64x1x2_t:int64x1x2_t, *const i64:int64x2x2_t:int64x2x2_t - -arm = vld2 -const-arm = LANE -link-arm = vld2lane._EXTpi82_ -generate *const i8:int8x8x2_t:int8x8x2_t, *const i16:int16x4x2_t:int16x4x2_t, *const i32:int32x2x2_t:int32x2x2_t -generate *const i16:int16x8x2_t:int16x8x2_t, *const i32:int32x4x2_t:int32x4x2_t - -/// Load multiple 2-element structures to two registers -name = vld2 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = transmute, {vld2-outsignedlanenox-::, transmute(a), transmute(b)} -constn = LANE -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -b = 0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 -n = 0 -validate 1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26 -load_fn - -aarch64 = ld2 -const-aarch64 = LANE - -target = aes -generate *const p64:poly64x1x2_t:poly64x1x2_t, *const p64:poly64x2x2_t:poly64x2x2_t - -target = default -generate *const u8:uint8x16x2_t:uint8x16x2_t, *const u64:uint64x1x2_t:uint64x1x2_t, *const u64:uint64x2x2_t:uint64x2x2_t -generate *const p8:poly8x16x2_t:poly8x16x2_t - -arm = vld2 -const-arm = LANE -generate *const u8:uint8x8x2_t:uint8x8x2_t, *const u16:uint16x4x2_t:uint16x4x2_t, *const u32:uint32x2x2_t:uint32x2x2_t -generate *const u16:uint16x8x2_t:uint16x8x2_t, *const u32:uint32x4x2_t:uint32x4x2_t -generate *const p8:poly8x8x2_t:poly8x8x2_t, *const p16:poly16x4x2_t:poly16x4x2_t -generate *const p16:poly16x8x2_t:poly16x8x2_t - -/// Load multiple 2-element structures to two registers -name = vld2 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0., 1., 2., 3., 4., 5., 6., 7., 8. -b = 0., 2., 2., 14., 2., 16., 17., 18. -n = 0 -validate 1., 2., 2., 14., 2., 16., 17., 18. -load_fn -arm-aarch64-separate - -aarch64 = ld2 -const-aarch64 = LANE -link-aarch64 = ld2lane._EXTpi82_ -generate *const f64:float64x1x2_t:float64x1x2_t, *const f64:float64x2x2_t:float64x2x2_t - -arm = vld2 -const-arm = LANE -link-arm = vld2lane._EXTpi82_ -generate *const f32:float32x2x2_t:float32x2x2_t, *const f32:float32x4x2_t:float32x4x2_t - -/// Load multiple 3-element structures to three registers -name = vld3 -out-nox -a = 0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48 -validate 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -load_fn -arm-aarch64-separate - -aarch64 = ld3 -link-aarch64 = ld3._EXTv2_ -generate *const i64:int64x2x3_t - -arm = vld3 -link-arm = vld3._EXTpi82_ -generate *const i8:int8x8x3_t, *const i16:int16x4x3_t, *const i32:int32x2x3_t -generate *const i8:int8x16x3_t, *const i16:int16x8x3_t, *const i32:int32x4x3_t -arm = nop -aarch64 = nop -generate *const i64:int64x1x3_t - -/// Load multiple 3-element structures to three registers -name = vld3 -out-nox -multi_fn = transmute, {vld3-outsignednox-noext, transmute(a)} -a = 0, 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48 -validate 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -load_fn - -aarch64 = ld3 -generate *const u64:uint64x2x3_t -target = aes -generate *const p64:poly64x2x3_t - -target = default -arm = vld3 -generate *const u8:uint8x8x3_t, *const u16:uint16x4x3_t, *const u32:uint32x2x3_t -generate *const u8:uint8x16x3_t, *const u16:uint16x8x3_t, *const u32:uint32x4x3_t -generate *const p8:poly8x8x3_t, *const p16:poly16x4x3_t, *const p8:poly8x16x3_t, *const p16:poly16x8x3_t -arm = nop -aarch64 = nop -generate *const u64:uint64x1x3_t -target = aes -generate *const p64:poly64x1x3_t - -/// Load multiple 3-element structures to three registers -name = vld3 -out-nox -a = 0., 1., 2., 2., 2., 4., 4., 2., 7., 7., 4., 8., 8. -validate 1., 2., 2., 4., 2., 4., 7., 8., 2., 4., 7., 8. -load_fn -arm-aarch64-separate - -aarch64 = nop -link-aarch64 = ld3._EXTv2_ -generate *const f64:float64x1x3_t -aarch64 = ld3 -generate *const f64:float64x2x3_t - -arm = vld3 -link-arm = vld3._EXTpi82_ -generate *const f32:float32x2x3_t, *const f32:float32x4x3_t - -/// Load single 3-element structure and replicate to all lanes of three registers -name = vld3 -out-dup-nox -a = 0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn -arm-aarch64-separate - -aarch64 = ld3r -link-aarch64 = ld3r._EXT2_ -generate *const i64:int64x2x3_t - -arm = vld3 -link-arm = vld3dup._EXTpi82_ -generate *const i8:int8x8x3_t, *const i16:int16x4x3_t, *const i32:int32x2x3_t -generate *const i8:int8x16x3_t, *const i16:int16x8x3_t, *const i32:int32x4x3_t -arm = nop -generate *const i64:int64x1x3_t - -/// Load single 3-element structure and replicate to all lanes of three registers -name = vld3 -out-dup-nox -multi_fn = transmute, {vld3-outsigneddupnox-noext, transmute(a)} -a = 0, 1, 1, 1, 3, 1, 4, 3, 5, 1, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17, 6, 14, 7, 15, 8, 16, 9, 17 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn - -aarch64 = ld3r -generate *const u64:uint64x2x3_t -target = aes -generate *const p64:poly64x2x3_t - -target = default -arm = vld3 -generate *const u8:uint8x8x3_t, *const u16:uint16x4x3_t, *const u32:uint32x2x3_t -generate *const u8:uint8x16x3_t, *const u16:uint16x8x3_t, *const u32:uint32x4x3_t -generate *const p8:poly8x8x3_t, *const p16:poly16x4x3_t, *const p8:poly8x16x3_t, *const p16:poly16x8x3_t -arm = nop -generate *const u64:uint64x1x3_t -target = aes -generate *const p64:poly64x1x3_t - -/// Load single 3-element structure and replicate to all lanes of three registers -name = vld3 -out-dup-nox -a = 0., 1., 1., 1., 3., 1., 4., 3., 5., 1., 4., 3., 5. -validate 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1. -load_fn -arm-aarch64-separate - -aarch64 = ld3r -link-aarch64 = ld3r._EXT2_ -generate *const f64:float64x1x3_t, *const f64:float64x2x3_t - -arm = vld3 -link-arm = vld3dup._EXTpi82_ -generate *const f32:float32x2x3_t, *const f32:float32x4x3_t - -/// Load multiple 3-element structures to two registers -name = vld3 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -b = 0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -n = 0 -validate 1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -load_fn -arm-aarch64-separate - -aarch64 = ld3 -const-aarch64 = LANE -link-aarch64 = ld3lane._EXTpi82_ -generate *const i8:int8x16x3_t:int8x16x3_t, *const i64:int64x1x3_t:int64x1x3_t, *const i64:int64x2x3_t:int64x2x3_t - -arm = vld3 -const-arm = LANE -link-arm = vld3lane._EXTpi82_ -generate *const i8:int8x8x3_t:int8x8x3_t, *const i16:int16x4x3_t:int16x4x3_t, *const i32:int32x2x3_t:int32x2x3_t -generate *const i16:int16x8x3_t:int16x8x3_t, *const i32:int32x4x3_t:int32x4x3_t - -/// Load multiple 3-element structures to three registers -name = vld3 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = transmute, {vld3-outsignedlanenox-::, transmute(a), transmute(b)} -constn = LANE -a = 0, 1, 2, 2, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -b = 0, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -n = 0 -validate 1, 2, 2, 14, 2, 16, 17, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -load_fn - -aarch64 = ld3 -const-aarch64 = LANE -target = aes -generate *const p64:poly64x1x3_t:poly64x1x3_t, *const p64:poly64x2x3_t:poly64x2x3_t -target = default -generate *const p8:poly8x16x3_t:poly8x16x3_t, *const u8:uint8x16x3_t:uint8x16x3_t, *const u64:uint64x1x3_t:uint64x1x3_t, *const u64:uint64x2x3_t:uint64x2x3_t - -arm = vld3 -const-arm = LANE -generate *const u8:uint8x8x3_t:uint8x8x3_t, *const u16:uint16x4x3_t:uint16x4x3_t, *const u32:uint32x2x3_t:uint32x2x3_t -generate *const u16:uint16x8x3_t:uint16x8x3_t, *const u32:uint32x4x3_t:uint32x4x3_t -generate *const p8:poly8x8x3_t:poly8x8x3_t, *const p16:poly16x4x3_t:poly16x4x3_t -generate *const p16:poly16x8x3_t:poly16x8x3_t - -/// Load multiple 3-element structures to three registers -name = vld3 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0., 1., 2., 2., 4., 5., 6., 7., 8., 5., 6., 7., 8. -b = 0., 2., 2., 14., 9., 16., 17., 18., 5., 6., 7., 8. -n = 0 -validate 1., 2., 2., 14., 2., 16., 17., 18., 2., 6., 7., 8. -load_fn -arm-aarch64-separate - -aarch64 = ld3 -const-aarch64 = LANE -link-aarch64 = ld3lane._EXTpi82_ -generate *const f64:float64x1x3_t:float64x1x3_t, *const f64:float64x2x3_t:float64x2x3_t - -arm = vld3 -const-arm = LANE -link-arm = vld3lane._EXTpi82_ -generate *const f32:float32x2x3_t:float32x2x3_t, *const f32:float32x4x3_t:float32x4x3_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-nox -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -validate 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -load_fn -arm-aarch64-separate - -aarch64 = ld4 -link-aarch64 = ld4._EXTv2_ -generate *const i64:int64x2x4_t - -arm = vld4 -link-arm = vld4._EXTpi82_ -generate *const i8:int8x8x4_t, *const i16:int16x4x4_t, *const i32:int32x2x4_t -generate *const i8:int8x16x4_t, *const i16:int16x8x4_t, *const i32:int32x4x4_t -aarch64 = nop -arm = nop -generate *const i64:int64x1x4_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-nox -multi_fn = transmute, {vld4-outsignednox-noext, transmute(a)} -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -validate 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -load_fn - -aarch64 = ld4 -generate *const u64:uint64x2x4_t -target = aes -generate *const p64:poly64x2x4_t - -target = default -arm = vld4 -generate *const u8:uint8x8x4_t, *const u16:uint16x4x4_t, *const u32:uint32x2x4_t -generate *const u8:uint8x16x4_t, *const u16:uint16x8x4_t, *const u32:uint32x4x4_t -generate *const p8:poly8x8x4_t, *const p16:poly16x4x4_t, *const p8:poly8x16x4_t, *const p16:poly16x8x4_t -aarch64 = nop -arm = nop -generate *const u64:uint64x1x4_t -target = aes -generate *const p64:poly64x1x4_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-nox -a = 0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 15., 16. -validate 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 15., 6., 8., 8., 16. -load_fn -arm-aarch64-separate - -aarch64 = nop -link-aarch64 = ld4._EXTv2_ -generate *const f64:float64x1x4_t -aarch64 = ld4 -generate *const f64:float64x2x4_t - -arm = vld4 -link-arm = vld4._EXTpi82_ -generate *const f32:float32x2x4_t, *const f32:float32x4x4_t - -/// Load single 4-element structure and replicate to all lanes of four registers -name = vld4 -out-dup-nox -a = 0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn -arm-aarch64-separate - -aarch64 = ld4r -link-aarch64 = ld4r._EXT2_ -generate *const i64:int64x2x4_t - -arm = vld4 -link-arm = vld4dup._EXTpi82_ -generate *const i8:int8x8x4_t, *const i16:int16x4x4_t, *const i32:int32x2x4_t -generate *const i8:int8x16x4_t, *const i16:int16x8x4_t, *const i32:int32x4x4_t -arm = nop -generate *const i64:int64x1x4_t - -/// Load single 4-element structure and replicate to all lanes of four registers -name = vld4 -out-dup-nox -multi_fn = transmute, {vld4-outsigneddupnox-noext, transmute(a)} -a = 0, 1, 1, 1, 1, 2, 4, 3, 5, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9, 8, 6, 3, 7, 4, 8, 5, 9 -validate 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -load_fn - -aarch64 = ld4r -generate *const u64:uint64x2x4_t -target = aes -generate *const p64:poly64x2x4_t - -target = default -arm = vld4 -generate *const u8:uint8x8x4_t, *const u16:uint16x4x4_t, *const u32:uint32x2x4_t -generate *const u8:uint8x16x4_t, *const u16:uint16x8x4_t, *const u32:uint32x4x4_t -generate *const p8:poly8x8x4_t, *const p16:poly16x4x4_t, *const p8:poly8x16x4_t, *const p16:poly16x8x4_t -arm = nop -generate *const u64:uint64x1x4_t -target = aes -generate *const p64:poly64x1x4_t - -/// Load single 4-element structure and replicate to all lanes of four registers -name = vld4 -out-dup-nox -a = 0., 1., 1., 1., 1., 6., 4., 3., 5., 7., 4., 3., 5., 8., 4., 3., 5., 9., 4., 3., 5. -validate 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1., 1. -load_fn -arm-aarch64-separate - -aarch64 = ld4r -link-aarch64 = ld4r._EXT2_ -generate *const f64:float64x1x4_t, *const f64:float64x2x4_t - -arm = vld4 -link-arm = vld4dup._EXTpi82_ -generate *const f32:float32x2x4_t, *const f32:float32x4x4_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -b = 0, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26, 11, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -n = 0 -validate 1, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26, 2, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 2, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -load_fn -arm-aarch64-separate - -aarch64 = ld4 -const-aarch64 = LANE -link-aarch64 = ld4lane._EXTpi82_ -generate *const i8:int8x16x4_t:int8x16x4_t, *const i64:int64x1x4_t:int64x1x4_t, *const i64:int64x2x4_t:int64x2x4_t - -arm = vld4 -const-arm = LANE -link-arm = vld4lane._EXTpi82_ -generate *const i8:int8x8x4_t:int8x8x4_t, *const i16:int16x4x4_t:int16x4x4_t, *const i32:int32x2x4_t:int32x2x4_t -generate *const i16:int16x8x4_t:int16x8x4_t, *const i32:int32x4x4_t:int32x4x4_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = transmute, {vld4-outsignedlanenox-::, transmute(a), transmute(b)} -constn = LANE -a = 0, 1, 2, 2, 2, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -b = 0, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26, 11, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -n = 0 -validate 1, 2, 2, 2, 2, 16, 2, 18, 2, 20, 21, 22, 2, 24, 25, 26, 2, 12, 13, 14, 15, 16, 2, 18, 2, 20, 21, 22, 23, 24, 25, 26, 2, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8, 2, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16 -load_fn - -aarch64 = ld4 -const-aarch64 = LANE -target = aes -generate *const p64:poly64x1x4_t:poly64x1x4_t, *const p64:poly64x2x4_t:poly64x2x4_t -target = default -generate *const p8:poly8x16x4_t:poly8x16x4_t, *const u8:uint8x16x4_t:uint8x16x4_t, *const u64:uint64x1x4_t:uint64x1x4_t, *const u64:uint64x2x4_t:uint64x2x4_t - -arm = vld4 -const-arm = LANE -generate *const u8:uint8x8x4_t:uint8x8x4_t, *const u16:uint16x4x4_t:uint16x4x4_t, *const u32:uint32x2x4_t:uint32x2x4_t -generate *const u16:uint16x8x4_t:uint16x8x4_t, *const u32:uint32x4x4_t:uint32x4x4_t -generate *const p8:poly8x8x4_t:poly8x8x4_t, *const p16:poly16x4x4_t:poly16x4x4_t -generate *const p16:poly16x8x4_t:poly16x8x4_t - -/// Load multiple 4-element structures to four registers -name = vld4 -out-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -constn = LANE -a = 0., 1., 2., 2., 2., 5., 6., 7., 8., 5., 6., 7., 8., 1., 4., 3., 5. -b = 0., 2., 2., 2., 2., 16., 2., 18., 5., 6., 7., 8., 1., 4., 3., 5. -n = 0 -validate 1., 2., 2., 2., 2., 16., 2., 18., 2., 6., 7., 8., 2., 4., 3., 5. -load_fn -arm-aarch64-separate - -aarch64 = ld4 -const-aarch64 = LANE -link-aarch64 = ld4lane._EXTpi82_ -generate *const f64:float64x1x4_t:float64x1x4_t, *const f64:float64x2x4_t:float64x2x4_t - -arm = vld4 -const-arm = LANE -link-arm = vld4lane._EXTpi82_ -generate *const f32:float32x2x4_t:float32x2x4_t, *const f32:float32x4x4_t:float32x4x4_t - -/// Store multiple single-element structures from one, two, three, or four registers -name = vst1 -in1-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = *a, {simd_extract!, b, LANE as u32} -constn = LANE -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -n = 0 -validate 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn - -aarch64 = nop -arm = nop -generate *mut i8:int8x8_t:void, *mut i16:int16x4_t:void, *mut i32:int32x2_t:void, *mut i64:int64x1_t:void -generate *mut i8:int8x16_t:void, *mut i16:int16x8_t:void, *mut i32:int32x4_t:void, *mut i64:int64x2_t:void -generate *mut u8:uint8x8_t:void, *mut u16:uint16x4_t:void, *mut u32:uint32x2_t:void, *mut u64:uint64x1_t:void -generate *mut u8:uint8x16_t:void, *mut u16:uint16x8_t:void, *mut u32:uint32x4_t:void, *mut u64:uint64x2_t:void -generate *mut p8:poly8x8_t:void, *mut p16:poly16x4_t:void, *mut p8:poly8x16_t:void, *mut p16:poly16x8_t:void -target = aes -generate *mut p64:poly64x1_t:void, *mut p64:poly64x2_t:void - -/// Store multiple single-element structures from one, two, three, or four registers -name = vst1 -in1-lane-nox -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = *a, {simd_extract!, b, LANE as u32} -constn = LANE -a = 0., 1., 2., 3., 4., 5., 6., 7., 8. -n = 0 -validate 1., 0., 0., 0., 0., 0., 0., 0. -store_fn - -aarch64 = nop -generate *mut f64:float64x1_t:void, *mut f64:float64x2_t:void - -arm = nop -generate *mut f32:float32x2_t:void, *mut f32:float32x4_t:void - -/// Store multiple single-element structures from one, two, three, or four registers -name = vst1 -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -store_fn -arm-aarch64-separate - -aarch64 = st1 -link-aarch64 = st1x2._EXT3_ -arm = vst1 -link-arm = vst1x2._EXTr3_ -generate *mut i8:int8x8x2_t:void, *mut i16:int16x4x2_t:void, *mut i32:int32x2x2_t:void, *mut i64:int64x1x2_t:void -generate *mut i8:int8x16x2_t:void, *mut i16:int16x8x2_t:void, *mut i32:int32x4x2_t:void, *mut i64:int64x2x2_t:void - -link-aarch64 = st1x3._EXT3_ -link-arm = vst1x3._EXTr3_ -generate *mut i8:int8x8x3_t:void, *mut i16:int16x4x3_t:void, *mut i32:int32x2x3_t:void, *mut i64:int64x1x3_t:void -generate *mut i8:int8x16x3_t:void, *mut i16:int16x8x3_t:void, *mut i32:int32x4x3_t:void, *mut i64:int64x2x3_t:void - -link-aarch64 = st1x4._EXT3_ -link-arm = vst1x4._EXTr3_ -generate *mut i8:int8x8x4_t:void, *mut i16:int16x4x4_t:void, *mut i32:int32x2x4_t:void, *mut i64:int64x1x4_t:void -generate *mut i8:int8x16x4_t:void, *mut i16:int16x8x4_t:void, *mut i32:int32x4x4_t:void, *mut i64:int64x2x4_t:void - -/// Store multiple single-element structures to one, two, three, or four registers -name = vst1 -multi_fn = vst1-signed-noext, transmute(a), transmute(b) -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32 - -store_fn -aarch64 = st1 -arm = vst1 -generate *mut u8:uint8x8x2_t:void, *mut u16:uint16x4x2_t:void, *mut u32:uint32x2x2_t:void, *mut u64:uint64x1x2_t:void -generate *mut u8:uint8x16x2_t:void, *mut u16:uint16x8x2_t:void, *mut u32:uint32x4x2_t:void, *mut u64:uint64x2x2_t:void -generate *mut u8:uint8x8x3_t:void, *mut u16:uint16x4x3_t:void, *mut u32:uint32x2x3_t:void, *mut u64:uint64x1x3_t:void -generate *mut u8:uint8x16x3_t:void, *mut u16:uint16x8x3_t:void, *mut u32:uint32x4x3_t:void, *mut u64:uint64x2x3_t:void -generate *mut u8:uint8x8x4_t:void, *mut u16:uint16x4x4_t:void, *mut u32:uint32x2x4_t:void, *mut u64:uint64x1x4_t:void -generate *mut u8:uint8x16x4_t:void, *mut u16:uint16x8x4_t:void, *mut u32:uint32x4x4_t:void, *mut u64:uint64x2x4_t:void -generate *mut p8:poly8x8x2_t:void, *mut p8:poly8x8x3_t:void, *mut p8:poly8x8x4_t:void -generate *mut p8:poly8x16x2_t:void, *mut p8:poly8x16x3_t:void, *mut p8:poly8x16x4_t:void -generate *mut p16:poly16x4x2_t:void, *mut p16:poly16x4x3_t:void, *mut p16:poly16x4x4_t:void -generate *mut p16:poly16x8x2_t:void, *mut p16:poly16x8x3_t:void, *mut p16:poly16x8x4_t:void -target = aes -generate *mut p64:poly64x1x2_t:void -arm = nop -generate *mut p64:poly64x1x3_t:void, *mut p64:poly64x1x4_t:void -generate *mut p64:poly64x2x2_t:void, *mut p64:poly64x2x3_t:void, *mut p64:poly64x2x4_t:void - -/// Store multiple single-element structures to one, two, three, or four registers -name = vst1 -a = 0., 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16. -validate 1., 2., 3., 4., 5., 6., 7., 8., 9., 10., 11., 12., 13., 14., 15., 16. -store_fn -arm-aarch64-separate - -aarch64 = st1 -link-aarch64 = st1x2._EXT3_ -generate *mut f64:float64x1x2_t:void, *mut f64:float64x2x2_t:void - -link-aarch64 = st1x3._EXT3_ -generate *mut f64:float64x1x3_t:void, *mut f64:float64x2x3_t:void - -link-aarch64 = st1x4._EXT3_ -generate *mut f64:float64x1x4_t:void, *mut f64:float64x2x4_t:void - -arm = vst1 -link-aarch64 = st1x2._EXT3_ -link-arm = vst1x2._EXTr3_ -generate *mut f32:float32x2x2_t:void, *mut f32:float32x4x2_t:void - -link-aarch64 = st1x3._EXT3_ -link-arm = vst1x3._EXTr3_ -generate *mut f32:float32x2x3_t:void, *mut f32:float32x4x3_t:void - -link-aarch64 = st1x4._EXT3_ -link-arm = vst1x4._EXTr3_ -generate *mut f32:float32x2x4_t:void, *mut f32:float32x4x4_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -in1-nox -a = 0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -validate 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -store_fn -arm-aarch64-separate - -aarch64 = st2 -link-aarch64 = st2._EXTpi8_ -generate *mut i64:int64x2x2_t:void - -arm = vst2 -link-arm = vst2._EXTpi8r_ -generate *mut i8:int8x8x2_t:void, *mut i16:int16x4x2_t:void, *mut i32:int32x2x2_t:void -generate *mut i8:int8x16x2_t:void, *mut i16:int16x8x2_t:void, *mut i32:int32x4x2_t:void -arm = nop -aarch64 = nop -generate *mut i64:int64x1x2_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -multi_fn = vst2-in1signednox-noext, transmute(a), transmute(b) -in1-nox -a = 0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -validate 1, 2, 2, 3, 2, 4, 3, 5, 2, 6, 3, 7, 4, 8, 5, 9, 2, 10, 3, 11, 4, 12, 5, 13, 6, 14, 7, 15, 8, 16, 9, 17 -store_fn - -aarch64 = st2 -generate *mut u64:uint64x2x2_t:void -target = aes -generate *mut p64:poly64x2x2_t:void - -target = default -arm = vst2 -generate *mut u8:uint8x8x2_t:void, *mut u16:uint16x4x2_t:void, *mut u32:uint32x2x2_t:void -generate *mut u8:uint8x16x2_t:void, *mut u16:uint16x8x2_t:void, *mut u32:uint32x4x2_t:void -generate *mut p8:poly8x8x2_t:void, *mut p16:poly16x4x2_t:void, *mut p8:poly8x16x2_t:void, *mut p16:poly16x8x2_t:void -arm = nop -aarch64 = nop -generate *mut u64:uint64x1x2_t:void -target = aes -generate *mut p64:poly64x1x2_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -in1-nox -a = 0., 1., 2., 2., 3., 2., 3., 4., 5., 2., 3., 4., 5., 6., 7., 8., 9. -validate 1., 2., 2., 3., 2., 4., 3., 5., 2., 6., 3., 7., 4., 8., 5., 9. -store_fn -arm-aarch64-separate - -aarch64 = st1 -link-aarch64 = st2._EXTpi8_ -generate *mut f64:float64x1x2_t:void -aarch64 = st2 -generate *mut f64:float64x2x2_t:void - -arm = vst2 -link-arm = vst2._EXTpi8r_ -generate *mut f32:float32x2x2_t:void, *mut f32:float32x4x2_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -n = 0 -validate 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn -arm-aarch64-separate - -aarch64 = st2 -link-aarch64 = st2lane._EXTpi8_ -const-aarch64 = LANE -generate *mut i8:int8x16x2_t:void, *mut i64:int64x1x2_t:void, *mut i64:int64x2x2_t:void - -arm = vst2 -link-arm = vst2lane._EXTpi8r_ -const-arm = LANE -generate *mut i8:int8x8x2_t:void, *mut i16:int16x4x2_t:void, *mut i32:int32x2x2_t:void -generate *mut i16:int16x8x2_t:void, *mut i32:int32x4x2_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vst2-in1signedlanenox-::, transmute(a), transmute(b) -a = 0, 1, 2, 2, 3, 2, 3, 4, 5, 2, 3, 4, 5, 6, 7, 8, 9, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 -n = 0 -validate 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn - -aarch64 = st2 -generate *mut u8:uint8x16x2_t:void, *mut u64:uint64x1x2_t:void, *mut u64:uint64x2x2_t:void, *mut p8:poly8x16x2_t:void -target = aes -generate *mut p64:poly64x1x2_t:void, *mut p64:poly64x2x2_t:void - -target = default -arm = vst2 -generate *mut u8:uint8x8x2_t:void, *mut u16:uint16x4x2_t:void, *mut u32:uint32x2x2_t:void -generate *mut u16:uint16x8x2_t:void, *mut u32:uint32x4x2_t:void -generate *mut p8:poly8x8x2_t:void, *mut p16:poly16x4x2_t:void, *mut p16:poly16x8x2_t:void - -/// Store multiple 2-element structures from two registers -name = vst2 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0., 1., 2., 2., 3., 2., 3., 4., 5., 2., 3., 4., 5., 6., 7., 8., 9. -n = 0 -validate 1., 2., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0. -store_fn -arm-aarch64-separate - -aarch64 = st2 -link-aarch64 = st2lane._EXTpi8_ -const-aarch64 = LANE -generate *mut f64:float64x1x2_t:void, *mut f64:float64x2x2_t:void - -arm = vst2 -link-arm = vst2lane._EXTpi8r_ -const-arm = LANE -generate *mut f32:float32x2x2_t:void, *mut f32:float32x4x2_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -in1-nox -a = 0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -validate 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48 -store_fn -arm-aarch64-separate - -aarch64 = st3 -link-aarch64 = st3._EXTpi8_ -generate *mut i64:int64x2x3_t:void - -arm = vst3 -link-arm = vst3._EXTpi8r_ -generate *mut i8:int8x8x3_t:void, *mut i16:int16x4x3_t:void, *mut i32:int32x2x3_t:void -generate *mut i8:int8x16x3_t:void, *mut i16:int16x8x3_t:void, *mut i32:int32x4x3_t:void -arm = nop -aarch64 = nop -generate *mut i64:int64x1x3_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -multi_fn = vst3-in1signednox-noext, transmute(a), transmute(b) -in1-nox -a = 0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -validate 1, 2, 2, 2, 4, 4, 2, 7, 7, 4, 8, 8, 2, 13, 13, 4, 14, 14, 7, 15, 15, 8, 16, 16, 2, 25, 41, 4, 26, 42, 7, 27, 43, 8, 28, 44, 13, 29, 45, 14, 30, 46, 15, 31, 47, 16, 32, 48 -store_fn - -aarch64 = st3 -generate *mut u64:uint64x2x3_t:void -target = aes -generate *mut p64:poly64x2x3_t:void - -target = default -arm = vst3 -generate *mut u8:uint8x8x3_t:void, *mut u16:uint16x4x3_t:void, *mut u32:uint32x2x3_t:void -generate *mut u8:uint8x16x3_t:void, *mut u16:uint16x8x3_t:void, *mut u32:uint32x4x3_t:void -generate *mut p8:poly8x8x3_t:void, *mut p16:poly16x4x3_t:void, *mut p8:poly8x16x3_t:void, *mut p16:poly16x8x3_t:void -arm = nop -aarch64 = nop -generate *mut u64:uint64x1x3_t:void -target = aes -generate *mut p64:poly64x1x3_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -in1-nox -a = 0., 1., 2., 2., 4., 2., 4., 7., 8., 2., 4., 7., 8., 13., 14., 15., 16 -validate 1., 2., 2., 2., 4., 4., 2., 7., 7., 4., 8., 8., 2., 13., 13., 4. -store_fn -arm-aarch64-separate - -aarch64 = nop -link-aarch64 = st3._EXTpi8_ -generate *mut f64:float64x1x3_t:void -aarch64 = st3 -generate *mut f64:float64x2x3_t:void - -arm = vst3 -link-arm = vst3._EXTpi8r_ -generate *mut f32:float32x2x3_t:void, *mut f32:float32x4x3_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -n = 0 -validate 1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn -arm-aarch64-separate - -aarch64 = st3 -link-aarch64 = st3lane._EXTpi8_ -const-aarch64 = LANE -generate *mut i8:int8x16x3_t:void, *mut i64:int64x1x3_t:void, *mut i64:int64x2x3_t:void - -arm = vst3 -link-arm = vst3lane._EXTpi8r_ -const-arm = LANE -generate *mut i8:int8x8x3_t:void, *mut i16:int16x4x3_t:void, *mut i32:int32x2x3_t:void -generate *mut i16:int16x8x3_t:void, *mut i32:int32x4x3_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vst3-in1signedlanenox-::, transmute(a), transmute(b) -a = 0, 1, 2, 2, 4, 2, 4, 7, 8, 2, 4, 7, 8, 13, 14, 15, 16, 2, 4, 7, 8, 13, 14, 15, 16, 25, 26, 27, 28, 29, 30, 31, 32, 2, 4, 7, 8, 13, 14, 15, 16, 41, 42, 43, 44, 45, 46, 47, 48 -n = 0 -validate 1, 2, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn - -aarch64 = st3 -generate *mut u8:uint8x16x3_t:void, *mut u64:uint64x1x3_t:void, *mut u64:uint64x2x3_t:void, *mut p8:poly8x16x3_t:void -target = aes -generate *mut p64:poly64x1x3_t:void, *mut p64:poly64x2x3_t:void - -target = default -arm = vst3 -generate *mut u8:uint8x8x3_t:void, *mut u16:uint16x4x3_t:void, *mut u32:uint32x2x3_t:void -generate *mut u16:uint16x8x3_t:void, *mut u32:uint32x4x3_t:void -generate *mut p8:poly8x8x3_t:void, *mut p16:poly16x4x3_t:void, *mut p16:poly16x8x3_t:void - -/// Store multiple 3-element structures from three registers -name = vst3 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0., 1., 2., 2., 3., 2., 3., 4., 5., 2., 3., 4., 5., 6., 7., 8., 9. -n = 0 -validate 1., 2., 2., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0. -store_fn -arm-aarch64-separate - -aarch64 = st3 -link-aarch64 = st3lane._EXTpi8_ -const-aarch64 = LANE -generate *mut f64:float64x1x3_t:void, *mut f64:float64x2x3_t:void - -arm = vst3 -link-arm = vst3lane._EXTpi8r_ -const-arm = LANE -generate *mut f32:float32x2x3_t:void, *mut f32:float32x4x3_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -in1-nox -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -validate 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -store_fn -arm-aarch64-separate - -aarch64 = st4 -link-aarch64 = st4._EXTpi8_ -generate *mut i64:int64x2x4_t:void - -arm = vst4 -link-arm = vst4._EXTpi8r_ -generate *mut i8:int8x8x4_t:void, *mut i16:int16x4x4_t:void, *mut i32:int32x2x4_t:void -generate *mut i8:int8x16x4_t:void, *mut i16:int16x8x4_t:void, *mut i32:int32x4x4_t:void -arm = nop -aarch64 = nop -generate *mut i64:int64x1x4_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -multi_fn = vst4-in1signednox-noext, transmute(a), transmute(b) -in1-nox -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -validate 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -store_fn - -aarch64 = st4 -generate *mut u64:uint64x2x4_t:void -target = aes -generate *mut p64:poly64x2x4_t:void - -target = default -arm = vst4 -generate *mut u8:uint8x8x4_t:void, *mut u16:uint16x4x4_t:void, *mut u32:uint32x2x4_t:void -generate *mut u8:uint8x16x4_t:void, *mut u16:uint16x8x4_t:void, *mut u32:uint32x4x4_t:void -generate *mut p8:poly8x8x4_t:void, *mut p16:poly16x4x4_t:void, *mut p8:poly8x16x4_t:void, *mut p16:poly16x8x4_t:void -arm = nop -aarch64 = nop -generate *mut u64:uint64x1x4_t:void -target = aes -generate *mut p64:poly64x1x4_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -in1-nox -a = 0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16. -validate 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16. -store_fn -arm-aarch64-separate - -aarch64 = nop -link-aarch64 = st4._EXTpi8_ -generate *mut f64:float64x1x4_t:void -aarch64 = st4 -generate *mut f64:float64x2x4_t:void - -arm = vst4 -link-arm = vst4._EXTpi8r_ -generate *mut f32:float32x2x4_t:void, *mut f32:float32x4x4_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -n = 0 -validate 1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn -arm-aarch64-separate - -aarch64 = st4 -link-aarch64 = st4lane._EXTpi8_ -const-aarch64 = LANE -generate *mut i8:int8x16x4_t:void, *mut i64:int64x1x4_t:void, *mut i64:int64x2x4_t:void - -arm = vst4 -link-arm = vst4lane._EXTpi8r_ -const-arm = LANE -generate *mut i8:int8x8x4_t:void, *mut i16:int16x4x4_t:void, *mut i32:int32x2x4_t:void -generate *mut i16:int16x8x4_t:void, *mut i32:int32x4x4_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vst4-in1signedlanenox-::, transmute(a), transmute(b) -a = 0, 1, 2, 2, 6, 2, 6, 6, 8, 2, 6, 6, 8, 6, 8, 8, 16, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 8, 16, 8, 16, 16, 32, 2, 6, 6, 8, 6, 8, 8, 16, 6, 8, 43, 44, 8, 16, 44, 48, 6, 8, 8, 16, 8, 16, 16, 32, 8, 16, 44, 48, 16, 32, 48, 64 -n = 0 -validate 1, 2, 2, 6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -store_fn - -aarch64 = st4 -generate *mut u8:uint8x16x4_t:void, *mut u64:uint64x1x4_t:void, *mut u64:uint64x2x4_t:void, *mut p8:poly8x16x4_t:void -target = aes -generate *mut p64:poly64x1x4_t:void, *mut p64:poly64x2x4_t:void - -target = default -arm = vst4 -generate *mut u8:uint8x8x4_t:void, *mut u16:uint16x4x4_t:void, *mut u32:uint32x2x4_t:void -generate *mut u16:uint16x8x4_t:void, *mut u32:uint32x4x4_t:void -generate *mut p8:poly8x8x4_t:void, *mut p16:poly16x4x4_t:void, *mut p16:poly16x8x4_t:void - -/// Store multiple 4-element structures from four registers -name = vst4 -in1-lane-nox -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -a = 0., 1., 2., 2., 6., 2., 6., 6., 8., 2., 6., 6., 8., 6., 8., 8., 16. -n = 0 -validate 1., 2., 2., 6., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0., 0. -store_fn -arm-aarch64-separate - -aarch64 = st4 -link-aarch64 = st4lane._EXTpi8_ -const-aarch64 = LANE -generate *mut f64:float64x1x4_t:void, *mut f64:float64x2x4_t:void - -arm = vst4 -link-arm = vst4lane._EXTpi8r_ -const-arm = LANE -generate *mut f32:float32x2x4_t:void, *mut f32:float32x4x4_t:void - -/// Dot product vector form with unsigned and signed integers -name = vusdot -out-suffix -a = 1000, -4200, -1000, 2000 -b = 100, 205, 110, 195, 120, 185, 130, 175, 140, 165, 150, 155, 160, 145, 170, 135 -c = 0, 1, 2, 3, -1, -2, -3, -4, 4, 5, 6, 7, -5, -6, -7, -8 -aarch64 = usdot -arm = vusdot -target = i8mm - -// 1000 + (100, 205, 110, 195) . ( 0, 1, 2, 3) -// -4200 + (120, 185, 130, 175) . (-1, -2, -3, -4) -// ... -validate 2010, -5780, 2370, -1940 - -link-arm = usdot._EXT2_._EXT4_:int32x2_t:uint8x8_t:int8x8_t:int32x2_t -link-aarch64 = usdot._EXT2_._EXT4_:int32x2_t:uint8x8_t:int8x8_t:int32x2_t -generate int32x2_t:uint8x8_t:int8x8_t:int32x2_t - -link-arm = usdot._EXT2_._EXT4_:int32x4_t:uint8x16_t:int8x16_t:int32x4_t -link-aarch64 = usdot._EXT2_._EXT4_:int32x4_t:uint8x16_t:int8x16_t:int32x4_t -generate int32x4_t:uint8x16_t:int8x16_t:int32x4_t - -/// Dot product index form with unsigned and signed integers -name = vusdot -out-lane-suffixes -constn = LANE -aarch64 = usdot -arm = vusdot -target = i8mm -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_signed, c, c, {dup-out_len-LANE as u32} -multi_fn = vusdot-out-noext, a, b, {transmute, c} -a = 1000, -4200, -1000, 2000 -b = 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250 -c = 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11 - -// 1000 + (100, 110, 120, 130) . (4, 3, 2, 1) -// -4200 + (140, 150, 160, 170) . (4, 3, 2, 1) -// ... -n = 0 -validate 2100, -2700, 900, 4300 - -// 1000 + (100, 110, 120, 130) . (0, -1, -2, -3) -// -4200 + (140, 150, 160, 170) . (0, -1, -2, -3) -// ... -n = 1 -validate 260, -5180, -2220, 540 - -generate int32x2_t:uint8x8_t:int8x8_t:int32x2_t -generate int32x4_t:uint8x16_t:int8x8_t:int32x4_t - -/// Dot product index form with unsigned and signed integers -name = vusdot -out-lane-suffixes -constn = LANE -// Only AArch64 has the laneq forms. -aarch64 = usdot -target = i8mm -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_signed, c, c, {dup-out_len-LANE as u32} -multi_fn = vusdot-out-noext, a, b, {transmute, c} -a = 1000, -4200, -1000, 2000 -b = 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250 -c = 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11 - -// 1000 + (100, 110, 120, 130) . (-4, -5, -6, -7) -// -4200 + (140, 150, 160, 170) . (-4, -5, -6, -7) -// ... -n = 3 -validate -3420, -10140, -8460, -6980 - -generate int32x2_t:uint8x8_t:int8x16_t:int32x2_t -generate int32x4_t:uint8x16_t:int8x16_t:int32x4_t - -/// Dot product index form with signed and unsigned integers -name = vsudot -out-lane-suffixes -constn = LANE -aarch64 = sudot -arm = vsudot -target = i8mm - -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_unsigned, c, c, {dup-out_len-LANE as u32} -multi_fn = vusdot-out-noext, a, {transmute, c}, b -a = -2000, 4200, -1000, 2000 -b = 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11 -c = 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250 - -// -2000 + (4, 3, 2, 1) . (100, 110, 120, 130) -// 4200 + (0, -1, -2, -3) . (100, 110, 120, 130) -// ... -n = 0 -validate -900, 3460, -3580, -2420 - -// -2000 + (4, 3, 2, 1) . (140, 150, 160, 170) -// 4200 + (0, -1, -2, -3) . (140, 150, 160, 170) -// ... -n = 1 -validate -500, 3220, -4460, -3940 - -generate int32x2_t:int8x8_t:uint8x8_t:int32x2_t -generate int32x4_t:int8x16_t:uint8x8_t:int32x4_t - -/// Dot product index form with signed and unsigned integers -name = vsudot -out-lane-suffixes -constn = LANE -// Only AArch64 has the laneq forms. -aarch64 = sudot -target = i8mm - -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_unsigned, c, c, {dup-out_len-LANE as u32} -multi_fn = vusdot-out-noext, a, {transmute, c}, b -a = -2000, 4200, -1000, 2000 -b = 4, 3, 2, 1, 0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11 -c = 100, 110, 120, 130, 140, 150, 160, 170, 180, 190, 200, 210, 220, 230, 240, 250 - -// -2000 + (4, 3, 2, 1) . (220, 230, 240, 250) -// 4200 + (0, -1, -2, -3) . (220, 230, 240, 250) -// ... -n = 3 -validate 300, 2740, -6220, -6980 - -generate int32x2_t:int8x8_t:uint8x16_t:int32x2_t -generate int32x4_t:int8x16_t:uint8x16_t:int32x4_t - -/// Multiply -name = vmul -a = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32 -arm = vmul. -aarch64 = mul -fn = simd_mul -generate int*_t, uint*_t - -/// Polynomial multiply -name = vmul -a = 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -validate 1, 6, 3, 12, 5, 10, 7, 24, 9, 30, 11, 20, 13, 18, 15, 48 - -aarch64 = pmul -link-aarch64 = pmul._EXT_ -arm = vmul -link-arm = vmulp._EXT_ -generate poly8x8_t, poly8x16_t - -/// Multiply -name = vmul -fn = simd_mul -a = 1.0, 2.0, 1.0, 2.0 -b = 2.0, 3.0, 4.0, 5.0 -validate 2.0, 6.0, 4.0, 10.0 - -aarch64 = fmul -generate float64x*_t - -arm = vmul. -generate float*_t - -/// Vector multiply by scalar -name = vmul -out-n-suffix -multi_fn = simd_mul, a, {vdup-nout-noext, b} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2 -validate 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 - -arm = vmul -aarch64 = mul -generate int16x4_t:i16:int16x4_t, int16x8_t:i16:int16x8_t, int32x2_t:i32:int32x2_t, int32x4_t:i32:int32x4_t -generate uint16x4_t:u16:uint16x4_t, uint16x8_t:u16:uint16x8_t, uint32x2_t:u32:uint32x2_t, uint32x4_t:u32:uint32x4_t - -/// Vector multiply by scalar -name = vmul -out-n-suffix -multi_fn = simd_mul, a, {vdup-nout-noext, b} -a = 1., 2., 3., 4. -b = 2. -validate 2., 4., 6., 8. - -aarch64 = fmul -generate float64x1_t:f64:float64x1_t, float64x2_t:f64:float64x2_t - -arm = vmul -generate float32x2_t:f32:float32x2_t, float32x4_t:f32:float32x4_t - -/// Multiply -name = vmul -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_mul, a, {simd_shuffle!, b, b, {dup-out_len-LANE as u32}} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 - -aarch64 = mul -arm = vmul -generate int16x4_t, int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x2_t:int32x4_t, int32x4_t -generate uint16x4_t, uint16x4_t:uint16x8_t:uint16x4_t, uint16x8_t:uint16x4_t:uint16x8_t, uint16x8_t -generate uint32x2_t, uint32x2_t:uint32x4_t:uint32x2_t, uint32x4_t:uint32x2_t:uint32x4_t, uint32x4_t - -/// Floating-point multiply -name = vmul -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_mul, a, {transmute--, {simd_extract!, b, LANE as u32}} -a = 1., 2., 3., 4. -b = 2., 0., 0., 0. -n = 0 -validate 2., 4., 6., 8. - -aarch64 = fmul -generate float64x1_t, float64x1_t:float64x2_t:float64x1_t - -/// Floating-point multiply -name = vmul -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_mul, a, {simd_shuffle!, b, b, {dup-out_len-LANE as u32}} -a = 1., 2., 3., 4. -b = 2., 0., 0., 0. -n = 0 -validate 2., 4., 6., 8. - -aarch64 = fmul -generate float64x2_t:float64x1_t:float64x2_t, float64x2_t - -arm = vmul -generate float32x2_t, float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Floating-point multiply -name = vmuls_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_extract!, b:f32, b, LANE as u32 -multi_fn = a * b -a = 1. -b = 2., 0., 0., 0. -n = 0 -validate 2. -aarch64 = fmul -generate f32:float32x2_t:f32, f32:float32x4_t:f32 - -/// Floating-point multiply -name = vmuld_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_extract!, b:f64, b, LANE as u32 -multi_fn = a * b -a = 1. -b = 2., 0. -n = 0 -validate 2. -aarch64 = fmul -generate f64:float64x1_t:f64, f64:float64x2_t:f64 - -/// Signed multiply long -name = vmull -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -validate 1, 4, 3, 8, 5, 12, 7, 16, 9, 20, 11, 24, 13, 28, 15, 32 - -arm = vmull.s -aarch64 = smull -link-arm = vmulls._EXT_ -link-aarch64 = smull._EXT_ -generate int8x8_t:int8x8_t:int16x8_t, int16x4_t:int16x4_t:int32x4_t, int32x2_t:int32x2_t:int64x2_t - -/// Signed multiply long -name = vmull_high -no-q -multi_fn = simd_shuffle!, a:half, a, a, {fixed-half-right} -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = vmull-noqself-noext, a, b -a = 1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 9, 20, 11, 24, 13, 28, 15, 32 - -aarch64 = smull2 -generate int8x16_t:int8x16_t:int16x8_t, int16x8_t:int16x8_t:int32x4_t, int32x4_t:int32x4_t:int64x2_t - -/// Unsigned multiply long -name = vmull -a = 1, 2, 3, 4, 5, 6, 7, 8 -b = 1, 2, 1, 2, 1, 2, 1, 2 -validate 1, 4, 3, 8, 5, 12, 7, 16 - -arm = vmull.s -aarch64 = umull -link-arm = vmullu._EXT_ -link-aarch64 = umull._EXT_ -generate uint8x8_t:uint8x8_t:uint16x8_t, uint16x4_t:uint16x4_t:uint32x4_t, uint32x2_t:uint32x2_t:uint64x2_t - -/// Unsigned multiply long -name = vmull_high -no-q -multi_fn = simd_shuffle!, a:half, a, a, {fixed-half-right} -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = vmull-noqself-noext, a, b -a = 1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 9, 20, 11, 24, 13, 28, 15, 32 - -aarch64 = umull2 -generate uint8x16_t:uint8x16_t:uint16x8_t, uint16x8_t:uint16x8_t:uint32x4_t, uint32x4_t:uint32x4_t:uint64x2_t - -/// Polynomial multiply long -name = vmull -a = 1, 2, 3, 4, 5, 6, 7, 8 -b = 1, 3, 1, 3, 1, 3, 1, 3 -validate 1, 6, 3, 12, 5, 10, 7, 24 - -arm = vmull.s -aarch64 = pmull -link-arm = vmullp._EXT_ -link-aarch64 = pmull._EXT_ -generate poly8x8_t:poly8x8_t:poly16x8_t - -/// Polynomial multiply long -name = vmull -no-q -a = 15 -b = 3 -validate 17 -target = aes - -aarch64 = pmull -link-aarch64 = pmull64:p64:p64:p64:int8x16_t -// Because of the support status of llvm, vmull_p64 is currently only available on arm -// arm = vmull -// link-arm = vmullp.v2i64:int64x1_t:int64x1_t:int64x1_t:int64x2_t -generate p64:p64:p128 - - -/// Polynomial multiply long -name = vmull_high -no-q -multi_fn = simd_shuffle!, a:half, a, a, {fixed-half-right} -multi_fn = simd_shuffle!, b:half, b, b, {fixed-half-right} -multi_fn = vmull-noqself-noext, a, b -a = 1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3, 1, 3 -fixed = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 9, 30, 11, 20, 13, 18, 15, 48 - -aarch64 = pmull -generate poly8x16_t:poly8x16_t:poly16x8_t - -/// Polynomial multiply long -name = vmull_high -no-q -multi_fn = vmull-noqself-noext, {simd_extract!, a, 1}, {simd_extract!, b, 1} -a = 1, 15 -b = 1, 3 -validate 17 -target = aes - -aarch64 = pmull -generate poly64x2_t:poly64x2_t:p128 - -/// Vector long multiply with scalar -name = vmull_n -no-q -multi_fn = vmull-in0-noext, a, {vdup-nin0-noext, b} -a = 1, 2, 3, 4, 5, 6, 7, 8 -b = 2 -validate 2, 4, 6, 8, 10, 12, 14, 16 - -arm = vmull -aarch64 = smull -generate int16x4_t:i16:int32x4_t, int32x2_t:i32:int64x2_t -aarch64 = umull -generate uint16x4_t:u16:uint32x4_t, uint32x2_t:u32:uint64x2_t - -/// Vector long multiply by scalar -name = vmull_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vmull-in0-noext, a, {simd_shuffle!, b, b, {dup-in0_len-LANE as u32}} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32 - -arm = vmull -aarch64 = smull -generate int16x4_t:int16x4_t:int32x4_t, int16x4_t:int16x8_t:int32x4_t -generate int32x2_t:int32x2_t:int64x2_t, int32x2_t:int32x4_t:int64x2_t -aarch64 = umull -generate uint16x4_t:uint16x4_t:uint32x4_t, uint16x4_t:uint16x8_t:uint32x4_t -generate uint32x2_t:uint32x2_t:uint64x2_t, uint32x2_t:uint32x4_t:uint64x2_t - -/// Multiply long -name = vmull_high_n -no-q -multi_fn = vmull_high-noqself-noext, a, {vdup-nin0-noext, b} -a = 1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2 -validate 18, 20, 22, 24, 26, 28, 30, 32 - -aarch64 = smull2 -generate int16x8_t:i16:int32x4_t, int32x4_t:i32:int64x2_t -aarch64 = umull2 -generate uint16x8_t:u16:uint32x4_t, uint32x4_t:u32:uint64x2_t - -/// Multiply long -name = vmull_high_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vmull_high-noqself-noext, a, {simd_shuffle!, b, b, {dup-in0_len-LANE as u32}} -a = 1, 2, 9, 10, 9, 10, 11, 12, 9, 10, 11, 12, 13, 14, 15, 16 -b = 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -n = 1 -validate 18, 20, 22, 24, 26, 28, 30, 32 - -aarch64 = smull2 -generate int16x8_t:int16x4_t:int32x4_t, int16x8_t:int16x8_t:int32x4_t -generate int32x4_t:int32x2_t:int64x2_t, int32x4_t:int32x4_t:int64x2_t -aarch64 = umull2 -generate uint16x8_t:uint16x4_t:uint32x4_t, uint16x8_t:uint16x8_t:uint32x4_t -generate uint32x4_t:uint32x2_t:uint64x2_t, uint32x4_t:uint32x4_t:uint64x2_t - -/// Floating-point multiply extended -name = vmulx -a = 1., 2., 3., 4. -b = 2., 2., 2., 2. -validate 2., 4., 6., 8. - -aarch64 = fmulx -link-aarch64 = fmulx._EXT_ -generate float*_t, float64x*_t - -/// Floating-point multiply extended -name = vmulx -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vmulx-in0-noext, a, {transmute--, {simd_extract!, b, LANE as u32}} -a = 1. -b = 2., 0. -n = 0 -validate 2. - -aarch64 = fmulx -generate float64x1_t, float64x1_t:float64x2_t:float64x1_t - -/// Floating-point multiply extended -name = vmulx -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vmulx-in0-noext, a, {simd_shuffle!, b, b, {dup-in0_len-LANE as u32}} -a = 1., 2., 3., 4. -b = 2., 0., 0., 0. -n = 0 -validate 2., 4., 6., 8. - -aarch64 = fmulx -generate float32x2_t, float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x2_t:float32x4_t, float32x4_t -generate float64x2_t:float64x1_t:float64x2_t, float64x2_t - -/// Floating-point multiply extended -name = vmulx -a = 2. -b = 3. -validate 6. - -aarch64 = fmulx -link-aarch64 = fmulx._EXT_ -generate f32, f64 - -/// Floating-point multiply extended -name = vmulx -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vmulx-out-noext, a, {simd_extract!, b, LANE as u32} - -a = 2. -b = 3., 0., 0., 0. -n = 0 -validate 6. - -aarch64 = fmulx -generate f32:float32x2_t:f32, f32:float32x4_t:f32, f64:float64x1_t:f64, f64:float64x2_t:f64 - -/// Floating-point fused Multiply-Add to accumulator(vector) -name = vfma -multi_fn = vfma-self-_, b, c, a -a = 8.0, 18.0, 12.0, 10.0 -b = 6.0, 4.0, 7.0, 8.0 -c = 2.0, 3.0, 4.0, 5.0 -validate 20.0, 30.0, 40.0, 50.0 - -link-aarch64 = llvm.fma._EXT_ -aarch64 = fmadd -generate float64x1_t -aarch64 = fmla -generate float64x2_t - -target = vfp4 -arm = vfma -link-arm = llvm.fma._EXT_ -generate float*_t - -/// Floating-point fused Multiply-Add to accumulator(vector) -name = vfma -n-suffix -multi_fn = vfma-self-noext, a, b, {vdup-nselfvfp4-noext, c} -a = 2.0, 3.0, 4.0, 5.0 -b = 6.0, 4.0, 7.0, 8.0 -c = 8.0 -validate 50.0, 35.0, 60.0, 69.0 - -aarch64 = fmadd -generate float64x1_t:float64x1_t:f64:float64x1_t -aarch64 = fmla -generate float64x2_t:float64x2_t:f64:float64x2_t - -target = vfp4 -arm = vfma -generate float32x2_t:float32x2_t:f32:float32x2_t, float32x4_t:float32x4_t:f32:float32x4_t - -/// Floating-point fused multiply-add to accumulator -name = vfma -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vfma-out-noext, a, b, {vdup-nout-noext, {simd_extract!, c, LANE as u32}} -a = 2., 3., 4., 5. -b = 6., 4., 7., 8. -c = 2., 0., 0., 0. -n = 0 -validate 14., 11., 18., 21. - -aarch64 = fmla -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t -aarch64 = fmadd -generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t -aarch64 = fmla -generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t - -/// Floating-point fused multiply-add to accumulator -name = vfma -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = simd_extract!, c:out_t, c, LANE as u32 -multi_fn = vfma-in2lane-_, b, c, a -a = 2. -b = 6. -c = 3., 0., 0., 0. -n = 0 -validate 20. - -aarch64 = fmadd -link-aarch64 = llvm.fma._EXT_:f32:f32:f32:f32 -generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32 -link-aarch64 = llvm.fma._EXT_:f64:f64:f64:f64 -generate f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64 - -/// Floating-point fused multiply-subtract from accumulator -name = vfms -multi_fn = simd_neg, b:in_t, b -multi_fn = vfma-self-noext, a, b, c -a = 20.0, 30.0, 40.0, 50.0 -b = 6.0, 4.0, 7.0, 8.0 -c = 2.0, 3.0, 4.0, 5.0 -validate 8.0, 18.0, 12.0, 10.0 - -aarch64 = fmsub -generate float64x1_t -aarch64 = fmls -generate float64x2_t - -target = vfp4 -arm = vfms -generate float*_t - -/// Floating-point fused Multiply-subtract to accumulator(vector) -name = vfms -n-suffix -multi_fn = vfms-self-noext, a, b, {vdup-nselfvfp4-noext, c} -a = 50.0, 35.0, 60.0, 69.0 -b = 6.0, 4.0, 7.0, 8.0 -c = 8.0 -validate 2.0, 3.0, 4.0, 5.0 - -aarch64 = fmsub -generate float64x1_t:float64x1_t:f64:float64x1_t -aarch64 = fmls -generate float64x2_t:float64x2_t:f64:float64x2_t - -target = vfp4 -arm = vfms -generate float32x2_t:float32x2_t:f32:float32x2_t, float32x4_t:float32x4_t:f32:float32x4_t - -/// Floating-point fused multiply-subtract to accumulator -name = vfms -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vfms-out-noext, a, b, {vdup-nout-noext, {simd_extract!, c, LANE as u32}} -a = 14., 11., 18., 21. -b = 6., 4., 7., 8. -c = 2., 0., 0., 0. -n = 0 -validate 2., 3., 4., 5. - -aarch64 = fmls -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t, float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t -aarch64 = fmsub -generate float64x1_t, float64x1_t:float64x1_t:float64x2_t:float64x1_t -aarch64 = fmls -generate float64x2_t:float64x2_t:float64x1_t:float64x2_t, float64x2_t - -/// Floating-point fused multiply-subtract to accumulator -name = vfms -in2-lane-suffixes -constn = LANE -multi_fn = vfma-in2lane-::, a, -b, c -a = 14. -b = 6. -c = 2., 0., 0., 0. -n = 0 -validate 2. - -aarch64 = fmsub -generate f32:f32:float32x2_t:f32, f32:f32:float32x4_t:f32, f64:f64:float64x1_t:f64, f64:f64:float64x2_t:f64 - -/// Divide -name = vdiv -fn = simd_div -a = 2.0, 6.0, 4.0, 10.0 -b = 1.0, 2.0, 1.0, 2.0 -validate 2.0, 3.0, 4.0, 5.0 - -aarch64 = fdiv -generate float*_t, float64x*_t - -/// Subtract -name = vsub -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -validate 0, 0, 2, 2, 4, 4, 6, 6, 8, 8, 10, 10, 12, 12, 14, 14 -arm = vsub. -aarch64 = sub -fn = simd_sub -generate int*_t, uint*_t, int64x*_t, uint64x*_t - -/// Subtract -name = vsub -fn = simd_sub -a = 1.0, 4.0, 3.0, 8.0 -b = 1.0, 2.0, 3.0, 4.0 -validate 0.0, 2.0, 0.0, 4.0 - -aarch64 = fsub -generate float64x*_t - -arm = vsub. -generate float*_t - -/// Subtract -name = vsub -multi_fn = a.wrapping_sub(b) -a = 3 -b = 2 -validate 1 - -aarch64 = nop -generate i64, u64 - -/// Add -name = vadd -multi_fn = a.wrapping_add(b) -a = 1 -b = 2 -validate 3 - -aarch64 = nop -generate i64, u64 - -/// Bitwise exclusive OR -name = vadd -multi_fn = simd_xor, a, b -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -validate 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14, 17 - -aarch64 = nop -arm = nop -generate poly8x8_t, poly16x4_t, poly8x16_t, poly16x8_t, poly64x1_t, poly64x2_t - -/// Bitwise exclusive OR -name = vaddq -no-q -multi_fn = a ^ b -a = 16 -b = 1 -validate 17 - -aarch64 = nop -arm = nop -generate p128 - -/// Floating-point add across vector -name = vaddv -a = 1., 2., 0., 0. -validate 3. - -aarch64 = faddp -link-aarch64 = faddv._EXT2_._EXT_ -generate float32x2_t:f32, float32x4_t:f32, float64x2_t:f64 - -/// Signed Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4 -validate 10 - -aarch64 = saddlv -link-aarch64 = llvm.aarch64.neon.saddlv.i32._EXT_ -generate int16x4_t:i32 - -/// Signed Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4, 5, 6, 7, 8 -validate 36 - -aarch64 = saddlv -link-aarch64 = llvm.aarch64.neon.saddlv.i32._EXT_ -generate int16x8_t:i32 - -/// Signed Add Long across Vector -name = vaddlv -a = 1, 2 -validate 3 - -aarch64 = saddlp -link-aarch64 = llvm.aarch64.neon.saddlv.i64._EXT_ -generate int32x2_t:i64 - -/// Signed Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4 -validate 10 - -aarch64 = saddlv -link-aarch64 = llvm.aarch64.neon.saddlv.i64._EXT_ -generate int32x4_t:i64 - -/// Unsigned Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4 -validate 10 - -aarch64 = uaddlv -link-aarch64 = llvm.aarch64.neon.uaddlv.i32._EXT_ -generate uint16x4_t:u32 - -/// Unsigned Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4, 5, 6, 7, 8 -validate 36 - -aarch64 = uaddlv -link-aarch64 = llvm.aarch64.neon.uaddlv.i32._EXT_ -generate uint16x8_t:u32 - -/// Unsigned Add Long across Vector -name = vaddlv -a = 1, 2 -validate 3 - -aarch64 = uaddlp -link-aarch64 = llvm.aarch64.neon.uaddlv.i64._EXT_ -generate uint32x2_t:u64 - -/// Unsigned Add Long across Vector -name = vaddlv -a = 1, 2, 3, 4 -validate 10 - -aarch64 = uaddlv -link-aarch64 = llvm.aarch64.neon.uaddlv.i64._EXT_ -generate uint32x4_t:u64 - -/// Subtract returning high narrow -name = vsubhn -no-q -multi_fn = fixed, c:in_t -multi_fn = simd_cast, {simd_shr, {simd_sub, a, b}, transmute(c)} -a = MAX, MIN, 1, 1, MAX, MIN, 1, 1 -b = 1, 0, 0, 0, 1, 0, 0, 0 -fixed = HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS, HFBITS -validate MAX, MIN, 0, 0, MAX, MIN, 0, 0 - -arm = vsubhn -aarch64 = subhn -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Subtract returning high narrow -name = vsubhn_high -no-q -multi_fn = vsubhn-noqself-noext, d:in_t0, b, c -multi_fn = simd_shuffle!, a, d, {asc-0-out_len} -a = MAX, 0, MAX, 0, MAX, 0, MAX, 0 -b = MAX, 1, MAX, 1, MAX, 1, MAX, 1 -c = 1, 0, 1, 0, 1, 0, 1, 0 -validate MAX, 0, MAX, 0, MAX, 0, MAX, 0, MAX, 0, MAX, 0, MAX, 0, MAX, 0 - -arm = vsubhn -aarch64 = subhn2 -generate int8x8_t:int16x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int64x2_t:int32x4_t -generate uint8x8_t:uint16x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint64x2_t:uint32x4_t - -/// Signed halving subtract -name = vhsub -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2, 1, 2 -validate 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7 - -arm = vhsub.s -aarch64 = uhsub -link-arm = vhsubu._EXT_ -link-aarch64 = uhsub._EXT_ -generate uint*_t - -arm = vhsub.s -aarch64 = shsub -link-arm = vhsubs._EXT_ -link-aarch64 = shsub._EXT_ -generate int*_t - -/// Signed Subtract Wide -name = vsubw -no-q -multi_fn = simd_sub, a, {simd_cast, b} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -arm = vsubw -aarch64 = ssubw -generate int16x8_t:int8x8_t:int16x8_t, int32x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int64x2_t - -/// Unsigned Subtract Wide -name = vsubw -no-q -multi_fn = simd_sub, a, {simd_cast, b} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -arm = vsubw -aarch64 = usubw -generate uint16x8_t:uint8x8_t:uint16x8_t, uint32x4_t:uint16x4_t:uint32x4_t, uint64x2_t:uint32x2_t:uint64x2_t - -/// Signed Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:int8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9, 10, 12, 13, 14, 15, 16 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 13, 14, 15, 16 -validate 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = ssubw -generate int16x8_t:int8x16_t:int16x8_t - -/// Signed Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:int16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9, 10, 11 -b = 0, 1, 2, 3, 8, 9, 10, 11 -validate 0, 0, 0, 0 - -aarch64 = ssubw -generate int32x4_t:int16x8_t:int32x4_t - -/// Signed Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:int32x2_t, b, b, [2, 3] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9 -b = 6, 7, 8, 9 -validate 0, 0 - -aarch64 = ssubw -generate int64x2_t:int32x4_t:int64x2_t - -/// Unsigned Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:uint8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9, 10, 11, 12, 13, 14, 15 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = usubw -generate uint16x8_t:uint8x16_t:uint16x8_t - -/// Unsigned Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:uint16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9, 10, 11 -b = 0, 1, 2, 3, 8, 9, 10, 11 -validate 0, 0, 0, 0 - -aarch64 = usubw -generate uint32x4_t:uint16x8_t:uint32x4_t - -/// Unsigned Subtract Wide -name = vsubw_high -no-q -multi_fn = simd_shuffle!, c:uint32x2_t, b, b, [2, 3] -multi_fn = simd_sub, a, {simd_cast, c} -a = 8, 9 -b = 6, 7, 8, 9 -validate 0, 0 - -aarch64 = usubw -generate uint64x2_t:uint32x4_t:uint64x2_t - -/// Signed Subtract Long -name = vsubl -no-q -multi_fn = simd_cast, c:out_t, a -multi_fn = simd_cast, d:out_t, b -multi_fn = simd_sub, c, d - -a = MAX, MIN, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = MAX, MIN, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -arm = vsubl -aarch64 = ssubl -generate int8x8_t:int8x8_t:int16x8_t, int16x4_t:int16x4_t:int32x4_t, int32x2_t:int32x2_t:int64x2_t - -/// Unsigned Subtract Long -name = vsubl -no-q -multi_fn = simd_cast, c:out_t, a -multi_fn = simd_cast, d:out_t, b -multi_fn = simd_sub, c, d - -a = MAX, MIN, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = MAX, MIN, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -arm = vsubl -aarch64 = usubl -generate uint8x8_t:uint8x8_t:uint16x8_t, uint16x4_t:uint16x4_t:uint32x4_t, uint32x2_t:uint32x2_t:uint64x2_t - -/// Signed Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:int8x8_t, a, a, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:int8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2 -validate 6, 7, 8, 9, 10, 11, 12, 13 - -aarch64 = ssubl -generate int8x16_t:int8x16_t:int16x8_t - -/// Signed Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:int16x4_t, a, a, [4, 5, 6, 7] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:int16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 8, 9, 10, 11, 12, 13, 14, 15 -b = 6, 6, 6, 6, 8, 8, 8, 8 -validate 4, 5, 6, 7 - -aarch64 = ssubl -generate int16x8_t:int16x8_t:int32x4_t - -/// Signed Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:int32x2_t, a, a, [2, 3] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:int32x2_t, b, b, [2, 3] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 12, 13, 14, 15 -b = 6, 6, 8, 8 -validate 6, 7 - -aarch64 = ssubl -generate int32x4_t:int32x4_t:int64x2_t - -/// Unsigned Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:uint8x8_t, a, a, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:uint8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2, 2 -validate 6, 7, 8, 9, 10, 11, 12, 13 - -aarch64 = usubl -generate uint8x16_t:uint8x16_t:uint16x8_t - -/// Unsigned Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:uint16x4_t, a, a, [4, 5, 6, 7] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:uint16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 8, 9, 10, 11, 12, 13, 14, 15 -b = 6, 6, 6, 6, 8, 8, 8, 8 -validate 4, 5, 6, 7 - -aarch64 = usubl -generate uint16x8_t:uint16x8_t:uint32x4_t - -/// Unsigned Subtract Long -name = vsubl_high -no-q -multi_fn = simd_shuffle!, c:uint32x2_t, a, a, [2, 3] -multi_fn = simd_cast, d:out_t, c -multi_fn = simd_shuffle!, e:uint32x2_t, b, b, [2, 3] -multi_fn = simd_cast, f:out_t, e -multi_fn = simd_sub, d, f - -a = 12, 13, 14, 15 -b = 6, 6, 8, 8 -validate 6, 7 - -aarch64 = usubl -generate uint32x4_t:uint32x4_t:uint64x2_t - -/// Bit clear and exclusive OR -name = vbcax -a = 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0 -b = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -c = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -validate 1, 0, 3, 2, 5, 4, 7, 6, 9, 8, 11, 10, 13, 12, 15, 14 -target = sha3 - -aarch64 = bcax -link-aarch64 = llvm.aarch64.crypto.bcaxs._EXT_ -generate int8x16_t, int16x8_t, int32x4_t, int64x2_t -link-aarch64 = llvm.aarch64.crypto.bcaxu._EXT_ -generate uint8x16_t, uint16x8_t, uint32x4_t, uint64x2_t - -/// Floating-point complex add -name = vcadd_rot270 -no-q -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -validate 2., 0., 2., 0. -target = fcma - -aarch64 = fcadd -link-aarch64 = vcadd.rot270._EXT_ -generate float32x2_t -name = vcaddq_rot270 -generate float32x4_t, float64x2_t - -/// Floating-point complex add -name = vcadd_rot90 -no-q -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -validate 0., -2., 0., -2. -target = fcma - -aarch64 = fcadd -link-aarch64 = vcadd.rot90._EXT_ -generate float32x2_t -name = vcaddq_rot90 -generate float32x4_t, float64x2_t - -/// Floating-point complex multiply accumulate -name = vcmla -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -c = 1., 1., -1., -1. -validate 0., -2., 2., 0. -target = fcma - -aarch64 = fcmla -link-aarch64 = vcmla.rot0._EXT_ -generate float32x2_t, float32x4_t, float64x2_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot90 -rot-suffix -a = 1., 1., 1., 1. -b = 1., -1., 1., -1. -c = 1., 1., 1., 1. -validate 2., 0., 2., 0. -target = fcma - -aarch64 = fcmla -link-aarch64 = vcmla.rot90._EXT_ -generate float32x2_t, float32x4_t, float64x2_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot180 -rot-suffix -a = 1., 1., 1., 1. -b = 1., -1., 1., -1. -c = 1., 1., 1., 1. -validate 0., 0., 0., 0. -target = fcma - -aarch64 = fcmla -link-aarch64 = vcmla.rot180._EXT_ -generate float32x2_t, float32x4_t, float64x2_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot270 -rot-suffix -a = 1., 1., 1., 1. -b = 1., -1., 1., -1. -c = 1., 1., 1., 1. -validate 0., 2., 0., 2. -target = fcma - -aarch64 = fcmla -link-aarch64 = vcmla.rot270._EXT_ -generate float32x2_t, float32x4_t, float64x2_t - -/// Floating-point complex multiply accumulate -name = vcmla -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_rot-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {base-2-LANE} -multi_fn = vcmla-self-noext, a, b, c -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -c = 1., 1., -1., -1. -n = 0 -validate 0., -2., 0., -2. -target = fcma - -aarch64 = fcmla -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t -generate float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot90 -rot-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_rot-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {base-2-LANE} -multi_fn = vcmla_rot90-rot-noext, a, b, c -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -c = 1., 1., -1., -1. -n = 0 -validate 0., 0., 0., 0. -target = fcma - -aarch64 = fcmla -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t -generate float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot180 -rot-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_rot-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {base-2-LANE} -multi_fn = vcmla_rot180-rot-noext, a, b, c -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -c = 1., 1., -1., -1. -n = 0 -validate 2., 0., 2., 0. -target = fcma - -aarch64 = fcmla -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t -generate float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Floating-point complex multiply accumulate -name = vcmla_rot270 -rot-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_rot-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {base-2-LANE} -multi_fn = vcmla_rot270-rot-noext, a, b, c -a = 1., -1., 1., -1. -b = -1., 1., -1., 1. -c = 1., 1., -1., -1. -n = 0 -validate 2., -2., 2., -2. -target = fcma - -aarch64 = fcmla -generate float32x2_t, float32x2_t:float32x2_t:float32x4_t:float32x2_t -generate float32x4_t:float32x4_t:float32x2_t:float32x4_t, float32x4_t - -/// Dot product arithmetic (vector) -name = vdot -out-suffix -a = 1, 2, 1, 2 -b = 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -c = 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -validate 31, 176, 31, 176 -target = dotprod - -arm = vsdot -aarch64 = sdot -link-arm = sdot._EXT_._EXT3_ -link-aarch64 = sdot._EXT_._EXT3_ -generate int32x2_t:int8x8_t:int8x8_t:int32x2_t, int32x4_t:int8x16_t:int8x16_t:int32x4_t - -arm = vudot -aarch64 = udot -link-arm = udot._EXT_._EXT3_ -link-aarch64 = udot._EXT_._EXT3_ -generate uint32x2_t:uint8x8_t:uint8x8_t:uint32x2_t, uint32x4_t:uint8x16_t:uint8x16_t:uint32x4_t - -/// Dot product arithmetic (indexed) -name = vdot -out-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_t, c, c, {dup-out_len-LANE as u32} -multi_fn = vdot-out-noext, a, b, {transmute, c} -a = 1, 2, 1, 2 -b = -1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -c = 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -n = 0 -validate 29, 72, 31, 72 -target = dotprod - -// Only AArch64 has the laneq forms. -aarch64 = sdot -generate int32x2_t:int8x8_t:int8x16_t:int32x2_t -generate int32x4_t:int8x16_t:int8x16_t:int32x4_t - -arm = vsdot -generate int32x2_t:int8x8_t:int8x8_t:int32x2_t -generate int32x4_t:int8x16_t:int8x8_t:int32x4_t - -/// Dot product arithmetic (indexed) -name = vdot -out-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_dot-LANE -multi_fn = transmute, c:merge4_t2, c -multi_fn = simd_shuffle!, c:out_t, c, c, {dup-out_len-LANE as u32} -multi_fn = vdot-out-noext, a, b, {transmute, c} -a = 1, 2, 1, 2 -b = 255, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -c = 1, 2, 3, 4, 5, 6, 7, 8, 1, 2, 3, 4, 5, 6, 7, 8 -n = 0 -validate 285, 72, 31, 72 -target = dotprod - -// Only AArch64 has the laneq forms. -aarch64 = udot -generate uint32x2_t:uint8x8_t:uint8x16_t:uint32x2_t -generate uint32x4_t:uint8x16_t:uint8x16_t:uint32x4_t - -arm = vudot -generate uint32x2_t:uint8x8_t:uint8x8_t:uint32x2_t -generate uint32x4_t:uint8x16_t:uint8x8_t:uint32x4_t - -/// Maximum (vector) -name = vmax -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 -validate 16, 15, 14, 13, 12, 11, 10, 9, 9, 10, 11, 12, 13, 14, 15, 16 - -arm = vmax -aarch64 = smax -link-arm = vmaxs._EXT_ -link-aarch64 = smax._EXT_ -generate int*_t - -arm = vmax -aarch64 = umax -link-arm = vmaxu._EXT_ -link-aarch64 = umax._EXT_ -generate uint*_t - -/// Maximum (vector) -name = vmax -a = 1.0, -2.0, 3.0, -4.0 -b = 0.0, 3.0, 2.0, 8.0 -validate 1.0, 3.0, 3.0, 8.0 - -aarch64 = fmax -link-aarch64 = fmax._EXT_ -generate float64x*_t - -arm = vmax -aarch64 = fmax -link-arm = vmaxs._EXT_ -link-aarch64 = fmax._EXT_ -generate float*_t - -/// Floating-point Maximum Number (vector) -name = vmaxnm -a = 1.0, 2.0, 3.0, -4.0 -b = 8.0, 16.0, -1.0, 6.0 -validate 8.0, 16.0, 3.0, 6.0 - -aarch64 = fmaxnm -link-aarch64 = fmaxnm._EXT_ -generate float64x*_t - -target = fp-armv8 -arm = vmaxnm -aarch64 = fmaxnm -link-arm = vmaxnm._EXT_ -link-aarch64 = fmaxnm._EXT_ -generate float*_t - -/// Floating-point maximum number across vector -name = vmaxnmv -a = 1., 2., 0., 1. -validate 2. - -aarch64 = fmaxnmp -link-aarch64 = fmaxnmv._EXT2_._EXT_ -generate float32x2_t:f32, float64x2_t:f64 -aarch64 = fmaxnmv -generate float32x4_t:f32 - -/// Floating-point Maximum Number Pairwise (vector). -name = vpmaxnm -a = 1.0, 2.0 -b = 6.0, -3.0 -validate 2.0, 6.0 -aarch64 = fmaxnmp -link-aarch64 = fmaxnmp._EXT_ -generate float32x2_t:float32x2_t:float32x2_t, float64x2_t:float64x2_t:float64x2_t - -/// Floating-point Maximum Number Pairwise (vector). -name = vpmaxnm -a = 1.0, 2.0, 3.0, -4.0 -b = 8.0, 16.0, -1.0, 6.0 -validate 2.0, 3.0, 16.0, 6.0 -aarch64 = fmaxnmp -link-aarch64 = fmaxnmp._EXT_ -generate float32x4_t:float32x4_t:float32x4_t - -/// Floating-point maximum number pairwise -name = vpmaxnm -out-suffix -a = 1., 2. -validate 2. - -aarch64 = fmaxnmp -link-aarch64 = fmaxnmv._EXT2_._EXT_ -generate float32x2_t:f32 -name = vpmaxnmq -generate float64x2_t:f64 - -/// Floating-point maximum pairwise -name = vpmax -out-suffix -a = 1., 2. -validate 2. - -aarch64 = fmaxp -link-aarch64 = fmaxv._EXT2_._EXT_ -generate float32x2_t:f32 -name = vpmaxq -generate float64x2_t:f64 - -/// Minimum (vector) -name = vmin -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 16, 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1 -validate 1, 2, 3, 4, 5, 6, 7, 8, 8, 7, 6, 5, 4, 3, 2, 1 - -arm = vmin -aarch64 = smin -link-arm = vmins._EXT_ -link-aarch64 = smin._EXT_ -generate int*_t - -arm = vmin -aarch64 = umin -link-arm = vminu._EXT_ -link-aarch64 = umin._EXT_ -generate uint*_t - -/// Minimum (vector) -name = vmin -a = 1.0, -2.0, 3.0, -4.0 -b = 0.0, 3.0, 2.0, 8.0 -validate 0.0, -2.0, 2.0, -4.0 - -aarch64 = fmin -link-aarch64 = fmin._EXT_ -generate float64x*_t - -arm = vmin -aarch64 = fmin -link-arm = vmins._EXT_ -link-aarch64 = fmin._EXT_ -generate float*_t - -/// Floating-point Minimum Number (vector) -name = vminnm -a = 1.0, 2.0, 3.0, -4.0 -b = 8.0, 16.0, -1.0, 6.0 -validate 1.0, 2.0, -1.0, -4.0 - -aarch64 = fminnm -link-aarch64 = fminnm._EXT_ -generate float64x*_t - -target = fp-armv8 -arm = vminnm -aarch64 = fminnm -link-arm = vminnm._EXT_ -link-aarch64 = fminnm._EXT_ -generate float*_t - -/// Floating-point minimum number across vector -name = vminnmv -a = 1., 0., 2., 3. -validate 0. - -aarch64 = fminnmp -link-aarch64 = fminnmv._EXT2_._EXT_ -generate float32x2_t:f32, float64x2_t:f64 -aarch64 = fminnmv -generate float32x4_t:f32 - -/// Vector move -name = vmovl_high -no-q -multi_fn = simd_shuffle!, a:half, a, a, {asc-halflen-halflen} -multi_fn = vmovl-noqself-noext, a -a = 1, 2, 3, 4, 3, 4, 5, 6, 3, 4, 5, 6, 7, 8, 9, 10 -validate 3, 4, 5, 6, 7, 8, 9, 10 - -aarch64 = sxtl2 -generate int8x16_t:int16x8_t, int16x8_t:int32x4_t, int32x4_t:int64x2_t - -aarch64 = uxtl2 -generate uint8x16_t:uint16x8_t, uint16x8_t:uint32x4_t, uint32x4_t:uint64x2_t - -/// Floating-point add pairwise -name = vpadd -a = 1., 2., 3., 4. -b = 3., 4., 5., 6. -validate 3., 7., 7., 11. - -aarch64 = faddp -link-aarch64 = faddp._EXT_ -generate float32x4_t, float64x2_t - -arm = vpadd -link-arm = vpadd._EXT_ -generate float32x2_t - -/// Floating-point add pairwise -name = vpadd -out-suffix -multi_fn = simd_extract!, a1:out_t, a, 0 -multi_fn = simd_extract!, a2:out_t, a, 1 -multi_fn = a1 + a2 -a = 1., 2. -validate 3. - -aarch64 = nop -generate float32x2_t:f32, float64x2_t:f64 - -/// Floating-point Minimum Number Pairwise (vector). -name = vpminnm -a = 1.0, 2.0 -b = 6.0, -3.0 -validate 1.0, -3.0 - -aarch64 = fminnmp -link-aarch64 = fminnmp._EXT_ -generate float32x2_t:float32x2_t:float32x2_t, float64x2_t:float64x2_t:float64x2_t - -/// Floating-point Minimum Number Pairwise (vector). -name = vpminnm -a = 1.0, 2.0, 3.0, -4.0 -b = 8.0, 16.0, -1.0, 6.0 -validate 1.0, -4.0, 8.0, -1.0 -aarch64 = fminnmp -link-aarch64 = fminnmp._EXT_ -generate float32x4_t:float32x4_t:float32x4_t - -/// Floating-point minimum number pairwise -name = vpminnm -out-suffix -a = 1., 2. -validate 1. - -aarch64 = fminnmp -link-aarch64 = fminnmv._EXT2_._EXT_ -generate float32x2_t:f32 -name = vpminnmq -generate float64x2_t:f64 - -/// Floating-point minimum pairwise -name = vpmin -out-suffix -a = 1., 2. -validate 1. - -aarch64 = fminp -link-aarch64 = fminv._EXT2_._EXT_ -generate float32x2_t:f32 -name = vpminq -generate float64x2_t:f64 - -/// Signed saturating doubling multiply long -name = vqdmull -a = 0, 1, 2, 3, 4, 5, 6, 7 -b = 1, 2, 3, 4, 5, 6, 7, 8 -validate 0, 4, 12, 24, 40, 60, 84, 108 - -aarch64 = sqdmull -link-aarch64 = sqdmull._EXT2_ -arm = vqdmull -link-arm = vqdmull._EXT2_ -generate int16x4_t:int16x4_t:int32x4_t, int32x2_t:int32x2_t:int64x2_t - -/// Signed saturating doubling multiply long -name = vqdmull -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqdmull-in_ntt-noext, a, b}, 0 -a = 2 -b = 3 -validate 12 - -aarch64 = sqdmull -generate i16:i16:i32 - -/// Signed saturating doubling multiply long -name = vqdmull -a = 2 -b = 3 -validate 12 - -aarch64 = sqdmull -link-aarch64 = sqdmulls.scalar -generate i32:i32:i64 - -/// Vector saturating doubling long multiply with scalar -name = vqdmull_n -no-q -multi_fn = vqdmull-in_ntt-noext, a, {vdup_n-in_ntt-noext, b} -a = 2, 4, 6, 8 -b = 2 -validate 8, 16, 24, 32 - -aarch64 = sqdmull -arm = vqdmull -generate int16x4_t:i16:int32x4_t, int32x2_t:i32:int64x2_t - -/// Signed saturating doubling multiply long -name = vqdmull_high -no-q -multi_fn = simd_shuffle!, a:half, a, a, {asc-halflen-halflen} -multi_fn = simd_shuffle!, b:half, b, b, {asc-halflen-halflen} -multi_fn = vqdmull-noqself-noext, a, b -a = 0, 1, 4, 5, 4, 5, 6, 7 -b = 1, 2, 5, 6, 5, 6, 7, 8 -validate 40, 60, 84, 112 - -aarch64 = sqdmull2 -generate int16x8_t:int16x8_t:int32x4_t, int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply long -name = vqdmull_high_n -no-q -multi_fn = simd_shuffle!, a:in_ntt, a, a, {asc-out_len-out_len} -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = vqdmull-in_ntt-noext, a, b -a = 0, 2, 8, 10, 8, 10, 12, 14 -b = 2 -validate 32, 40, 48, 56 - -aarch64 = sqdmull2 -generate int16x8_t:i16:int32x4_t, int32x4_t:i32:int64x2_t - -/// Vector saturating doubling long multiply by scalar -name = vqdmull_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, b:in_t0, b, b, {dup-out_len-N as u32} -multi_fn = vqdmull-noqself-noext, a, b -a = 1, 2, 3, 4 -b = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 4, 8, 12, 16 - -aarch64 = sqdmull -generate int16x4_t:int16x8_t:int32x4_t, int32x2_t:int32x4_t:int64x2_t - -arm = vqdmull -generate int16x4_t:int16x4_t:int32x4_t, int32x2_t:int32x2_t:int64x2_t - -/// Signed saturating doubling multiply long -name = vqdmullh_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, b:in_t0, b, N as u32 -multi_fn = vqdmullh-noqself-noext, a, b -a = 2 -b = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 8 - -aarch64 = sqdmull -generate i16:int16x4_t:i32, i16:int16x8_t:i32 - -/// Signed saturating doubling multiply long -name = vqdmulls_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, b:in_t0, b, N as u32 -multi_fn = vqdmulls-noqself-noext, a, b -a = 2 -b = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 8 - -aarch64 = sqdmull -generate i32:int32x2_t:i64, i32:int32x4_t:i64 - -/// Signed saturating doubling multiply long -name = vqdmull_high_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, a:in_t, a, a, {asc-out_len-out_len} -multi_fn = simd_shuffle!, b:in_t, b, b, {dup-out_len-N as u32} -multi_fn = vqdmull-self-noext, a, b -a = 0, 1, 4, 5, 4, 5, 6, 7 -b = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 16, 20, 24, 28 - -aarch64 = sqdmull2 -generate int16x8_t:int16x4_t:int32x4_t, int32x4_t:int32x2_t:int64x2_t - -/// Signed saturating doubling multiply long -name = vqdmull_high_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_shuffle!, a:half, a, a, {asc-out_len-out_len} -multi_fn = simd_shuffle!, b:half, b, b, {dup-out_len-N as u32} -multi_fn = vqdmull-noqself-noext, a, b -a = 0, 1, 4, 5, 4, 5, 6, 7 -b = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 16, 20, 24, 28 - -aarch64 = sqdmull2 -generate int16x8_t:int16x8_t:int32x4_t, int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply-add long -name = vqdmlal -multi_fn = vqadd-out-noext, a, {vqdmull-self-noext, b, c} -a = 1, 1, 1, 1 -b = 1, 2, 3, 4 -c = 2, 2, 2, 2 -validate 5, 9, 13, 17 - -aarch64 = sqdmlal -arm = vqdmlal -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Vector widening saturating doubling multiply accumulate with scalar -name = vqdmlal -n-suffix -multi_fn = vqadd-out-noext, a, {vqdmull_n-self-noext, b, c} -a = 1, 1, 1, 1 -b = 1, 2, 3, 4 -c = 2 -validate 5, 9, 13, 17 - -aarch64 = sqdmlal -arm = vqdmlal -generate int32x4_t:int16x4_t:i16:int32x4_t, int64x2_t:int32x2_t:i32:int64x2_t - -/// Signed saturating doubling multiply-add long -name = vqdmlal_high -no-q -multi_fn = vqadd-out-noext, a, {vqdmull_high-noqself-noext, b, c} -a = 1, 2, 3, 4 -b = 0, 1, 4, 5, 4, 5, 6, 7 -c = 1, 2, 5, 6, 5, 6, 7, 8 -validate 41, 62, 87, 116 - -aarch64 = sqdmlal2 -generate int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply-add long -name = vqdmlal_high_n -no-q -multi_fn = vqadd-out-noext, a, {vqdmull_high_n-noqself-noext, b, c} -a = 1, 2, 3, 4 -b = 0, 2, 8, 10, 8, 10, 12, 14 -c = 2 -validate 33, 42, 51, 60 - -aarch64 = sqdmlal2 -generate int32x4_t:int16x8_t:i16:int32x4_t, int64x2_t:int32x4_t:i32:int64x2_t - -/// Vector widening saturating doubling multiply accumulate with scalar -name = vqdmlal_lane -in2-suffix -constn = N -multi_fn = static_assert_imm-in2_exp_len-N -multi_fn = vqadd-out-noext, a, {vqdmull_lane-in2-::, b, c} -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -c = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate 5, 10, 15, 20 - -aarch64 = sqdmlal -generate int32x4_t:int16x4_t:int16x8_t:int32x4_t, int64x2_t:int32x2_t:int32x4_t:int64x2_t - -arm = vqdmlal -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Signed saturating doubling multiply-add long -name = vqdmlal_high_lane -in2-suffix -constn = N -multi_fn = static_assert_imm-in2_exp_len-N -multi_fn = vqadd-out-noext, a, {vqdmull_high_lane-in2-::, b, c} -a = 1, 2, 3, 4 -b = 0, 1, 4, 5, 4, 5, 6, 7 -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate 17, 22, 27, 32 - -aarch64 = sqdmlal2 -generate int32x4_t:int16x8_t:int16x4_t:int32x4_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t: int32x4_t:int32x2_t:int64x2_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply-add long -name = vqdmlal -multi_fn = vqdmull-in_ntt-noext, x:out_long_ntt, {vdup_n-in_ntt-noext, b}, {vdup_n-in_ntt-noext, c} -multi_fn = vqadd-out-noext, a, {simd_extract!, x, 0} -a = 1 -b = 1 -c = 2 -validate 5 - -aarch64 = sqdmlal -generate i32:i16:i16:i32 - -/// Signed saturating doubling multiply-add long -name = vqdmlal -multi_fn = vqadd-out-noext, x:out_t, a, {vqdmulls-in_ntt-noext, b, c} -multi_fn = x as out_t -a = 1 -b = 1 -c = 2 -validate 5 - -aarch64 = sqdmlal -generate i64:i32:i32:i64 - -/// Signed saturating doubling multiply-add long -name = vqdmlalh_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vqdmlal-self-noext, a, b, {simd_extract!, c, LANE as u32} -a = 1 -b = 1 -c = 2, 1, 1, 1, 1, 1, 1, 1 -n = 0 -validate 5 - -aarch64 = sqdmlal -generate i32:i16:int16x4_t:i32, i32:i16:int16x8_t:i32 -name = vqdmlals_lane -aarch64 = sqdmlal -generate i64:i32:int32x2_t:i64, i64:i32:int32x4_t:i64 - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl -multi_fn = vqsub-out-noext, a, {vqdmull-self-noext, b, c} -a = 3, 7, 11, 15 -b = 1, 2, 3, 4 -c = 2, 2, 2, 2 -validate -1, -1, -1, -1 - -aarch64 = sqdmlsl -arm = vqdmlsl -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Vector widening saturating doubling multiply subtract with scalar -name = vqdmlsl -n-suffix -multi_fn = vqsub-out-noext, a, {vqdmull_n-self-noext, b, c} -a = 3, 7, 11, 15 -b = 1, 2, 3, 4 -c = 2 -validate -1, -1, -1, -1 - -aarch64 = sqdmlsl -arm = vqdmlsl -generate int32x4_t:int16x4_t:i16:int32x4_t, int64x2_t:int32x2_t:i32:int64x2_t - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl_high -no-q -multi_fn = vqsub-out-noext, a, {vqdmull_high-noqself-noext, b, c} -a = 39, 58, 81, 108 -b = 0, 1, 4, 5, 4, 5, 6, 7 -c = 1, 2, 5, 6, 5, 6, 7, 8 -validate -1, -2, -3, -4 - -aarch64 = sqdmlsl2 -generate int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl_high_n -no-q -multi_fn = vqsub-out-noext, a, {vqdmull_high_n-noqself-noext, b, c} -a = 31, 38, 45, 52 -b = 0, 2, 8, 10, 8, 10, 12, 14 -c = 2 -validate -1, -2, -3, -4 - -aarch64 = sqdmlsl2 -generate int32x4_t:int16x8_t:i16:int32x4_t, int64x2_t:int32x4_t:i32:int64x2_t - -/// Vector widening saturating doubling multiply subtract with scalar -name = vqdmlsl_lane -in2-suffix -constn = N -multi_fn = static_assert_imm-in2_exp_len-N -multi_fn = vqsub-out-noext, a, {vqdmull_lane-in2-::, b, c} -a = 3, 6, 9, 12 -b = 1, 2, 3, 4 -c = 0, 2, 2, 0, 2, 0, 0, 0 -n = HFLEN -validate -1, -2, -3, -4 - -aarch64 = sqdmlsl -generate int32x4_t:int16x4_t:int16x8_t:int32x4_t, int64x2_t:int32x2_t:int32x4_t:int64x2_t - -arm = vqdmlsl -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t, int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl_high_lane -in2-suffix -constn = N -multi_fn = static_assert_imm-in2_exp_len-N -multi_fn = vqsub-out-noext, a, {vqdmull_high_lane-in2-::, b, c} -a = 15, 18, 21, 24 -b = 0, 1, 4, 5, 4, 5, 6, 7 -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate -1, -2, -3, -4 - -aarch64 = sqdmlsl2 -generate int32x4_t:int16x8_t:int16x4_t:int32x4_t, int32x4_t:int16x8_t:int16x8_t:int32x4_t, int64x2_t: int32x4_t:int32x2_t:int64x2_t, int64x2_t:int32x4_t:int32x4_t:int64x2_t - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl -multi_fn = vqdmull-in_ntt-noext, x:out_long_ntt, {vdup_n-in_ntt-noext, b}, {vdup_n-in_ntt-noext, c} -multi_fn = vqsub-out-noext, a, {simd_extract!, x, 0} -a = 10 -b = 1 -c = 2 -validate 6 - -aarch64 = sqdmlsl -generate i32:i16:i16:i32 - -/// Signed saturating doubling multiply-subtract long -name = vqdmlsl -multi_fn = vqsub-out-noext, x:out_t, a, {vqdmulls-in_ntt-noext, b, c} -multi_fn = x as out_t -a = 10 -b = 1 -c = 2 -validate 6 - -aarch64 = sqdmlsl -generate i64:i32:i32:i64 - -/// Signed saturating doubling multiply-subtract long -name = vqdmlslh_lane -in2-suffix -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vqdmlsl-self-noext, a, b, {simd_extract!, c, LANE as u32} -a = 10 -b = 1 -c = 2, 1, 1, 1, 1, 1, 1, 1 -n = 0 -validate 6 - -aarch64 = sqdmlsl -generate i32:i16:int16x4_t:i32, i32:i16:int16x8_t:i32 -name = vqdmlsls_lane -aarch64 = sqdmlsl -generate i64:i32:int32x2_t:i64, i64:i32:int32x4_t:i64 - -/// Signed saturating doubling multiply returning high half -name = vqdmulh -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 2, 2, 2, 2, 2, 2, 2, 2 -validate 1, 1, 1, 1, 1, 1, 1, 1 - -aarch64 = sqdmulh -link-aarch64 = sqdmulh._EXT_ -arm = vqdmulh -link-arm = vqdmulh._EXT_ -generate int16x4_t, int16x8_t, int32x2_t, int32x4_t - -/// Signed saturating doubling multiply returning high half -name = vqdmulh -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqdmulh-in_ntt-noext, a, b}, 0 -a = 1 -b = 2 -validate 0 - -aarch64 = sqdmulh -generate i16, i32 - -/// Vector saturating doubling multiply high with scalar -name = vqdmulh_n -out-suffix -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = vqdmulh-out-noext, a, b -a = MAX, MAX, MAX, MAX -b = 2 -validate 1, 1, 1, 1 - -aarch64 = sqdmulh -arm = vqdmulh -generate int16x4_t:i16:int16x4_t, int32x2_t:i32:int32x2_t - -/// Vector saturating doubling multiply high with scalar -name = vqdmulhq_n -no-q -multi_fn = vdupq_n-in_ntt-noext, b:out_t, b -multi_fn = vqdmulh-out-noext, a, b -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 2 -validate 1, 1, 1, 1, 1, 1, 1, 1 - -aarch64 = sqdmulh -arm = vqdmulh -generate int16x8_t:i16:int16x8_t, int32x4_t:i32:int32x4_t - -/// Signed saturating doubling multiply returning high half -name = vqdmulhh_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, b:in_t0, b, N as u32 -multi_fn = vqdmulhh-out_ntt-noext, a, b -a = 2 -b = 0, 0, MAX, 0, 0, 0, 0, 0 -n = 2 -validate 1 - -aarch64 = sqdmulh -generate i16:int16x4_t:i16, i16:int16x8_t:i16 - -/// Signed saturating doubling multiply returning high half -name = vqdmulhs_lane -constn = N -multi_fn = static_assert_imm-in_exp_len-N -multi_fn = simd_extract!, b:in_t0, b, N as u32 -multi_fn = vqdmulhs-out_ntt-noext, a, b -a = 2 -b = 0, MAX, 0, 0 -n = 1 -validate 1 - -aarch64 = sqdmulh -generate i32:int32x2_t:i32, i32:int32x4_t:i32 - -/// Vector saturating doubling multiply high by scalar -name = vqdmulh -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vqdmulh-out-noext, a, {vdup-nout-noext, {simd_extract!, b, LANE as u32}} -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 2, 1, 1, 1, 1, 1, 1, 1 -n = 0 -validate 1, 1, 1, 1, 1, 1, 1, 1 - -aarch64 = sqdmulh -generate int16x4_t, int16x8_t:int16x4_t:int16x8_t -generate int32x2_t, int32x4_t:int32x2_t:int32x4_t -arm = vqdmulh -generate int16x8_t, int16x4_t:int16x8_t:int16x4_t -generate int32x4_t, int32x2_t:int32x4_t:int32x2_t - -/// Signed saturating extract narrow -name = vqmovn -no-q -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -validate MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX - -aarch64 = sqxtn -link-aarch64 = sqxtn._EXT2_ -arm = vqmovn -link-arm = vqmovns._EXT2_ -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t - -/// Unsigned saturating extract narrow -name = vqmovn -no-q -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -validate MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX - -aarch64 = uqxtn -link-aarch64 = uqxtn._EXT2_ -arm = vqmovn -link-arm = vqmovnu._EXT2_ -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Saturating extract narrow -name = vqmovn -multi_fn = simd_extract!, {vqmovn-in_ntt-noext, {vdupq_n-in_ntt-noext, a}}, 0 -a = 1 -validate 1 - -aarch64 = sqxtn -generate i16:i8, i32:i16 -aarch64 = uqxtn -generate u16:u8, u32:u16 - -/// Saturating extract narrow -name = vqmovn -a = 1 -validate 1 - -aarch64 = sqxtn -link-aarch64 = scalar.sqxtn._EXT2_._EXT_ -generate i64:i32 - -aarch64 = uqxtn -link-aarch64 = scalar.uqxtn._EXT2_._EXT_ -generate u64:u32 - -/// Signed saturating extract narrow -name = vqmovn_high -no-q -multi_fn = simd_shuffle!, a, {vqmovn-noqself-noext, b}, {asc-0-out_len} -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -validate MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX - -aarch64 = sqxtn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t -aarch64 = uqxtn2 -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Signed saturating extract unsigned narrow -name = vqmovun -no-q -a = -1, -1, -1, -1, -1, -1, -1, -1 -validate 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = sqxtun -link-aarch64 = sqxtun._EXT2_ -arm = vqmovun -link-arm = vqmovnsu._EXT2_ -generate int16x8_t:uint8x8_t, int32x4_t:uint16x4_t, int64x2_t:uint32x2_t - -/// Signed saturating extract unsigned narrow -name = vqmovun -multi_fn = simd_extract!, {vqmovun-in_ntt-noext, {vdupq_n-in_ntt-noext, a}}, 0 -a = 1 -validate 1 - -aarch64 = sqxtun -generate i16:u8, i32:u16, i64:u32 - -/// Signed saturating extract unsigned narrow -name = vqmovun_high -no-q -multi_fn = simd_shuffle!, a, {vqmovun-noqself-noext, b}, {asc-0-out_len} -a = 0, 0, 0, 0, 0, 0, 0, 0 -b = -1, -1, -1, -1, -1, -1, -1, -1 -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = sqxtun2 -generate uint8x8_t:int16x8_t:uint8x16_t, uint16x4_t:int32x4_t:uint16x8_t, uint32x2_t:int64x2_t:uint32x4_t - -/// Signed saturating rounding doubling multiply returning high half -name = vqrdmulh -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 2, 2, 2, 2, 2, 2, 2, 2 -validate 2, 2, 2, 2, 2, 2, 2, 2 - -aarch64 = sqrdmulh -link-aarch64 = sqrdmulh._EXT_ -arm = vqrdmulh -link-arm = vqrdmulh._EXT_ -generate int16x4_t, int16x8_t, int32x2_t, int32x4_t - -/// Signed saturating rounding doubling multiply returning high half -name = vqrdmulh -multi_fn = simd_extract!, {vqrdmulh-in_ntt-noext, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 1 -b = 2 -validate 0 - -aarch64 = sqrdmulh -generate i16, i32 - -/// Vector saturating rounding doubling multiply high with scalar -name = vqrdmulh -out-n-suffix -multi_fn = vqrdmulh-out-noext, a, {vdup-nout-noext, b} -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 2 -validate 2, 2, 2, 2, 2, 2, 2, 2 - -aarch64 = sqrdmulh -arm = vqrdmulh -generate int16x4_t:i16:int16x4_t, int16x8_t:i16:int16x8_t, int32x2_t:i32:int32x2_t, int32x4_t:i32:int32x4_t - -/// Vector rounding saturating doubling multiply high by scalar -name = vqrdmulh -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_shuffle!, b:out_t, b, b, {dup-out_len-LANE as u32} -multi_fn = vqrdmulh-out-noext, a, b -a = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -b = 0, 2, 0, 0, 0, 0, 0, 0, -n = 1 -validate 2, 2, 2, 2, 2, 2, 2, 2 - -aarch64 = sqrdmulh -arm = vqrdmulh -generate int16x4_t, int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x2_t:int32x4_t, int32x4_t - -/// Signed saturating rounding doubling multiply returning high half -name = vqrdmulh -lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = vqrdmulh-out-noext, a, {simd_extract!, b, LANE as u32} -a = 1 -b = 0, 2, 0, 0, 0, 0, 0, 0, -n = 1 -validate 0 - -aarch64 = sqrdmulh -generate i16:int16x4_t:i16, i16:int16x8_t:i16, i32:int32x2_t:i32, i32:int32x4_t:i32 - -/// Signed saturating rounding doubling multiply accumulate returning high half -name = vqrdmlah -a = 1, 1, 1, 1, 1, 1, 1, 1 -b = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -c = 2, 2, 2, 2, 2, 2, 2, 2 -validate 3, 3, 3, 3, 3, 3, 3, 3 - -aarch64 = sqrdmlah -link-aarch64 = sqrdmlah._EXT_ -target = rdm -generate int16x4_t, int16x8_t, int32x2_t, int32x4_t - -/// Signed saturating rounding doubling multiply accumulate returning high half -name = vqrdmlah -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = vdup_n-in_ntt-noext, c:in_ntt, c -multi_fn = simd_extract!, {vqrdmlah-in_ntt-noext, a, b, c}, 0 -a = 1 -b = 1 -c = 2 -validate 1 - -aarch64 = sqrdmlah -target = rdm -generate i16, i32 - -/// Signed saturating rounding doubling multiply accumulate returning high half -name = vqrdmlah -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {dup-out_len-LANE as u32} -multi_fn = vqrdmlah-out-noext, a, b, c -a = 1, 1, 1, 1, 1, 1, 1, 1 -b = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate 3, 3, 3, 3, 3, 3, 3, 3 - -aarch64 = sqrdmlah -target = rdm -generate int16x4_t, int16x4_t:int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x4_t:int32x2_t:int32x4_t, int32x4_t - -/// Signed saturating rounding doubling multiply accumulate returning high half -name = vqrdmlah -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vqrdmlah-self-noext, a, b, {simd_extract!, c, LANE as u32} -a = 1 -b = 1 -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate 1 - -aarch64 = sqrdmlah -target = rdm -generate i16:i16:int16x4_t:i16, i16:i16:int16x8_t:i16, i32:i32:int32x2_t:i32, i32:i32:int32x4_t:i32 - -/// Signed saturating rounding doubling multiply subtract returning high half -name = vqrdmlsh -link-aarch64 = sqrdmlsh._EXT_ -a = 1, 1, 1, 1, 1, 1, 1, 1 -b = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -c = 2, 2, 2, 2, 2, 2, 2, 2 -validate -1, -1, -1, -1, -1, -1, -1, -1 - -aarch64 = sqrdmlsh -target = rdm -generate int16x4_t, int16x8_t, int32x2_t, int32x4_t - -/// Signed saturating rounding doubling multiply subtract returning high half -name = vqrdmlsh -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = vdup_n-in_ntt-noext, c:in_ntt, c -multi_fn = simd_extract!, {vqrdmlsh-in_ntt-noext, a, b, c}, 0 -a = 1 -b = 1 -c = 2 -validate 1 - -aarch64 = sqrdmlsh -target = rdm -generate i16, i32 - -/// Signed saturating rounding doubling multiply subtract returning high half -name = vqrdmlsh -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = simd_shuffle!, c:out_t, c, c, {dup-out_len-LANE as u32} -multi_fn = vqrdmlsh-out-noext, a, b, c -a = 1, 1, 1, 1, 1, 1, 1, 1 -b = MAX, MAX, MAX, MAX, MAX, MAX, MAX, MAX -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate -1, -1, -1, -1, -1, -1, -1, -1 - -aarch64 = sqrdmlsh -target = rdm -generate int16x4_t, int16x4_t:int16x4_t:int16x8_t:int16x4_t, int16x8_t:int16x8_t:int16x4_t:int16x8_t, int16x8_t -generate int32x2_t, int32x2_t:int32x2_t:int32x4_t:int32x2_t, int32x4_t:int32x4_t:int32x2_t:int32x4_t, int32x4_t - -/// Signed saturating rounding doubling multiply subtract returning high half -name = vqrdmlsh -in2-lane-suffixes -constn = LANE -multi_fn = static_assert_imm-in2_exp_len-LANE -multi_fn = vqrdmlsh-self-noext, a, b, {simd_extract!, c, LANE as u32} -a = 1 -b = 1 -c = 0, 2, 0, 0, 0, 0, 0, 0 -n = 1 -validate 1 - -aarch64 = sqrdmlsh -target = rdm -generate i16:i16:int16x4_t:i16, i16:i16:int16x8_t:i16, i32:i32:int32x2_t:i32, i32:i32:int32x4_t:i32 - -/// Signed saturating rounding shift left -name = vqrshl -a = 2, MIN, MAX, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 8, MIN, MAX, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = sqrshl -link-aarch64 = sqrshl._EXT_ -generate i32, i64 - -arm = vqrshl -link-arm = vqrshifts._EXT_ -generate int*_t, int64x*_t - -/// Signed saturating rounding shift left -name = vqrshl -multi_fn = vdup_n-in_ntt-noext, a:in_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqrshl-in_ntt-noext, a, b}, 0 -a = 1 -b = 2 -validate 4 - -aarch64 = sqrshl -generate i8, i16 - -/// Unsigned signed saturating rounding shift left -name = vqrshl -out-suffix -a = 2, MIN, MAX, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 8, 0, MAX, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = uqrshl -link-aarch64 = uqrshl._EXT_ -generate u32:i32:u32, u64:i64:u64 - -arm = vqrshl -link-arm = vqrshiftu._EXT_ -generate uint8x8_t:int8x8_t:uint8x8_t, uint8x16_t:int8x16_t:uint8x16_t, uint16x4_t:int16x4_t:uint16x4_t, uint16x8_t:int16x8_t:uint16x8_t -generate uint32x2_t:int32x2_t:uint32x2_t, uint32x4_t:int32x4_t:uint32x4_t, uint64x1_t:int64x1_t:uint64x1_t, uint64x2_t:int64x2_t:uint64x2_t - -/// Unsigned signed saturating rounding shift left -name = vqrshl -out-suffix -multi_fn = vdup_n-out_ntt-noext, a:out_ntt, a -multi_fn = vdup_n-in_ntt-noext, b:in_ntt, b -multi_fn = simd_extract!, {vqrshl-out_ntt-noext, a, b}, 0 -a = 1 -b = 2 -validate 4 - -aarch64 = uqrshl -generate u8:i8:u8, u16:i16:u16 - -/// Signed saturating rounded shift right narrow -name = vqrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = MIN, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate MIN, 1, 2, 3, 4, 5, 6, 7 - -aarch64 = sqrshrn -link-aarch64 = sqrshrn._EXT2_ -const-aarch64 = N - -arm = vqrshrn -link-arm = vqrshiftns._EXT2_ -const-arm = -N as ttn -arm-aarch64-separate -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t - -/// Signed saturating rounded shift right narrow -name = vqrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = vdupq_n-in_ntt-noext, a:in_long_ntt, a -multi_fn = simd_extract!, {vqrshrn_n-in_ntt-::, a}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = sqrshrn -generate i16:i8, i32:i16, i64:i32 - -/// Signed saturating rounded shift right narrow -name = vqrshrn_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqrshrn_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 2, 3, 2, 3, 6, 7 -b = 8, 12, 24, 28, 48, 52, 56, 60 -n = 2 -validate 0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15 - -aarch64 = sqrshrn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t - -/// Unsigned signed saturating rounded shift right narrow -name = vqrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = MIN, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate 0, 1, 2, 3, 4, 5, 6, 7 - -aarch64 = uqrshrn -link-aarch64 = uqrshrn._EXT2_ -const-aarch64 = N - -arm = vqrshrn -link-arm = vqrshiftnu._EXT2_ -const-arm = -N as ttn -arm-aarch64-separate -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Unsigned saturating rounded shift right narrow -name = vqrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = vdupq_n-in_ntt-noext, a:in_long_ntt, a -multi_fn = simd_extract!, {vqrshrn_n-in_ntt-::, a}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = uqrshrn -generate u16:u8, u32:u16, u64:u32 - -/// Unsigned saturating rounded shift right narrow -name = vqrshrn_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqrshrn_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 2, 3, 2, 3, 6, 7 -b = 8, 12, 24, 28, 48, 52, 56, 60 -n = 2 -validate 0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15 - -aarch64 = uqrshrn2 -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Signed saturating rounded shift right unsigned narrow -name = vqrshrun -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = 0, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate 0, 1, 2, 3, 4, 5, 6, 7 - -aarch64 = sqrshrun -link-aarch64 = sqrshrun._EXT2_ -const-aarch64 = N - -arm = vqrshrun -link-arm = vqrshiftnsu._EXT2_ -const-arm = -N as ttn -arm-aarch64-separate -generate int16x8_t:uint8x8_t, int32x4_t:uint16x4_t, int64x2_t:uint32x2_t - -/// Signed saturating rounded shift right unsigned narrow -name = vqrshrun -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = vdupq_n-in_ntt-noext, a:in_long_ntt, a -multi_fn = simd_extract!, {vqrshrun_n-in_ntt-::, a}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = sqrshrun -generate i16:u8, i32:u16, i64:u32 - -/// Signed saturating rounded shift right unsigned narrow -name = vqrshrun_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqrshrun_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 2, 3, 2, 3, 6, 7 -b = 8, 12, 24, 28, 48, 52, 56, 60 -n = 2 -validate 0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 12, 13, 14, 15 - -aarch64 = sqrshrun2 -generate uint8x8_t:int16x8_t:uint8x16_t, uint16x4_t:int32x4_t:uint16x8_t, uint32x2_t:int64x2_t:uint32x4_t - -/// Signed saturating shift left -name = vqshl -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = sqshl -link-aarch64 = sqshl._EXT_ -generate i64 - -arm = vqshl -link-arm = vqshifts._EXT_ -generate int*_t, int64x*_t - -/// Signed saturating shift left -name = vqshl -multi_fn = vqshl-in_ntt-noext, c:in_ntt, {vdup_n-in_ntt-noext, a}, {vdup_n-in_ntt-noext, b} -multi_fn = simd_extract!, c, 0 -a = 1 -b = 2 -validate 4 - -aarch64 = sqshl -generate i8, i16, i32 - -/// Unsigned saturating shift left -name = vqshl -out-suffix -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = uqshl -link-aarch64 = uqshl._EXT_ -generate u64:i64:u64 - -arm = vqshl -link-arm = vqshiftu._EXT_ -generate uint8x8_t:int8x8_t:uint8x8_t, uint8x16_t:int8x16_t:uint8x16_t, uint16x4_t:int16x4_t:uint16x4_t, uint16x8_t:int16x8_t:uint16x8_t -generate uint32x2_t:int32x2_t:uint32x2_t, uint32x4_t:int32x4_t:uint32x4_t, uint64x1_t:int64x1_t:uint64x1_t, uint64x2_t:int64x2_t:uint64x2_t - -/// Unsigned saturating shift left -name = vqshl -out-suffix -multi_fn = vqshl-out_ntt-noext, c:out_ntt, {vdup_n-out_ntt-noext, a}, {vdup_n-in_ntt-noext, b} -multi_fn = simd_extract!, c, 0 -a = 1 -b = 2 -validate 4 - -aarch64 = uqshl -generate u8:i8:u8, u16:i16:u16, u32:i32:u32 - -/// Signed saturating shift left -name = vqshl -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = vqshl-self-noext, a, {vdup-nself-noext, N as _} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -n = 2 -validate 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = sqshl -arm = vqshl -generate int*_t, int64x*_t - -/// Signed saturating shift left -name = vqshl -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = simd_extract!, {vqshl_n-in_ntt-::, {vdup_n-in_ntt-noext, a}}, 0 -a = 1 -n = 2 -validate 4 - -aarch64 = sqshl -generate i8, i16, i32, i64 - -/// Unsigned saturating shift left -name = vqshl -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = vqshl-self-noext, a, {vdup-nsigned-noext, N as _} -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -n = 2 -validate 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 - -aarch64 = uqshl -arm = vqshl -generate uint*_t, uint64x*_t - -/// Unsigned saturating shift left -name = vqshl -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = simd_extract!, {vqshl_n-in_ntt-::, {vdup_n-in_ntt-noext, a}}, 0 -a = 1 -n = 2 -validate 4 - -aarch64 = uqshl -generate u8, u16, u32, u64 - -/// Signed saturating shift left unsigned -name = vqshlu -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -n = 2 -validate 0, 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60 -arm-aarch64-separate - -aarch64 = sqshlu -link-aarch64 = sqshlu._EXT_ -const-aarch64 = {dup-in_len-N as ttn} -arm = vqshlu -link-arm = vqshiftsu._EXT_ -const-arm = N as ttn -generate int8x8_t:uint8x8_t, int16x4_t:uint16x4_t, int32x2_t:uint32x2_t, int64x1_t:uint64x1_t -generate int8x16_t:uint8x16_t, int16x8_t:uint16x8_t, int32x4_t:uint32x4_t, int64x2_t:uint64x2_t - -/// Signed saturating shift left unsigned -name = vqshlu -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = simd_extract!, {vqshlu_n-in_ntt-::, {vdup_n-in_ntt-noext, a}}, 0 -a = 1 -n = 2 -validate 4 - -aarch64 = sqshlu -generate i8:u8, i16:u16, i32:u32, i64:u64 - -/// Signed saturating shift right narrow -name = vqshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = 0, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate 0, 1, 2, 3, 4, 5, 6, 7 -arm-aarch64-separate - -aarch64 = sqshrn -link-aarch64 = sqshrn._EXT2_ -const-aarch64 = N -generate i64:i32 - -arm = vqshrn -link-arm = vqshiftns._EXT2_ -const-arm = -N as ttn -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t - -/// Signed saturating shift right narrow -name = vqshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_extract!, {vqshrn_n-in_ntt-::, {vdupq_n-in_ntt-noext, a}}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = sqshrn -generate i16:i8, i32:i16 - -/// Signed saturating shift right narrow -name = vqshrn_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqshrn_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 8, 9, 8, 9, 10, 11 -b = 32, 36, 40, 44, 48, 52, 56, 60 -n = 2 -validate 0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = sqshrn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t - -/// Unsigned saturating shift right narrow -name = vqshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = 0, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate 0, 1, 2, 3, 4, 5, 6, 7 -arm-aarch64-separate - -aarch64 = uqshrn -link-aarch64 = uqshrn._EXT2_ -const-aarch64 = N -generate u64:u32 - -arm = vqshrn -link-arm = vqshiftnu._EXT2_ -const-arm = -N as ttn -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Unsigned saturating shift right narrow -name = vqshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_extract!, {vqshrn_n-in_ntt-::, {vdupq_n-in_ntt-noext, a}}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = uqshrn -generate u16:u8, u32:u16 - -/// Unsigned saturating shift right narrow -name = vqshrn_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqshrn_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 8, 9, 8, 9, 10, 11 -b = 32, 36, 40, 44, 48, 52, 56, 60 -n = 2 -validate 0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = uqshrn2 -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Signed saturating shift right unsigned narrow -name = vqshrun -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = 0, 4, 8, 12, 16, 20, 24, 28 -n = 2 -validate 0, 1, 2, 3, 4, 5, 6, 7 -arm-aarch64-separate - -aarch64 = sqshrun -link-aarch64 = sqshrun._EXT2_ -const-aarch64 = N - -arm = vqshrun -link-arm = vqshiftnsu._EXT2_ -const-arm = -N as ttn -generate int16x8_t:uint8x8_t, int32x4_t:uint16x4_t, int64x2_t:uint32x2_t - -/// Signed saturating shift right unsigned narrow -name = vqshrun -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_extract!, {vqshrun_n-in_ntt-::, {vdupq_n-in_ntt-noext, a}}, 0 -a = 4 -n = 2 -validate 1 - -aarch64 = sqshrun -generate i16:u8, i32:u16, i64:u32 - -/// Signed saturating shift right unsigned narrow -name = vqshrun_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vqshrun_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 8, 9, 8, 9, 10, 11 -b = 32, 36, 40, 44, 48, 52, 56, 60 -n = 2 -validate 0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = sqshrun2 -generate uint8x8_t:int16x8_t:uint8x16_t, uint16x4_t:int32x4_t:uint16x8_t, uint32x2_t:int64x2_t:uint32x4_t - -/// Unsigned saturating accumulate of signed value -name = vsqadd -out-suffix -multi_fn = simd_extract!, {vsqadd-out_ntt-noext, {vdup_n-out_ntt-noext, a}, {vdup_n-in_ntt-noext, b}}, 0 -a = 2 -b = 2 -validate 4 - -aarch64 = usqadd -generate u8:i8:u8, u16:i16:u16 - -/// Unsigned saturating accumulate of signed value -name = vsqadd -out-suffix -a = 2 -b = 2 -validate 4 - -aarch64 = usqadd -link-aarch64 = usqadd._EXT_ -generate u32:i32:u32, u64:i64:u64 - -/// Calculates the square root of each lane. -name = vsqrt -fn = simd_fsqrt -a = 4.0, 9.0, 16.0, 25.0 -validate 2.0, 3.0, 4.0, 5.0 - -aarch64 = fsqrt -generate float*_t, float64x*_t - -/// Reciprocal square-root estimate. -name = vrsqrte -a = 1.0, 2.0, 3.0, 4.0 -validate 0.998046875, 0.705078125, 0.576171875, 0.4990234375 - -aarch64 = frsqrte -link-aarch64 = frsqrte._EXT_ -generate float64x*_t, f32, f64 - -arm = vrsqrte -link-arm = vrsqrte._EXT_ -generate float*_t - -/// Unsigned reciprocal square root estimate -name = vrsqrte -a = 1, 2, 3, 4 -validate 4294967295, 4294967295, 4294967295, 4294967295 - -aarch64 = ursqrte -link-aarch64 = ursqrte._EXT_ -arm = vrsqrte -link-arm = vrsqrte._EXT_ -generate uint32x2_t, uint32x4_t - -/// Floating-point reciprocal square root step -name = vrsqrts -a = 1.0, 2.0, 3.0, 4.0 -b = 1.0, 2.0, 3.0, 4.0 -validate 1., -0.5, -3.0, -6.5 - -aarch64 = frsqrts -link-aarch64 = frsqrts._EXT_ -generate float64x*_t, f32, f64 - -arm = vrsqrts -link-arm = vrsqrts._EXT_ -generate float*_t - -/// Reciprocal estimate. -name = vrecpe -a = 4.0, 3.0, 2.0, 1.0 -validate 0.24951171875, 0.3330078125, 0.4990234375, 0.998046875 - -aarch64 = frecpe -link-aarch64 = frecpe._EXT_ -generate float64x*_t, f32, f64 - -arm = vrecpe -link-arm = vrecpe._EXT_ -generate float*_t - -/// Unsigned reciprocal estimate -name = vrecpe -a = 4, 3, 2, 1 -validate 4294967295, 4294967295, 4294967295, 4294967295 - -aarch64 = urecpe -link-aarch64 = urecpe._EXT_ -arm = vrecpe -link-arm = vrecpe._EXT_ -generate uint32x2_t, uint32x4_t - -/// Floating-point reciprocal step -name = vrecps -a = 4.0, 3.0, 2.0, 1.0 -b = 4.0, 3.0, 2.0, 1.0 -validate -14., -7., -2., 1. - -aarch64 = frecps -link-aarch64 = frecps._EXT_ -generate float64x*_t, f32, f64 - -arm = vrecps -link-arm = vrecps._EXT_ -generate float*_t - -/// Floating-point reciprocal exponent -name = vrecpx -a = 4.0 -validate 0.5 - -aarch64 = frecpx -link-aarch64 = frecpx._EXT_ -generate f32, f64 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = nop -generate poly64x1_t:int64x1_t, poly64x1_t:uint64x1_t, int64x1_t:poly64x1_t, uint64x1_t:poly64x1_t -generate poly64x2_t:int64x2_t, poly64x2_t:uint64x2_t, int64x2_t:poly64x2_t, uint64x2_t:poly64x2_t - -arm = nop -generate uint8x8_t:int8x8_t, poly8x8_t:int8x8_t, poly16x4_t:int16x4_t, uint16x4_t:int16x4_t, uint32x2_t:int32x2_t, uint64x1_t:int64x1_t -generate uint8x16_t:int8x16_t, poly8x16_t:int8x16_t, poly16x8_t:int16x8_t, uint16x8_t:int16x8_t, uint32x4_t:int32x4_t, uint64x2_t:int64x2_t -generate poly8x8_t:uint8x8_t, int8x8_t:uint8x8_t, poly16x4_t:uint16x4_t, int16x4_t:uint16x4_t, int32x2_t:uint32x2_t, int64x1_t:uint64x1_t -generate poly8x16_t:uint8x16_t, int8x16_t:uint8x16_t, poly16x8_t:uint16x8_t, int16x8_t:uint16x8_t, int32x4_t:uint32x4_t, int64x2_t:uint64x2_t -generate int8x8_t:poly8x8_t, uint8x8_t:poly8x8_t, int16x4_t:poly16x4_t, uint16x4_t:poly16x4_t -generate int8x16_t:poly8x16_t, uint8x16_t:poly8x16_t, int16x8_t:poly16x8_t, uint16x8_t:poly16x8_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 1, 2, 3, 4, 5, 6, 7 -validate 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0 - -aarch64 = nop -arm = nop -generate int16x4_t:int8x8_t, uint16x4_t:int8x8_t, poly16x4_t:int8x8_t, int32x2_t:int16x4_t, uint32x2_t:int16x4_t, int64x1_t:int32x2_t, uint64x1_t:int32x2_t -generate int16x8_t:int8x16_t, uint16x8_t:int8x16_t, poly16x8_t:int8x16_t, int32x4_t:int16x8_t, uint32x4_t:int16x8_t, int64x2_t:int32x4_t, uint64x2_t:int32x4_t -generate poly16x4_t:uint8x8_t, int16x4_t:uint8x8_t, uint16x4_t:uint8x8_t, int32x2_t:uint16x4_t, uint32x2_t:uint16x4_t, int64x1_t:uint32x2_t, uint64x1_t:uint32x2_t -generate poly16x8_t:uint8x16_t, int16x8_t:uint8x16_t, uint16x8_t:uint8x16_t, int32x4_t:uint16x8_t, uint32x4_t:uint16x8_t, int64x2_t:uint32x4_t, uint64x2_t:uint32x4_t -generate poly16x4_t:poly8x8_t, int16x4_t:poly8x8_t, uint16x4_t:poly8x8_t, int32x2_t:poly16x4_t, uint32x2_t:poly16x4_t -generate poly16x8_t:poly8x16_t, int16x8_t:poly8x16_t, uint16x8_t:poly8x16_t, int32x4_t:poly16x8_t, uint32x4_t:poly16x8_t -target = aes -generate poly64x1_t:int32x2_t, poly64x1_t:uint32x2_t -generate poly64x2_t:int32x4_t, poly64x2_t:uint32x4_t -generate p128:int64x2_t, p128:uint64x2_t, p128:poly64x2_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 0, 1, 0, 2, 0, 3, 0, 4, 0, 5, 0, 6, 0, 7, 0 -validate 0, 1, 2, 3, 4, 5, 6, 7 - -aarch64 = nop -arm = nop -generate poly8x8_t:int16x4_t, int8x8_t:int16x4_t, uint8x8_t:int16x4_t, poly16x4_t:int32x2_t, int16x4_t:int32x2_t, uint16x4_t:int32x2_t, int32x2_t:int64x1_t, uint32x2_t:int64x1_t -generate poly8x16_t:int16x8_t, int8x16_t:int16x8_t, uint8x16_t:int16x8_t, poly16x8_t:int32x4_t, int16x8_t:int32x4_t, uint16x8_t:int32x4_t, int32x4_t:int64x2_t, uint32x4_t:int64x2_t -generate poly8x8_t:uint16x4_t, int8x8_t:uint16x4_t, uint8x8_t:uint16x4_t, poly16x4_t:uint32x2_t, int16x4_t:uint32x2_t, uint16x4_t:uint32x2_t, int32x2_t:uint64x1_t, uint32x2_t:uint64x1_t -generate poly8x16_t:uint16x8_t, int8x16_t:uint16x8_t, uint8x16_t:uint16x8_t, poly16x8_t:uint32x4_t, int16x8_t:uint32x4_t, uint16x8_t:uint32x4_t, int32x4_t:uint64x2_t, uint32x4_t:uint64x2_t -generate poly8x8_t:poly16x4_t, int8x8_t:poly16x4_t, uint8x8_t:poly16x4_t -generate poly8x16_t:poly16x8_t, int8x16_t:poly16x8_t, uint8x16_t:poly16x8_t -target = aes -generate int32x2_t:poly64x1_t, uint32x2_t:poly64x1_t -generate int32x4_t:poly64x2_t, uint32x4_t:poly64x2_t -generate int64x2_t:p128, uint64x2_t:p128, poly64x2_t:p128 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 1, 2, 3 -validate 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0 - -aarch64 = nop -arm = nop -generate int32x2_t:int8x8_t, uint32x2_t:int8x8_t, int64x1_t:int16x4_t, uint64x1_t:int16x4_t -generate int32x4_t:int8x16_t, uint32x4_t:int8x16_t, int64x2_t:int16x8_t, uint64x2_t:int16x8_t -generate int32x2_t:uint8x8_t, uint32x2_t:uint8x8_t, int64x1_t:uint16x4_t, uint64x1_t:uint16x4_t -generate int32x4_t:uint8x16_t, uint32x4_t:uint8x16_t, int64x2_t:uint16x8_t, uint64x2_t:uint16x8_t -generate int32x2_t:poly8x8_t, uint32x2_t:poly8x8_t, int64x1_t:poly16x4_t, uint64x1_t:poly16x4_t -generate int32x4_t:poly8x16_t, uint32x4_t:poly8x16_t, int64x2_t:poly16x8_t, uint64x2_t:poly16x8_t -target = aes -generate poly64x1_t:int16x4_t, poly64x1_t:uint16x4_t, poly64x1_t:poly16x4_t -generate poly64x2_t:int16x8_t, poly64x2_t:uint16x8_t, poly64x2_t:poly16x8_t -generate p128:int32x4_t, p128:uint32x4_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 0, 0, 0, 1, 0, 0, 0, 2, 0, 0, 0, 3, 0, 0, 0 -validate 0, 1, 2, 3 - -aarch64 = nop -arm = nop -generate poly8x8_t:int32x2_t, int8x8_t:int32x2_t, uint8x8_t:int32x2_t, poly16x4_t:int64x1_t, int16x4_t:int64x1_t, uint16x4_t:int64x1_t -generate poly8x16_t:int32x4_t, int8x16_t:int32x4_t, uint8x16_t:int32x4_t, poly16x8_t:int64x2_t, int16x8_t:int64x2_t, uint16x8_t:int64x2_t -generate poly8x8_t:uint32x2_t, int8x8_t:uint32x2_t, uint8x8_t:uint32x2_t, poly16x4_t:uint64x1_t, int16x4_t:uint64x1_t, uint16x4_t:uint64x1_t -generate poly8x16_t:uint32x4_t, int8x16_t:uint32x4_t, uint8x16_t:uint32x4_t, poly16x8_t:uint64x2_t, int16x8_t:uint64x2_t, uint16x8_t:uint64x2_t -target = aes -generate poly16x4_t:poly64x1_t, int16x4_t:poly64x1_t, uint16x4_t:poly64x1_t -generate poly16x8_t:poly64x2_t, int16x8_t:poly64x2_t, uint16x8_t:poly64x2_t -generate int32x4_t:p128, uint32x4_t:p128 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 1 -validate 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = nop -arm = nop -generate int64x1_t:int8x8_t, uint64x1_t:int8x8_t, int64x1_t:uint8x8_t, uint64x1_t:uint8x8_t, int64x1_t:poly8x8_t, uint64x1_t:poly8x8_t -generate int64x2_t:int8x16_t, uint64x2_t:int8x16_t, int64x2_t:uint8x16_t, uint64x2_t:uint8x16_t, int64x2_t:poly8x16_t, uint64x2_t:poly8x16_t -target = aes -generate poly64x1_t:int8x8_t, poly64x1_t:uint8x8_t, poly64x1_t:poly8x8_t -generate poly64x2_t:int8x16_t, poly64x2_t:uint8x16_t, poly64x2_t:poly8x16_t -generate p128:int16x8_t, p128:uint16x8_t, p128:poly16x8_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 0, 0, 0, 0 -validate 0, 1 - -aarch64 = nop -arm = nop -generate poly8x8_t:int64x1_t, int8x8_t:int64x1_t, uint8x8_t:int64x1_t, poly8x8_t:uint64x1_t, int8x8_t:uint64x1_t, uint8x8_t:uint64x1_t -generate poly8x16_t:int64x2_t, int8x16_t:int64x2_t, uint8x16_t:int64x2_t, poly8x16_t:uint64x2_t, int8x16_t:uint64x2_t, uint8x16_t:uint64x2_t -target = aes -generate poly8x8_t:poly64x1_t, int8x8_t:poly64x1_t, uint8x8_t:poly64x1_t -generate poly8x16_t:poly64x2_t, int8x16_t:poly64x2_t, uint8x16_t:poly64x2_t -generate int16x8_t:p128, uint16x8_t:p128, poly16x8_t:p128 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate 1 -target = aes - -aarch64 = nop -arm = nop -generate int8x16_t:p128, uint8x16_t:p128, poly8x16_t:p128 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 1 -validate 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -target = aes - -aarch64 = nop -arm = nop -generate p128:int8x16_t, p128:uint8x16_t, p128:poly8x16_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0., 0., 0., 0., 0., 0., 0., 0. -validate 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = nop -generate float64x1_t:int8x8_t, float64x1_t:int16x4_t, float64x1_t:int32x2_t, float64x1_t:int64x1_t -generate float64x2_t:int8x16_t, float64x2_t:int16x8_t, float64x2_t:int32x4_t, float64x2_t:int64x2_t -generate float64x1_t:uint8x8_t, float64x1_t:uint16x4_t, float64x1_t:uint32x2_t, float64x1_t:uint64x1_t -generate float64x2_t:uint8x16_t, float64x2_t:uint16x8_t, float64x2_t:uint32x4_t, float64x2_t:uint64x2_t -generate float64x1_t:poly8x8_t, float64x1_t:poly16x4_t, float32x2_t:poly64x1_t, float64x1_t:poly64x1_t -generate float64x2_t:poly8x16_t, float64x2_t:poly16x8_t, float32x4_t:poly64x2_t, float64x2_t:poly64x2_t -generate float64x2_t:p128 - -arm = nop -generate float32x2_t:int8x8_t, float32x2_t:int16x4_t, float32x2_t:int32x2_t, float32x2_t:int64x1_t -generate float32x4_t:int8x16_t, float32x4_t:int16x8_t, float32x4_t:int32x4_t, float32x4_t:int64x2_t -generate float32x2_t:uint8x8_t, float32x2_t:uint16x4_t, float32x2_t:uint32x2_t, float32x2_t:uint64x1_t -generate float32x4_t:uint8x16_t, float32x4_t:uint16x8_t, float32x4_t:uint32x4_t, float32x4_t:uint64x2_t -generate float32x2_t:poly8x8_t, float32x2_t:poly16x4_t -generate float32x4_t:poly8x16_t, float32x4_t:poly16x8_t -generate float32x4_t:p128 - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 -validate 0., 0., 0., 0., 0., 0., 0., 0. - -aarch64 = nop -generate int8x8_t:float64x1_t, int16x4_t:float64x1_t, int32x2_t:float64x1_t, int64x1_t:float64x1_t -generate int8x16_t:float64x2_t, int16x8_t:float64x2_t, int32x4_t:float64x2_t, int64x2_t:float64x2_t -generate poly8x8_t:float64x1_t, uint16x4_t:float64x1_t, uint32x2_t:float64x1_t, uint64x1_t:float64x1_t -generate poly8x16_t:float64x2_t, uint16x8_t:float64x2_t, uint32x4_t:float64x2_t, uint64x2_t:float64x2_t -generate uint8x8_t:float64x1_t, poly16x4_t:float64x1_t, poly64x1_t:float64x1_t, poly64x1_t:float32x2_t -generate uint8x16_t:float64x2_t, poly16x8_t:float64x2_t, poly64x2_t:float64x2_t, poly64x2_t:float32x4_t -generate p128:float64x2_t - -arm = nop -generate int8x8_t:float32x2_t, int16x4_t:float32x2_t, int32x2_t:float32x2_t, int64x1_t:float32x2_t -generate int8x16_t:float32x4_t, int16x8_t:float32x4_t, int32x4_t:float32x4_t, int64x2_t:float32x4_t -generate uint8x8_t:float32x2_t, uint16x4_t:float32x2_t, uint32x2_t:float32x2_t, uint64x1_t:float32x2_t -generate uint8x16_t:float32x4_t, uint16x8_t:float32x4_t, uint32x4_t:float32x4_t, uint64x2_t:float32x4_t -generate poly8x8_t:float32x2_t, poly16x4_t:float32x2_t -generate poly8x16_t:float32x4_t, poly16x8_t:float32x4_t -generate p128:float32x4_t - -/// Vector reinterpret cast operation -name = vreinterpret -double-suffixes -fn = transmute -a = 0., 0., 0., 0., 0., 0., 0., 0. -validate 0., 0., 0., 0., 0., 0., 0., 0. - -aarch64 = nop -generate float32x2_t:float64x1_t, float64x1_t:float32x2_t -generate float32x4_t:float64x2_t, float64x2_t:float32x4_t - -/// Signed rounding shift left -name = vrshl -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 - -aarch64 = srshl -link-aarch64 = srshl._EXT_ -generate i64 - -arm = vrshl -link-arm = vrshifts._EXT_ -generate int*_t, int64x*_t - -/// Unsigned rounding shift left -name = vrshl -out-suffix -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 - -aarch64 = urshl -link-aarch64 = urshl._EXT_ -generate u64:i64:u64 - -arm = vrshl -link-arm = vrshiftu._EXT_ -generate uint8x8_t:int8x8_t:uint8x8_t, uint8x16_t:int8x16_t:uint8x16_t, uint16x4_t:int16x4_t:uint16x4_t, uint16x8_t:int16x8_t:uint16x8_t -generate uint32x2_t:int32x2_t:uint32x2_t, uint32x4_t:int32x4_t:uint32x4_t, uint64x1_t:int64x1_t:uint64x1_t, uint64x2_t:int64x2_t:uint64x2_t - -/// Signed rounding shift right -name = vrshr -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshl-self-noext, a, {vdup-nself-noext, -N as _} -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = srshr -arm = vrshr -generate int*_t, int64x*_t - -/// Signed rounding shift right -name = vrshr -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshl-self-noext, a, -N as i64 -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = srshr -generate i64 - -/// Unsigned rounding shift right -name = vrshr -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshl-self-noext, a, {vdup-nsigned-noext, -N as _} -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = urshr -arm = vrshr -generate uint*_t, uint64x*_t - -/// Unsigned rounding shift right -name = vrshr -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshl-self-noext, a, -N as i64 -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = urshr -generate u64 - -/// Rounding shift right narrow -name = vrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -arm-aarch64-separate - -aarch64 = rshrn -link-aarch64 = rshrn._EXT2_ -const-aarch64 = N - -arm = vrshrn -link-arm = vrshiftn._EXT2_ -const-arm = -N as ttn -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t - -/// Rounding shift right narrow -name = vrshrn -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = transmute, {vrshrn_n-noqsigned-::, transmute(a)} -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = rshrn -arm = vrshrn -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Rounding shift right narrow -name = vrshrn_high -noq-n-suffix -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vrshrn_n-noqself-::, b}, {asc-0-out_len} -a = 0, 1, 8, 9, 8, 9, 10, 11 -b = 32, 36, 40, 44, 48, 52, 56, 60 -n = 2 -validate 0, 1, 8, 9, 8, 9, 10, 11, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = rshrn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Signed rounding shift right and accumulate -name = vrsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = simd_add, a, {vrshr-nself-::, b} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 - -aarch64 = srsra -arm = vrsra -generate int*_t, int64x*_t - -/// Unsigned rounding shift right and accumulate -name = vrsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = simd_add, a, {vrshr-nself-::, b} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 - -aarch64 = ursra -arm = vrsra -generate uint*_t, uint64x*_t - -/// Signed rounding shift right and accumulate. -name = vrsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshr-nself-::, b:in_t, b -multi_fn = a.wrapping_add(b) -a = 1 -b = 4 -n = 2 -validate 2 - -aarch64 = srshr -generate i64 - -/// Unsigned rounding shift right and accumulate. -name = vrsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = vrshr-nself-::, b:in_t, b -multi_fn = a.wrapping_add(b) -a = 1 -b = 4 -n = 2 -validate 2 - -aarch64 = urshr -generate u64 - -/// Rounding subtract returning high narrow -name = vrsubhn -no-q -a = MAX, MIN, 0, 4, 5, 6, 7, 8 -b = 1, 2, 3, 4, 5, 6, 7, 8 -validate MIN, MIN, 0, 0, 0, 0, 0, 0 - -aarch64 = rsubhn -link-aarch64 = rsubhn._EXT2_ -arm = vrsubhn -link-arm = vrsubhn._EXT2_ -generate int16x8_t:int16x8_t:int8x8_t, int32x4_t:int32x4_t:int16x4_t, int64x2_t:int64x2_t:int32x2_t - -/// Rounding subtract returning high narrow -name = vrsubhn -no-q -multi_fn = transmute, {vrsubhn-noqsigned-noext, {transmute, a}, {transmute, b}} -a = MAX, MIN, 3, 4, 5, 6, 7, 8 -b = 1, 2, 3, 4, 5, 6, 7, 8 -validate 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = rsubhn -arm = vrsubhn -generate uint16x8_t:uint16x8_t:uint8x8_t, uint32x4_t:uint32x4_t:uint16x4_t, uint64x2_t:uint64x2_t:uint32x2_t - -/// Rounding subtract returning high narrow -name = vrsubhn_high -no-q -multi_fn = vrsubhn-noqself-noext, x:in_t0, b, c -multi_fn = simd_shuffle!, a, x, {asc-0-out_len} -a = 1, 2, 0, 0, 0, 0, 0, 0 -b = 1, 2, 3, 4, 5, 6, 7, 8 -c = 1, 2, 3, 4, 5, 6, 7, 8 -validate 1, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 - -aarch64 = rsubhn2 -generate int8x8_t:int16x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int64x2_t:int32x4_t -generate uint8x8_t:uint16x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint64x2_t:uint32x4_t - -/// Insert vector element from another vector element -name = vset_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_insert!, b, LANE as u32, a -a = 1 -b = 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -n = 0 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = nop -arm = nop -generate i8:int8x8_t:int8x8_t, i16:int16x4_t:int16x4_t -generate i32:int32x2_t:int32x2_t, i64:int64x1_t:int64x1_t -generate u8:uint8x8_t:uint8x8_t, u16:uint16x4_t:uint16x4_t -generate u32:uint32x2_t:uint32x2_t, u64:uint64x1_t:uint64x1_t -generate p8:poly8x8_t:poly8x8_t, p16:poly16x4_t:poly16x4_t - -target = aes -generate p64:poly64x1_t:poly64x1_t - -/// Insert vector element from another vector element -name = vsetq_lane -no-q -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_insert!, b, LANE as u32, a -a = 1 -b = 0, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -n = 0 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -aarch64 = nop -arm = nop -generate i8:int8x16_t:int8x16_t, i16:int16x8_t:int16x8_t -generate i32:int32x4_t:int32x4_t, i64:int64x2_t:int64x2_t -generate u8:uint8x16_t:uint8x16_t, u16:uint16x8_t:uint16x8_t -generate u32:uint32x4_t:uint32x4_t, u64:uint64x2_t:uint64x2_t -generate p8:poly8x16_t:poly8x16_t, p16:poly16x8_t:poly16x8_t - -target = aes -generate p64:poly64x2_t:poly64x2_t - -/// Insert vector element from another vector element -name = vset_lane -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_insert!, b, LANE as u32, a -a = 1. -b = 0., 2., 3., 4. -n = 0 -validate 1., 2., 3., 4. - -aarch64 = nop -generate f64:float64x1_t:float64x1_t - -arm = nop -generate f32:float32x2_t:float32x2_t - -/// Insert vector element from another vector element -name = vsetq_lane -no-q -constn = LANE -multi_fn = static_assert_imm-in_exp_len-LANE -multi_fn = simd_insert!, b, LANE as u32, a -a = 1. -b = 0., 2., 3., 4. -n = 0 -validate 1., 2., 3., 4. - -aarch64 = nop -generate f64:float64x2_t:float64x2_t - -arm = nop -generate f32:float32x4_t:float32x4_t - -/// Signed Shift left -name = vshl -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 - -aarch64 = sshl -link-aarch64 = sshl._EXT_ -arm = vshl -link-arm = vshifts._EXT_ -generate int*_t, int64x*_t - -/// Signed Shift left -name = vshl -multi_fn = transmute, {vshl-in_ntt-noext, transmute(a), transmute(b)} -a = 1 -b = 2 -validate 4 - -aarch64 = sshl -generate i64 - -/// Unsigned Shift left -name = vshl -out-suffix -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2 -validate 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 - -aarch64 = ushl -link-aarch64 = ushl._EXT_ -arm = vshl -link-arm = vshiftu._EXT_ -generate uint8x8_t:int8x8_t:uint8x8_t, uint8x16_t:int8x16_t:uint8x16_t, uint16x4_t:int16x4_t:uint16x4_t, uint16x8_t:int16x8_t:uint16x8_t -generate uint32x2_t:int32x2_t:uint32x2_t, uint32x4_t:int32x4_t:uint32x4_t, uint64x1_t:int64x1_t:uint64x1_t, uint64x2_t:int64x2_t:uint64x2_t - -/// Unsigned Shift left -out-suffix -name = vshl -multi_fn = transmute, {vshl-out_ntt-noext, transmute(a), transmute(b)} -a = 1 -b = 2 -validate 4 - -aarch64 = ushl -generate u64:i64:u64 - -/// Shift left -name = vshl -n-suffix -constn = N -multi_fn = static_assert_imm-out_bits_exp_len-N -multi_fn = simd_shl, a, {vdup-nself-noext, N as _} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -n = 2 -validate 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 - -arm = vshl -aarch64 = shl -generate int*_t, uint*_t, int64x*_t, uint64x*_t - -/// Signed shift left long -name = vshll -n-suffix -constn = N -multi_fn = static_assert-N-0-bits -multi_fn = simd_shl, {simd_cast, a}, {vdup-nout-noext, N as _} -a = 1, 2, 3, 4, 5, 6, 7, 8 -n = 2 -validate 4, 8, 12, 16, 20, 24, 28, 32 - -arm = vshll.s -aarch64 = sshll -generate int8x8_t:int16x8_t, int16x4_t:int32x4_t, int32x2_t:int64x2_t -aarch64 = ushll -generate uint8x8_t:uint16x8_t, uint16x4_t:uint32x4_t, uint32x2_t:uint64x2_t - -/// Signed shift left long -name = vshll_high_n -no-q -constn = N -multi_fn = static_assert-N-0-bits -multi_fn = simd_shuffle!, b:half, a, a, {asc-halflen-halflen} -multi_fn = vshll_n-noqself-::, b -a = 0, 0, 1, 2, 1, 2, 3, 4, 1, 2, 3, 4, 5, 6, 7, 8 -n = 2 -validate 4, 8, 12, 16, 20, 24, 28, 32 - -aarch64 = sshll2 -generate int8x16_t:int16x8_t, int16x8_t:int32x4_t, int32x4_t:int64x2_t -aarch64 = ushll2 -generate uint8x16_t:uint16x8_t, uint16x8_t:uint32x4_t, uint32x4_t:uint64x2_t - -/// Shift right -name = vshr -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = fix_right_shift_imm-N-bits -multi_fn = simd_shr, a, {vdup-nself-noext, n as _} -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -arm = vshr.s -aarch64 = sshr -generate int*_t, int64x*_t -aarch64 = ushr -generate uint*_t, uint64x*_t - -/// Shift right narrow -name = vshrn_n -no-q -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_cast, {simd_shr, a, {vdup-nself-noext, N as _}} -a = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 - -arm = vshrn. -aarch64 = shrn -generate int16x8_t:int8x8_t, int32x4_t:int16x4_t, int64x2_t:int32x2_t -generate uint16x8_t:uint8x8_t, uint32x4_t:uint16x4_t, uint64x2_t:uint32x2_t - -/// Shift right narrow -name = vshrn_high_n -no-q -constn = N -multi_fn = static_assert-N-1-halfbits -multi_fn = simd_shuffle!, a, {vshrn_n-noqself-::, b}, {asc-0-out_len} -a = 1, 2, 5, 6, 5, 6, 7, 8 -b = 20, 24, 28, 32, 52, 56, 60, 64 -n = 2 -validate 1, 2, 5, 6, 5, 6, 7, 8, 5, 6, 7, 8, 13, 14, 15, 16 - -aarch64 = shrn2 -generate int8x8_t:int16x8_t:int8x16_t, int16x4_t:int32x4_t:int16x8_t, int32x2_t:int64x2_t:int32x4_t -generate uint8x8_t:uint16x8_t:uint8x16_t, uint16x4_t:uint32x4_t:uint16x8_t, uint32x2_t:uint64x2_t:uint32x4_t - -/// Signed shift right and accumulate -name = vsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = simd_add, a, {vshr-nself-::, b} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 - -aarch64 = ssra -arm = vsra -generate int*_t, int64x*_t - -/// Unsigned shift right and accumulate -name = vsra -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = simd_add, a, {vshr-nself-::, b} -a = 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1 -b = 4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44, 48, 52, 56, 60, 64 -n = 2 -validate 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17 - -aarch64 = usra -arm = vsra -generate uint*_t, uint64x*_t - -/// SM3PARTW1 -name = vsm3partw1 -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -c = 1, 2, 3, 4 -validate 2147549312, 3221323968, 131329, 2684362752 -target = sm4 - -aarch64 = sm3partw1 -link-aarch64 = llvm.aarch64.crypto.sm3partw1 -generate uint32x4_t - -/// SM3PARTW2 -name = vsm3partw2 -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -c = 1, 2, 3, 4 -validate 128, 256, 384, 1077977696 -target = sm4 - -aarch64 = sm3partw2 -link-aarch64 = llvm.aarch64.crypto.sm3partw2 -generate uint32x4_t - -/// SM3SS1 -name = vsm3ss1 -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -c = 1, 2, 3, 4 -validate 0, 0, 0, 2098176 -target = sm4 - -aarch64 = sm3ss1 -link-aarch64 = llvm.aarch64.crypto.sm3ss1 -generate uint32x4_t - -/// SM4 key -name = vsm4ekey -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -validate 1784948604, 136020997, 2940231695, 3789947679 -target = sm4 - -aarch64 = sm4ekey -link-aarch64 = llvm.aarch64.crypto.sm4ekey -generate uint32x4_t - -/// SM4 encode -name = vsm4e -a = 1, 2, 3, 4 -b = 1, 2, 3, 4 -validate 1093874472, 3616769504, 3878330411, 2765298765 -target = sm4 - -aarch64 = sm4e -link-aarch64 = llvm.aarch64.crypto.sm4e -generate uint32x4_t - -/// Rotate and exclusive OR -name = vrax1 -a = 1, 2 -b = 3, 4 -validate 7, 10 -target = sha3 - -aarch64 = rax1 -link-aarch64 = llvm.aarch64.crypto.rax1 -generate uint64x2_t - -/// SHA512 hash update part 1 -name = vsha512h -a = 1, 2 -b = 3, 4 -c = 5, 6 -validate 11189044327219203, 7177611956453380 -target = sha3 - -aarch64 = sha512h -link-aarch64 = llvm.aarch64.crypto.sha512h -generate uint64x2_t - -/// SHA512 hash update part 2 -name = vsha512h2 -a = 1, 2 -b = 3, 4 -c = 5, 6 -validate 5770237651009406214, 349133864969 -target = sha3 - -aarch64 = sha512h2 -link-aarch64 = llvm.aarch64.crypto.sha512h2 -generate uint64x2_t - -/// SHA512 schedule update 0 -name = vsha512su0 -a = 1, 2 -b = 3, 4 -validate 144115188075855874, 9439544818968559619 -target = sha3 - -aarch64 = sha512su0 -link-aarch64 = llvm.aarch64.crypto.sha512su0 -generate uint64x2_t - -/// SHA512 schedule update 1 -name = vsha512su1 -a = 1, 2 -b = 3, 4 -c = 5, 6 -validate 105553116266526, 140737488355368 -target = sha3 - -aarch64 = sha512su1 -link-aarch64 = llvm.aarch64.crypto.sha512su1 -generate uint64x2_t - -/// Floating-point round to 32-bit integer, using current rounding mode -name = vrnd32x -target = frintts - -// For validation, the rounding mode should be the default: round-to-nearest (ties-to-even). -a = -1.5, 2.9, 1.5, -2.5 -validate -2.0, 3.0, 2.0, -2.0 - -aarch64 = frint32x -link-aarch64 = frint32x._EXT_ -// dumpbin doesn't know how to disassembly this -assert_instr_cfg = not(target_env = "msvc") -generate float32x2_t, float32x4_t - -// The float64x1_t form uses a different LLVM link and isn't supported by Clang -// (and so has no intrinsic-test), so perform extra validation to make sure -// that it matches the float64x2_t form. - -a = 1.5, -2.5 -validate 2.0, -2.0 -// - The biggest f64 that rounds to i32::MAX. -// - The smallest positive f64 that rounds out of range. -a = 2147483647.499999762, 2147483647.5 -validate 2147483647.0, -2147483648.0 -// - The smallest f64 that rounds to i32::MIN + 1. -// - The largest negative f64 that rounds out of range. -a = -2147483647.499999762, -2147483648.500000477 -validate -2147483647.0, -2147483648.0 -generate float64x2_t - -// Odd-numbered tests for float64x1_t coverage. -a = 2.9 -validate 3.0 -a = -2.5 -validate -2.0 -a = 2147483647.5 -validate -2147483648.0 -a = -2147483648.500000477 -validate -2147483648.0 - -multi_fn = transmute, {self-out-_, {simd_extract!, a, 0}} -link-aarch64 = llvm.aarch64.frint32x.f64:f64:::f64 -generate float64x1_t - -/// Floating-point round to 32-bit integer toward zero -name = vrnd32z -target = frintts - -a = -1.5, 2.9, 1.5, -2.5 -validate -1.0, 2.0, 1.0, -2.0 - -aarch64 = frint32z -link-aarch64 = frint32z._EXT_ -// dumpbin doesn't know how to disassembly this -assert_instr_cfg = not(target_env = "msvc") -generate float32x2_t, float32x4_t - -// The float64x1_t form uses a different LLVM link and isn't supported by Clang -// (and so has no intrinsic-test), so perform extra validation to make sure -// that it matches the float64x2_t form. - -a = 1.5, -2.5 -validate 1.0, -2.0 -// - The biggest f64 that rounds to i32::MAX. -// - The smallest positive f64 that rounds out of range. -a = 2147483647.999999762, 2147483648.0 -validate 2147483647.0, -2147483648.0 -// - The smallest f64 that rounds to i32::MIN + 1. -// - The largest negative f64 that rounds out of range. -a = -2147483647.999999762, -2147483649.0 -validate -2147483647.0, -2147483648.0 -generate float64x2_t - -// Odd-numbered tests for float64x1_t coverage. -a = 2.9 -validate 2.0 -a = -2.5 -validate -2.0 -a = 2147483648.0 -validate -2147483648.0 -a = -2147483649.0 -validate -2147483648.0 - -multi_fn = transmute, {self-out-_, {simd_extract!, a, 0}} -link-aarch64 = llvm.aarch64.frint32z.f64:f64:::f64 -generate float64x1_t - -/// Floating-point round to 64-bit integer, using current rounding mode -name = vrnd64x -target = frintts - -// For validation, the rounding mode should be the default: round-to-nearest (ties-to-even). -a = -1.5, 2.9, 1.5, -2.5 -validate -2.0, 3.0, 2.0, -2.0 - -aarch64 = frint64x -link-aarch64 = frint64x._EXT_ -// dumpbin doesn't know how to disassembly this -assert_instr_cfg = not(target_env = "msvc") -generate float32x2_t, float32x4_t - -// The float64x1_t form uses a different LLVM link and isn't supported by Clang -// (and so has no intrinsic-test), so perform extra validation to make sure -// that it matches the float64x2_t form. - -a = 1.5, -2.5 -validate 2.0, -2.0 -// - The biggest f64 representable as an i64 (0x7ffffffffffffc00). -// - The smallest positive f64 that is out of range (2^63). -a = 9223372036854774784.0, 9223372036854775808.0 -validate 9223372036854774784.0, -9223372036854775808.0 -// - The smallest f64 representable as an i64 (i64::MIN). -// - The biggest negative f64 that is out of range. -a = -9223372036854775808.0, -9223372036854777856.0 -validate -9223372036854775808.0, -9223372036854775808.0 -generate float64x2_t - -// Odd-numbered tests for float64x1_t coverage. -a = 2.9 -validate 3.0 -a = -2.5 -validate -2.0 -a = 9223372036854775808.0 -validate -9223372036854775808.0 -a = -9223372036854777856.0 -validate -9223372036854775808.0 - -multi_fn = transmute, {self-out-_, {simd_extract!, a, 0}} -link-aarch64 = llvm.aarch64.frint64x.f64:f64:::f64 -generate float64x1_t - -/// Floating-point round to 64-bit integer toward zero -name = vrnd64z -target = frintts - -a = -1.5, 2.9, 1.5, -2.5 -validate -1.0, 2.0, 1.0, -2.0 - -aarch64 = frint64z -link-aarch64 = frint64z._EXT_ -// dumpbin doesn't know how to disassembly this -assert_instr_cfg = not(target_env = "msvc") -generate float32x2_t, float32x4_t - -// The float64x1_t form uses a different LLVM link and isn't supported by Clang -// (and so has no intrinsic-test), so perform extra validation to make sure -// that it matches the float64x2_t form. - -a = 1.5, -2.5 -validate 1.0, -2.0 -// - The biggest f64 representable as an i64 (0x7ffffffffffffc00). -// - The smallest positive f64 that is out of range (2^63). -a = 9223372036854774784.0, 9223372036854775808.0 -validate 9223372036854774784.0, -9223372036854775808.0 -// - The smallest f64 representable as an i64 (i64::MIN). -// - The biggest negative f64 that is out of range. -a = -9223372036854775808.0, -9223372036854777856.0 -validate -9223372036854775808.0, -9223372036854775808.0 -generate float64x2_t - -// Odd-numbered tests for float64x1_t coverage. -a = 2.9 -validate 2.0 -a = -2.5 -validate -2.0 -a = 9223372036854775808.0 -validate -9223372036854775808.0 -a = -9223372036854777856.0 -validate -9223372036854775808.0 - -multi_fn = transmute, {self-out-_, {simd_extract!, a, 0}} -link-aarch64 = llvm.aarch64.frint64z.f64:f64:::f64 -generate float64x1_t - -/// Transpose elements -name = vtrn -multi_fn = simd_shuffle!, a1:in_t, a, b, {transpose-1-in_len} -multi_fn = simd_shuffle!, b1:in_t, a, b, {transpose-2-in_len} -multi_fn = transmute, (a1, b1) -a = 0, 2, 2, 6, 2, 10, 6, 14, 2, 18, 6, 22, 10, 26, 14, 30 -b = 1, 3, 3, 7, 3, 1, 7, 15, 3, 19, 7, 23, 1, 27, 15, 31 -validate 0, 1, 2, 3, 2, 3, 6, 7, 2, 3, 6, 7, 10, 1, 14, 15, 2, 3, 6, 7, 10, 1, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 - -aarch64 = trn -arm = vtrn -generate int8x8_t:int8x8_t:int8x8x2_t, int16x4_t:int16x4_t:int16x4x2_t, int8x16_t:int8x16_t:int8x16x2_t, int16x8_t:int16x8_t:int16x8x2_t, int32x4_t:int32x4_t:int32x4x2_t -generate uint8x8_t:uint8x8_t:uint8x8x2_t, uint16x4_t:uint16x4_t:uint16x4x2_t, uint8x16_t:uint8x16_t:uint8x16x2_t, uint16x8_t:uint16x8_t:uint16x8x2_t, uint32x4_t:uint32x4_t:uint32x4x2_t -generate poly8x8_t:poly8x8_t:poly8x8x2_t, poly16x4_t:poly16x4_t:poly16x4x2_t, poly8x16_t:poly8x16_t:poly8x16x2_t, poly16x8_t:poly16x8_t:poly16x8x2_t -aarch64 = zip -generate int32x2_t:int32x2_t:int32x2x2_t, uint32x2_t:uint32x2_t:uint32x2x2_t - -/// Transpose elements -name = vtrn -multi_fn = simd_shuffle!, a1:in_t, a, b, {transpose-1-in_len} -multi_fn = simd_shuffle!, b1:in_t, a, b, {transpose-2-in_len} -multi_fn = transmute, (a1, b1) -a = 0., 2., 2., 6. -b = 1., 3., 3., 7. -validate 0., 1., 2., 3., 2., 3., 6., 7. - -aarch64 = zip -arm = vtrn -generate float32x2_t:float32x2_t:float32x2x2_t -aarch64 = trn -generate float32x4_t:float32x4_t:float32x4x2_t - -/// Transpose vectors -name = vtrn1 -multi_fn = simd_shuffle!, a, b, {transpose-1-in_len} -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 -validate 0, 1, 4, 5, 8, 9, 12, 13, 16, 17, 20, 21, 24, 25, 28, 29 - -aarch64 = trn1 -generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t - -aarch64 = zip1 -generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t - -/// Transpose vectors -name = vtrn1 -multi_fn = simd_shuffle!, a, b, {transpose-1-in_len} -a = 0., 2., 4., 6., 8., 10., 12., 14. -b = 1., 3., 5., 7., 9., 11., 13., 15. -validate 0., 1., 4., 5., 8., 9., 12., 13. - -aarch64 = trn1 -generate float32x4_t - -aarch64 = zip1 -generate float32x2_t, float64x2_t - -/// Transpose vectors -name = vtrn2 -multi_fn = simd_shuffle!, a, b, {transpose-2-in_len} -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 -validate 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 - -aarch64 = trn2 -generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t - -aarch64 = zip2 -generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t - -/// Transpose vectors -name = vtrn2 -multi_fn = simd_shuffle!, a, b, {transpose-2-in_len} -a = 0., 2., 4., 6., 8., 10., 12., 14. -b = 1., 3., 5., 7., 9., 11., 13., 15. -validate 2., 3., 6., 7., 10., 11., 14., 15. - -aarch64 = trn2 -generate float32x4_t - -aarch64 = zip2 -generate float32x2_t, float64x2_t - -/// Zip vectors -name = vzip -multi_fn = simd_shuffle!, a0:in_t, a, b, {zip-1-in_len} -multi_fn = simd_shuffle!, b0:in_t, a, b, {zip-2-in_len} -multi_fn = transmute, (a0, b0) -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 - -aarch64 = zip -arm = vzip -generate int8x8_t:int8x8_t:int8x8x2_t, int16x4_t:int16x4_t:int16x4x2_t -generate uint8x8_t:uint8x8_t:uint8x8x2_t, uint16x4_t:uint16x4_t:uint16x4x2_t -generate poly8x8_t:poly8x8_t:poly8x8x2_t, poly16x4_t:poly16x4_t:poly16x4x2_t -arm = vtrn -generate int32x2_t:int32x2_t:int32x2x2_t, uint32x2_t:uint32x2_t:uint32x2x2_t -aarch64 = zip -arm = vorr -generate int8x16_t:int8x16_t:int8x16x2_t, int16x8_t:int16x8_t:int16x8x2_t, int32x4_t:int32x4_t:int32x4x2_t -generate uint8x16_t:uint8x16_t:uint8x16x2_t, uint16x8_t:uint16x8_t:uint16x8x2_t, uint32x4_t:uint32x4_t:uint32x4x2_t -generate poly8x16_t:poly8x16_t:poly8x16x2_t, poly16x8_t:poly16x8_t:poly16x8x2_t - -/// Zip vectors -name = vzip -multi_fn = simd_shuffle!, a0:in_t, a, b, {zip-1-in_len} -multi_fn = simd_shuffle!, b0:in_t, a, b, {zip-2-in_len} -multi_fn = transmute, (a0, b0) -a = 1., 2., 3., 4. -b = 5., 6., 7., 8. -validate 1., 5., 2., 6., 3., 7., 4., 8. - -aarch64 = zip -arm = vtrn -generate float32x2_t:float32x2_t:float32x2x2_t -aarch64 = zip -arm = vorr -generate float32x4_t:float32x4_t:float32x4x2_t - -/// Zip vectors -name = vzip1 -multi_fn = simd_shuffle!, a, b, {zip-1-in_len} -a = 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 -b = 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 -validate 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 - -aarch64 = zip1 -generate int*_t, int64x2_t, uint*_t, uint64x2_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t, poly64x2_t - -/// Zip vectors -name = vzip1 -multi_fn = simd_shuffle!, a, b, {zip-1-in_len} -a = 0., 2., 4., 6., 8., 10., 12., 14. -b = 1., 3., 5., 7., 9., 11., 13., 15. -validate 0., 1., 2., 3., 4., 5., 6., 7. - -aarch64 = zip1 -generate float32x2_t, float32x4_t, float64x2_t - -/// Zip vectors -name = vzip2 -multi_fn = simd_shuffle!, a, b, {zip-2-in_len} -a = 0, 16, 16, 18, 16, 18, 20, 22, 16, 18, 20, 22, 24, 26, 28, 30 -b = 1, 17, 17, 19, 17, 19, 21, 23, 17, 19, 21, 23, 25, 27, 29, 31 -validate 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 - -aarch64 = zip2 -generate int*_t, int64x2_t, uint*_t, uint64x2_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t, poly64x2_t - -/// Zip vectors -name = vzip2 -multi_fn = simd_shuffle!, a, b, {zip-2-in_len} -a = 0., 8., 8., 10., 8., 10., 12., 14. -b = 1., 9., 9., 11., 9., 11., 13., 15. -validate 8., 9., 10., 11., 12., 13., 14., 15. - -aarch64 = zip2 -generate float32x2_t, float32x4_t, float64x2_t - -/// Unzip vectors -name = vuzp -multi_fn = simd_shuffle!, a0:in_t, a, b, {unzip-1-in_len} -multi_fn = simd_shuffle!, b0:in_t, a, b, {unzip-2-in_len} -multi_fn = transmute, (a0, b0) -a = 1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 15, 8, 16 -b = 2, 3, 3, 8, 3, 15, 8, 16, 3, 29, 8, 30, 15, 31, 16, 32 -validate 1, 2, 2, 3, 2, 3, 3, 8, 2, 3, 3, 8, 3, 8, 15, 16, 2, 3, 3, 8, 3, 8, 15, 16, 3, 8, 15, 16, 29, 30, 31, 32 - -aarch64 = uzp -arm = vuzp -generate int8x8_t:int8x8_t:int8x8x2_t, int16x4_t:int16x4_t:int16x4x2_t, int8x16_t:int8x16_t:int8x16x2_t, int16x8_t:int16x8_t:int16x8x2_t, int32x4_t:int32x4_t:int32x4x2_t -generate uint8x8_t:uint8x8_t:uint8x8x2_t, uint16x4_t:uint16x4_t:uint16x4x2_t, uint8x16_t:uint8x16_t:uint8x16x2_t, uint16x8_t:uint16x8_t:uint16x8x2_t, uint32x4_t:uint32x4_t:uint32x4x2_t -generate poly8x8_t:poly8x8_t:poly8x8x2_t, poly16x4_t:poly16x4_t:poly16x4x2_t, poly8x16_t:poly8x16_t:poly8x16x2_t, poly16x8_t:poly16x8_t:poly16x8x2_t -aarch64 = zip -arm = vtrn -generate int32x2_t:int32x2_t:int32x2x2_t, uint32x2_t:uint32x2_t:uint32x2x2_t - -/// Unzip vectors -name = vuzp -multi_fn = simd_shuffle!, a0:in_t, a, b, {unzip-1-in_len} -multi_fn = simd_shuffle!, b0:in_t, a, b, {unzip-2-in_len} -multi_fn = transmute, (a0, b0) -a = 1., 2., 2., 4. -b = 2., 6., 6., 8. -validate 1., 2., 2., 6., 2., 4., 6., 8. - -aarch64 = zip -arm = vtrn -generate float32x2_t:float32x2_t:float32x2x2_t -aarch64 = uzp -arm = vuzp -generate float32x4_t:float32x4_t:float32x4x2_t - -/// Unzip vectors -name = vuzp1 -multi_fn = simd_shuffle!, a, b, {unzip-1-in_len} -a = 1, 0, 2, 0, 2, 0, 3, 0, 2, 0, 3, 0, 7, 0, 8, 0 -b = 2, 0, 3, 0, 7, 0, 8, 0, 13, 0, 14, 0, 15, 0, 16, 0 -validate 1, 2, 2, 3, 2, 3, 7, 8, 2, 3, 7, 8, 13, 14, 15, 16 - -aarch64 = uzp1 -generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t - -aarch64 = zip1 -generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t - -/// Unzip vectors -name = vuzp1 -multi_fn = simd_shuffle!, a, b, {unzip-1-in_len} -a = 0., 8., 1., 9., 4., 12., 5., 13. -b = 1., 10., 3., 11., 6., 14., 7., 15. -validate 0., 1., 1., 3., 4., 5., 6., 7. - -aarch64 = uzp1 -generate float32x4_t - -aarch64 = zip1 -generate float32x2_t, float64x2_t - -/// Unzip vectors -name = vuzp2 -multi_fn = simd_shuffle!, a, b, {unzip-2-in_len} -a = 0, 17, 0, 18, 0, 18, 0, 19, 0, 18, 0, 19, 0, 23, 0, 24 -b = 0, 18, 0, 19, 0, 23, 0, 24, 0, 29, 0, 30, 0, 31, 0, 32 -validate 17, 18, 18, 19, 18, 19, 23, 24, 18, 19, 23, 24, 29, 30, 31, 32 - -aarch64 = uzp2 -generate int8x8_t, int8x16_t, int16x4_t, int16x8_t, int32x4_t, uint8x8_t, uint8x16_t, uint16x4_t, uint16x8_t, uint32x4_t, poly8x8_t, poly8x16_t, poly16x4_t, poly16x8_t - -aarch64 = zip2 -generate int32x2_t, int64x2_t, uint32x2_t, uint64x2_t, poly64x2_t - -/// Unzip vectors -name = vuzp2 -multi_fn = simd_shuffle!, a, b, {unzip-2-in_len} -a = 0., 8., 1., 9., 4., 12., 5., 13. -b = 2., 9., 3., 11., 6., 14., 7., 15. -validate 8., 9., 9., 11., 12., 13., 14., 15. - -aarch64 = uzp2 -generate float32x4_t - -aarch64 = zip2 -generate float32x2_t, float64x2_t - -//////////////////// -// Unsigned Absolute difference and Accumulate Long -//////////////////// - -/// Unsigned Absolute difference and Accumulate Long -name = vabal -multi_fn = vabd-unsigned-noext, b, c, d:in_t -multi_fn = simd_add, a, {simd_cast, d} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20 - -arm = vabal.s -aarch64 = uabal -generate uint16x8_t:uint8x8_t:uint8x8_t:uint16x8_t, uint32x4_t:uint16x4_t:uint16x4_t:uint32x4_t, uint64x2_t:uint32x2_t:uint32x2_t:uint64x2_t - -/// Unsigned Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:uint8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_shuffle!, e:uint8x8_t, c, c, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = vabd_u8, d, e, f:uint8x8_t -multi_fn = simd_add, a, {simd_cast, f} -a = 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 20, 20, 20, 20, 20, 20, 20, 20 - -aarch64 = uabal -generate uint16x8_t:uint8x16_t:uint8x16_t:uint16x8_t - -/// Unsigned Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:uint16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_shuffle!, e:uint16x4_t, c, c, [4, 5, 6, 7] -multi_fn = vabd_u16, d, e, f:uint16x4_t -multi_fn = simd_add, a, {simd_cast, f} -a = 9, 10, 11, 12 -b = 1, 2, 3, 4, 9, 10, 11, 12 -c = 10, 10, 10, 10, 20, 0, 2, 4 -validate 20, 20, 20, 20 - -aarch64 = uabal -generate uint32x4_t:uint16x8_t:uint16x8_t:uint32x4_t - -/// Unsigned Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:uint32x2_t, b, b, [2, 3] -multi_fn = simd_shuffle!, e:uint32x2_t, c, c, [2, 3] -multi_fn = vabd_u32, d, e, f:uint32x2_t -multi_fn = simd_add, a, {simd_cast, f} -a = 15, 16 -b = 1, 2, 15, 16 -c = 10, 10, 10, 12 -validate 20, 20 - -aarch64 = uabal -generate uint64x2_t:uint32x4_t:uint32x4_t:uint64x2_t - -//////////////////// -// Signed Absolute difference and Accumulate Long -//////////////////// - -/// Signed Absolute difference and Accumulate Long -name = vabal -multi_fn = vabd-signed-noext, b, c, d:int8x8_t -multi_fn = simd_cast, e:uint8x8_t, d -multi_fn = simd_add, a, {simd_cast, e} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20 - -arm = vabal.s -aarch64 = sabal -generate int16x8_t:int8x8_t:int8x8_t:int16x8_t - -/// Signed Absolute difference and Accumulate Long -name = vabal -multi_fn = vabd-signed-noext, b, c, d:int16x4_t -multi_fn = simd_cast, e:uint16x4_t, d -multi_fn = simd_add, a, {simd_cast, e} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20 - -arm = vabal.s -aarch64 = sabal -generate int32x4_t:int16x4_t:int16x4_t:int32x4_t - -/// Signed Absolute difference and Accumulate Long -name = vabal -multi_fn = vabd-signed-noext, b, c, d:int32x2_t -multi_fn = simd_cast, e:uint32x2_t, d -multi_fn = simd_add, a, {simd_cast, e} -a = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 10, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 20, 20, 20 - -arm = vabal.s -aarch64 = sabal -generate int64x2_t:int32x2_t:int32x2_t:int64x2_t - -/// Signed Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:int8x8_t, b, b, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = simd_shuffle!, e:int8x8_t, c, c, [8, 9, 10, 11, 12, 13, 14, 15] -multi_fn = vabd_s8, d, e, f:int8x8_t -multi_fn = simd_cast, f:uint8x8_t, f -multi_fn = simd_add, a, {simd_cast, f} -a = 9, 10, 11, 12, 13, 14, 15, 16 -b = 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16 -c = 10, 10, 10, 10, 10, 10, 10, 10, 20, 0, 2, 4, 6, 8, 10, 12 -validate 20, 20, 20, 20, 20, 20, 20, 20 - -aarch64 = sabal -generate int16x8_t:int8x16_t:int8x16_t:int16x8_t - -/// Signed Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:int16x4_t, b, b, [4, 5, 6, 7] -multi_fn = simd_shuffle!, e:int16x4_t, c, c, [4, 5, 6, 7] -multi_fn = vabd_s16, d, e, f:int16x4_t -multi_fn = simd_cast, f:uint16x4_t, f -multi_fn = simd_add, a, {simd_cast, f} -a = 9, 10, 11, 12 -b = 1, 2, 3, 4, 9, 10, 11, 12 -c = 10, 10, 10, 10, 20, 0, 2, 4 -validate 20, 20, 20, 20 - -aarch64 = sabal -generate int32x4_t:int16x8_t:int16x8_t:int32x4_t - -/// Signed Absolute difference and Accumulate Long -name = vabal_high -no-q -multi_fn = simd_shuffle!, d:int32x2_t, b, b, [2, 3] -multi_fn = simd_shuffle!, e:int32x2_t, c, c, [2, 3] -multi_fn = vabd_s32, d, e, f:int32x2_t -multi_fn = simd_cast, f:uint32x2_t, f -multi_fn = simd_add, a, {simd_cast, f} -a = 15, 16 -b = 1, 2, 15, 16 -c = 10, 10, 10, 12 -validate 20, 20 - -aarch64 = sabal -generate int64x2_t:int32x4_t:int32x4_t:int64x2_t - -//////////////////// -// Signed saturating Absolute value -//////////////////// - -/// Signed saturating Absolute value -name = vqabs -a = MIN, MAX, -6, -5, -4, -3, -2, -1, 0, -127, 127, 1, 2, 3, 4, 5 -validate MAX, MAX, 6, 5, 4, 3, 2, 1, 0, 127, 127, 1, 2, 3, 4, 5 - -arm = vqabs.s -aarch64 = sqabs -link-arm = vqabs._EXT_ -link-aarch64 = sqabs._EXT_ -generate int*_t - -/// Signed saturating Absolute value -name = vqabs -a = MIN, -7 -validate MAX, 7 - -aarch64 = sqabs -link-aarch64 = sqabs._EXT_ -generate int64x*_t - -/// Signed saturating absolute value -name = vqabs -multi_fn = simd_extract!, {vqabs-in_ntt-noext, {vdup_n-in_ntt-noext, a}}, 0 -a = -7 -validate 7 - -aarch64 = sqabs -generate i8:i8, i16:i16 - -/// Signed saturating absolute value -name = vqabs -a = -7 -validate 7 - -aarch64 = sqabs -link-aarch64 = sqabs._EXT_ -generate i32:i32, i64:i64 - -/// Shift left and insert -name = vsli -n-suffix -constn = N -multi_fn = static_assert-N-0-63 -multi_fn = transmute, {vsli_n-in_ntt-::, transmute(a), transmute(b)} -a = 333 -b = 2042 -n = 2 -validate 8169 - -aarch64 = sli -generate i64, u64 - -/// Shift right and insert -name = vsri -n-suffix -constn = N -multi_fn = static_assert-N-1-bits -multi_fn = transmute, {vsri_n-in_ntt-::, transmute(a), transmute(b)} -a = 333 -b = 2042 -n = 2 -validate 510 - -aarch64 = sri -generate i64, u64 diff --git a/crates/stdarch-gen-arm/src/main.rs b/crates/stdarch-gen-arm/src/main.rs deleted file mode 100644 index 1d2a0ce04e..0000000000 --- a/crates/stdarch-gen-arm/src/main.rs +++ /dev/null @@ -1,3499 +0,0 @@ -#![allow( - clippy::too_many_arguments, - clippy::type_complexity, - clippy::wrong_self_convention -)] - -use self::Suffix::*; -use self::TargetFeature::*; -use std::env; -use std::fmt::{self, Write as _}; -use std::fs::File; -use std::io::prelude::*; -use std::io::{self, BufReader}; -use std::path::PathBuf; - -const IN: &str = "neon.spec"; -const ARM_OUT: &str = "generated.rs"; -const AARCH64_OUT: &str = "generated.rs"; - -const UINT_TYPES: [&str; 6] = [ - "uint8x8_t", - "uint8x16_t", - "uint16x4_t", - "uint16x8_t", - "uint32x2_t", - "uint32x4_t", -]; - -const UINT_TYPES_64: [&str; 2] = ["uint64x1_t", "uint64x2_t"]; - -const INT_TYPES: [&str; 6] = [ - "int8x8_t", - "int8x16_t", - "int16x4_t", - "int16x8_t", - "int32x2_t", - "int32x4_t", -]; - -const INT_TYPES_64: [&str; 2] = ["int64x1_t", "int64x2_t"]; - -const FLOAT_TYPES: [&str; 2] = [ - //"float8x8_t", not supported by rust - //"float8x16_t", not supported by rust - //"float16x4_t", not supported by rust - //"float16x8_t", not supported by rust - "float32x2_t", - "float32x4_t", -]; - -const FLOAT_TYPES_64: [&str; 2] = [ - //"float8x8_t", not supported by rust - //"float8x16_t", not supported by rust - //"float16x4_t", not supported by rust - //"float16x8_t", not supported by rust - "float64x1_t", - "float64x2_t", -]; - -fn type_len(t: &str) -> usize { - let s: Vec<_> = t.split('x').collect(); - if s.len() == 2 { - match &s[1][0..2] { - "1_" => 1, - "2_" => 2, - "4_" => 4, - "8_" => 8, - "16" => 16, - _ => panic!("unknown type: {t}"), - } - } else if s.len() == 3 { - s[1].parse::().unwrap() * type_sub_len(t) - } else { - 1 - } -} - -fn type_sub_len(t: &str) -> usize { - let s: Vec<_> = t.split('x').collect(); - if s.len() != 3 { - 1 - } else { - match s[2] { - "2_t" => 2, - "3_t" => 3, - "4_t" => 4, - _ => panic!("unknown type len: {t}"), - } - } -} - -fn type_bits(t: &str) -> usize { - match t { - "int8x8_t" | "int8x16_t" | "uint8x8_t" | "uint8x16_t" | "poly8x8_t" | "poly8x16_t" - | "i8" | "u8" => 8, - "int16x4_t" | "int16x8_t" | "uint16x4_t" | "uint16x8_t" | "poly16x4_t" | "poly16x8_t" - | "i16" | "u16" => 16, - "int32x2_t" | "int32x4_t" | "uint32x2_t" | "uint32x4_t" | "i32" | "u32" | "float32x2_t" - | "float32x4_t" | "f32" => 32, - "int64x1_t" | "int64x2_t" | "uint64x1_t" | "uint64x2_t" | "poly64x1_t" | "poly64x2_t" - | "i64" | "u64" | "float64x1_t" | "float64x2_t" | "f64" => 64, - _ => panic!("unknown type: {t}"), - } -} - -fn type_exp_len(t: &str, base_len: usize) -> usize { - let t = type_to_sub_type(t); - let len = type_len(&t) / base_len; - match len { - 1 => 0, - 2 => 1, - 4 => 2, - 8 => 3, - 16 => 4, - _ => panic!("unknown type: {t}"), - } -} - -fn type_bits_exp_len(t: &str) -> usize { - match t { - "int8x8_t" | "int8x16_t" | "uint8x8_t" | "uint8x16_t" | "poly8x8_t" | "poly8x16_t" - | "i8" | "u8" => 3, - "int16x4_t" | "int16x8_t" | "uint16x4_t" | "uint16x8_t" | "poly16x4_t" | "poly16x8_t" - | "i16" | "u16" => 4, - "int32x2_t" | "int32x4_t" | "uint32x2_t" | "uint32x4_t" | "i32" | "u32" => 5, - "int64x1_t" | "int64x2_t" | "uint64x1_t" | "uint64x2_t" | "poly64x1_t" | "poly64x2_t" - | "i64" | "u64" => 6, - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_suffix(t: &str) -> &str { - match t { - "int8x8_t" => "_s8", - "int8x16_t" => "q_s8", - "int16x4_t" => "_s16", - "int16x8_t" => "q_s16", - "int32x2_t" => "_s32", - "int32x4_t" => "q_s32", - "int64x1_t" => "_s64", - "int64x2_t" => "q_s64", - "uint8x8_t" => "_u8", - "uint8x16_t" => "q_u8", - "uint16x4_t" => "_u16", - "uint16x8_t" => "q_u16", - "uint32x2_t" => "_u32", - "uint32x4_t" => "q_u32", - "uint64x1_t" => "_u64", - "uint64x2_t" => "q_u64", - "float16x4_t" => "_f16", - "float16x8_t" => "q_f16", - "float32x2_t" => "_f32", - "float32x4_t" => "q_f32", - "float64x1_t" => "_f64", - "float64x2_t" => "q_f64", - "poly8x8_t" => "_p8", - "poly8x16_t" => "q_p8", - "poly16x4_t" => "_p16", - "poly16x8_t" => "q_p16", - "poly64x1_t" => "_p64", - "poly64x2_t" => "q_p64", - "int8x8x2_t" => "_s8_x2", - "int8x8x3_t" => "_s8_x3", - "int8x8x4_t" => "_s8_x4", - "int16x4x2_t" => "_s16_x2", - "int16x4x3_t" => "_s16_x3", - "int16x4x4_t" => "_s16_x4", - "int32x2x2_t" => "_s32_x2", - "int32x2x3_t" => "_s32_x3", - "int32x2x4_t" => "_s32_x4", - "int64x1x2_t" => "_s64_x2", - "int64x1x3_t" => "_s64_x3", - "int64x1x4_t" => "_s64_x4", - "uint8x8x2_t" => "_u8_x2", - "uint8x8x3_t" => "_u8_x3", - "uint8x8x4_t" => "_u8_x4", - "uint16x4x2_t" => "_u16_x2", - "uint16x4x3_t" => "_u16_x3", - "uint16x4x4_t" => "_u16_x4", - "uint32x2x2_t" => "_u32_x2", - "uint32x2x3_t" => "_u32_x3", - "uint32x2x4_t" => "_u32_x4", - "uint64x1x2_t" => "_u64_x2", - "uint64x1x3_t" => "_u64_x3", - "uint64x1x4_t" => "_u64_x4", - "poly8x8x2_t" => "_p8_x2", - "poly8x8x3_t" => "_p8_x3", - "poly8x8x4_t" => "_p8_x4", - "poly16x4x2_t" => "_p16_x2", - "poly16x4x3_t" => "_p16_x3", - "poly16x4x4_t" => "_p16_x4", - "poly64x1x2_t" => "_p64_x2", - "poly64x1x3_t" => "_p64_x3", - "poly64x1x4_t" => "_p64_x4", - "float32x2x2_t" => "_f32_x2", - "float32x2x3_t" => "_f32_x3", - "float32x2x4_t" => "_f32_x4", - "float64x1x2_t" => "_f64_x2", - "float64x1x3_t" => "_f64_x3", - "float64x1x4_t" => "_f64_x4", - "int8x16x2_t" => "q_s8_x2", - "int8x16x3_t" => "q_s8_x3", - "int8x16x4_t" => "q_s8_x4", - "int16x8x2_t" => "q_s16_x2", - "int16x8x3_t" => "q_s16_x3", - "int16x8x4_t" => "q_s16_x4", - "int32x4x2_t" => "q_s32_x2", - "int32x4x3_t" => "q_s32_x3", - "int32x4x4_t" => "q_s32_x4", - "int64x2x2_t" => "q_s64_x2", - "int64x2x3_t" => "q_s64_x3", - "int64x2x4_t" => "q_s64_x4", - "uint8x16x2_t" => "q_u8_x2", - "uint8x16x3_t" => "q_u8_x3", - "uint8x16x4_t" => "q_u8_x4", - "uint16x8x2_t" => "q_u16_x2", - "uint16x8x3_t" => "q_u16_x3", - "uint16x8x4_t" => "q_u16_x4", - "uint32x4x2_t" => "q_u32_x2", - "uint32x4x3_t" => "q_u32_x3", - "uint32x4x4_t" => "q_u32_x4", - "uint64x2x2_t" => "q_u64_x2", - "uint64x2x3_t" => "q_u64_x3", - "uint64x2x4_t" => "q_u64_x4", - "poly8x16x2_t" => "q_p8_x2", - "poly8x16x3_t" => "q_p8_x3", - "poly8x16x4_t" => "q_p8_x4", - "poly16x8x2_t" => "q_p16_x2", - "poly16x8x3_t" => "q_p16_x3", - "poly16x8x4_t" => "q_p16_x4", - "poly64x2x2_t" => "q_p64_x2", - "poly64x2x3_t" => "q_p64_x3", - "poly64x2x4_t" => "q_p64_x4", - "float32x4x2_t" => "q_f32_x2", - "float32x4x3_t" => "q_f32_x3", - "float32x4x4_t" => "q_f32_x4", - "float64x2x2_t" => "q_f64_x2", - "float64x2x3_t" => "q_f64_x3", - "float64x2x4_t" => "q_f64_x4", - "i8" => "b_s8", - "i16" => "h_s16", - "i32" => "s_s32", - "i64" => "d_s64", - "u8" => "b_u8", - "u16" => "h_u16", - "u32" => "s_u32", - "u64" => "d_u64", - "f32" => "s_f32", - "f64" => "d_f64", - "p8" => "b_p8", - "p16" => "h_p16", - "p128" => "q_p128", - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_dup_suffix(t: &str) -> String { - let s: Vec<_> = type_to_suffix(t).split('_').collect(); - assert_eq!(s.len(), 2); - format!("{}_dup_{}", s[0], s[1]) -} - -fn type_to_lane_suffix(t: &str) -> String { - let s: Vec<_> = type_to_suffix(t).split('_').collect(); - assert_eq!(s.len(), 2); - format!("{}_lane_{}", s[0], s[1]) -} - -fn type_to_n_suffix(t: &str) -> &str { - match t { - "int8x8_t" => "_n_s8", - "int8x16_t" => "q_n_s8", - "int16x4_t" => "_n_s16", - "int16x8_t" => "q_n_s16", - "int32x2_t" => "_n_s32", - "int32x4_t" => "q_n_s32", - "int64x1_t" => "_n_s64", - "int64x2_t" => "q_n_s64", - "uint8x8_t" => "_n_u8", - "uint8x16_t" => "q_n_u8", - "uint16x4_t" => "_n_u16", - "uint16x8_t" => "q_n_u16", - "uint32x2_t" => "_n_u32", - "uint32x4_t" => "q_n_u32", - "uint64x1_t" => "_n_u64", - "uint64x2_t" => "q_n_u64", - "float16x4_t" => "_n_f16", - "float16x8_t" => "q_n_f16", - "float32x2_t" => "_n_f32", - "float32x4_t" => "q_n_f32", - "float64x1_t" => "_n_f64", - "float64x2_t" => "q_n_f64", - "poly8x8_t" => "_n_p8", - "poly8x16_t" => "q_n_p8", - "poly16x4_t" => "_n_p16", - "poly16x8_t" => "q_n_p16", - "poly64x1_t" => "_n_p64", - "poly64x2_t" => "q_n_p64", - "i8" => "b_n_s8", - "i16" => "h_n_s16", - "i32" => "s_n_s32", - "i64" => "d_n_s64", - "u8" => "b_n_u8", - "u16" => "h_n_u16", - "u32" => "s_n_u32", - "u64" => "d_n_u64", - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_noq_n_suffix(t: &str) -> &str { - match t { - "int8x8_t" | "int8x16_t" => "_n_s8", - "int16x4_t" | "int16x8_t" => "_n_s16", - "int32x2_t" | "int32x4_t" => "_n_s32", - "int64x1_t" | "int64x2_t" => "_n_s64", - "uint8x8_t" | "uint8x16_t" => "_n_u8", - "uint16x4_t" | "uint16x8_t" => "_n_u16", - "uint32x2_t" | "uint32x4_t" => "_n_u32", - "uint64x1_t" | "uint64x2_t" => "_n_u64", - "float16x4_t" | "float16x8_t" => "_n_f16", - "float32x2_t" | "float32x4_t" => "_n_f32", - "float64x1_t" | "float64x2_t" => "_n_f64", - "poly8x8_t" | "poly8x16_t" => "_n_p8", - "poly16x4_t" | "poly16x8_t" => "_n_p16", - "poly64x1_t" | "poly64x2_t" => "_n_p64", - "i8" => "b_n_s8", - "i16" => "h_n_s16", - "i32" => "s_n_s32", - "i64" => "d_n_s64", - "u8" => "b_n_u8", - "u16" => "h_n_u16", - "u32" => "s_n_u32", - "u64" => "d_n_u64", - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_lane_suffixes<'a>(out_t: &'a str, in_t: &'a str, re_to_out: bool) -> String { - let mut str = String::new(); - let suf = type_to_suffix(out_t); - if !suf.starts_with('_') { - str.push_str(&suf[0..1]); - } - str.push_str("_lane"); - if !re_to_out { - str.push_str(type_to_suffix(in_t)); - } else { - if type_to_suffix(in_t).starts_with('q') { - str.push('q'); - }; - let suf2 = type_to_noq_suffix(out_t); - str.push_str(suf2); - } - str -} - -fn type_to_rot_suffix(c_name: &str, suf: &str) -> String { - let ns: Vec<_> = c_name.split('_').collect(); - assert_eq!(ns.len(), 2); - if let Some(suf) = suf.strip_prefix('q') { - format!("{}q_{}{}", ns[0], ns[1], suf) - } else { - format!("{c_name}{suf}") - } -} - -fn type_to_signed(t: &str) -> String { - t.replace("uint", "int").replace("poly", "int") -} - -fn type_to_unsigned(t: &str) -> String { - if t.contains("uint") { - return t.to_string(); - } - t.replace("int", "uint").replace("poly", "uint") -} - -fn type_to_double_suffixes<'a>(out_t: &'a str, in_t: &'a str) -> String { - let mut str = String::new(); - let suf = type_to_suffix(in_t); - if suf.starts_with('q') && type_to_suffix(out_t).starts_with('q') { - str.push('q'); - } - if !suf.starts_with('_') && !suf.starts_with('q') { - str.push_str(&suf[0..1]); - } - str.push_str(type_to_noq_suffix(out_t)); - str.push_str(type_to_noq_suffix(in_t)); - str -} - -fn type_to_double_n_suffixes<'a>(out_t: &'a str, in_t: &'a str) -> String { - let mut str = String::new(); - let suf = type_to_suffix(in_t); - if suf.starts_with('q') && type_to_suffix(out_t).starts_with('q') { - str.push('q'); - } - if !suf.starts_with('_') && !suf.starts_with('q') { - str.push_str(&suf[0..1]); - } - str.push_str("_n"); - str.push_str(type_to_noq_suffix(out_t)); - str.push_str(type_to_noq_suffix(in_t)); - str -} - -fn type_to_noq_double_suffixes<'a>(out_t: &'a str, in_t: &'a str) -> String { - let mut str = String::new(); - str.push_str(type_to_noq_suffix(out_t)); - str.push_str(type_to_noq_suffix(in_t)); - str -} - -fn type_to_noq_suffix(t: &str) -> &str { - match t { - "int8x8_t" | "int8x16_t" | "i8" => "_s8", - "int16x4_t" | "int16x8_t" | "i16" => "_s16", - "int32x2_t" | "int32x4_t" | "i32" => "_s32", - "int64x1_t" | "int64x2_t" | "i64" => "_s64", - "uint8x8_t" | "uint8x16_t" | "u8" => "_u8", - "uint16x4_t" | "uint16x8_t" | "u16" => "_u16", - "uint32x2_t" | "uint32x4_t" | "u32" => "_u32", - "uint64x1_t" | "uint64x2_t" | "u64" => "_u64", - "float16x4_t" | "float16x8_t" => "_f16", - "float32x2_t" | "float32x4_t" | "f32" => "_f32", - "float64x1_t" | "float64x2_t" | "f64" => "_f64", - "poly8x8_t" | "poly8x16_t" => "_p8", - "poly16x4_t" | "poly16x8_t" => "_p16", - "poly64x1_t" | "poly64x2_t" | "p64" => "_p64", - "p128" => "_p128", - _ => panic!("unknown type: {t}"), - } -} - -#[allow(clippy::enum_variant_names)] -#[derive(Clone, Copy)] -enum Suffix { - Normal, - Double, - NoQ, - NoQDouble, - NSuffix, - DoubleN, - NoQNSuffix, - OutSuffix, - OutNSuffix, - OutNox, - In1Nox, - OutDupNox, - OutLaneNox, - In1LaneNox, - Lane, - In2, - In2Lane, - OutLane, - Rot, - RotLane, -} - -#[derive(Clone, Copy)] -enum TargetFeature { - Default, - ArmV7, - Vfp4, - FPArmV8, - Aes, - Fcma, - Dotprod, - I8MM, - Sha3, - Rdm, - Sm4, - Ftts, -} - -impl TargetFeature { - /// A string for use with `#[target_feature(...)]`. - fn as_target_feature_arg_aarch64(&self) -> &str { - match *self { - // Features included with AArch64 NEON. - Self::Default => "neon", - Self::ArmV7 => "neon", - Self::Vfp4 => "neon", - Self::FPArmV8 => "neon", - // Optional features. - Self::Aes => "neon,aes", - Self::Fcma => "neon,fcma", - Self::Dotprod => "neon,dotprod", - Self::I8MM => "neon,i8mm", - Self::Sha3 => "neon,sha3", - Self::Rdm => "rdm", - Self::Sm4 => "neon,sm4", - Self::Ftts => "neon,frintts", - } - } - - /// A string for use with #[simd_test(...)] (or `is_aarch64_feature_detected!(...)`). - fn as_simd_test_arg_aarch64(&self) -> &str { - self.as_target_feature_arg_aarch64() - } - - /// A string for use with `#[target_feature(...)]`. - fn as_target_feature_arg_arm(&self) -> &str { - match *self { - Self::Default => "neon,v7", - Self::ArmV7 => "neon,v7", - Self::Vfp4 => "neon,vfp4", - Self::FPArmV8 => "neon,fp-armv8,v8", - Self::Aes => "neon,v8,aes", - Self::Fcma => "neon,v8,fcma", - Self::Dotprod => "neon,v8,dotprod", - Self::I8MM => "neon,v8,i8mm", - // Features not supported on 32-bit "arm". - Self::Sha3 => unimplemented!(), - Self::Rdm => unimplemented!(), - Self::Sm4 => unimplemented!(), - Self::Ftts => unimplemented!(), - } - } - - /// A stability attribute for the intrinsic. - fn stability(&self, aarch64: bool) -> &str { - // 32-bit intrinsics are all unstable for now - if !aarch64 { - return "unstable(feature = \"stdarch_arm_neon_intrinsics\", issue = \"111800\")"; - } - match *self { - Default | ArmV7 | Vfp4 | FPArmV8 | Aes => { - "stable(feature = \"neon_intrinsics\", since = \"1.59.0\")" - } - Fcma => "unstable(feature = \"stdarch_neon_fcma\", issue = \"117222\")", - Dotprod => "unstable(feature = \"stdarch_neon_dotprod\", issue = \"117224\")", - I8MM => "unstable(feature = \"stdarch_neon_i8mm\", issue = \"117223\")", - Sha3 => "stable(feature = \"stdarch_neon_sha3\", since = \"1.79.0\")", - Rdm => "stable(feature = \"rdm_intrinsics\", since = \"1.62.0\")", - Sm4 => "unstable(feature = \"stdarch_neon_sm4\", issue = \"117226\")", - Ftts => "unstable(feature = \"stdarch_neon_ftts\", issue = \"117227\")", - } - } - - /// A string for use with #[simd_test(...)] (or `is_arm_feature_detected!(...)`). - fn as_simd_test_arg_arm(&self) -> &str { - // TODO: Ideally, these would match the target_feature strings (as for AArch64). - match *self { - // We typically specify the "v7" or "v8" target_features for codegen, but we can't test - // them at runtime. However, in many cases we can test a specific named feature, and - // this is sufficient. For example, Neon always requires at least Armv7. - - // "v7" extensions. - Self::Default => "neon", - Self::ArmV7 => "neon", - - // TODO: We can specify these features for code generation, but they have no runtime - // detection, so we can't provide an accurate string for simd_test. For now, we use a - // common Armv8 feature as a proxy, but we should improve std_detect support here and - // update these accordingly. - Self::Vfp4 => "neon,crc", - Self::FPArmV8 => "neon,crc", - - // "v8" extensions. - Self::Aes => "neon,aes", - Self::Fcma => "neon,fcma", - Self::Dotprod => "neon,dotprod", - Self::I8MM => "neon,i8mm", - - // Features not supported on 32-bit "arm". - Self::Sha3 => unimplemented!(), - Self::Rdm => unimplemented!(), - Self::Sm4 => unimplemented!(), - Self::Ftts => unimplemented!(), - } - } - - fn attr(name: &str, value: impl fmt::Display) -> String { - format!(r#"#[{name}(enable = "{value}")]"#) - } - - fn attr_for_arch(arch: &str, name: &str, value: impl fmt::Display) -> String { - format!(r#"#[cfg_attr(target_arch = "{arch}", {name}(enable = "{value}"))]"#) - } - - /// Generate target_feature attributes for a test that will compile for "arm", "aarch64" and "arm64ec". - fn to_target_feature_attr_shared(&self) -> Lines { - let arm = self.as_target_feature_arg_arm().split(','); - let aarch64 = self.as_target_feature_arg_aarch64().split(','); - - // Combine common features into an unconditional `target_feature` annotation, but guard - // others behind `cfg_attr`. - // TODO: It's much simpler to emit separate, guarded attributes for each architecture (as - // for `simd_test`). However, this has an unfortunate impact on documentation, since - // rustdoc can't currently look inside `cfg_attr` (stdarch/issues/1268). - let mut aarch64: Vec<_> = aarch64.collect(); - let (both, arm): (Vec<_>, Vec<_>) = arm.partition(|v| aarch64.contains(v)); - aarch64.retain(|v| !both.contains(v)); - let mut lines = Vec::new(); - if !both.is_empty() { - lines.push(Self::attr("target_feature", both.join(","))); - }; - if !arm.is_empty() { - lines.push(Self::attr_for_arch("arm", "target_feature", arm.join(","))); - } - if !aarch64.is_empty() { - lines.push(Self::attr_for_arch( - "aarch64", - "target_feature", - aarch64.join(","), - )); - lines.push(Self::attr_for_arch( - "arm64ec", - "target_feature", - aarch64.join(","), - )); - } - lines.into() - } - - /// Generate a target_feature attribute for a test that will compile only for "aarch64" and "arm64ec". - fn to_target_feature_attr_aarch64(&self) -> Lines { - Lines::single(Self::attr( - "target_feature", - self.as_target_feature_arg_aarch64(), - )) - } - - /// Generate a target_feature attribute for a test that will compile only for "arm". - fn to_target_feature_attr_arm(&self) -> Lines { - Lines::single(Self::attr( - "target_feature", - self.as_target_feature_arg_arm(), - )) - } - - /// Generate simd_test attributes for a test that will compile for "arm", "aarch64" and "arm64ec". - fn to_simd_test_attr_shared(&self) -> Lines { - let arm = self.as_simd_test_arg_arm(); - let aarch64 = self.as_simd_test_arg_aarch64(); - if arm == aarch64 { - Lines::single(Self::attr("simd_test", arm)) - } else { - vec![ - Self::attr_for_arch("arm", "simd_test", arm), - Self::attr_for_arch("aarch64", "simd_test", aarch64), - Self::attr_for_arch("arm64ec", "simd_test", aarch64), - ] - .into() - } - } - - /// Generate a simd_test attribute for a test that will compile only for "aarch64" and "arm64ec". - fn to_simd_test_attr_aarch64(&self) -> Lines { - Lines::single(Self::attr("simd_test", self.as_simd_test_arg_aarch64())) - } -} - -/// Complete lines of generated source. -/// -/// This enables common generation tasks to be factored out without precluding basic -/// context-specific formatting. -/// -/// The convention in this generator is to prefix (not suffix) lines with a newline, so the -/// implementation of `std::fmt::Display` behaves in the same way. -struct Lines { - indent: usize, - lines: Vec, -} - -impl Lines { - fn indented(self, indent: usize) -> Self { - Self { - indent: indent + self.indent, - ..self - } - } - - fn single(line: String) -> Self { - Self::from(vec![line]) - } -} - -impl From> for Lines { - fn from(lines: Vec) -> Self { - Self { indent: 0, lines } - } -} - -impl fmt::Display for Lines { - fn fmt(&self, f: &mut fmt::Formatter<'_>) -> fmt::Result { - for line in self.lines.iter() { - write!(f, "\n{:width$}{line}", "", width = self.indent)?; - } - Ok(()) - } -} - -#[derive(Clone, Copy)] -enum Fntype { - Normal, - Load, - Store, -} - -fn type_to_global_type(t: &str) -> &str { - match t { - "int8x8_t" | "int8x8x2_t" | "int8x8x3_t" | "int8x8x4_t" => "i8x8", - "int8x16_t" | "int8x16x2_t" | "int8x16x3_t" | "int8x16x4_t" => "i8x16", - "int16x4_t" | "int16x4x2_t" | "int16x4x3_t" | "int16x4x4_t" => "i16x4", - "int16x8_t" | "int16x8x2_t" | "int16x8x3_t" | "int16x8x4_t" => "i16x8", - "int32x2_t" | "int32x2x2_t" | "int32x2x3_t" | "int32x2x4_t" => "i32x2", - "int32x4_t" | "int32x4x2_t" | "int32x4x3_t" | "int32x4x4_t" => "i32x4", - "int64x1_t" | "int64x1x2_t" | "int64x1x3_t" | "int64x1x4_t" => "i64x1", - "int64x2_t" | "int64x2x2_t" | "int64x2x3_t" | "int64x2x4_t" => "i64x2", - "uint8x8_t" | "uint8x8x2_t" | "uint8x8x3_t" | "uint8x8x4_t" => "u8x8", - "uint8x16_t" | "uint8x16x2_t" | "uint8x16x3_t" | "uint8x16x4_t" => "u8x16", - "uint16x4_t" | "uint16x4x2_t" | "uint16x4x3_t" | "uint16x4x4_t" => "u16x4", - "uint16x8_t" | "uint16x8x2_t" | "uint16x8x3_t" | "uint16x8x4_t" => "u16x8", - "uint32x2_t" | "uint32x2x2_t" | "uint32x2x3_t" | "uint32x2x4_t" => "u32x2", - "uint32x4_t" | "uint32x4x2_t" | "uint32x4x3_t" | "uint32x4x4_t" => "u32x4", - "uint64x1_t" | "uint64x1x2_t" | "uint64x1x3_t" | "uint64x1x4_t" => "u64x1", - "uint64x2_t" | "uint64x2x2_t" | "uint64x2x3_t" | "uint64x2x4_t" => "u64x2", - "float16x4_t" => "f16x4", - "float16x8_t" => "f16x8", - "float32x2_t" | "float32x2x2_t" | "float32x2x3_t" | "float32x2x4_t" => "f32x2", - "float32x4_t" | "float32x4x2_t" | "float32x4x3_t" | "float32x4x4_t" => "f32x4", - "float64x1_t" | "float64x1x2_t" | "float64x1x3_t" | "float64x1x4_t" => "f64", - "float64x2_t" | "float64x2x2_t" | "float64x2x3_t" | "float64x2x4_t" => "f64x2", - "poly8x8_t" | "poly8x8x2_t" | "poly8x8x3_t" | "poly8x8x4_t" => "i8x8", - "poly8x16_t" | "poly8x16x2_t" | "poly8x16x3_t" | "poly8x16x4_t" => "i8x16", - "poly16x4_t" | "poly16x4x2_t" | "poly16x4x3_t" | "poly16x4x4_t" => "i16x4", - "poly16x8_t" | "poly16x8x2_t" | "poly16x8x3_t" | "poly16x8x4_t" => "i16x8", - "poly64x1_t" | "poly64x1x2_t" | "poly64x1x3_t" | "poly64x1x4_t" => "i64x1", - "poly64x2_t" | "poly64x2x2_t" | "poly64x2x3_t" | "poly64x2x4_t" => "i64x2", - "i8" => "i8", - "i16" => "i16", - "i32" => "i32", - "i64" => "i64", - "u8" => "u8", - "u16" => "u16", - "u32" => "u32", - "u64" => "u64", - "f32" => "f32", - "f64" => "f64", - "p8" => "p8", - "p16" => "p16", - "p64" => "p64", - "p128" => "p128", - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_sub_type(t: &str) -> String { - let s: Vec<_> = t.split('x').collect(); - match s.len() { - 2 => String::from(t), - 3 => format!("{}x{}_t", s[0], s[1]), - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_native_type(t: &str) -> String { - let s: Vec<_> = t.split('x').collect(); - match s.len() { - 1 => { - assert!(t.contains("*const") || t.contains("*mut")); - let sub: Vec<_> = t.split(' ').collect(); - String::from(sub[1]) - } - 2 | 3 => match &s[0][0..3] { - "int" => format!("i{}", &s[0][3..]), - "uin" => format!("u{}", &s[0][4..]), - "flo" => format!("f{}", &s[0][5..]), - "pol" => format!("u{}", &s[0][4..]), - _ => panic!("unknown type: {t}"), - }, - _ => panic!("unknown type: {t}"), - } -} - -fn native_type_to_type(t: &str) -> &str { - match t { - "i8" => "int8x8_t", - "i16" => "int16x4_t", - "i32" => "int32x2_t", - "i64" => "int64x1_t", - "u8" => "uint8x8_t", - "u16" => "uint16x4_t", - "u32" => "uint32x2_t", - "u64" => "uint64x1_t", - "f16" => "float16x4_t", - "f32" => "float32x2_t", - "f64" => "float64x1_t", - _ => panic!("unknown type: {t}"), - } -} - -fn native_type_to_long_type(t: &str) -> &str { - match t { - "i8" => "int8x16_t", - "i16" => "int16x8_t", - "i32" => "int32x4_t", - "i64" => "int64x2_t", - "u8" => "uint8x16_t", - "u16" => "uint16x8_t", - "u32" => "uint32x4_t", - "u64" => "uint64x2_t", - "f16" => "float16x8_t", - "f32" => "float32x4_t", - "f64" => "float64x2_t", - _ => panic!("unknown type: {t}"), - } -} - -fn type_to_half(t: &str) -> &str { - match t { - "int8x16_t" => "int8x8_t", - "int16x8_t" => "int16x4_t", - "int32x4_t" => "int32x2_t", - "int64x2_t" => "int64x1_t", - "uint8x16_t" => "uint8x8_t", - "uint16x8_t" => "uint16x4_t", - "uint32x4_t" => "uint32x2_t", - "uint64x2_t" => "uint64x1_t", - "poly8x16_t" => "poly8x8_t", - "poly16x8_t" => "poly16x4_t", - "float32x4_t" => "float32x2_t", - "float64x2_t" => "float64x1_t", - _ => panic!("unknown half type for {t}"), - } -} - -fn type_with_merged_lanes(t: &str, elements_per_lane: usize) -> String { - assert_eq!(type_len(t) % elements_per_lane, 0); - let prefix_len = t.find(|c: char| c.is_ascii_digit()).unwrap_or(t.len()); - format!( - "{prefix}{bits}x{len}_t", - prefix = &t[0..prefix_len], - bits = type_bits(t) * elements_per_lane, - len = type_len(t) / elements_per_lane - ) -} - -fn asc(start: i32, len: usize) -> String { - let mut s = String::from("["); - for i in 0..len { - if i != 0 { - s.push_str(", "); - } - let n = start + i as i32; - s.push_str(&n.to_string()); - } - s.push(']'); - s -} - -fn transpose1(x: usize) -> &'static str { - match x { - 2 => "[0, 2]", - 4 => "[0, 4, 2, 6]", - 8 => "[0, 8, 2, 10, 4, 12, 6, 14]", - 16 => "[0, 16, 2, 18, 4, 20, 6, 22, 8, 24, 10, 26, 12, 28, 14, 30]", - _ => panic!("unknown transpose order of len {x}"), - } -} - -fn transpose2(x: usize) -> &'static str { - match x { - 2 => "[1, 3]", - 4 => "[1, 5, 3, 7]", - 8 => "[1, 9, 3, 11, 5, 13, 7, 15]", - 16 => "[1, 17, 3, 19, 5, 21, 7, 23, 9, 25, 11, 27, 13, 29, 15, 31]", - _ => panic!("unknown transpose order of len {x}"), - } -} - -fn zip1(x: usize) -> &'static str { - match x { - 2 => "[0, 2]", - 4 => "[0, 4, 1, 5]", - 8 => "[0, 8, 1, 9, 2, 10, 3, 11]", - 16 => "[0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23]", - _ => panic!("unknown zip order of len {x}"), - } -} - -fn zip2(x: usize) -> &'static str { - match x { - 2 => "[1, 3]", - 4 => "[2, 6, 3, 7]", - 8 => "[4, 12, 5, 13, 6, 14, 7, 15]", - 16 => "[8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31]", - _ => panic!("unknown zip order of len {x}"), - } -} - -fn unzip1(x: usize) -> &'static str { - match x { - 2 => "[0, 2]", - 4 => "[0, 2, 4, 6]", - 8 => "[0, 2, 4, 6, 8, 10, 12, 14]", - 16 => "[0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30]", - _ => panic!("unknown unzip order of len {x}"), - } -} - -fn unzip2(x: usize) -> &'static str { - match x { - 2 => "[1, 3]", - 4 => "[1, 3, 5, 7]", - 8 => "[1, 3, 5, 7, 9, 11, 13, 15]", - 16 => "[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]", - _ => panic!("unknown unzip order of len {x}"), - } -} - -fn values(t: &str, vs: &[String]) -> String { - if vs.len() == 1 && !t.contains('x') { - format!(": {t} = {}", vs[0]) - } else if vs.len() == 1 && type_to_global_type(t) == "f64" { - format!(": {} = {}", type_to_global_type(t), vs[0]) - } else { - let s: Vec<_> = t.split('x').collect(); - if s.len() == 3 { - format!( - ": [{}; {}] = [{}]", - type_to_native_type(t), - type_len(t), - vs.iter() - .map(|v| map_val(type_to_global_type(t), v)) - //.map(|v| format!("{}{}", v, type_to_native_type(t))) - .collect::>() - .join(", ") - ) - } else { - format!( - ": {} = {}::new({})", - type_to_global_type(t), - type_to_global_type(t), - vs.iter() - .map(|v| map_val(type_to_global_type(t), v)) - //.map(|v| format!("{}{}", v, type_to_native_type(t))) - .collect::>() - .join(", ") - ) - } - } -} - -fn max_val(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "0xFF", - "u16" => "0xFF_FF", - "u32" => "0xFF_FF_FF_FF", - "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF", - "i8x" => "0x7F", - "i16" => "0x7F_FF", - "i32" => "0x7F_FF_FF_FF", - "i64" => "0x7F_FF_FF_FF_FF_FF_FF_FF", - "f32" => "3.40282347e+38", - "f64" => "1.7976931348623157e+308", - _ => panic!("No TRUE for type {t}"), - } -} - -fn min_val(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "0", - "u16" => "0", - "u32" => "0", - "u64" => "0", - "i8x" => "-128", - "i16" => "-32768", - "i32" => "-2147483648", - "i64" => "-9223372036854775808", - "f32" => "-3.40282347e+38", - "f64" => "-1.7976931348623157e+308", - _ => panic!("No TRUE for type {t}"), - } -} - -fn true_val(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "0xFF", - "u16" => "0xFF_FF", - "u32" => "0xFF_FF_FF_FF", - "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF", - _ => panic!("No TRUE for type {t}"), - } -} - -fn ff_val(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "0xFF", - "u16" => "0xFF_FF", - "u32" => "0xFF_FF_FF_FF", - "u64" => "0xFF_FF_FF_FF_FF_FF_FF_FF", - "i8x" => "0xFF", - "i16" => "0xFF_FF", - "i32" => "0xFF_FF_FF_FF", - "i64" => "0xFF_FF_FF_FF_FF_FF_FF_FF", - _ => panic!("No TRUE for type {t}"), - } -} - -fn false_val(_t: &str) -> &'static str { - "0" -} - -fn bits(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "8", - "u16" => "16", - "u32" => "32", - "u64" => "64", - "i8x" => "8", - "i16" => "16", - "i32" => "32", - "i64" => "64", - "p8x" => "8", - "p16" => "16", - "p64" => "64", - _ => panic!("Unknown bits for type {t}"), - } -} - -fn bits_minus_one(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "7", - "u16" => "15", - "u32" => "31", - "u64" => "63", - "i8x" => "7", - "i16" => "15", - "i32" => "31", - "i64" => "63", - "p8x" => "7", - "p16" => "15", - "p64" => "63", - _ => panic!("Unknown bits for type {t}"), - } -} - -fn half_bits(t: &str) -> &'static str { - match &t[..3] { - "u8x" => "4", - "u16" => "8", - "u32" => "16", - "u64" => "32", - "i8x" => "4", - "i16" => "8", - "i32" => "16", - "i64" => "32", - "p8x" => "4", - "p16" => "8", - "p64" => "32", - _ => panic!("Unknown bits for type {t}"), - } -} - -fn type_len_str(t: &str) -> &'static str { - match t { - "int8x8_t" => "8", - "int8x16_t" => "16", - "int16x4_t" => "4", - "int16x8_t" => "8", - "int32x2_t" => "2", - "int32x4_t" => "4", - "int64x1_t" => "1", - "int64x2_t" => "2", - "uint8x8_t" => "8", - "uint8x16_t" => "16", - "uint16x4_t" => "4", - "uint16x8_t" => "8", - "uint32x2_t" => "2", - "uint32x4_t" => "4", - "uint64x1_t" => "1", - "uint64x2_t" => "2", - "float16x4_t" => "4", - "float16x8_t" => "8", - "float32x2_t" => "2", - "float32x4_t" => "4", - "float64x1_t" => "1", - "float64x2_t" => "2", - "poly8x8_t" => "8", - "poly8x16_t" => "16", - "poly16x4_t" => "4", - "poly16x8_t" => "8", - "poly64x1_t" => "1", - "poly64x2_t" => "2", - _ => panic!("unknown type: {t}"), - } -} - -fn type_len_minus_one_str(t: &str) -> &'static str { - match t { - "int8x8_t" => "7", - "int8x16_t" => "15", - "int16x4_t" => "3", - "int16x8_t" => "7", - "int32x2_t" => "1", - "int32x4_t" => "3", - "int64x1_t" => "0", - "int64x2_t" => "1", - "uint8x8_t" => "7", - "uint8x16_t" => "15", - "uint16x4_t" => "3", - "uint16x8_t" => "7", - "uint32x2_t" => "1", - "uint32x4_t" => "3", - "uint64x1_t" => "0", - "uint64x2_t" => "1", - "float16x4_t" => "3", - "float16x8_t" => "7", - "float32x2_t" => "1", - "float32x4_t" => "3", - "float64x1_t" => "0", - "float64x2_t" => "1", - "poly8x8_t" => "7", - "poly8x16_t" => "15", - "poly16x4_t" => "3", - "poly16x8_t" => "7", - "poly64x1_t" => "0", - "poly64x2_t" => "1", - _ => panic!("unknown type: {t}"), - } -} - -fn type_half_len_str(t: &str) -> &'static str { - match t { - "int8x8_t" => "4", - "int8x16_t" => "8", - "int16x4_t" => "2", - "int16x8_t" => "4", - "int32x2_t" => "1", - "int32x4_t" => "2", - "int64x1_t" => "0", - "int64x2_t" => "1", - "uint8x8_t" => "4", - "uint8x16_t" => "8", - "uint16x4_t" => "2", - "uint16x8_t" => "4", - "uint32x2_t" => "1", - "uint32x4_t" => "2", - "uint64x1_t" => "0", - "uint64x2_t" => "1", - "float16x4_t" => "2", - "float16x8_t" => "4", - "float32x2_t" => "1", - "float32x4_t" => "2", - "float64x1_t" => "0", - "float64x2_t" => "1", - "poly8x8_t" => "4", - "poly8x16_t" => "8", - "poly16x4_t" => "2", - "poly16x8_t" => "4", - "poly64x1_t" => "0", - "poly64x2_t" => "1", - _ => panic!("unknown type: {t}"), - } -} - -fn map_val<'v>(t: &str, v: &'v str) -> &'v str { - match v { - "FALSE" => false_val(t), - "TRUE" => true_val(t), - "MAX" => max_val(t), - "MIN" => min_val(t), - "FF" => ff_val(t), - "BITS" => bits(t), - "BITS_M1" => bits_minus_one(t), - "HFBITS" => half_bits(t), - "LEN" => type_len_str(t), - "LEN_M1" => type_len_minus_one_str(t), - "HFLEN" => type_half_len_str(t), - o => o, - } -} - -fn type_to_ext(t: &str, v: bool, r: bool, pi8: bool) -> String { - if !t.contains('x') { - return t.replace('u', "i"); - } - let native = type_to_native_type(t); - let sub_ext = match type_sub_len(t) { - 1 => String::new(), - _ if v => format!(".p0v{}{native}", type_len(&type_to_sub_type(t))), - _ if pi8 => ".p0i8".to_string(), - _ => format!(".p0{native}"), - }; - let sub_type = match &native[0..1] { - "i" | "f" => native, - "u" => native.replace('u', "i"), - _ => panic!("unknown type: {t}"), - }; - let ext = format!("v{}{sub_type}{sub_ext}", type_len(&type_to_sub_type(t))); - if r { - let ss: Vec<_> = ext.split('.').collect(); - if ss.len() != 2 { - ext - } else { - format!("{}.{}", ss[1], ss[0]) - } - } else { - ext - } -} - -fn ext(s: &str, in_t: &[&str; 3], out_t: &str) -> String { - s.replace("_EXT_", &type_to_ext(in_t[0], false, false, false)) - .replace("_EXT2_", &type_to_ext(out_t, false, false, false)) - .replace("_EXT3_", &type_to_ext(in_t[1], false, false, false)) - .replace("_EXT4_", &type_to_ext(in_t[2], false, false, false)) - .replace("_EXTr3_", &type_to_ext(in_t[1], false, true, false)) - .replace("_EXTv2_", &type_to_ext(out_t, true, false, false)) - .replace("_EXTpi8_", &type_to_ext(in_t[1], false, false, true)) - .replace("_EXTpi82_", &type_to_ext(out_t, false, false, true)) - .replace("_EXTpi8r_", &type_to_ext(in_t[1], false, true, true)) -} - -fn is_vldx(name: &str) -> bool { - let s: Vec<_> = name.split('_').collect(); - &name[0..3] == "vld" - && name[3..4].parse::().unwrap() > 1 - && (s.last().unwrap().starts_with('s') || s.last().unwrap().starts_with('f')) -} - -fn is_vstx(name: &str) -> bool { - let s: Vec<_> = name.split('_').collect(); - s.len() == 2 - && &name[0..3] == "vst" - && name[3..4].parse::().unwrap() > 1 - && (s[1].starts_with('s') || s[1].starts_with('f')) -} - -fn create_doc_string(comment_string: &str, fn_name: &str) -> String { - format!( - r#"{comment_string} -/// -/// [Arm's documentation](https://developer.arm.com/architectures/instruction-sets/intrinsics/{fn_name})"# - ) -} - -#[allow(clippy::too_many_arguments)] -fn gen_aarch64( - current_comment: &str, - current_fn: Option<&str>, - current_name: &str, - current_aarch64: Option<&str>, - link_aarch64: Option<&str>, - const_aarch64: Option<&str>, - constn: Option<&str>, - in_t: &[&str; 3], - out_t: &str, - current_tests: &[( - Vec, - Vec, - Vec, - Option, - Vec, - )], - suffix: Suffix, - para_num: i32, - target: TargetFeature, - fixed: &[String], - multi_fn: &[String], - fn_type: Fntype, - assert_instr_cfg: Option<&str>, -) -> (String, String) { - let name = match suffix { - Normal => format!("{current_name}{}", type_to_suffix(in_t[1])), - NoQ => format!("{current_name}{}", type_to_noq_suffix(in_t[1])), - Double => format!( - "{}{}", - current_name, - type_to_double_suffixes(out_t, in_t[1]) - ), - NoQDouble => format!( - "{}{}", - current_name, - type_to_noq_double_suffixes(out_t, in_t[1]) - ), - NSuffix => format!("{current_name}{}", type_to_n_suffix(in_t[1])), - DoubleN => format!( - "{}{}", - current_name, - type_to_double_n_suffixes(out_t, in_t[1]) - ), - NoQNSuffix => format!("{current_name}{}", type_to_noq_n_suffix(in_t[1])), - OutSuffix => format!("{current_name}{}", type_to_suffix(out_t)), - OutNSuffix => format!("{current_name}{}", type_to_n_suffix(out_t)), - OutNox => format!( - "{}{}", - current_name, - type_to_suffix(&type_to_sub_type(out_t)) - ), - In1Nox => format!( - "{}{}", - current_name, - type_to_suffix(&type_to_sub_type(in_t[1])) - ), - OutDupNox => format!( - "{}{}", - current_name, - type_to_dup_suffix(&type_to_sub_type(out_t)) - ), - OutLaneNox => format!( - "{}{}", - current_name, - type_to_lane_suffix(&type_to_sub_type(out_t)) - ), - In1LaneNox => format!( - "{}{}", - current_name, - type_to_lane_suffix(&type_to_sub_type(in_t[1])) - ), - Lane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[1], false) - ), - In2 => format!("{current_name}{}", type_to_suffix(in_t[2])), - In2Lane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[2], false) - ), - OutLane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[2], true) - ), - Rot => type_to_rot_suffix(current_name, type_to_suffix(out_t)), - RotLane => type_to_rot_suffix(current_name, &type_to_lane_suffixes(out_t, in_t[2], false)), - }; - let current_fn = if let Some(current_fn) = current_fn { - if link_aarch64.is_some() { - panic!("[{name}] Can't specify link and fn at the same time.") - } - current_fn.to_string() - } else if link_aarch64.is_some() { - format!("{name}_") - } else { - if multi_fn.is_empty() { - panic!("[{name}] Either (multi) fn or link-aarch have to be specified.") - } - String::new() - }; - let current_aarch64 = current_aarch64.unwrap(); - let mut link_t: Vec = vec![ - in_t[0].to_string(), - in_t[1].to_string(), - in_t[2].to_string(), - out_t.to_string(), - ]; - let mut ext_c = String::new(); - if let Some(link_aarch64) = link_aarch64 { - let link_aarch64 = if link_aarch64.contains(':') { - let links: Vec<_> = link_aarch64.split(':').map(|v| v.to_string()).collect(); - assert_eq!(links.len(), 5); - link_t = vec![ - links[1].clone(), - links[2].clone(), - links[3].clone(), - links[4].clone(), - ]; - links[0].to_string() - } else { - link_aarch64.to_string() - }; - let link_aarch64 = if link_aarch64.starts_with("llvm") { - ext(&link_aarch64, in_t, out_t) - } else { - let mut link = String::from("llvm.aarch64.neon."); - link.push_str(&link_aarch64); - ext(&link, in_t, out_t) - }; - let (ext_inputs, ext_output) = { - if const_aarch64.is_some() { - if !matches!(fn_type, Fntype::Normal) { - let ptr_type = match fn_type { - Fntype::Load => "*const i8", - Fntype::Store => "*mut i8", - _ => panic!("unsupported fn type"), - }; - let sub = type_to_sub_type(in_t[1]); - ( - match type_sub_len(in_t[1]) { - 1 => format!("a: {sub}, n: i64, ptr: {ptr_type}"), - 2 => format!("a: {sub}, b: {sub}, n: i64, ptr: {ptr_type}"), - 3 => format!("a: {sub}, b: {sub}, c: {sub}, n: i64, ptr: {ptr_type}"), - 4 => format!( - "a: {sub}, b: {sub}, c: {sub}, d: {sub}, n: i64, ptr: {ptr_type}" - ), - _ => panic!("unsupported type: {}", in_t[1]), - }, - if out_t != "void" { - format!(" -> {out_t}") - } else { - String::new() - }, - ) - } else { - ( - match para_num { - 1 => format!("a: {}, n: i32", in_t[0]), - 2 => format!("a: {}, b: {}, n: i32", in_t[0], in_t[1]), - 3 => format!("a: {}, b: {}, c: {}, n: i32", in_t[0], in_t[1], in_t[2]), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {out_t}"), - ) - } - } else if matches!(fn_type, Fntype::Store) { - let sub = type_to_sub_type(in_t[1]); - let ptr_type = if is_vstx(&name) { - "i8".to_string() - } else { - type_to_native_type(in_t[1]) - }; - let subs = match type_sub_len(in_t[1]) { - 1 => format!("a: {sub}"), - 2 => format!("a: {sub}, b: {sub}"), - 3 => format!("a: {sub}, b: {sub}, c: {sub}"), - 4 => format!("a: {sub}, b: {sub}, c: {sub}, d: {sub}"), - _ => panic!("unsupported type: {}", in_t[1]), - }; - (format!("{subs}, ptr: *mut {ptr_type}"), String::new()) - } else if is_vldx(&name) { - let ptr_type = if name.contains("dup") { - type_to_native_type(out_t) - } else { - type_to_sub_type(out_t) - }; - (format!("ptr: *const {ptr_type}"), format!(" -> {out_t}")) - } else { - ( - match para_num { - 1 => format!("a: {}", link_t[0]), - 2 => format!("a: {}, b: {}", link_t[0], link_t[1]), - 3 => format!("a: {}, b: {}, c: {}", link_t[0], link_t[1], link_t[2]), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {}", link_t[3]), - ) - } - }; - ext_c = format!( - r#"#[allow(improper_ctypes)] - extern "unadjusted" {{ - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "{link_aarch64}")] - fn {current_fn}({ext_inputs}){ext_output}; - }} - "#, - ); - }; - let const_declare = if let Some(constn) = constn { - if constn.contains(':') { - let constns: Vec<_> = constn.split(':').map(|v| v.to_string()).collect(); - assert_eq!(constns.len(), 2); - format!(r#""#, constns[0], constns[1]) - } else { - format!(r#""#) - } - } else { - String::new() - }; - let multi_calls = if !multi_fn.is_empty() { - let mut calls = String::new(); - for (i, item) in multi_fn.iter().enumerate() { - if i > 0 { - calls.push_str("\n "); - } - calls.push_str(&get_call( - item, - current_name, - in_t, - out_t, - fixed, - None, - true, - )); - } - calls - } else { - String::new() - }; - let const_assert = if let Some(constn) = constn { - if constn.contains(':') { - let constns: Vec<_> = constn.split(':').map(|v| v.to_string()).collect(); - let const_test = current_tests[0].3.as_ref().unwrap(); - let const_tests: Vec<_> = const_test.split(':').map(|v| v.to_string()).collect(); - assert_eq!(constns.len(), 2); - assert_eq!(const_tests.len(), 2); - format!( - r#", {} = {}, {} = {}"#, - constns[0], - map_val(in_t[1], &const_tests[0]), - constns[1], - map_val(in_t[1], &const_tests[1]), - ) - } else { - format!( - r#", {} = {}"#, - constn, - map_val(in_t[1], current_tests[0].3.as_ref().unwrap()) - ) - } - } else { - String::new() - }; - let const_legacy = if let Some(constn) = constn { - if constn.contains(':') { - format!( - "\n#[rustc_legacy_const_generics({}, {})]", - para_num - 1, - para_num + 1 - ) - } else { - format!("\n#[rustc_legacy_const_generics({para_num})]") - } - } else { - String::new() - }; - let fn_decl = { - let fn_output = if out_t == "void" { - String::new() - } else { - format!("-> {out_t} ") - }; - let fn_inputs = match para_num { - 1 => format!("(a: {})", in_t[0]), - 2 => format!("(a: {}, b: {})", in_t[0], in_t[1]), - 3 => format!("(a: {}, b: {}, c: {})", in_t[0], in_t[1], in_t[2]), - _ => panic!("unsupported parameter number"), - }; - format!("pub unsafe fn {name}{const_declare}{fn_inputs} {fn_output}") - }; - let call_params = { - if let (Some(const_aarch64), Some(_)) = (const_aarch64, link_aarch64) { - if !matches!(fn_type, Fntype::Normal) { - let subs = match type_sub_len(in_t[1]) { - 1 => "b", - 2 => "b.0, b.1", - 3 => "b.0, b.1, b.2", - 4 => "b.0, b.1, b.2, b.3", - _ => panic!("unsupported type: {}", in_t[1]), - }; - format!( - r#"{} - {}{}({}, {} as i64, a as _)"#, - multi_calls, - ext_c, - current_fn, - subs, - constn.unwrap() - ) - } else { - match para_num { - 1 => format!( - r#"{multi_calls} - {ext_c}{current_fn}(a, {const_aarch64})"# - ), - 2 => format!( - r#"{multi_calls} - {ext_c}{current_fn}(a, b, {const_aarch64})"# - ), - _ => String::new(), - } - } - } else if link_aarch64.is_some() && matches!(fn_type, Fntype::Store) { - let cast = if is_vstx(&name) { " as _" } else { "" }; - match type_sub_len(in_t[1]) { - 1 => format!(r#"{ext_c}{current_fn}(b, a{cast})"#), - 2 => format!(r#"{ext_c}{current_fn}(b.0, b.1, a{cast})"#), - 3 => format!(r#"{ext_c}{current_fn}(b.0, b.1, b.2, a{cast})"#), - 4 => format!(r#"{ext_c}{current_fn}(b.0, b.1, b.2, b.3, a{cast})"#), - _ => panic!("unsupported type: {}", in_t[1]), - } - } else if link_aarch64.is_some() && is_vldx(&name) { - format!(r#"{ext_c}{current_fn}(a as _)"#,) - } else { - let trans: [&str; 2] = if link_t[3] != out_t { - ["transmute(", ")"] - } else { - ["", ""] - }; - match (multi_calls.len(), para_num, fixed.len()) { - (0, 1, 0) => format!(r#"{ext_c}{}{current_fn}(a){}"#, trans[0], trans[1]), - (0, 1, _) => { - let fixed: Vec = - fixed.iter().take(type_len(in_t[0])).cloned().collect(); - format!( - r#"let b{}; - {}{}{}(a, transmute(b)){}"#, - values(in_t[0], &fixed), - ext_c, - trans[0], - current_fn, - trans[1], - ) - } - (0, 2, _) => format!(r#"{ext_c}{}{current_fn}(a, b){}"#, trans[0], trans[1],), - (0, 3, _) => format!(r#"{ext_c}{current_fn}(a, b, c)"#,), - (_, 1, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, 2, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, 3, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, _, _) => String::new(), - } - } - }; - let assert_instr_cfg = if let Some(assert_instr_cfg) = assert_instr_cfg { - format!("all(test, {assert_instr_cfg})") - } else { - "test".to_string() - }; - let stable = target.stability(true); - let function = format!( - r#" -{function_doc} -#[inline]{target_feature} -#[cfg_attr({assert_instr_cfg}, assert_instr({current_aarch64}{const_assert}))]{const_legacy} -#[{stable}] -{fn_decl}{{ - {call_params} -}} -"#, - function_doc = create_doc_string(current_comment, &name), - target_feature = target.to_target_feature_attr_aarch64() - ); - let test = match fn_type { - Fntype::Normal => gen_test( - &name, - in_t, - out_t, - current_tests, - [type_len(in_t[0]), type_len(in_t[1]), type_len(in_t[2])], - type_len(out_t), - para_num, - target.to_simd_test_attr_aarch64(), - ), - Fntype::Load => gen_load_test(&name, in_t, out_t, current_tests, type_len(out_t)), - Fntype::Store => gen_store_test(&name, in_t, out_t, current_tests, type_len(in_t[1])), - }; - (function, test) -} - -fn gen_load_test( - name: &str, - in_t: &[&str; 3], - out_t: &str, - current_tests: &[( - Vec, - Vec, - Vec, - Option, - Vec, - )], - type_len: usize, -) -> String { - let mut test = format!( - r#"{simd_test} - unsafe fn test_{name}() {{"#, - simd_test = Default.to_simd_test_attr_shared().indented(4) - ); - for (a, b, _, n, e) in current_tests { - let a: Vec = a.iter().take(type_len + 1).cloned().collect(); - let e: Vec = e.iter().take(type_len).cloned().collect(); - let has_b = !b.is_empty(); - let has_n = n.is_some(); - let mut input = String::from("["); - for (i, item) in a[..type_len + 1].iter().enumerate() { - if i != 0 { - input.push_str(", "); - } - input.push_str(item) - } - input.push(']'); - let output = |v: &Vec| { - let mut output = String::from("["); - for i in 0..type_sub_len(out_t) { - if i != 0 { - output.push_str(", "); - } - let sub_len = type_len / type_sub_len(out_t); - if type_to_global_type(out_t) != "f64" { - let mut sub_output = format!("{}::new(", type_to_global_type(out_t)); - for j in 0..sub_len { - if j != 0 { - sub_output.push_str(", "); - } - sub_output.push_str(&v[i * sub_len + j]); - } - sub_output.push(')'); - output.push_str(&sub_output); - } else { - output.push_str(&v[i]); - } - } - output.push(']'); - output - }; - let input_b = if has_b { - let b: Vec = b.iter().take(type_len).cloned().collect(); - format!( - r#" - let b: [{}; {}] = {};"#, - type_to_global_type(in_t[1]), - type_sub_len(in_t[1]), - output(&b), - ) - } else { - String::new() - }; - let t = format!( - r#" - let a: [{}; {}] = {};{} - let e: [{}; {}] = {}; - let r: [{}; {}] = transmute({}{}(a[1..].as_ptr(){})); - assert_eq!(r, e); -"#, - type_to_native_type(out_t), - type_len + 1, - input, - input_b, - type_to_global_type(out_t), - type_sub_len(out_t), - output(&e), - type_to_global_type(out_t), - type_sub_len(out_t), - name, - if has_n { - format!("::<{}>", n.as_deref().unwrap()) - } else { - String::new() - }, - if has_b { ", transmute(b)" } else { "" }, - ); - test.push_str(&t); - } - test.push_str(" }\n"); - test -} - -fn gen_store_test( - name: &str, - in_t: &[&str; 3], - _out_t: &str, - current_tests: &[( - Vec, - Vec, - Vec, - Option, - Vec, - )], - type_len: usize, -) -> String { - let mut test = format!( - r#"{simd_test} - unsafe fn test_{name}() {{"#, - simd_test = Default.to_simd_test_attr_shared().indented(4) - ); - for (a, _, _, constn, e) in current_tests { - let a: Vec = a.iter().take(type_len + 1).cloned().collect(); - let e: Vec = e.iter().take(type_len).cloned().collect(); - let mut input = String::from("["); - for (i, item) in a[..type_len + 1].iter().enumerate() { - if i != 0 { - input.push_str(", "); - } - input.push_str(item) - } - input.push(']'); - let mut output = String::from("["); - for (i, item) in e.iter().enumerate() { - if i != 0 { - output.push_str(", "); - } - output.push_str(item) - } - output.push(']'); - let const_n = constn - .as_deref() - .map_or(String::new(), |n| format!("::<{n}>")); - let t = format!( - r#" - let a: [{}; {}] = {}; - let e: [{}; {}] = {}; - let mut r: [{}; {}] = [0{}; {}]; - {}{}(r.as_mut_ptr(), core::ptr::read_unaligned(a[1..].as_ptr() as _)); - assert_eq!(r, e); -"#, - type_to_native_type(in_t[1]), - type_len + 1, - input, - type_to_native_type(in_t[1]), - type_len, - output, - type_to_native_type(in_t[1]), - type_len, - type_to_native_type(in_t[1]), - type_len, - name, - const_n, - ); - test.push_str(&t); - } - test.push_str(" }\n"); - test -} - -fn gen_test( - name: &str, - in_t: &[&str; 3], - out_t: &str, - current_tests: &[( - Vec, - Vec, - Vec, - Option, - Vec, - )], - len_in: [usize; 3], - len_out: usize, - para_num: i32, - attributes: Lines, -) -> String { - let mut test = attributes.indented(4).to_string(); - test.push_str(&format!("\n unsafe fn test_{name}() {{")); - for (a, b, c, n, e) in current_tests { - let a: Vec = a.iter().take(len_in[0]).cloned().collect(); - let b: Vec = b.iter().take(len_in[1]).cloned().collect(); - let c: Vec = c.iter().take(len_in[2]).cloned().collect(); - let e: Vec = e.iter().take(len_out).cloned().collect(); - let const_value = if let Some(constn) = n { - if constn.contains(':') { - let constns: Vec<_> = constn.split(':').map(|v| v.to_string()).collect(); - format!( - r#"::<{}, {}>"#, - map_val(in_t[1], &constns[0]), - map_val(in_t[1], &constns[1]) - ) - } else { - format!(r#"::<{}>"#, map_val(in_t[1], constn)) - } - } else { - String::new() - }; - let r_type = match type_sub_len(out_t) { - 1 => type_to_global_type(out_t).to_string(), - _ => format!("[{}; {}]", type_to_native_type(out_t), type_len(out_t)), - }; - let mut call_params = String::new(); - assert!(matches!(para_num, 1..=3)); - for i in 0..para_num { - let chr = char::from(b'a' + i as u8); - let v = match i { - 0 => &a, - 1 => &b, - 2 => &c, - _ => unreachable!(), - }; - let param_type = in_t[i as usize]; - write!(test, "\n let {chr}{};", values(param_type, v)).unwrap(); - if i != 0 { - call_params.push_str(", "); - } - if param_type != type_to_global_type(param_type) { - write!(call_params, "transmute({chr})").unwrap(); - } else { - call_params.push(chr); - } - } - let r_trans = if r_type != out_t { - ("transmute(", ")") - } else { - ("", "") - }; - write!( - test, - r#" - let e{}; - let r: {r_type} = {}{name}{const_value}({call_params}){}; - assert_eq!(r, e); -"#, - values(out_t, &e), - r_trans.0, - r_trans.1, - ) - .unwrap(); - } - test.push_str(" }\n"); - test -} - -#[allow(clippy::too_many_arguments)] -fn gen_arm( - current_comment: &str, - current_fn: Option<&str>, - current_name: &str, - current_arm: &str, - link_arm: Option<&str>, - current_aarch64: Option<&str>, - link_aarch64: Option<&str>, - const_arm: Option<&str>, - const_aarch64: Option<&str>, - constn: Option<&str>, - in_t: &[&str; 3], - out_t: &str, - current_tests: &[( - Vec, - Vec, - Vec, - Option, - Vec, - )], - suffix: Suffix, - para_num: i32, - target: TargetFeature, - fixed: &[String], - multi_fn: &[String], - fn_type: Fntype, - separate: bool, -) -> (String, String) { - let name = match suffix { - Normal => format!("{current_name}{}", type_to_suffix(in_t[1])), - NoQ => format!("{current_name}{}", type_to_noq_suffix(in_t[1])), - Double => format!( - "{}{}", - current_name, - type_to_double_suffixes(out_t, in_t[1]) - ), - NoQDouble => format!( - "{}{}", - current_name, - type_to_noq_double_suffixes(out_t, in_t[1]) - ), - NSuffix => format!("{current_name}{}", type_to_n_suffix(in_t[1])), - DoubleN => format!( - "{}{}", - current_name, - type_to_double_n_suffixes(out_t, in_t[1]) - ), - NoQNSuffix => format!("{current_name}{}", type_to_noq_n_suffix(in_t[1])), - OutSuffix => format!("{current_name}{}", type_to_suffix(out_t)), - OutNSuffix => format!("{current_name}{}", type_to_n_suffix(out_t)), - OutNox => format!( - "{}{}", - current_name, - type_to_suffix(&type_to_sub_type(out_t)) - ), - In1Nox => format!( - "{}{}", - current_name, - type_to_suffix(&type_to_sub_type(in_t[1])) - ), - OutDupNox => format!( - "{}{}", - current_name, - type_to_dup_suffix(&type_to_sub_type(out_t)) - ), - OutLaneNox => format!( - "{}{}", - current_name, - type_to_lane_suffix(&type_to_sub_type(out_t)) - ), - In1LaneNox => format!( - "{}{}", - current_name, - type_to_lane_suffix(&type_to_sub_type(in_t[1])) - ), - Lane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[1], false) - ), - In2 => format!("{current_name}{}", type_to_suffix(in_t[2])), - In2Lane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[2], false) - ), - OutLane => format!( - "{}{}", - current_name, - type_to_lane_suffixes(out_t, in_t[2], true) - ), - Rot => type_to_rot_suffix(current_name, type_to_suffix(out_t)), - RotLane => type_to_rot_suffix(current_name, &type_to_lane_suffixes(out_t, in_t[2], false)), - }; - let current_aarch64 = current_aarch64.to_owned().unwrap_or(current_arm); - let current_fn = if let Some(current_fn) = current_fn { - if link_aarch64.is_some() || link_arm.is_some() { - panic!( - "[{name}] Can't specify link and function at the same time. {current_fn} / {link_aarch64:?} / {link_arm:?}" - ) - } - current_fn.to_string() - } else if link_aarch64.is_some() || link_arm.is_some() { - format!("{name}_") - } else { - if multi_fn.is_empty() { - panic!("[{name}] Either fn or link-arm and link-aarch have to be specified.") - } - String::new() - }; - let mut ext_c = String::new(); - let mut ext_c_arm = if multi_fn.is_empty() || link_arm.is_none() { - String::new() - } else { - String::from( - r#" - "#, - ) - }; - let mut ext_c_aarch64 = if multi_fn.is_empty() || link_aarch64.is_none() { - String::new() - } else { - String::from( - r#" - "#, - ) - }; - let mut link_arm_t: Vec = vec![ - in_t[0].to_string(), - in_t[1].to_string(), - in_t[2].to_string(), - out_t.to_string(), - ]; - let mut link_aarch64_t: Vec = vec![ - in_t[0].to_string(), - in_t[1].to_string(), - in_t[2].to_string(), - out_t.to_string(), - ]; - if let (Some(link_arm), Some(link_aarch64)) = (link_arm, link_aarch64) { - let link_arm = if link_arm.contains(':') { - let links: Vec<_> = link_arm.split(':').map(|v| v.to_string()).collect(); - assert_eq!(links.len(), 5); - link_arm_t = vec![ - links[1].clone(), - links[2].clone(), - links[3].clone(), - links[4].clone(), - ]; - links[0].to_string() - } else { - link_arm.to_string() - }; - let link_aarch64 = if link_aarch64.contains(':') { - let links: Vec<_> = link_aarch64.split(':').map(|v| v.to_string()).collect(); - assert_eq!(links.len(), 5); - link_aarch64_t = vec![ - links[1].clone(), - links[2].clone(), - links[3].clone(), - links[4].clone(), - ]; - links[0].to_string() - } else { - link_aarch64.to_string() - }; - let link_arm = if link_arm.starts_with("llvm") { - ext(&link_arm, in_t, out_t) - } else { - let mut link = String::from("llvm.arm.neon."); - link.push_str(&link_arm); - ext(&link, in_t, out_t) - }; - let link_aarch64 = if link_aarch64.starts_with("llvm") { - ext(&link_aarch64, in_t, out_t) - } else { - let mut link = String::from("llvm.aarch64.neon."); - link.push_str(&link_aarch64); - ext(&link, in_t, out_t) - }; - if out_t == link_arm_t[3] && out_t == link_aarch64_t[3] { - ext_c = format!( - r#"#[allow(improper_ctypes)] - extern "unadjusted" {{ - #[cfg_attr(target_arch = "arm", link_name = "{}")] - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "{}")] - fn {}({}) -> {}; - }} -"#, - link_arm, - link_aarch64, - current_fn, - match para_num { - 1 => format!("a: {}", in_t[0]), - 2 => format!("a: {}, b: {}", in_t[0], in_t[1]), - 3 => format!("a: {}, b: {}, c: {}", in_t[0], in_t[1], in_t[2]), - _ => unimplemented!("unknown para_num"), - }, - out_t - ); - }; - let (arm_ext_inputs, arm_ext_output) = { - if let Some(const_arm) = const_arm { - if !matches!(fn_type, Fntype::Normal) { - let ptr_type = match fn_type { - Fntype::Load => "*const i8", - Fntype::Store => "*mut i8", - _ => panic!("unsupported fn type"), - }; - let sub_type = type_to_sub_type(in_t[1]); - let inputs = match type_sub_len(in_t[1]) { - 1 => format!("a: {sub_type}"), - 2 => format!("a: {sub_type}, b: {sub_type}",), - 3 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}",), - 4 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}, d: {sub_type}",), - _ => panic!("unknown type: {}", in_t[1]), - }; - let out = if out_t == "void" { - String::new() - } else { - format!(" -> {out_t}") - }; - (format!("ptr: {ptr_type}, {inputs}, n: i32, size: i32"), out) - } else { - let (_, const_type) = if const_arm.contains(':') { - let consts: Vec<_> = - const_arm.split(':').map(|v| v.trim().to_string()).collect(); - (consts[0].clone(), consts[1].clone()) - } else { - ( - const_arm.to_string(), - in_t[para_num as usize - 1].to_string(), - ) - }; - ( - match para_num { - 1 => format!("a: {}, n: {const_type}", in_t[0]), - 2 => format!("a: {}, b: {}, n: {const_type}", in_t[0], in_t[1]), - 3 => format!( - "a: {}, b: {}, c: {}, n: {const_type}", - in_t[0], in_t[1], in_t[2] - ), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {out_t}"), - ) - } - } else if out_t != link_arm_t[3] { - ( - match para_num { - 1 => format!("a: {}", link_arm_t[0]), - 2 => format!("a: {}, b: {}", link_arm_t[0], link_arm_t[1]), - 3 => format!( - "a: {}, b: {}, c: {}", - link_arm_t[0], link_arm_t[1], link_arm_t[2] - ), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {}", link_arm_t[3]), - ) - } else if matches!(fn_type, Fntype::Store) { - let sub_type = type_to_sub_type(in_t[1]); - let inputs = match type_sub_len(in_t[1]) { - 1 => format!("a: {sub_type}"), - 2 => format!("a: {sub_type}, b: {sub_type}",), - 3 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}",), - 4 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}, d: {sub_type}",), - _ => panic!("unknown type: {}", in_t[1]), - }; - let (ptr_type, size) = if is_vstx(&name) { - ("i8".to_string(), ", size: i32") - } else { - (type_to_native_type(in_t[1]), "") - }; - ( - format!("ptr: *mut {ptr_type}, {inputs}{size}"), - String::new(), - ) - } else if is_vldx(&name) { - ( - "ptr: *const i8, size: i32".to_string(), - format!(" -> {out_t}"), - ) - } else { - (String::new(), String::new()) - } - }; - ext_c_arm.push_str(&format!( - r#"#[allow(improper_ctypes)] - extern "unadjusted" {{ - #[cfg_attr(target_arch = "arm", link_name = "{link_arm}")] - fn {current_fn}({arm_ext_inputs}){arm_ext_output}; - }} -"#, - )); - let (aarch64_ext_inputs, aarch64_ext_output) = { - if let Some(const_aarch64) = const_aarch64 { - if !matches!(fn_type, Fntype::Normal) { - let ptr_type = match fn_type { - Fntype::Load => "*const i8", - Fntype::Store => "*mut i8", - _ => panic!("unsupported fn type"), - }; - let sub_type = type_to_sub_type(in_t[1]); - let mut inputs = match type_sub_len(in_t[1]) { - 1 => format!("a: {sub_type}",), - 2 => format!("a: {sub_type}, b: {sub_type}",), - 3 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}",), - 4 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}, d: {sub_type}",), - _ => panic!("unknown type: {}", in_t[1]), - }; - inputs.push_str(&format!(", n: i64, ptr: {ptr_type}")); - let out = if out_t == "void" { - String::new() - } else { - format!(" -> {out_t}") - }; - (inputs, out) - } else if const_aarch64.contains("dup-in_len-N as ttn") { - ( - match para_num { - 1 => format!("a: {}, n: {}", in_t[0], in_t[0]), - 2 => format!("a: {}, b: {}, n: {}", in_t[0], in_t[1], in_t[1]), - 3 => format!( - "a: {}, b: {}, c: {}, n: {}", - in_t[0], in_t[1], in_t[2], in_t[1] - ), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {out_t}"), - ) - } else { - ( - match para_num { - 1 => format!("a: {}, n: i32", in_t[0]), - 2 => format!("a: {}, b: {}, n: i32", in_t[0], in_t[1]), - 3 => format!("a: {}, b: {}, c: {}, n: i32", in_t[0], in_t[1], in_t[2]), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {out_t}"), - ) - } - } else if out_t != link_aarch64_t[3] { - ( - match para_num { - 1 => format!("a: {}", link_aarch64_t[0]), - 2 => format!("a: {}, b: {}", link_aarch64_t[0], link_aarch64_t[1]), - 3 => format!( - "a: {}, b: {}, c: {}", - link_aarch64_t[0], link_aarch64_t[1], link_aarch64_t[2] - ), - _ => unimplemented!("unknown para_num"), - }, - format!(" -> {}", link_aarch64_t[3]), - ) - } else if matches!(fn_type, Fntype::Store) { - let sub_type = type_to_sub_type(in_t[1]); - let mut inputs = match type_sub_len(in_t[1]) { - 1 => format!("a: {sub_type}",), - 2 => format!("a: {sub_type}, b: {sub_type}",), - 3 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}",), - 4 => format!("a: {sub_type}, b: {sub_type}, c: {sub_type}, d: {sub_type}",), - _ => panic!("unknown type: {}", in_t[1]), - }; - let ptr_type = if is_vstx(&name) { - "i8".to_string() - } else { - type_to_native_type(in_t[1]) - }; - inputs.push_str(&format!(", ptr: *mut {ptr_type}")); - (inputs, String::new()) - } else if is_vldx(&name) { - let ptr_type = if name.contains("dup") { - type_to_native_type(out_t) - } else { - type_to_sub_type(out_t) - }; - (format!("ptr: *const {ptr_type}"), format!(" -> {out_t}")) - } else { - (String::new(), String::new()) - } - }; - ext_c_aarch64.push_str(&format!( - r#"#[allow(improper_ctypes)] - extern "unadjusted" {{ - #[cfg_attr(any(target_arch = "aarch64", target_arch = "arm64ec"), link_name = "{link_aarch64}")] - fn {current_fn}({aarch64_ext_inputs}){aarch64_ext_output}; - }} -"#, - )); - }; - let const_declare = if let Some(constn) = constn { - format!(r#""#) - } else { - String::new() - }; - let multi_calls = if !multi_fn.is_empty() { - let mut calls = String::new(); - for (i, item) in multi_fn.iter().enumerate() { - if i > 0 { - calls.push_str("\n "); - } - calls.push_str(&get_call( - item, - current_name, - in_t, - out_t, - fixed, - None, - false, - )); - } - calls - } else { - String::new() - }; - let const_assert = if let Some(constn) = constn { - format!( - r#", {} = {}"#, - constn, - map_val(in_t[1], current_tests[0].3.as_ref().unwrap()) - ) - } else { - String::new() - }; - let const_legacy = if constn.is_some() { - format!("\n#[rustc_legacy_const_generics({para_num})]") - } else { - String::new() - }; - let fn_decl = { - let fn_output = if out_t == "void" { - String::new() - } else { - format!("-> {out_t} ") - }; - let fn_inputs = match para_num { - 1 => format!("(a: {})", in_t[0]), - 2 => format!("(a: {}, b: {})", in_t[0], in_t[1]), - 3 => format!("(a: {}, b: {}, c: {})", in_t[0], in_t[1], in_t[2]), - _ => panic!("unsupported parameter number"), - }; - format!("pub unsafe fn {name}{const_declare}{fn_inputs} {fn_output}") - }; - let function = if separate { - let call_arm = { - let arm_params = if let (Some(const_arm), Some(_)) = (const_arm, link_arm) { - if !matches!(fn_type, Fntype::Normal) { - let subs = match type_sub_len(in_t[1]) { - 1 => "b", - 2 => "b.0, b.1", - 3 => "b.0, b.1, b.2", - 4 => "b.0, b.1, b.2, b.3", - _ => "", - }; - format!( - "{}(a as _, {}, {}, {})", - current_fn, - subs, - constn.unwrap(), - type_bits(&type_to_sub_type(in_t[1])) / 8, - ) - } else { - let cnt = if const_arm.contains(':') { - let consts: Vec<_> = - const_arm.split(':').map(|v| v.trim().to_string()).collect(); - consts[0].clone() - } else { - let const_arm = const_arm.replace("ttn", &type_to_native_type(in_t[1])); - let mut cnt = format!("const {{ {}", in_t[1]); - cnt.push_str("(["); - for i in 0..type_len(in_t[1]) { - if i != 0 { - cnt.push_str(", "); - } - cnt.push_str(&const_arm); - } - cnt.push_str("]) }"); - cnt - }; - match para_num { - 1 => format!("{current_fn}(a, {cnt})"), - 2 => format!("{current_fn}(a, b, {cnt})"), - _ => String::new(), - } - } - } else if out_t != link_arm_t[3] { - match para_num { - 1 => format!("transmute({current_fn}(a))",), - 2 => format!("transmute({current_fn}(transmute(a), transmute(b)))",), - _ => String::new(), - } - } else if matches!(fn_type, Fntype::Store) { - let (cast, size) = if is_vstx(&name) { - ( - " as _", - format!(", {}", type_bits(&type_to_sub_type(in_t[1])) / 8), - ) - } else { - ("", String::new()) - }; - match type_sub_len(in_t[1]) { - 1 => format!("{current_fn}(a{cast}, b{size})"), - 2 => format!("{current_fn}(a{cast}, b.0, b.1{size})"), - 3 => format!("{current_fn}(a{cast}, b.0, b.1, b.2{size})"), - 4 => format!("{current_fn}(a{cast}, b.0, b.1, b.2, b.3{size})"), - _ => String::new(), - } - } else if link_arm.is_some() && is_vldx(&name) { - format!( - "{}(a as *const i8, {})", - current_fn, - type_bits(&type_to_sub_type(out_t)) / 8 - ) - } else { - String::new() - }; - format!( - r#"{fn_decl}{{ - {multi_calls}{ext_c_arm}{arm_params} -}}"# - ) - }; - let call_aarch64 = { - let aarch64_params = - if let (Some(const_aarch64), Some(_)) = (const_aarch64, link_aarch64) { - if !matches!(fn_type, Fntype::Normal) { - let subs = match type_sub_len(in_t[1]) { - 1 => "b", - 2 => "b.0, b.1", - 3 => "b.0, b.1, b.2", - 4 => "b.0, b.1, b.2, b.3", - _ => "", - }; - format!( - "{}({}, {} as i64, a as _)", - current_fn, - subs, - constn.unwrap() - ) - } else if const_aarch64.contains("dup-in_len-N as ttn") { - let const_aarch64 = format!("N as {}", type_to_native_type(in_t[1])); - let mut cnt = String::from(in_t[1]); - cnt.push_str("(["); - for i in 0..type_len(in_t[1]) { - if i != 0 { - cnt.push_str(", "); - } - cnt.push_str(&const_aarch64); - } - cnt.push_str("])"); - format!("{current_fn}(a, const {{ {cnt} }})") - } else { - match para_num { - 1 => format!("{current_fn}(a, {const_aarch64})"), - 2 => format!("{current_fn}(a, b, {const_aarch64})"), - _ => String::new(), - } - } - } else if out_t != link_aarch64_t[3] { - match para_num { - 1 => format!("transmute({current_fn}(a))",), - 2 => format!("transmute({current_fn}(a, b))",), - _ => String::new(), - } - } else if matches!(fn_type, Fntype::Store) { - let cast = if is_vstx(&name) { " as _" } else { "" }; - match type_sub_len(in_t[1]) { - 1 => format!("{current_fn}(b, a{cast})"), - 2 => format!("{current_fn}(b.0, b.1, a{cast})"), - 3 => format!("{current_fn}(b.0, b.1, b.2, a{cast})"), - 4 => format!("{current_fn}(b.0, b.1, b.2, b.3, a{cast})"), - _ => String::new(), - } - } else if link_aarch64.is_some() && is_vldx(&name) { - format!("{current_fn}(a as _)") - } else { - String::new() - }; - format!( - r#"{fn_decl}{{ - {multi_calls}{ext_c_aarch64}{aarch64_params} -}}"# - ) - }; - let stable_aarch64 = target.stability(true); - let stable_arm = target.stability(false); - let function_doc = create_doc_string(current_comment, &name); - format!( - r#" -{function_doc} -#[inline] -#[cfg(target_arch = "arm")]{target_feature_arm} -#[cfg_attr(test, assert_instr({assert_arm}{const_assert}))]{const_legacy} -#[{stable_arm}] -{call_arm} - -{function_doc} -#[inline] -#[cfg(not(target_arch = "arm"))]{target_feature_aarch64} -#[cfg_attr(test, assert_instr({assert_aarch64}{const_assert}))]{const_legacy} -#[{stable_aarch64}] -{call_aarch64} -"#, - target_feature_arm = target.to_target_feature_attr_arm(), - target_feature_aarch64 = target.to_target_feature_attr_aarch64(), - assert_arm = expand_intrinsic(current_arm, in_t[1]), - assert_aarch64 = expand_intrinsic(current_aarch64, in_t[1]), - ) - } else { - let call = { - let stmts = match (multi_calls.len(), para_num, fixed.len()) { - (0, 1, 0) => format!(r#"{ext_c}{current_fn}(a)"#,), - (0, 1, _) => { - let fixed: Vec = - fixed.iter().take(type_len(in_t[0])).cloned().collect(); - format!( - r#"let b{}; - {}{}(a, transmute(b))"#, - values(in_t[0], &fixed), - ext_c, - current_fn, - ) - } - (0, 2, _) => format!(r#"{ext_c}{current_fn}(a, b)"#,), - (0, 3, _) => format!(r#"{ext_c}{current_fn}(a, b, c)"#,), - (_, 1, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, 2, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, 3, _) => format!(r#"{ext_c}{multi_calls}"#,), - (_, _, _) => String::new(), - }; - if stmts != String::new() { - format!( - r#"{fn_decl}{{ - {stmts} -}}"# - ) - } else { - String::new() - } - }; - let stable_aarch64 = target.stability(true); - let stable_arm = target.stability(false); - format!( - r#" -{function_doc} -#[inline]{target_feature} -#[cfg_attr(all(test, target_arch = "arm"), assert_instr({assert_arm}{const_assert}))] -#[cfg_attr(all(test, any(target_arch = "aarch64", target_arch = "arm64ec")), assert_instr({assert_aarch64}{const_assert}))]{const_legacy} -#[cfg_attr(not(target_arch = "arm"), {stable_aarch64})] -#[cfg_attr(target_arch = "arm", {stable_arm})] -{call} -"#, - function_doc = create_doc_string(current_comment, &name), - assert_arm = expand_intrinsic(current_arm, in_t[1]), - assert_aarch64 = expand_intrinsic(current_aarch64, in_t[1]), - target_feature = target.to_target_feature_attr_shared(), - ) - }; - let test = match fn_type { - Fntype::Normal => gen_test( - &name, - in_t, - out_t, - current_tests, - [type_len(in_t[0]), type_len(in_t[1]), type_len(in_t[2])], - type_len(out_t), - para_num, - target.to_simd_test_attr_shared(), - ), - Fntype::Load => gen_load_test(&name, in_t, out_t, current_tests, type_len(out_t)), - Fntype::Store => gen_store_test(&name, in_t, out_t, current_tests, type_len(in_t[1])), - }; - (function, test) -} - -fn expand_intrinsic(intr: &str, t: &str) -> String { - if intr.ends_with('.') { - let ext = match t { - "int8x8_t" => "i8", - "int8x16_t" => "i8", - "int16x4_t" => "i16", - "int16x8_t" => "i16", - "int32x2_t" => "i32", - "int32x4_t" => "i32", - "int64x1_t" => "i64", - "int64x2_t" => "i64", - "uint8x8_t" => "i8", - "uint8x16_t" => "i8", - "uint16x4_t" => "i16", - "uint16x8_t" => "i16", - "uint32x2_t" => "i32", - "uint32x4_t" => "i32", - "uint64x1_t" => "i64", - "uint64x2_t" => "i64", - "float16x4_t" => "f16", - "float16x8_t" => "f16", - "float32x2_t" => "f32", - "float32x4_t" => "f32", - "float64x1_t" => "f64", - "float64x2_t" => "f64", - "poly8x8_t" => "i8", - "poly8x16_t" => "i8", - "poly16x4_t" => "i16", - "poly16x8_t" => "i16", - /* - "poly64x1_t" => "i64x1", - "poly64x2_t" => "i64x2", - */ - _ => panic!("unknown type for extension: {t}"), - }; - format!(r#""{intr}{ext}""#) - } else if intr.ends_with(".s") { - let ext = match t { - "int8x8_t" => "s8", - "int8x16_t" => "s8", - "int16x4_t" => "s16", - "int16x8_t" => "s16", - "int32x2_t" => "s32", - "int32x4_t" => "s32", - "int64x1_t" => "s64", - "int64x2_t" => "s64", - "uint8x8_t" => "u8", - "uint8x16_t" => "u8", - "uint16x4_t" => "u16", - "uint16x8_t" => "u16", - "uint32x2_t" => "u32", - "uint32x4_t" => "u32", - "uint64x1_t" => "u64", - "uint64x2_t" => "u64", - "poly8x8_t" => "p8", - "poly8x16_t" => "p8", - "poly16x4_t" => "p16", - "poly16x8_t" => "p16", - "float16x4_t" => "f16", - "float16x8_t" => "f16", - "float32x2_t" => "f32", - "float32x4_t" => "f32", - "float64x1_t" => "f64", - "float64x2_t" => "f64", - /* - "poly64x1_t" => "i64x1", - "poly64x2_t" => "i64x2", - */ - _ => panic!("unknown type for extension: {t}"), - }; - format!(r#""{}{ext}""#, &intr[..intr.len() - 1]) - } else if intr.ends_with(".l") { - let ext = match t { - "int8x8_t" => "8", - "int8x16_t" => "8", - "int16x4_t" => "16", - "int16x8_t" => "16", - "int32x2_t" => "32", - "int32x4_t" => "32", - "int64x1_t" => "64", - "int64x2_t" => "64", - "uint8x8_t" => "8", - "uint8x16_t" => "8", - "uint16x4_t" => "16", - "uint16x8_t" => "16", - "uint32x2_t" => "32", - "uint32x4_t" => "32", - "uint64x1_t" => "64", - "uint64x2_t" => "64", - "poly8x8_t" => "8", - "poly8x16_t" => "8", - "poly16x4_t" => "16", - "poly16x8_t" => "16", - "float16x4_t" => "16", - "float16x8_t" => "16", - "float32x2_t" => "32", - "float32x4_t" => "32", - "float64x1_t" => "64", - "float64x2_t" => "64", - "poly64x1_t" => "64", - "poly64x2_t" => "64", - _ => panic!("unknown type for extension: {t}"), - }; - format!(r#""{}{ext}""#, &intr[..intr.len() - 1]) - } else { - intr.to_string() - } -} - -fn get_call( - in_str: &str, - current_name: &str, - in_t: &[&str; 3], - out_t: &str, - fixed: &[String], - n: Option, - aarch64: bool, -) -> String { - let params: Vec<_> = in_str.split(',').map(|v| v.trim().to_string()).collect(); - assert!(!params.is_empty()); - let mut fn_name = params[0].clone(); - if fn_name == "a" { - return String::from("a"); - } - if fn_name == "transpose-1-in_len" { - return transpose1(type_len(in_t[1])).to_string(); - } - if fn_name == "transpose-2-in_len" { - return transpose2(type_len(in_t[1])).to_string(); - } - if fn_name == "zip-1-in_len" { - return zip1(type_len(in_t[1])).to_string(); - } - if fn_name == "zip-2-in_len" { - return zip2(type_len(in_t[1])).to_string(); - } - if fn_name == "unzip-1-in_len" { - return unzip1(type_len(in_t[1])).to_string(); - } - if fn_name == "unzip-2-in_len" { - return unzip2(type_len(in_t[1])).to_string(); - } - if fn_name.starts_with("dup") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let len = match &*fn_format[1] { - "out_len" => type_len(out_t), - "in_len" => type_len(in_t[1]), - "in0_len" => type_len(in_t[0]), - "halflen" => type_len(in_t[1]) / 2, - _ => 0, - }; - let mut s = "[".to_string(); - for i in 0..len { - if i != 0 { - s.push_str(", "); - } - s.push_str(&fn_format[2]); - } - s.push(']'); - return s; - } - if fn_name.starts_with("asc") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let start = match &*fn_format[1] { - "0" => 0, - "n" => n.unwrap(), - "out_len" => type_len(out_t) as i32, - "halflen" => (type_len(in_t[1]) / 2) as i32, - s => s.parse::().unwrap(), - }; - let len = match &*fn_format[2] { - "out_len" => type_len(out_t), - "in_len" => type_len(in_t[1]), - "in0_len" => type_len(in_t[0]), - "halflen" => type_len(in_t[1]) / 2, - _ => 0, - }; - return asc(start, len); - } - if fn_name.starts_with("base") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - assert_eq!(fn_format.len(), 3); - let mut s = "[".to_string(); - let base_len = fn_format[1].parse::().unwrap(); - for i in 0..type_len(in_t[1]) / base_len { - for j in 0..base_len { - if i != 0 || j != 0 { - s.push_str(", "); - } - s.push_str(&format!("{base_len} * {} as u32", fn_format[2])); - if j != 0 { - s.push_str(&format!(" + {j}")); - } - } - } - s.push(']'); - return s; - } - if fn_name.starts_with("as") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - assert_eq!(fn_format.len(), 3); - let t = match &*fn_format[2] { - "in_ttn" => type_to_native_type(in_t[1]), - _ => String::new(), - }; - return format!("{} as {t}", fn_format[1]); - } - if fn_name.starts_with("ins") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let n = n.unwrap(); - let len = match &*fn_format[1] { - "out_len" => type_len(out_t), - "in_len" => type_len(in_t[1]), - "in0_len" => type_len(in_t[0]), - _ => 0, - }; - let offset = match &*fn_format[2] { - "out_len" => type_len(out_t), - "in_len" => type_len(in_t[1]), - "in0_len" => type_len(in_t[0]), - _ => 0, - }; - let mut s = "[".to_string(); - for i in 0..len { - if i != 0 { - s.push_str(", "); - } - if i == n as usize { - s.push_str(&format!("{} + {} as u32", offset, fn_format[3])); - } else { - s.push_str(&i.to_string()); - } - } - s.push(']'); - return s; - } - if fn_name.starts_with("static_assert_imm") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let len = match &*fn_format[1] { - "out_exp_len" => type_exp_len(out_t, 1), - "out_bits_exp_len" => type_bits_exp_len(out_t), - "in_exp_len" => type_exp_len(in_t[1], 1), - "in_bits_exp_len" => type_bits_exp_len(in_t[1]), - "in0_exp_len" => type_exp_len(in_t[0], 1), - "in1_exp_len" => type_exp_len(in_t[1], 1), - "in2_exp_len" => type_exp_len(in_t[2], 1), - "in2_rot" => type_exp_len(in_t[2], 2), - "in2_dot" => type_exp_len(in_t[2], 4), - _ => 0, - }; - return if len == 0 { - format!(r#"static_assert!({} == 0);"#, fn_format[2]) - } else { - format!(r#"static_assert_uimm_bits!({}, {len});"#, fn_format[2]) - }; - } - if fn_name.starts_with("static_assert") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let lim1 = if fn_format[2] == "bits" { - type_bits(in_t[1]).to_string() - } else if fn_format[2] == "halfbits" { - (type_bits(in_t[1]) / 2).to_string() - } else { - fn_format[2].clone() - }; - let lim2 = if fn_format[3] == "bits" { - type_bits(in_t[1]).to_string() - } else if fn_format[3] == "halfbits" { - (type_bits(in_t[1]) / 2).to_string() - } else { - fn_format[3].clone() - }; - if lim1 == lim2 { - return format!(r#"static_assert!({} == {lim1});"#, fn_format[1]); - } else { - return format!( - r#"static_assert!({} >= {lim1} && {} <= {lim2});"#, - fn_format[1], fn_format[1] - ); - } - } - if fn_name.starts_with("fix_right_shift_imm") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let lim = if fn_format[2] == "bits" { - type_bits(in_t[1]).to_string() - } else { - fn_format[2].clone() - }; - let fixed = if in_t[1].starts_with('u') { - format!("return vdup{nself}(0);", nself = type_to_n_suffix(in_t[1])) - } else { - (lim.parse::().unwrap() - 1).to_string() - }; - - return format!( - r#"let {name}: i32 = if {const_name} == {upper} {{ {fixed} }} else {{ N }};"#, - name = fn_format[1].to_lowercase(), - const_name = fn_format[1], - upper = lim, - fixed = fixed, - ); - } - - if fn_name.starts_with("matchn") { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - let len = match &*fn_format[1] { - "out_exp_len" => type_exp_len(out_t, 1), - "in_exp_len" => type_exp_len(in_t[1], 1), - "in0_exp_len" => type_exp_len(in_t[0], 1), - _ => 0, - }; - let mut call = format!("match {} & 0b{} {{\n", &fn_format[2], "1".repeat(len)); - let mut sub_call = String::new(); - for param in params[1..].iter() { - if !sub_call.is_empty() { - sub_call.push_str(", "); - } - sub_call.push_str(param); - } - for i in 0..(2u32.pow(len as u32) as usize) { - let sub_match = format!( - " {} => {},\n", - i, - get_call( - &sub_call, - current_name, - in_t, - out_t, - fixed, - Some(i as i32), - aarch64 - ) - ); - call.push_str(&sub_match); - } - call.push_str(" _ => unreachable_unchecked(),\n }"); - return call; - } - let mut re: Option<(String, String)> = None; - let mut param_str = String::new(); - let mut i = 1; - while i < params.len() { - let s = ¶ms[i]; - if s.starts_with('{') { - let mut sub_fn = String::new(); - let mut parentheses = 0; - while i < params.len() { - if !sub_fn.is_empty() { - sub_fn.push_str(", "); - } - sub_fn.push_str(¶ms[i]); - let l = params[i].len(); - for j in 0..l { - if ¶ms[i][j..j + 1] == "{" { - parentheses += 1; - } else { - break; - } - } - for j in 0..l { - if ¶ms[i][l - j - 1..l - j] == "}" { - parentheses -= 1; - } else { - break; - } - } - if parentheses == 0 { - break; - } - i += 1; - } - let sub_call = get_call( - &sub_fn[1..sub_fn.len() - 1], - current_name, - in_t, - out_t, - fixed, - n, - aarch64, - ); - if !param_str.is_empty() { - param_str.push_str(", "); - } - param_str.push_str(&sub_call); - } else if s.contains(':') { - let re_params: Vec<_> = s.split(':').map(|v| v.to_string()).collect(); - #[allow(clippy::if_same_then_else)] - if re_params[1].is_empty() { - re = Some((re_params[0].clone(), in_t[1].to_string())); - } else if re_params[1] == "in_t" { - re = Some((re_params[0].clone(), in_t[1].to_string())); - } else if re_params[1] == "signed" { - re = Some((re_params[0].clone(), type_to_signed(in_t[1]))); - } else if re_params[1] == "unsigned" { - re = Some((re_params[0].clone(), type_to_unsigned(in_t[1]))); - } else if re_params[1] == "in_t0" { - re = Some((re_params[0].clone(), in_t[0].to_string())); - } else if re_params[1] == "in_t1" { - re = Some((re_params[0].clone(), in_t[1].to_string())); - } else if re_params[1] == "out_t" { - re = Some((re_params[0].clone(), out_t.to_string())); - } else if re_params[1] == "out_unsigned" { - re = Some((re_params[0].clone(), type_to_unsigned(out_t).to_string())); - } else if re_params[1] == "out_signed" { - re = Some((re_params[0].clone(), type_to_signed(out_t).to_string())); - } else if re_params[1] == "merge4_t2" { - re = Some((re_params[0].clone(), type_with_merged_lanes(in_t[2], 4))); - } else if re_params[1] == "half" { - re = Some((re_params[0].clone(), type_to_half(in_t[1]).to_string())); - } else if re_params[1] == "in_ntt" { - re = Some(( - re_params[0].clone(), - native_type_to_type(in_t[1]).to_string(), - )); - } else if re_params[1] == "in_long_ntt" { - re = Some(( - re_params[0].clone(), - native_type_to_long_type(in_t[1]).to_string(), - )); - } else if re_params[1] == "out_ntt" { - re = Some((re_params[0].clone(), native_type_to_type(out_t).to_string())); - } else if re_params[1] == "out_long_ntt" { - re = Some(( - re_params[0].clone(), - native_type_to_long_type(out_t).to_string(), - )); - } else { - re = Some((re_params[0].clone(), re_params[1].clone())); - } - } else { - if !param_str.is_empty() { - param_str.push_str(", "); - } - param_str.push_str(s); - } - i += 1; - } - if fn_name == "fixed" { - let (re_name, re_type) = re.unwrap(); - let fixed: Vec = fixed.iter().take(type_len(in_t[1])).cloned().collect(); - return format!(r#"let {re_name}{};"#, values(&re_type, &fixed)); - } - if fn_name == "fixed-half-right" { - let fixed: Vec = fixed.iter().take(type_len(in_t[1])).cloned().collect(); - let half = fixed[type_len(in_t[1]) / 2..] - .iter() - .fold(String::new(), |mut s, fix| { - s.push_str(fix); - s.push_str(", "); - s - }); - return format!(r#"[{}]"#, &half[..half.len() - 2]); - } - if fn_name == "a - b" { - return fn_name; - } - if fn_name == "-a" { - return fn_name; - } - if fn_name.contains('-') { - let fn_format: Vec<_> = fn_name.split('-').map(|v| v.to_string()).collect(); - assert_eq!(fn_format.len(), 3); - fn_name = if fn_format[0] == "self" { - current_name.to_string() - } else { - fn_format[0].clone() - }; - if fn_format[1] == "self" { - fn_name.push_str(type_to_suffix(in_t[1])); - } else if fn_format[1] == "nself" { - fn_name.push_str(type_to_n_suffix(in_t[1])); - } else if fn_format[1] == "nselfvfp4" { - fn_name.push_str(type_to_n_suffix(in_t[1])); - if !aarch64 { - fn_name.push_str("_vfp4"); - } - } else if fn_format[1] == "out" { - fn_name.push_str(type_to_suffix(out_t)); - } else if fn_format[1] == "in0" { - fn_name.push_str(type_to_suffix(in_t[0])); - } else if fn_format[1] == "in2" { - fn_name.push_str(type_to_suffix(in_t[2])); - } else if fn_format[1] == "in2lane" { - fn_name.push_str(&type_to_lane_suffixes(out_t, in_t[2], false)); - } else if fn_format[1] == "outlane" { - fn_name.push_str(&type_to_lane_suffixes(out_t, in_t[2], true)); - } else if fn_format[1] == "signed" { - fn_name.push_str(type_to_suffix(&type_to_signed(&String::from(in_t[1])))); - } else if fn_format[1] == "outsigned" { - fn_name.push_str(type_to_suffix(&type_to_signed(&String::from(out_t)))); - } else if fn_format[1] == "outsignednox" { - fn_name.push_str(type_to_suffix(&type_to_sub_type(&type_to_signed( - &String::from(out_t), - )))); - } else if fn_format[1] == "in1signednox" { - fn_name.push_str(type_to_suffix(&type_to_sub_type(&type_to_signed( - &String::from(in_t[1]), - )))); - } else if fn_format[1] == "outsigneddupnox" { - fn_name.push_str(&type_to_dup_suffix(&type_to_sub_type(&type_to_signed( - &String::from(out_t), - )))); - } else if fn_format[1] == "outsignedlanenox" { - fn_name.push_str(&type_to_lane_suffix(&type_to_sub_type(&type_to_signed( - &String::from(out_t), - )))); - } else if fn_format[1] == "in1signedlanenox" { - fn_name.push_str(&type_to_lane_suffix(&type_to_sub_type(&type_to_signed( - &String::from(in_t[1]), - )))); - } else if fn_format[1] == "unsigned" { - fn_name.push_str(type_to_suffix(&type_to_unsigned(in_t[1]))); - } else if fn_format[1] == "doubleself" { - fn_name.push_str(&type_to_double_suffixes(out_t, in_t[1])); - } else if fn_format[1] == "noq_doubleself" { - fn_name.push_str(&type_to_noq_double_suffixes(out_t, in_t[1])); - } else if fn_format[1] == "noqself" { - fn_name.push_str(type_to_noq_suffix(in_t[1])); - } else if fn_format[1] == "noqsigned" { - fn_name.push_str(type_to_noq_suffix(&type_to_signed(&String::from(in_t[1])))); - } else if fn_format[1] == "nosuffix" { - } else if fn_format[1] == "in_len" { - fn_name.push_str(&type_len(in_t[1]).to_string()); - } else if fn_format[1] == "in0_len" { - fn_name.push_str(&type_len(in_t[0]).to_string()); - } else if fn_format[1] == "out_len" { - fn_name.push_str(&type_len(out_t).to_string()); - } else if fn_format[1] == "halflen" { - fn_name.push_str(&(type_len(in_t[1]) / 2).to_string()); - } else if fn_format[1] == "nout" { - fn_name.push_str(type_to_n_suffix(out_t)); - } else if fn_format[1] == "nin0" { - fn_name.push_str(type_to_n_suffix(in_t[0])); - } else if fn_format[1] == "nsigned" { - fn_name.push_str(type_to_n_suffix(&type_to_signed(&String::from(in_t[1])))); - } else if fn_format[1] == "in_ntt" { - fn_name.push_str(type_to_suffix(native_type_to_type(in_t[1]))); - } else if fn_format[1] == "out_ntt" { - fn_name.push_str(type_to_suffix(native_type_to_type(out_t))); - } else if fn_format[1] == "rot" { - fn_name = type_to_rot_suffix(&fn_name, type_to_suffix(out_t)); - } else { - fn_name.push_str(&fn_format[1]); - }; - if fn_format[2] == "ext" { - fn_name.push('_'); - } else if fn_format[2] == "noext" { - } else if fn_format[2].starts_with('<') { - assert!(fn_format[2].ends_with('>')); - let types: Vec<_> = fn_format[2][1..fn_format[2].len() - 1] - .split(' ') - .map(|v| v.to_string()) - .collect(); - assert_eq!(types.len(), 2); - let type1 = if types[0] == "element_t" { - type_to_native_type(in_t[1]) - } else { - String::from(&types[0]) - }; - let type2 = if types[1] == "element_t" { - type_to_native_type(in_t[1]) - } else { - String::from(&types[1]) - }; - fn_name.push_str(&format!("::<{type1}, {type2}>")); - } else { - fn_name.push_str(&fn_format[2]); - } - } - if param_str.is_empty() { - fn_name.replace("out_t", out_t) - } else if let Some((re_name, re_type)) = re.clone() { - format!("let {re_name}: {re_type} = {fn_name}({param_str});") - } else if fn_name.starts_with('*') { - format!("{fn_name} = {param_str};") - } else { - format!("{fn_name}({param_str})") - } -} - -fn main() -> io::Result<()> { - let args: Vec = env::args().collect(); - let in_file = args.get(1).cloned().unwrap_or_else(|| IN.to_string()); - - let f = File::open(in_file).expect("Failed to open neon.spec"); - let f = BufReader::new(f); - - let mut current_comment = String::new(); - let mut current_name: Option = None; - let mut current_fn: Option = None; - let mut current_arm: Option = None; - let mut current_aarch64: Option = None; - let mut link_arm: Option = None; - let mut link_aarch64: Option = None; - let mut const_arm: Option = None; - let mut const_aarch64: Option = None; - let mut constn: Option = None; - let mut para_num = 2; - let mut suffix: Suffix = Normal; - let mut a: Vec = Vec::new(); - let mut b: Vec = Vec::new(); - let mut c: Vec = Vec::new(); - let mut n: Option = None; - let mut fixed: Vec = Vec::new(); - let mut current_tests: Vec<( - Vec, - Vec, - Vec, - Option, - Vec, - )> = Vec::new(); - let mut multi_fn: Vec = Vec::new(); - let mut target: TargetFeature = Default; - let mut fn_type: Fntype = Fntype::Normal; - let mut separate = false; - let mut assert_instr_cfg = None; - - // - // THIS FILE IS GENERATED FORM neon.spec DO NOT CHANGE IT MANUALLY - // - let mut out_arm = String::from( - r#"// This code is automatically generated. DO NOT MODIFY. -// -// Instead, modify `crates/stdarch-gen-arm/neon.spec` and run the following command to re-generate this file: -// -// ``` -// OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-arm -- crates/stdarch-gen-arm/neon.spec -// ``` -use super::*; -#[cfg(test)] -use stdarch_test::assert_instr; -"#, - ); - let mut tests_arm = String::from( - r#" -#[cfg(test)] -#[allow(overflowing_literals)] -mod test { - use super::*; - use crate::core_arch::simd::*; - use std::mem::transmute; - use stdarch_test::simd_test; -"#, - ); - // - // THIS FILE IS GENERATED FORM neon.spec DO NOT CHANGE IT MANUALLY - // - let mut out_aarch64 = String::from( - r#"// This code is automatically generated. DO NOT MODIFY. -// -// Instead, modify `crates/stdarch-gen-arm/neon.spec` and run the following command to re-generate this file: -// -// ``` -// OUT_DIR=`pwd`/crates/core_arch cargo run -p stdarch-gen-arm -- crates/stdarch-gen-arm/neon.spec -// ``` -use super::*; -#[cfg(test)] -use stdarch_test::assert_instr; -"#, - ); - let mut tests_aarch64 = String::from( - r#" -#[cfg(test)] -mod test { - use super::*; - use crate::core_arch::simd::*; - use std::mem::transmute; - use stdarch_test::simd_test; -"#, - ); - - for line in f.lines() { - let line = line.unwrap(); - if line.is_empty() { - continue; - } - if line.starts_with("/// ") { - current_comment = line; - current_name = None; - current_fn = None; - current_arm = None; - current_aarch64 = None; - link_aarch64 = None; - link_arm = None; - const_aarch64 = None; - const_arm = None; - current_tests = Vec::new(); - constn = None; - para_num = 2; - suffix = Normal; - a = Vec::new(); - b = Vec::new(); - c = Vec::new(); - fixed = Vec::new(); - n = None; - multi_fn = Vec::new(); - target = Default; - fn_type = Fntype::Normal; - separate = false; - } else if line.starts_with("//") { - } else if let Some(line) = line.strip_prefix("name = ") { - current_name = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("fn = ") { - current_fn = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("multi_fn = ") { - multi_fn.push(String::from(line)); - } else if let Some(line) = line.strip_prefix("constn = ") { - constn = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("arm = ") { - current_arm = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("aarch64 = ") { - current_aarch64 = Some(String::from(line)); - } else if line.starts_with("double-suffixes") { - suffix = Double; - } else if line.starts_with("no-q") { - suffix = NoQ; - } else if line.starts_with("noq-double-suffixes") { - suffix = NoQDouble; - } else if line.starts_with("n-suffix") { - suffix = NSuffix; - } else if line.starts_with("double-n-suffixes") { - suffix = DoubleN; - } else if line.starts_with("out-n-suffix") { - suffix = OutNSuffix; - } else if line.starts_with("noq-n-suffix") { - suffix = NoQNSuffix; - } else if line.starts_with("out-suffix") { - suffix = OutSuffix; - } else if line.starts_with("out-nox") { - suffix = OutNox; - } else if line.starts_with("in1-nox") { - suffix = In1Nox; - } else if line.starts_with("out-dup-nox") { - suffix = OutDupNox; - } else if line.starts_with("out-lane-nox") { - suffix = OutLaneNox; - } else if line.starts_with("in1-lane-nox") { - suffix = In1LaneNox; - } else if line.starts_with("lane-suffixes") { - suffix = Lane; - } else if line.starts_with("in2-suffix") { - suffix = In2; - } else if line.starts_with("in2-lane-suffixes") { - suffix = In2Lane; - } else if line.starts_with("out-lane-suffixes") { - suffix = OutLane; - } else if line.starts_with("rot-suffix") { - suffix = Rot; - } else if line.starts_with("rot-lane-suffixes") { - suffix = RotLane; - } else if let Some(line) = line.strip_prefix("a = ") { - a = line.split(',').map(|v| v.trim().to_string()).collect(); - } else if let Some(line) = line.strip_prefix("b = ") { - b = line.split(',').map(|v| v.trim().to_string()).collect(); - } else if let Some(line) = line.strip_prefix("c = ") { - c = line.split(',').map(|v| v.trim().to_string()).collect(); - } else if let Some(line) = line.strip_prefix("n = ") { - n = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("fixed = ") { - fixed = line.split(',').map(|v| v.trim().to_string()).collect(); - } else if let Some(line) = line.strip_prefix("validate ") { - let e = line.split(',').map(|v| v.trim().to_string()).collect(); - current_tests.push((a.clone(), b.clone(), c.clone(), n.clone(), e)); - } else if let Some(line) = line.strip_prefix("link-aarch64 = ") { - link_aarch64 = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("const-aarch64 = ") { - const_aarch64 = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("link-arm = ") { - link_arm = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("const-arm = ") { - const_arm = Some(String::from(line)); - } else if line.starts_with("load_fn") { - fn_type = Fntype::Load; - } else if line.starts_with("store_fn") { - fn_type = Fntype::Store; - } else if line.starts_with("arm-aarch64-separate") { - separate = true; - } else if let Some(line) = line.strip_prefix("target = ") { - target = match Some(String::from(line)) { - Some(input) => match input.as_str() { - "v7" => ArmV7, - "vfp4" => Vfp4, - "fp-armv8" => FPArmV8, - "aes" => Aes, - "fcma" => Fcma, - "dotprod" => Dotprod, - "i8mm" => I8MM, - "sha3" => Sha3, - "rdm" => Rdm, - "sm4" => Sm4, - "frintts" => Ftts, - _ => Default, - }, - _ => Default, - } - } else if let Some(line) = line.strip_prefix("assert_instr_cfg = ") { - assert_instr_cfg = Some(String::from(line)); - } else if let Some(line) = line.strip_prefix("generate ") { - let types: Vec = line - .split(',') - .map(|v| v.trim().to_string()) - .flat_map(|v| match v.as_str() { - "uint*_t" => UINT_TYPES.iter().map(|v| v.to_string()).collect(), - "uint64x*_t" => UINT_TYPES_64.iter().map(|v| v.to_string()).collect(), - "int*_t" => INT_TYPES.iter().map(|v| v.to_string()).collect(), - "int64x*_t" => INT_TYPES_64.iter().map(|v| v.to_string()).collect(), - "float*_t" => FLOAT_TYPES.iter().map(|v| v.to_string()).collect(), - "float64x*_t" => FLOAT_TYPES_64.iter().map(|v| v.to_string()).collect(), - _ => vec![v], - }) - .collect(); - - for line in types { - let spec: Vec<&str> = line.split(':').map(|e| e.trim()).collect(); - let in_t: [&str; 3]; - let out_t; - if spec.len() == 1 { - in_t = [spec[0], spec[0], spec[0]]; - out_t = spec[0]; - } else if spec.len() == 2 { - in_t = [spec[0], spec[0], spec[0]]; - out_t = spec[1]; - } else if spec.len() == 3 { - in_t = [spec[0], spec[1], spec[1]]; - out_t = spec[2]; - } else if spec.len() == 4 { - in_t = [spec[0], spec[1], spec[2]]; - out_t = spec[3]; - } else { - panic!("Bad spec: {line}") - } - if b.is_empty() { - if matches!(fn_type, Fntype::Store) { - para_num = 2; - } else { - para_num = 1; - } - } else if !c.is_empty() { - para_num = 3; - } - let current_name = current_name.clone().unwrap(); - if let Some(current_arm) = current_arm.clone() { - let (function, test) = gen_arm( - ¤t_comment, - current_fn.as_deref(), - ¤t_name, - ¤t_arm, - link_arm.as_deref(), - current_aarch64.as_deref(), - link_aarch64.as_deref(), - const_arm.as_deref(), - const_aarch64.as_deref(), - constn.as_deref(), - &in_t, - out_t, - ¤t_tests, - suffix, - para_num, - target, - &fixed, - &multi_fn, - fn_type, - separate, - ); - out_arm.push_str(&function); - tests_arm.push_str(&test); - } else { - let (function, test) = gen_aarch64( - ¤t_comment, - current_fn.as_deref(), - ¤t_name, - current_aarch64.as_deref(), - link_aarch64.as_deref(), - const_aarch64.as_deref(), - constn.as_deref(), - &in_t, - out_t, - ¤t_tests, - suffix, - para_num, - target, - &fixed, - &multi_fn, - fn_type, - assert_instr_cfg.as_deref(), - ); - out_aarch64.push_str(&function); - tests_aarch64.push_str(&test); - } - } - } - } - tests_arm.push('}'); - tests_arm.push('\n'); - tests_aarch64.push('}'); - tests_aarch64.push('\n'); - - let arm_out_path: PathBuf = - PathBuf::from(env::var("OUT_DIR").unwrap_or("crates/core_arch".to_string())) - .join("src") - .join("arm_shared") - .join("neon"); - std::fs::create_dir_all(&arm_out_path)?; - - let mut file_arm = File::create(arm_out_path.join(ARM_OUT))?; - file_arm.write_all(out_arm.as_bytes())?; - file_arm.write_all(tests_arm.as_bytes())?; - - let aarch64_out_path: PathBuf = - PathBuf::from(env::var("OUT_DIR").unwrap_or("crates/core_arch".to_string())) - .join("src") - .join("aarch64") - .join("neon"); - std::fs::create_dir_all(&aarch64_out_path)?; - - let mut file_aarch = File::create(aarch64_out_path.join(AARCH64_OUT))?; - file_aarch.write_all(out_aarch64.as_bytes())?; - file_aarch.write_all(tests_aarch64.as_bytes())?; - /* - if let Err(e) = Command::new("rustfmt") - .arg(&arm_out_path) - .arg(&aarch64_out_path) - .status() { - eprintln!("Could not format `{}`: {e}", arm_out_path.to_str().unwrap()); - eprintln!("Could not format `{}`: {e}", aarch64_out_path.to_str().unwrap()); - }; - */ - Ok(()) -} From 04ef1bdb19f1663294760d5ab504ae1f9617ab91 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Wed, 18 Dec 2024 15:42:53 +0000 Subject: [PATCH 5/8] PR feedback & pipeline --- Cargo.toml | 9 +- .../core_arch/src/aarch64/neon/generated.rs | 2 +- .../src/arm_shared/neon/generated.rs | 109 +- crates/core_arch/src/arm_shared/neon/mod.rs | 73 +- .../Cargo.toml | 5 +- .../spec/neon/aarch64.spec.yml | 2 +- .../spec/neon/arm_shared.spec.yml | 30 +- .../src/assert_instr.rs | 0 .../src/context.rs | 0 .../src/expression.rs | 0 .../src/fn_suffix.rs | 0 .../src/input.rs | 0 .../src/intrinsic.rs | 0 .../src/load_store_tests.rs | 0 .../src/main.rs | 0 .../src/matching.rs | 0 .../src/predicate_forms.rs | 0 .../src/typekinds.rs | 0 .../src/wildcards.rs | 0 .../src/wildstring.rs | 0 crates/stdarch-verify/src/lib.rs | 88 +- crates/stdarch-verify/tests/arm.rs | 172 +- intrinsics_data/arm_intrinsics.json | 190680 +-------------- 23 files changed, 137 insertions(+), 191033 deletions(-) rename crates/{stdarch-gen2 => stdarch-gen-arm}/Cargo.toml (79%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/spec/neon/aarch64.spec.yml (99%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/spec/neon/arm_shared.spec.yml (99%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/assert_instr.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/context.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/expression.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/fn_suffix.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/input.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/intrinsic.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/load_store_tests.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/main.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/matching.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/predicate_forms.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/typekinds.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/wildcards.rs (100%) rename crates/{stdarch-gen2 => stdarch-gen-arm}/src/wildstring.rs (100%) diff --git a/Cargo.toml b/Cargo.toml index d4864a24c4..0db26f31a2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -2,14 +2,7 @@ resolver = "1" members = [ "crates/*", - "examples" - "crates/stdarch-verify", - "crates/core_arch", - "crates/std_detect", - "crates/stdarch-gen-loongarch", - "crates/stdarch-gen2", - "crates/intrinsic-test", - "examples/" + "examples", ] exclude = [ "crates/wasm-assert-instr-tests" diff --git a/crates/core_arch/src/aarch64/neon/generated.rs b/crates/core_arch/src/aarch64/neon/generated.rs index 08f7aecdb6..cedc0c458b 100644 --- a/crates/core_arch/src/aarch64/neon/generated.rs +++ b/crates/core_arch/src/aarch64/neon/generated.rs @@ -7953,7 +7953,7 @@ pub unsafe fn vcvts_n_f32_u32(a: u32) -> f32 { #[rustc_legacy_const_generics(1)] #[stable(feature = "neon_intrinsics", since = "1.59.0")] pub unsafe fn vcvtd_n_f64_u64(a: u64) -> f64 { - static_assert!(N >= 1 && N <= 32); + static_assert!(N >= 1 && N <= 64); extern "unadjusted" { #[cfg_attr( any(target_arch = "aarch64", target_arch = "arm64ec"), diff --git a/crates/core_arch/src/arm_shared/neon/generated.rs b/crates/core_arch/src/arm_shared/neon/generated.rs index e89067142b..09be5282e9 100644 --- a/crates/core_arch/src/arm_shared/neon/generated.rs +++ b/crates/core_arch/src/arm_shared/neon/generated.rs @@ -15227,7 +15227,7 @@ pub unsafe fn vld4_lane_f32(a: *const f32, b: float32x2x4_t) -> size: i32, ) -> float32x2x4_t; } - vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vld4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15254,7 +15254,7 @@ pub unsafe fn vld4q_lane_f32(a: *const f32, b: float32x4x4_t) - size: i32, ) -> float32x4x4_t; } - vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vld4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15281,7 +15281,7 @@ pub unsafe fn vld4_lane_s8(a: *const i8, b: int8x8x4_t) -> int8 size: i32, ) -> int8x8x4_t; } - vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) + _vld4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15308,7 +15308,7 @@ pub unsafe fn vld4_lane_s16(a: *const i16, b: int16x4x4_t) -> i size: i32, ) -> int16x4x4_t; } - vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15335,7 +15335,7 @@ pub unsafe fn vld4q_lane_s16(a: *const i16, b: int16x8x4_t) -> size: i32, ) -> int16x8x4_t; } - vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vld4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15362,7 +15362,7 @@ pub unsafe fn vld4_lane_s32(a: *const i32, b: int32x2x4_t) -> i size: i32, ) -> int32x2x4_t; } - vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vld4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Load multiple 4-element structures to four registers"] @@ -15389,7 +15389,7 @@ pub unsafe fn vld4q_lane_s32(a: *const i32, b: int32x4x4_t) -> size: i32, ) -> int32x4x4_t; } - vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vld4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Load multiple 4-element structures to four registers"] @@ -25928,7 +25928,7 @@ pub unsafe fn vqrshrn_n_s32(a: int32x4_t) -> int16x4_t { } _vqrshrn_n_s32( a, - const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, + const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, ) } @@ -25948,7 +25948,7 @@ pub unsafe fn vqrshrn_n_s64(a: int64x2_t) -> int32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftns.v2i32")] fn _vqrshrn_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqrshrn_n_s64(a, const { int16x8_t([-N as i64, -N as i64]) }) + _vqrshrn_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }) } #[doc = "Signed saturating rounded shift right narrow"] @@ -26033,15 +26033,17 @@ pub unsafe fn vqrshrn_n_u16(a: uint16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v8i8")] fn _vqrshrn_n_u16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } - _vqrshrnq_n_u16( + _vqrshrn_n_u16( a.as_signed(), const { uint16x8_t([ -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, ]) - }, + } + .as_signed(), ) + .as_unsigned() } #[doc = "Unsigned signed saturating rounded shift right narrow"] @@ -26060,10 +26062,11 @@ pub unsafe fn vqrshrn_n_u32(a: uint32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v4i16")] fn _vqrshrn_n_u32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } - _vqrshrnq_n_u32( + _vqrshrn_n_u32( a.as_signed(), - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed(), ) + .as_unsigned() } #[doc = "Unsigned signed saturating rounded shift right narrow"] @@ -26082,7 +26085,11 @@ pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnu.v2i32")] fn _vqrshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqrshrnq_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) }) + _vqrshrn_n_u64( + a.as_signed(), + const { uint64x2_t([-N as u64, -N as u64]) }.as_signed(), + ) + .as_unsigned() } #[doc = "Unsigned signed saturating rounded shift right narrow"] @@ -26162,14 +26169,7 @@ pub unsafe fn vqrshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { - static_assert!( - const { - int16x8_t([ - -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, - -N as i16, - ]) - } - ); + static_assert!(N >= 1 && N <= 8); extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v8i8")] fn _vqrshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; @@ -26197,7 +26197,7 @@ pub unsafe fn vqrshrun_n_s16(a: int16x8_t) -> uint8x8_t { #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { - static_assert!(const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }); + static_assert!(N >= 1 && N <= 16); extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v4i16")] fn _vqrshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; @@ -26220,7 +26220,7 @@ pub unsafe fn vqrshrun_n_s32(a: int32x4_t) -> uint16x4_t { #[rustc_legacy_const_generics(1)] #[unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800")] pub unsafe fn vqrshrun_n_s64(a: int64x2_t) -> uint32x2_t { - static_assert!(const { int64x2_t([-N as i64, -N as i64]) }); + static_assert!(N >= 1 && N <= 32); extern "unadjusted" { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqrshiftnsu.v2i32")] fn _vqrshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; @@ -27773,7 +27773,8 @@ pub unsafe fn vqshrn_n_u16(a: uint16x8_t) -> uint8x8_t { -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, ]) - }, + } + .as_signed(), ) .as_unsigned() } @@ -27796,7 +27797,7 @@ pub unsafe fn vqshrn_n_u32(a: uint32x4_t) -> uint16x4_t { } _vqshrn_n_u32( a.as_signed(), - const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }, + const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed(), ) .as_unsigned() } @@ -27817,7 +27818,11 @@ pub unsafe fn vqshrn_n_u64(a: uint64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnu.v2i32")] fn _vqshrn_n_u64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqshrn_n_u64(a.as_signed(), const { uint64x2_t([-N as u64, -N as u64]) }).as_unsigned() + _vqshrn_n_u64( + a.as_signed(), + const { uint64x2_t([-N as u64, -N as u64]) }.as_signed(), + ) + .as_unsigned() } #[doc = "Unsigned saturating shift right narrow"] @@ -27902,7 +27907,7 @@ pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v8i8")] fn _vqshrun_n_s16(a: int16x8_t, n: int16x8_t) -> int8x8_t; } - _vqshrun_n_u8( + _vqshrun_n_s16( a, const { int16x8_t([ @@ -27911,6 +27916,7 @@ pub unsafe fn vqshrun_n_s16(a: int16x8_t) -> uint8x8_t { ]) }, ) + .as_unsigned() } #[doc = "Signed saturating shift right unsigned narrow"] @@ -27929,10 +27935,11 @@ pub unsafe fn vqshrun_n_s32(a: int32x4_t) -> uint16x4_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v4i16")] fn _vqshrun_n_s32(a: int32x4_t, n: int32x4_t) -> int16x4_t; } - _vqshrun_n_u16( + _vqshrun_n_s32( a, const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }, ) + .as_unsigned() } #[doc = "Signed saturating shift right unsigned narrow"] @@ -27951,7 +27958,7 @@ pub unsafe fn vqshrun_n_s64(a: int64x2_t) -> uint32x2_t { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vqshiftnsu.v2i32")] fn _vqshrun_n_s64(a: int64x2_t, n: int64x2_t) -> int32x2_t; } - _vqshrun_n_u32(a, const { int64x2_t([-N as i64, -N as i64]) }) + _vqshrun_n_s64(a, const { int64x2_t([-N as i64, -N as i64]) }).as_unsigned() } #[doc = "Signed saturating shift right unsigned narrow"] @@ -43688,7 +43695,7 @@ pub unsafe fn vst2_lane_f32(a: *mut f32, b: float32x2x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2f32")] fn _vst2_lane_f32(ptr: *mut i8, a: float32x2_t, b: float32x2_t, n: i32, size: i32); } - _vst2_f32(a as _, b.0, b.1, LANE, 4) + _vst2_lane_f32(a as _, b.0, b.1, LANE, 4) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43707,7 +43714,7 @@ pub unsafe fn vst2q_lane_f32(a: *mut f32, b: float32x4x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4f32")] fn _vst2q_lane_f32(ptr: *mut i8, a: float32x4_t, b: float32x4_t, n: i32, size: i32); } - _vst2q_f32(a as _, b.0, b.1, LANE, 4) + _vst2q_lane_f32(a as _, b.0, b.1, LANE, 4) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43726,7 +43733,7 @@ pub unsafe fn vst2_lane_s8(a: *mut i8, b: int8x8x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i8")] fn _vst2_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, n: i32, size: i32); } - _vst2_s8(a as _, b.0, b.1, LANE, 1) + _vst2_lane_s8(a as _, b.0, b.1, LANE, 1) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43745,7 +43752,7 @@ pub unsafe fn vst2_lane_s16(a: *mut i16, b: int16x4x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i16")] fn _vst2_lane_s16(ptr: *mut i8, a: int16x4_t, b: int16x4_t, n: i32, size: i32); } - _vst2_s16(a as _, b.0, b.1, LANE, 2) + _vst2_lane_s16(a as _, b.0, b.1, LANE, 2) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43764,7 +43771,7 @@ pub unsafe fn vst2q_lane_s16(a: *mut i16, b: int16x8x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v8i16")] fn _vst2q_lane_s16(ptr: *mut i8, a: int16x8_t, b: int16x8_t, n: i32, size: i32); } - _vst2q_s16(a as _, b.0, b.1, LANE, 2) + _vst2q_lane_s16(a as _, b.0, b.1, LANE, 2) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43783,7 +43790,7 @@ pub unsafe fn vst2_lane_s32(a: *mut i32, b: int32x2x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v2i32")] fn _vst2_lane_s32(ptr: *mut i8, a: int32x2_t, b: int32x2_t, n: i32, size: i32); } - _vst2_s32(a as _, b.0, b.1, LANE, 4) + _vst2_lane_s32(a as _, b.0, b.1, LANE, 4) } #[doc = "Store multiple 2-element structures from two registers"] @@ -43802,7 +43809,7 @@ pub unsafe fn vst2q_lane_s32(a: *mut i32, b: int32x4x2_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst2lane.p0i8.v4i32")] fn _vst2q_lane_s32(ptr: *mut i8, a: int32x4_t, b: int32x4_t, n: i32, size: i32); } - _vst2q_s32(a as _, b.0, b.1, LANE, 4) + _vst2q_lane_s32(a as _, b.0, b.1, LANE, 4) } #[doc = "Store multiple 2-element structures from two registers"] @@ -44657,7 +44664,7 @@ pub unsafe fn vst3_lane_f32(a: *mut f32, b: float32x2x3_t) { size: i32, ); } - _vst3_f32(a as _, b.0, b.1, b.2, LANE, 4) + _vst3_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44683,7 +44690,7 @@ pub unsafe fn vst3q_lane_f32(a: *mut f32, b: float32x4x3_t) { size: i32, ); } - _vst3q_f32(a as _, b.0, b.1, b.2, LANE, 4) + _vst3q_lane_f32(a as _, b.0, b.1, b.2, LANE, 4) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44702,7 +44709,7 @@ pub unsafe fn vst3_lane_s8(a: *mut i8, b: int8x8x3_t) { #[cfg_attr(target_arch = "arm", link_name = "llvm.arm.neon.vst3lane.p0i8.v8i8")] fn _vst3_lane_s8(ptr: *mut i8, a: int8x8_t, b: int8x8_t, c: int8x8_t, n: i32, size: i32); } - _vst3_s8(a as _, b.0, b.1, b.2, LANE, 1) + _vst3_lane_s8(a as _, b.0, b.1, b.2, LANE, 1) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44728,7 +44735,7 @@ pub unsafe fn vst3_lane_s16(a: *mut i16, b: int16x4x3_t) { size: i32, ); } - _vst3_s16(a as _, b.0, b.1, b.2, LANE, 2) + _vst3_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44754,7 +44761,7 @@ pub unsafe fn vst3q_lane_s16(a: *mut i16, b: int16x8x3_t) { size: i32, ); } - _vst3q_s16(a as _, b.0, b.1, b.2, LANE, 2) + _vst3q_lane_s16(a as _, b.0, b.1, b.2, LANE, 2) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44780,7 +44787,7 @@ pub unsafe fn vst3_lane_s32(a: *mut i32, b: int32x2x3_t) { size: i32, ); } - _vst3_s32(a as _, b.0, b.1, b.2, LANE, 4) + _vst3_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } #[doc = "Store multiple 3-element structures from three registers"] @@ -44806,7 +44813,7 @@ pub unsafe fn vst3q_lane_s32(a: *mut i32, b: int32x4x3_t) { size: i32, ); } - _vst3q_s32(a as _, b.0, b.1, b.2, LANE, 4) + _vst3q_lane_s32(a as _, b.0, b.1, b.2, LANE, 4) } #[doc = "Store multiple 3-element structures from three registers"] @@ -45865,7 +45872,7 @@ pub unsafe fn vst4_lane_f32(a: *mut f32, b: float32x2x4_t) { size: i32, ); } - _vst4_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vst4_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Store multiple 4-element structures from four registers"] @@ -45892,7 +45899,7 @@ pub unsafe fn vst4q_lane_f32(a: *mut f32, b: float32x4x4_t) { size: i32, ); } - _vst4q_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vst4q_lane_f32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Store multiple 4-element structures from four registers"] @@ -45919,7 +45926,7 @@ pub unsafe fn vst4_lane_s8(a: *mut i8, b: int8x8x4_t) { size: i32, ); } - _vst4_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) + _vst4_lane_s8(a as _, b.0, b.1, b.2, b.3, LANE, 1) } #[doc = "Store multiple 4-element structures from four registers"] @@ -45946,7 +45953,7 @@ pub unsafe fn vst4_lane_s16(a: *mut i16, b: int16x4x4_t) { size: i32, ); } - _vst4_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vst4_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } #[doc = "Store multiple 4-element structures from four registers"] @@ -45973,7 +45980,7 @@ pub unsafe fn vst4q_lane_s16(a: *mut i16, b: int16x8x4_t) { size: i32, ); } - _vst4q_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) + _vst4q_lane_s16(a as _, b.0, b.1, b.2, b.3, LANE, 2) } #[doc = "Store multiple 4-element structures from four registers"] @@ -46000,7 +46007,7 @@ pub unsafe fn vst4_lane_s32(a: *mut i32, b: int32x2x4_t) { size: i32, ); } - _vst4_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vst4_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Store multiple 4-element structures from four registers"] @@ -46027,7 +46034,7 @@ pub unsafe fn vst4q_lane_s32(a: *mut i32, b: int32x4x4_t) { size: i32, ); } - _vst4q_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) + _vst4q_lane_s32(a as _, b.0, b.1, b.2, b.3, LANE, 4) } #[doc = "Store multiple 4-element structures from four registers"] diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index 52707f527d..fe5f8361e0 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -11,89 +11,33 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::* #[cfg(test)] use stdarch_test::assert_instr; -#[unstable(feature = "stdarch_internal", issue = "none")] pub(crate) trait AsUnsigned { type Unsigned: ?Sized; - unsafe fn as_unsigned(self) -> Self::Unsigned; + fn as_unsigned(self) -> Self::Unsigned; } -#[unstable(feature = "stdarch_internal", issue = "none")] pub(crate) trait AsSigned { type Signed: ?Sized; - unsafe fn as_signed(self) -> Self::Signed; -} - -macro_rules! impl_sign_conversions { - ($(($signed:ty, $unsigned:ty))*) => ($( - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] - impl AsUnsigned for $signed { - type Unsigned = $unsigned; - - #[inline] - unsafe fn as_unsigned(self) -> $unsigned { - crate::mem::transmute(self) - } - } - - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] - impl AsSigned for $unsigned { - type Signed = $signed; - - #[inline] - unsafe fn as_signed(self) -> $signed { - crate::mem::transmute(self) - } - } - )*) + fn as_signed(self) -> Self::Signed; } macro_rules! impl_sign_conversions_neon { ($(($signed:ty, $unsigned:ty))*) => ($( - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] impl AsUnsigned for $signed { type Unsigned = $unsigned; #[inline] - unsafe fn as_unsigned(self) -> $unsigned { - crate::mem::transmute(self) + fn as_unsigned(self) -> $unsigned { + unsafe { transmute(self) } } } - #[cfg_attr( - not(target_arch = "arm"), - stable(feature = "neon_intrinsics", since = "1.59.0") - )] - #[cfg_attr( - target_arch = "arm", - unstable(feature = "stdarch_arm_neon_intrinsics", issue = "111800") - )] impl AsSigned for $unsigned { type Signed = $signed; #[inline] - unsafe fn as_signed(self) -> $signed { - crate::mem::transmute(self) + fn as_signed(self) -> $signed { + unsafe { transmute(self) } } } )*) @@ -1121,7 +1065,7 @@ pub struct poly64x2x4_t( pub poly64x2_t, ); -impl_sign_conversions! { +impl_sign_conversions_neon! { (i8, u8) (i16, u16) (i32, u32) @@ -1150,9 +1094,6 @@ impl_sign_conversions! { (uint64x2_t, int64x2_t) (uint8x16_t, int8x16_t) (uint8x8_t, int8x8_t) -} - -impl_sign_conversions_neon! { (int16x4x2_t, uint16x4x2_t) (int16x4x3_t, uint16x4x3_t) (int16x4x4_t, uint16x4x4_t) diff --git a/crates/stdarch-gen2/Cargo.toml b/crates/stdarch-gen-arm/Cargo.toml similarity index 79% rename from crates/stdarch-gen2/Cargo.toml rename to crates/stdarch-gen-arm/Cargo.toml index c9a039ea6b..3cc4982549 100644 --- a/crates/stdarch-gen2/Cargo.toml +++ b/crates/stdarch-gen-arm/Cargo.toml @@ -1,10 +1,11 @@ [package] -name = "stdarch-gen2" +name = "stdarch-gen-arm" version = "0.1.0" authors = ["Luca Vizzarro ", "Jamie Cunliffe ", "Adam Gemmell "] + "Jacob Bramley ", + "James Barford-Evans "] license = "MIT OR Apache-2.0" edition = "2021" diff --git a/crates/stdarch-gen2/spec/neon/aarch64.spec.yml b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml similarity index 99% rename from crates/stdarch-gen2/spec/neon/aarch64.spec.yml rename to crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml index fd704c305e..6f622b18be 100644 --- a/crates/stdarch-gen2/spec/neon/aarch64.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/aarch64.spec.yml @@ -1089,7 +1089,7 @@ intrinsics: - ["u32", "f32", 's_n_f32_u32', 'N >= 1 && N <= 32'] - ["u64", "f64", 'd_n_f64_u64', 'N >= 1 && N <= 64'] compose: - - FnCall: [static_assert!, ['N >= 1 && N <= 32']] + - FnCall: [static_assert!, ["{type[3]}"]] - LLVMLink: name: "vcvt{type[2]}" arguments: diff --git a/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml similarity index 99% rename from crates/stdarch-gen2/spec/neon/arm_shared.spec.yml rename to crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml index 87559963ed..a3c26a709b 100644 --- a/crates/stdarch-gen2/spec/neon/arm_shared.spec.yml +++ b/crates/stdarch-gen-arm/spec/neon/arm_shared.spec.yml @@ -3687,7 +3687,7 @@ intrinsics: links: - link: 'llvm.arm.neon.vld4lane.v{neon_type[1].lane}{type[3]}.p0i8' arch: arm - - FnCall: ['vld4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', LANE, '{type[4]}']] + - FnCall: ['_vld4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', LANE, '{type[4]}']] - name: "vld4{neon_type[1].lane_nox}" doc: Load multiple 4-element structures to four registers @@ -4323,7 +4323,7 @@ intrinsics: links: - link: 'llvm.arm.neon.vst2lane.p0i8.v{neon_type[1].lane}{type[0]}' arch: arm - - FnCall: ['_vst2{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'LANE', "{type[4]}"]] + - FnCall: ['_vst2{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'LANE', "{type[4]}"]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -4538,7 +4538,7 @@ intrinsics: links: - link: 'llvm.arm.neon.vst3lane.p0i8.v{neon_type[1].lane}{type[0]}' arch: arm - - FnCall: ['_vst3{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', "{type[4]}"]] + - FnCall: ['_vst3{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'LANE', "{type[4]}"]] - name: "vst3{neon_type[1].nox}" doc: "Store multiple 3-element structures from three registers" @@ -4820,7 +4820,7 @@ intrinsics: links: - link: 'llvm.arm.neon.vst4lane.p0i8.v{neon_type[1].lane}{type[0]}' arch: arm - - FnCall: ['_vst4{neon_type[1].nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', 'LANE', "{type[4]}"]] + - FnCall: ['_vst4{neon_type[1].lane_nox}', ['a as _', 'b.0', 'b.1', 'b.2', 'b.3', 'LANE', "{type[4]}"]] - name: "vst4{neon_type[1].nox}" doc: "Store multiple 4-element structures from four registers" @@ -6473,8 +6473,8 @@ intrinsics: unsafe: [neon] types: - [int16x8_t, int8x8_t, 'N >= 1 && N <= 8', 'const { int16x8_t([-N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16, -N as i16]) }'] - - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int16x8_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] - - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int16x8_t([-N as i64, -N as i64]) }'] + - [int32x4_t, int16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] + - [int64x2_t, int32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] compose: - FnCall: [static_assert!, ["{type[2]}"]] - LLVMLink: @@ -6533,7 +6533,7 @@ intrinsics: - [int32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { int32x4_t([-N as i32, -N as i32, -N as i32, -N as i32]) }'] - [int64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { int64x2_t([-N as i64, -N as i64]) }'] compose: - - FnCall: [static_assert!, ["{type[3]}"]] + - FnCall: [static_assert!, ["{type[2]}"]] - LLVMLink: name: "vqrshrun_n{neon_type[0].noq}" arguments: @@ -6766,9 +6766,9 @@ intrinsics: safety: unsafe: [neon] types: - - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, 'N >= 1 && N <= 8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }.as_signed()'] + - [uint32x4_t, uint16x4_t, 'N >= 1 && N <= 16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed()'] + - [uint64x2_t, uint32x2_t, 'N >= 1 && N <= 32', 'const { uint64x2_t([-N as u64, -N as u64]) }.as_signed()'] compose: - FnCall: [static_assert!, ["{type[2]}"]] - LLVMLink: @@ -6836,7 +6836,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqshiftnsu.{neon_type[1]}" arch: arm - - FnCall: ["_vqshrun_n_{neon_type[1]}", [a, "{type[3]}"]] + - FnCall: ["_vqshrun_n_{neon_type[0]}", [a, "{type[3]}"]] - name: "vqshrun_n_{neon_type[0]}" doc: "Signed saturating shift right unsigned narrow" @@ -8784,9 +8784,9 @@ intrinsics: safety: unsafe: [neon] types: - - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }'] - - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }'] - - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }'] + - [uint16x8_t, uint8x8_t, '8', 'const { uint16x8_t([-N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16, -N as u16]) }.as_signed()'] + - [uint32x4_t, uint16x4_t, '16', 'const { uint32x4_t([-N as u32, -N as u32, -N as u32, -N as u32]) }.as_signed()'] + - [uint64x2_t, uint32x2_t, '32', 'const { uint64x2_t([-N as u64, -N as u64]) }.as_signed()'] compose: - FnCall: [static_assert!, ['N >= 1 && N <= {type[2]}']] - LLVMLink: @@ -8797,7 +8797,7 @@ intrinsics: links: - link: "llvm.arm.neon.vqrshiftnu.{neon_type[1]}" arch: arm - - FnCall: ["_vqrshrn{neon_type[0].N}", ["a.as_signed()", "{type[3]}"]] + - FnCall: ["_vqrshrn_n{neon_type[0].noq}", ["a.as_signed()", "{type[3]}"]] - name: "vqrshrn_n_{neon_type[0]}" doc: "Unsigned signed saturating rounded shift right narrow" diff --git a/crates/stdarch-gen2/src/assert_instr.rs b/crates/stdarch-gen-arm/src/assert_instr.rs similarity index 100% rename from crates/stdarch-gen2/src/assert_instr.rs rename to crates/stdarch-gen-arm/src/assert_instr.rs diff --git a/crates/stdarch-gen2/src/context.rs b/crates/stdarch-gen-arm/src/context.rs similarity index 100% rename from crates/stdarch-gen2/src/context.rs rename to crates/stdarch-gen-arm/src/context.rs diff --git a/crates/stdarch-gen2/src/expression.rs b/crates/stdarch-gen-arm/src/expression.rs similarity index 100% rename from crates/stdarch-gen2/src/expression.rs rename to crates/stdarch-gen-arm/src/expression.rs diff --git a/crates/stdarch-gen2/src/fn_suffix.rs b/crates/stdarch-gen-arm/src/fn_suffix.rs similarity index 100% rename from crates/stdarch-gen2/src/fn_suffix.rs rename to crates/stdarch-gen-arm/src/fn_suffix.rs diff --git a/crates/stdarch-gen2/src/input.rs b/crates/stdarch-gen-arm/src/input.rs similarity index 100% rename from crates/stdarch-gen2/src/input.rs rename to crates/stdarch-gen-arm/src/input.rs diff --git a/crates/stdarch-gen2/src/intrinsic.rs b/crates/stdarch-gen-arm/src/intrinsic.rs similarity index 100% rename from crates/stdarch-gen2/src/intrinsic.rs rename to crates/stdarch-gen-arm/src/intrinsic.rs diff --git a/crates/stdarch-gen2/src/load_store_tests.rs b/crates/stdarch-gen-arm/src/load_store_tests.rs similarity index 100% rename from crates/stdarch-gen2/src/load_store_tests.rs rename to crates/stdarch-gen-arm/src/load_store_tests.rs diff --git a/crates/stdarch-gen2/src/main.rs b/crates/stdarch-gen-arm/src/main.rs similarity index 100% rename from crates/stdarch-gen2/src/main.rs rename to crates/stdarch-gen-arm/src/main.rs diff --git a/crates/stdarch-gen2/src/matching.rs b/crates/stdarch-gen-arm/src/matching.rs similarity index 100% rename from crates/stdarch-gen2/src/matching.rs rename to crates/stdarch-gen-arm/src/matching.rs diff --git a/crates/stdarch-gen2/src/predicate_forms.rs b/crates/stdarch-gen-arm/src/predicate_forms.rs similarity index 100% rename from crates/stdarch-gen2/src/predicate_forms.rs rename to crates/stdarch-gen-arm/src/predicate_forms.rs diff --git a/crates/stdarch-gen2/src/typekinds.rs b/crates/stdarch-gen-arm/src/typekinds.rs similarity index 100% rename from crates/stdarch-gen2/src/typekinds.rs rename to crates/stdarch-gen-arm/src/typekinds.rs diff --git a/crates/stdarch-gen2/src/wildcards.rs b/crates/stdarch-gen-arm/src/wildcards.rs similarity index 100% rename from crates/stdarch-gen2/src/wildcards.rs rename to crates/stdarch-gen-arm/src/wildcards.rs diff --git a/crates/stdarch-gen2/src/wildstring.rs b/crates/stdarch-gen-arm/src/wildstring.rs similarity index 100% rename from crates/stdarch-gen2/src/wildstring.rs rename to crates/stdarch-gen-arm/src/wildstring.rs diff --git a/crates/stdarch-verify/src/lib.rs b/crates/stdarch-verify/src/lib.rs index c53f1e6297..5e4db96a70 100644 --- a/crates/stdarch-verify/src/lib.rs +++ b/crates/stdarch-verify/src/lib.rs @@ -45,9 +45,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { for &mut (ref mut file, ref path) in &mut files { for mut item in file.items.drain(..) { match item { - syn::Item::Fn(f) => { - functions.push((f, path)); - } + syn::Item::Fn(f) => functions.push((f, path)), syn::Item::Mod(ref mut m) => { if let Some(ref mut m) = m.content { for i in m.1.drain(..) { @@ -73,9 +71,12 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { assert!(!tests.is_empty()); functions.retain(|(f, _)| { - matches!(f.vis, syn::Visibility::Public(_)) - // Many SVE intrinsics are safe - && (f.sig.unsafety.is_some() || f.sig.ident.to_string().starts_with("sv")) + if let syn::Visibility::Public(_) = f.vis { + if f.sig.unsafety.is_some() { + return true; + } + } + false }); assert!(!functions.is_empty()); @@ -98,7 +99,7 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { for generic in f.sig.generics.params.iter() { match *generic { syn::GenericParam::Const(ref c) => const_arguments.push(to_type(&c.ty)), - syn::GenericParam::Type(_) => (), + syn::GenericParam::Type(ref _t) => (), _ => panic!("invalid generic argument on {name}"), }; } @@ -117,31 +118,25 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { }; let required_const = find_required_const("rustc_args_required_const", &f.attrs); - let mut const_generics_indices = + let mut legacy_const_generics = find_required_const("rustc_legacy_const_generics", &f.attrs); - if !required_const.is_empty() && !const_generics_indices.is_empty() { + if !required_const.is_empty() && !legacy_const_generics.is_empty() { panic!( "Can't have both #[rustc_args_required_const] and \ #[rustc_legacy_const_generics]" ); } - // Newer intrinsics don't have legacy support - assume they belong at the end of the argument list - if required_const.is_empty() && const_generics_indices.is_empty() { - const_generics_indices = - (arguments.len()..(arguments.len() + const_arguments.len())).collect(); - } - // The list of required consts, used to verify the arguments, comes from either the // `rustc_args_required_const` or the `rustc_legacy_const_generics` attribute. let required_const = if required_const.is_empty() { - const_generics_indices.clone() + legacy_const_generics.clone() } else { required_const }; - const_generics_indices.sort(); - for (idx, ty) in const_generics_indices + legacy_const_generics.sort(); + for (idx, ty) in legacy_const_generics .into_iter() .zip(const_arguments.into_iter()) { @@ -150,12 +145,12 @@ fn functions(input: TokenStream, dirs: &[&str]) -> TokenStream { // strip leading underscore from fn name when building a test // _mm_foo -> mm_foo such that the test name is test_mm_foo. - let test_name = name.to_string(); - let test_name_id = test_name.trim_start_matches('_'); - let has_test = tests.contains(&format!("test_{test_name_id}")) - // SVE load/store tests - || tests.iter().any(|t| t.starts_with(&format!("test_{test_name_id}")) - || t.ends_with(&format!("_with_{test_name_id}"))); + let test_name_string = format!("{name}"); + let mut test_name_id = test_name_string.as_str(); + while test_name_id.starts_with('_') { + test_name_id = &test_name_id[1..]; + } + let has_test = tests.contains(&format!("test_{test_name_id}")); let doc = find_doc(&f.attrs); @@ -226,53 +221,8 @@ fn to_type(t: &syn::Type) -> proc_macro2::TokenStream { "p16" => quote! { &P16 }, "Ordering" => quote! { &ORDERING }, "CpuidResult" => quote! { &CPUID }, - "T" => quote! { &GENERICT }, // arm ... - "svbool_t" => quote! { &SVBOOL }, - "svint8_t" => quote! { &SVI8 }, - "svint8x2_t" => quote! { &SVI8X2 }, - "svint8x3_t" => quote! { &SVI8X3 }, - "svint8x4_t" => quote! { &SVI8X4 }, - "svint16_t" => quote! { &SVI16 }, - "svint16x2_t" => quote! { &SVI16X2 }, - "svint16x3_t" => quote! { &SVI16X3 }, - "svint16x4_t" => quote! { &SVI16X4 }, - "svint32_t" => quote! { &SVI32 }, - "svint32x2_t" => quote! { &SVI32X2 }, - "svint32x3_t" => quote! { &SVI32X3 }, - "svint32x4_t" => quote! { &SVI32X4 }, - "svint64_t" => quote! { &SVI64 }, - "svint64x2_t" => quote! { &SVI64X2 }, - "svint64x3_t" => quote! { &SVI64X3 }, - "svint64x4_t" => quote! { &SVI64X4 }, - "svuint8_t" => quote! { &SVU8 }, - "svuint8x2_t" => quote! { &SVU8X2 }, - "svuint8x3_t" => quote! { &SVU8X3 }, - "svuint8x4_t" => quote! { &SVU8X4 }, - "svuint16_t" => quote! { &SVU16 }, - "svuint16x2_t" => quote! { &SVU16X2 }, - "svuint16x3_t" => quote! { &SVU16X3 }, - "svuint16x4_t" => quote! { &SVU16X4 }, - "svuint32_t" => quote! { &SVU32 }, - "svuint32x2_t" => quote! { &SVU32X2 }, - "svuint32x3_t" => quote! { &SVU32X3 }, - "svuint32x4_t" => quote! { &SVU32X4 }, - "svuint64_t" => quote! { &SVU64 }, - "svuint64x2_t" => quote! { &SVU64X2 }, - "svuint64x3_t" => quote! { &SVU64X3 }, - "svuint64x4_t" => quote! { &SVU64X4 }, - "svfloat32_t" => quote! { &SVF32 }, - "svfloat32x2_t" => quote! { &SVF32X2 }, - "svfloat32x3_t" => quote! { &SVF32X3 }, - "svfloat32x4_t" => quote! { &SVF32X4 }, - "svfloat64_t" => quote! { &SVF64 }, - "svfloat64x2_t" => quote! { &SVF64X2 }, - "svfloat64x3_t" => quote! { &SVF64X3 }, - "svfloat64x4_t" => quote! { &SVF64X4 }, - "svprfop" => quote! { &SVPRFOP }, - "svpattern" => quote! { &SVPATTERN }, - "int8x4_t" => quote! { &I8X4 }, "int8x8_t" => quote! { &I8X8 }, "int8x8x2_t" => quote! { &I8X8X2 }, diff --git a/crates/stdarch-verify/tests/arm.rs b/crates/stdarch-verify/tests/arm.rs index fe51a6730c..a35b8175fb 100644 --- a/crates/stdarch-verify/tests/arm.rs +++ b/crates/stdarch-verify/tests/arm.rs @@ -27,8 +27,6 @@ static U16: Type = Type::PrimUnsigned(16); static U32: Type = Type::PrimUnsigned(32); static U64: Type = Type::PrimUnsigned(64); static U8: Type = Type::PrimUnsigned(8); -static BOOL: Type = Type::PrimBool; -static VOID: Type = Type::Void; static NEVER: Type = Type::Never; static GENERICT: Type = Type::GenericParam("T"); static GENERICU: Type = Type::GenericParam("U"); @@ -153,70 +151,19 @@ static U8X8X2: Type = Type::U(8, 8, 2); static U8X8X3: Type = Type::U(8, 8, 3); static U8X8X4: Type = Type::U(8, 8, 4); -static SVBOOL: Type = Type::Pred; -static SVF32: Type = Type::SVF(32, 1); -static SVF32X2: Type = Type::SVF(32, 2); -static SVF32X3: Type = Type::SVF(32, 3); -static SVF32X4: Type = Type::SVF(32, 4); -static SVF64: Type = Type::SVF(64, 1); -static SVF64X2: Type = Type::SVF(64, 2); -static SVF64X3: Type = Type::SVF(64, 3); -static SVF64X4: Type = Type::SVF(64, 4); -static SVI8: Type = Type::SVI(8, 1); -static SVI8X2: Type = Type::SVI(8, 2); -static SVI8X3: Type = Type::SVI(8, 3); -static SVI8X4: Type = Type::SVI(8, 4); -static SVI16: Type = Type::SVI(16, 1); -static SVI16X2: Type = Type::SVI(16, 2); -static SVI16X3: Type = Type::SVI(16, 3); -static SVI16X4: Type = Type::SVI(16, 4); -static SVI32: Type = Type::SVI(32, 1); -static SVI32X2: Type = Type::SVI(32, 2); -static SVI32X3: Type = Type::SVI(32, 3); -static SVI32X4: Type = Type::SVI(32, 4); -static SVI64: Type = Type::SVI(64, 1); -static SVI64X2: Type = Type::SVI(64, 2); -static SVI64X3: Type = Type::SVI(64, 3); -static SVI64X4: Type = Type::SVI(64, 4); -static SVU8: Type = Type::SVU(8, 1); -static SVU8X2: Type = Type::SVU(8, 2); -static SVU8X3: Type = Type::SVU(8, 3); -static SVU8X4: Type = Type::SVU(8, 4); -static SVU16: Type = Type::SVU(16, 1); -static SVU16X2: Type = Type::SVU(16, 2); -static SVU16X3: Type = Type::SVU(16, 3); -static SVU16X4: Type = Type::SVU(16, 4); -static SVU32: Type = Type::SVU(32, 1); -static SVU32X2: Type = Type::SVU(32, 2); -static SVU32X3: Type = Type::SVU(32, 3); -static SVU32X4: Type = Type::SVU(32, 4); -static SVU64: Type = Type::SVU(64, 1); -static SVU64X2: Type = Type::SVU(64, 2); -static SVU64X3: Type = Type::SVU(64, 3); -static SVU64X4: Type = Type::SVU(64, 4); -static SVPRFOP: Type = Type::Enum("svprfop"); -static SVPATTERN: Type = Type::Enum("svpattern"); - #[derive(Debug, Copy, Clone, PartialEq)] enum Type { - Void, - PrimBool, PrimFloat(u8), PrimSigned(u8), PrimUnsigned(u8), PrimPoly(u8), MutPtr(&'static Type), ConstPtr(&'static Type), - Enum(&'static str), GenericParam(&'static str), I(u8, u8, u8), U(u8, u8, u8), P(u8, u8, u8), F(u8, u8, u8), - Pred, - SVI(u8, u8), - SVU(u8, u8), - SVF(u8, u8), Never, } @@ -235,7 +182,6 @@ fn verify_all_signatures() { let mut all_valid = true; for rust in FUNCTIONS { - // Most SVE intrinsics just rely on the intrinsics test tool for validation if !rust.has_test { let skip = [ "vaddq_s64", @@ -461,18 +407,6 @@ fn verify_all_signatures() { "__clrex", "__dbg", ]; - if !skip.contains(&rust.name) - // Most run-time tests are handled by the intrinsic-test tool, except for - // load/stores (which have generated tests) - && (!rust.name.starts_with("sv") || rust.name.starts_with("svld") - || rust.name.starts_with("svst")) - // The load/store test generator can't handle these cases yet - && (!rust.name.contains("_u32base_") || rust.name.contains("index") || rust.name.contains("offset")) - && !(rust.name.starts_with("svldff1") && rust.name.contains("gather")) - { - println!("missing run-time test for `{}`", rust.name); - all_valid = false; - } } // Skip some intrinsics that aren't NEON and are located in different @@ -545,21 +479,12 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { let mut nconst = 0; let iter = rust.arguments.iter().zip(&arm.arguments).enumerate(); for (i, (rust_ty, (arm, arm_const))) in iter { - match (*rust_ty, arm) { - // SVE uses generic type parameters to handle void pointers - (Type::ConstPtr(Type::GenericParam("T")), Type::ConstPtr(Type::Void)) => (), - // SVE const generics use i32 over u64 for usability reasons - (Type::PrimSigned(32), Type::PrimUnsigned(64)) if rust.required_const.contains(&i) => { - () - } - // svset doesn't have its const argument last as we assumed when building the Function - _ if rust.name.starts_with("svset") => (), - (x, y) if x == y => (), - _ => bail!("mismatched arguments: {rust_ty:?} != {arm:?}"), + if *rust_ty != arm { + bail!("mismatched arguments: {rust_ty:?} != {arm:?}") } if *arm_const { nconst += 1; - if !rust.required_const.contains(&i) && !rust.name.starts_with("svset") { + if !rust.required_const.contains(&i) { bail!("argument const mismatch"); } } @@ -568,7 +493,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { bail!("wrong number of const arguments"); } - if rust.instrs.is_empty() && arm.instruction != "" { + if rust.instrs.is_empty() { bail!( "instruction not listed for `{}`, but arm lists {:?}", rust.name, @@ -607,7 +532,7 @@ fn matches(rust: &Function, arm: &Intrinsic) -> Result<(), String> { Ok(()) } -#[derive(Debug, PartialEq)] +#[derive(PartialEq)] struct Intrinsic { name: String, ret: Option, @@ -622,7 +547,7 @@ struct JsonIntrinsic { arguments: Vec, return_type: ReturnType, #[serde(default)] - instructions: Option>>, + instructions: Vec>, } #[derive(Deserialize, Debug)] @@ -639,8 +564,8 @@ fn parse_intrinsics(intrinsics: Vec) -> HashMap Intrinsic { - let name = intr.name.replace('[', "").replace(']', ""); +fn parse_intrinsic(mut intr: JsonIntrinsic) -> Intrinsic { + let name = intr.name; let ret = if intr.return_type.value == "void" { None } else { @@ -649,24 +574,18 @@ fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic { // This ignores multiple instructions and different optional sequences for now to mimic // the old HTML scraping behaviour - let instruction = intr - .instructions - .map_or(String::new(), |mut i| i.swap_remove(0).swap_remove(0)); + let instruction = intr.instructions.swap_remove(0).swap_remove(0); let arguments = intr .arguments .iter() .map(|s| { - let ty = if let Some(i) = s.find('*') { - &s[..i + 1] - } else { - s.rsplit_once(' ').unwrap().0.trim_start_matches("const ") + let (ty, konst) = match s.strip_prefix("const") { + Some(stripped) => (stripped.trim_start(), true), + None => (s.as_str(), false), }; - let ty = parse_ty(ty); - let konst = s.contains("const") && !matches!(ty, Type::ConstPtr(_)) - || s.starts_with("enum") - || s.rsplit_once(" ").unwrap().1.starts_with("imm"); - (ty, konst) + let ty = ty.rsplit_once(' ').unwrap().0; + (parse_ty(ty), konst) }) .collect::>(); @@ -679,26 +598,18 @@ fn parse_intrinsic(intr: JsonIntrinsic) -> Intrinsic { } fn parse_ty(s: &str) -> Type { - if let Some(ty) = s.strip_suffix("*") { - let ty = ty.trim(); - if let Some(ty) = ty.strip_prefix("const") { - // SVE intrinsics are west-const (const int8_t *) - Type::ConstPtr(parse_ty_base(ty)) - } else if let Some(ty) = ty.strip_suffix("const") { - // Neon intrinsics are east-const (int8_t const *) - Type::ConstPtr(parse_ty_base(ty)) - } else { - Type::MutPtr(parse_ty_base(ty)) - } + let suffix = " const *"; + if let Some(base) = s.strip_suffix(suffix) { + Type::ConstPtr(parse_ty_base(base)) + } else if let Some(base) = s.strip_suffix(" *") { + Type::MutPtr(parse_ty_base(base)) } else { *parse_ty_base(s) } } fn parse_ty_base(s: &str) -> &'static Type { - match s.trim() { - "bool" => &BOOL, - "void" => &VOID, + match s { "float16_t" => &F16, "float16x4_t" => &F16X4, "float16x4x2_t" => &F16X4X2, @@ -828,49 +739,6 @@ fn parse_ty_base(s: &str) -> &'static Type { "uint8x8x2_t" => &U8X8X2, "uint8x8x3_t" => &U8X8X3, "uint8x8x4_t" => &U8X8X4, - "svbool_t" => &SVBOOL, - "svfloat32_t" => &SVF32, - "svfloat32x2_t" => &SVF32X2, - "svfloat32x3_t" => &SVF32X3, - "svfloat32x4_t" => &SVF32X4, - "svfloat64_t" => &SVF64, - "svfloat64x2_t" => &SVF64X2, - "svfloat64x3_t" => &SVF64X3, - "svfloat64x4_t" => &SVF64X4, - "svint8_t" => &SVI8, - "svint8x2_t" => &SVI8X2, - "svint8x3_t" => &SVI8X3, - "svint8x4_t" => &SVI8X4, - "svint16_t" => &SVI16, - "svint16x2_t" => &SVI16X2, - "svint16x3_t" => &SVI16X3, - "svint16x4_t" => &SVI16X4, - "svint32_t" => &SVI32, - "svint32x2_t" => &SVI32X2, - "svint32x3_t" => &SVI32X3, - "svint32x4_t" => &SVI32X4, - "svint64_t" => &SVI64, - "svint64x2_t" => &SVI64X2, - "svint64x3_t" => &SVI64X3, - "svint64x4_t" => &SVI64X4, - "svuint8_t" => &SVU8, - "svuint8x2_t" => &SVU8X2, - "svuint8x3_t" => &SVU8X3, - "svuint8x4_t" => &SVU8X4, - "svuint16_t" => &SVU16, - "svuint16x2_t" => &SVU16X2, - "svuint16x3_t" => &SVU16X3, - "svuint16x4_t" => &SVU16X4, - "svuint32_t" => &SVU32, - "svuint32x2_t" => &SVU32X2, - "svuint32x3_t" => &SVU32X3, - "svuint32x4_t" => &SVU32X4, - "svuint64_t" => &SVU64, - "svuint64x2_t" => &SVU64X2, - "svuint64x3_t" => &SVU64X3, - "svuint64x4_t" => &SVU64X4, - "enum svprfop" => &SVPRFOP, - "enum svpattern" => &SVPATTERN, _ => panic!("failed to parse json type {s:?}"), } diff --git a/intrinsics_data/arm_intrinsics.json b/intrinsics_data/arm_intrinsics.json index dedb98092d..a463564932 100644 --- a/intrinsics_data/arm_intrinsics.json +++ b/intrinsics_data/arm_intrinsics.json @@ -7,7 +7,6 @@ "uint8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -36,7 +35,6 @@ "uint8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -65,7 +63,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -94,7 +91,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -123,7 +119,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -152,7 +147,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -181,7 +175,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -210,7 +203,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -231,186920 +223,6 @@ ] ] }, - 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"value": "svuint8_t" - }, - "Arguments_Preparation": { - "op1": { - "register": "Zop1.Q" - }, - "op2": { - "register": "Zop2.Q" - } - }, - "Architectures": [ - "A64" - ], - "instructions": [ - [ - "ZIP2" - ] - ] - }, { "SIMD_ISA": "Neon", "name": "vaba_s16", @@ -187154,7 +232,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -187188,7 +265,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -187222,7 +298,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -187256,7 +331,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -187290,7 +364,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -187324,7 +397,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -187358,7 +430,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -187390,7 +461,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -187422,7 +492,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -187454,7 +523,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -187486,7 +554,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -187518,7 +585,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -187550,7 +616,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -187584,7 +649,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -187618,7 +682,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -187652,7 +715,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -187686,7 +748,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -187720,7 +781,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -187754,7 +814,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -187788,7 +847,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -187822,7 +880,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -187856,7 +913,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -187890,7 +946,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -187924,7 +979,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -187957,7 +1011,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -187987,7 +1040,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -188015,7 +1067,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -188045,7 +1096,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -188075,7 +1125,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -188105,7 +1154,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -188135,7 +1183,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -188165,7 +1212,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -188195,7 +1241,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -188223,7 +1268,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -188251,7 +1295,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -188279,7 +1322,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -188307,7 +1349,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -188335,7 +1376,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -188363,7 +1403,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -188391,7 +1430,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -188421,7 +1459,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -188451,7 +1488,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -188481,7 +1517,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -188511,7 +1546,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -188541,7 +1575,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -188571,7 +1604,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -188601,7 +1633,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -188629,7 +1660,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -188659,7 +1689,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -188689,7 +1718,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -188719,7 +1747,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -188749,7 +1776,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -188779,7 +1805,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -188809,7 +1834,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -188836,7 +1860,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -188862,7 +1885,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -188886,7 +1908,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -188912,7 +1933,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -188938,7 +1958,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -188962,7 +1981,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -188988,7 +2006,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -189012,7 +2029,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -189038,7 +2054,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -189062,7 +2077,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -189088,7 +2102,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -189114,7 +2127,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -189138,7 +2150,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -189165,7 +2176,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -189195,7 +2205,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -189223,7 +2232,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -189253,7 +2261,6 @@ "poly64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -189283,7 +2290,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -189313,7 +2319,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -189343,7 +2348,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -189373,7 +2377,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -189403,7 +2406,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -189433,7 +2435,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -189463,7 +2464,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -189493,7 +2493,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -189523,7 +2522,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -189553,7 +2551,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -189581,7 +2578,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -189610,7 +2606,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -189642,7 +2637,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -189674,7 +2668,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -189706,7 +2699,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -189738,7 +2730,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -189770,7 +2761,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -189801,7 +2791,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -189831,7 +2820,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -189861,7 +2849,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -189891,7 +2878,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -189921,7 +2907,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -189951,7 +2936,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -189981,7 +2965,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -190009,7 +2992,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -190037,7 +3019,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -190065,7 +3046,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -190093,7 +3073,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -190121,7 +3100,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -190149,7 +3127,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -190179,7 +3156,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -190209,7 +3185,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -190239,7 +3214,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -190269,7 +3243,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -190299,7 +3272,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -190328,7 +3300,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -190352,7 +3323,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -190376,7 +3346,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -190400,7 +3369,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -190424,7 +3392,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -190448,7 +3415,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -190472,7 +3438,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -190496,7 +3461,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -190520,7 +3484,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -190544,7 +3507,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -190568,7 +3530,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -190592,7 +3553,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -190617,7 +3577,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -190647,7 +3606,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -190675,7 +3633,6 @@ "poly128_t b" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -190705,7 +3662,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -190735,7 +3691,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -190765,7 +3720,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -190795,7 +3749,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -190825,7 +3778,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -190855,7 +3807,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -190885,7 +3836,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -190915,7 +3865,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -190945,7 +3894,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -190975,7 +3923,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -191005,7 +3952,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -191034,7 +3980,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -191058,7 +4003,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -191082,7 +4026,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -191106,7 +4049,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -191130,7 +4072,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -191154,7 +4095,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -191178,7 +4118,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -191202,7 +4141,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -191227,7 +4165,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -191251,7 +4188,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -191275,7 +4211,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -191299,7 +4234,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -191323,7 +4257,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -191347,7 +4280,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -191371,7 +4303,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -191395,7 +4326,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -191419,7 +4349,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -191444,7 +4373,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -191472,7 +4400,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -191500,7 +4427,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -191528,7 +4454,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -191556,7 +4481,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -191584,7 +4508,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -191612,7 +4535,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -191642,7 +4564,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -191672,7 +4593,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -191702,7 +4622,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -191732,7 +4651,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -191762,7 +4680,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -191792,7 +4709,6 @@ "uint8x16_t key" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -191821,7 +4737,6 @@ "uint8x16_t key" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -191849,7 +4764,6 @@ "uint8x16_t data" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -191874,7 +4788,6 @@ "uint8x16_t data" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -191900,7 +4813,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -191930,7 +4842,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -191960,7 +4871,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -191990,7 +4900,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -192020,7 +4929,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -192050,7 +4958,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -192080,7 +4987,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -192110,7 +5016,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -192140,7 +5045,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -192170,7 +5074,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -192200,7 +5103,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -192230,7 +5132,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -192260,7 +5161,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -192290,7 +5190,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -192320,7 +5219,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -192350,7 +5248,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -192381,7 +5278,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -192409,7 +5305,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -192437,7 +5332,6 @@ "int64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -192465,7 +5359,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -192493,7 +5386,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -192521,7 +5413,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -192549,7 +5440,6 @@ "uint64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -192577,7 +5467,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -192604,7 +5493,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -192634,7 +5522,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -192664,7 +5551,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -192694,7 +5580,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -192724,7 +5609,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -192754,7 +5638,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -192784,7 +5667,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -192814,7 +5696,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -192844,7 +5725,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -192874,7 +5754,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -192904,7 +5783,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -192934,7 +5812,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -192964,7 +5841,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -192994,7 +5870,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -193024,7 +5899,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -193054,7 +5928,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -193085,7 +5958,6 @@ "float32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -193119,7 +5991,6 @@ "float64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -193151,7 +6022,6 @@ "poly16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -193185,7 +6055,6 @@ "poly64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -193218,7 +6087,6 @@ "poly8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -193252,7 +6120,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -193286,7 +6153,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -193320,7 +6186,6 @@ "int64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -193354,7 +6219,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -193388,7 +6252,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -193422,7 +6285,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -193456,7 +6318,6 @@ "uint64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -193490,7 +6351,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -193524,7 +6384,6 @@ "float32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -193558,7 +6417,6 @@ "float64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -193590,7 +6448,6 @@ "poly16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -193624,7 +6481,6 @@ "poly64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -193657,7 +6513,6 @@ "poly8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -193691,7 +6546,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -193725,7 +6579,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -193759,7 +6612,6 @@ "int64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -193793,7 +6645,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -193827,7 +6678,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -193861,7 +6711,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -193895,7 +6744,6 @@ "uint64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -193929,7 +6777,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -193962,7 +6809,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -193991,7 +6837,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -194020,7 +6865,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -194049,7 +6893,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -194077,7 +6920,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -194106,7 +6948,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -194134,7 +6975,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194164,7 +7004,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194192,7 +7031,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -194220,7 +7058,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -194250,7 +7087,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -194278,7 +7114,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -194306,7 +7141,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194336,7 +7170,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194364,7 +7197,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -194392,7 +7224,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -194422,7 +7253,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -194450,7 +7280,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -194478,7 +7307,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194508,7 +7336,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194536,7 +7363,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -194564,7 +7390,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -194594,7 +7419,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -194622,7 +7446,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -194650,7 +7473,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194680,7 +7502,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194708,7 +7529,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -194736,7 +7556,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -194766,7 +7585,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -194794,7 +7612,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -194822,7 +7639,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194852,7 +7668,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194880,7 +7695,6 @@ "poly64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -194909,7 +7723,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -194939,7 +7752,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -194969,7 +7781,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -194999,7 +7810,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195027,7 +7837,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -195057,7 +7866,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -195087,7 +7895,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -195117,7 +7924,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195145,7 +7951,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -195175,7 +7980,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -195203,7 +8007,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -195231,7 +8034,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -195259,7 +8061,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -195289,7 +8090,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -195317,7 +8117,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -195346,7 +8145,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -195376,7 +8174,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -195406,7 +8203,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -195436,7 +8232,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -195464,7 +8259,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -195494,7 +8288,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -195524,7 +8317,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -195554,7 +8346,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -195582,7 +8373,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -195612,7 +8402,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -195639,7 +8428,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -195663,7 +8451,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195687,7 +8474,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195712,7 +8498,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -195736,7 +8521,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -195760,7 +8544,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -195784,7 +8567,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195808,7 +8590,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -195832,7 +8613,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -195856,7 +8636,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -195880,7 +8659,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -195904,7 +8682,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -195928,7 +8705,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -195952,7 +8728,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -195976,7 +8751,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -196000,7 +8774,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196024,7 +8797,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196048,7 +8820,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196073,7 +8844,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -196097,7 +8867,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -196121,7 +8890,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196145,7 +8913,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196169,7 +8936,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -196193,7 +8959,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -196217,7 +8982,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196241,7 +9005,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196265,7 +9028,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -196289,7 +9051,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -196314,7 +9075,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -196344,7 +9104,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -196372,7 +9131,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -196402,7 +9160,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -196432,7 +9189,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -196460,7 +9216,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -196490,7 +9245,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -196520,7 +9274,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -196550,7 +9303,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -196578,7 +9330,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -196608,7 +9359,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -196636,7 +9386,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -196664,7 +9413,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -196692,7 +9440,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196722,7 +9469,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196750,7 +9496,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -196780,7 +9525,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196810,7 +9554,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196838,7 +9581,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -196868,7 +9610,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -196898,7 +9639,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -196928,7 +9668,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -196956,7 +9695,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -196986,7 +9724,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -197013,7 +9750,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -197037,7 +9773,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -197061,7 +9796,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -197085,7 +9819,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -197109,7 +9842,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -197133,7 +9865,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -197157,7 +9888,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -197181,7 +9911,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -197205,7 +9934,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -197229,7 +9957,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -197253,7 +9980,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -197277,7 +10003,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -197301,7 +10026,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -197325,7 +10049,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -197349,7 +10072,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -197374,7 +10096,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -197404,7 +10125,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -197432,7 +10152,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -197462,7 +10181,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -197492,7 +10210,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -197520,7 +10237,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -197550,7 +10266,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -197580,7 +10295,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -197610,7 +10324,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -197638,7 +10351,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -197668,7 +10380,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -197696,7 +10407,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -197724,7 +10434,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -197752,7 +10461,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -197782,7 +10490,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -197810,7 +10517,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -197840,7 +10546,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -197870,7 +10575,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -197898,7 +10602,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -197928,7 +10631,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -197958,7 +10660,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -197988,7 +10689,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -198016,7 +10716,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -198046,7 +10745,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -198073,7 +10771,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -198097,7 +10794,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -198121,7 +10817,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -198145,7 +10840,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -198169,7 +10863,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -198193,7 +10886,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -198217,7 +10909,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -198241,7 +10932,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -198265,7 +10955,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -198289,7 +10978,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -198313,7 +11001,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -198337,7 +11024,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -198361,7 +11047,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -198385,7 +11070,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -198409,7 +11093,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -198434,7 +11117,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -198464,7 +11146,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -198492,7 +11173,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -198522,7 +11202,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -198552,7 +11231,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -198580,7 +11258,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -198610,7 +11287,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -198640,7 +11316,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -198670,7 +11345,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -198698,7 +11372,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -198728,7 +11401,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -198756,7 +11428,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -198784,7 +11455,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -198812,7 +11482,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -198842,7 +11511,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -198870,7 +11538,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -198900,7 +11567,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -198930,7 +11596,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -198958,7 +11623,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -198988,7 +11652,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -199018,7 +11681,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -199048,7 +11710,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -199076,7 +11737,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -199106,7 +11766,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -199133,7 +11792,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -199157,7 +11815,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -199181,7 +11838,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -199205,7 +11861,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -199229,7 +11884,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -199253,7 +11907,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -199277,7 +11930,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -199301,7 +11953,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -199325,7 +11976,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -199349,7 +11999,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -199373,7 +12022,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -199397,7 +12045,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -199421,7 +12068,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -199445,7 +12091,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -199469,7 +12114,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -199493,7 +12137,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -199519,7 +12162,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -199545,7 +12187,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -199571,7 +12212,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -199597,7 +12237,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -199623,7 +12262,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -199649,7 +12287,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -199675,7 +12312,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -199701,7 +12337,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -199727,7 +12362,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -199753,7 +12387,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -199779,7 +12412,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -199806,7 +12438,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -199836,7 +12467,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -199864,7 +12494,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -199894,7 +12523,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -199924,7 +12552,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -199952,7 +12579,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -199982,7 +12608,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -200012,7 +12637,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -200042,7 +12666,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -200070,7 +12693,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -200100,7 +12722,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -200128,7 +12749,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -200156,7 +12776,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -200184,7 +12803,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -200214,7 +12832,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -200242,7 +12859,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -200272,7 +12888,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -200302,7 +12917,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -200330,7 +12944,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -200360,7 +12973,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -200390,7 +13002,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -200420,7 +13031,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -200448,7 +13058,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -200478,7 +13087,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -200505,7 +13113,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -200529,7 +13136,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -200553,7 +13159,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -200577,7 +13182,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -200601,7 +13205,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -200625,7 +13228,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -200649,7 +13251,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -200673,7 +13274,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -200697,7 +13297,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -200721,7 +13320,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -200745,7 +13343,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -200769,7 +13366,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -200793,7 +13389,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -200817,7 +13412,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -200841,7 +13435,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -200865,7 +13458,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -200891,7 +13483,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -200917,7 +13508,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -200943,7 +13533,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -200969,7 +13558,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -200995,7 +13583,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -201021,7 +13608,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -201047,7 +13633,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -201073,7 +13658,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -201099,7 +13683,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -201125,7 +13708,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -201151,7 +13733,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -201179,7 +13760,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201209,7 +13789,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201243,7 +13822,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201277,7 +13855,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201307,7 +13884,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201341,7 +13917,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201375,7 +13950,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201405,7 +13979,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201439,7 +14012,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201473,7 +14045,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201503,7 +14074,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201537,7 +14107,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -201571,7 +14140,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201600,7 +14168,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -201629,7 +14196,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201663,7 +14229,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201696,7 +14261,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201725,7 +14289,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -201754,7 +14317,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201788,7 +14350,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201821,7 +14382,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201850,7 +14410,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -201879,7 +14438,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201913,7 +14471,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201946,7 +14503,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -201975,7 +14531,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -202004,7 +14559,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -202038,7 +14592,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -202069,7 +14622,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -202095,7 +14647,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -202121,7 +14672,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -202147,7 +14697,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -202173,7 +14722,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -202199,7 +14747,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -202226,7 +14773,6 @@ "float32x2_t high" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -202257,7 +14803,6 @@ "float64x1_t high" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -202286,7 +14831,6 @@ "poly16x4_t high" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -202317,7 +14861,6 @@ "poly64x1_t high" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -202347,7 +14890,6 @@ "poly8x8_t high" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -202378,7 +14920,6 @@ "int16x4_t high" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -202409,7 +14950,6 @@ "int32x2_t high" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -202440,7 +14980,6 @@ "int64x1_t high" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -202471,7 +15010,6 @@ "int8x8_t high" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -202502,7 +15040,6 @@ "uint16x4_t high" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -202533,7 +15070,6 @@ "uint32x2_t high" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -202564,7 +15100,6 @@ "uint64x1_t high" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -202595,7 +15130,6 @@ "uint8x8_t high" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -202628,7 +15162,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -202666,7 +15199,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -202704,7 +15236,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -202742,7 +15273,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -202781,7 +15311,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -202819,7 +15348,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -202857,7 +15385,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -202895,7 +15422,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -202933,7 +15459,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -202971,7 +15496,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -203009,7 +15533,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -203047,7 +15570,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -203085,7 +15607,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -203123,7 +15644,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -203161,7 +15681,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -203199,7 +15718,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -203237,7 +15755,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -203276,7 +15793,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -203314,7 +15830,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -203352,7 +15867,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -203390,7 +15904,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -203428,7 +15941,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -203466,7 +15978,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -203504,7 +16015,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -203542,7 +16052,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -203580,7 +16089,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -203618,7 +16126,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -203656,7 +16163,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -203694,7 +16200,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -203732,7 +16237,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -203771,7 +16275,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -203809,7 +16312,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -203847,7 +16349,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -203885,7 +16386,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -203923,7 +16423,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -203961,7 +16460,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -203999,7 +16497,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -204037,7 +16534,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -204075,7 +16571,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -204113,7 +16608,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -204151,7 +16645,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -204189,7 +16682,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -204227,7 +16719,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -204266,7 +16757,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -204304,7 +16794,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -204342,7 +16831,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -204380,7 +16868,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -204418,7 +16905,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -204456,7 +16942,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -204494,7 +16979,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -204532,7 +17016,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -204570,7 +17053,6 @@ "const int lane2" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -204605,7 +17087,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -204631,7 +17112,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -204655,7 +17135,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -204681,7 +17160,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -204706,7 +17184,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -204732,7 +17209,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -204758,7 +17234,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -204784,7 +17259,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -204810,7 +17284,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -204836,7 +17309,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -204862,7 +17334,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -204888,7 +17359,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -204914,7 +17384,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -204940,7 +17409,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -204964,7 +17432,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -204990,7 +17457,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -205016,7 +17482,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -205040,7 +17505,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -205064,7 +17528,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -205089,7 +17552,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -205116,7 +17578,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -205141,7 +17602,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -205172,7 +17632,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -205203,7 +17662,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -205232,7 +17690,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -205261,7 +17718,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -205292,7 +17748,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -205321,7 +17776,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -205352,7 +17806,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -205380,7 +17833,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -205406,7 +17858,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -205430,7 +17881,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -205456,7 +17906,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -205480,7 +17929,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -205505,7 +17953,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -205529,7 +17976,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -205554,7 +18000,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -205578,7 +18023,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -205602,7 +18046,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -205626,7 +18069,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -205651,7 +18093,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -205675,7 +18116,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -205700,7 +18140,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -205724,7 +18163,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -205748,7 +18186,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -205772,7 +18209,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -205796,7 +18232,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -205821,7 +18256,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -205850,7 +18284,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -205879,7 +18312,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -205908,7 +18340,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -205936,7 +18367,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -205960,7 +18390,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -205984,7 +18413,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -206009,7 +18437,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -206033,7 +18460,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -206058,7 +18484,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -206082,7 +18507,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -206106,7 +18530,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -206130,7 +18553,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -206155,7 +18577,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -206179,7 +18600,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -206204,7 +18624,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -206228,7 +18647,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -206252,7 +18670,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -206276,7 +18693,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -206301,7 +18717,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -206325,7 +18740,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -206350,7 +18764,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -206374,7 +18787,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -206398,7 +18810,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -206422,7 +18833,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -206447,7 +18857,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -206471,7 +18880,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -206496,7 +18904,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -206520,7 +18927,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -206544,7 +18950,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -206568,7 +18973,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -206593,7 +18997,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -206617,7 +19020,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -206642,7 +19044,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -206666,7 +19067,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -206690,7 +19090,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -206714,7 +19113,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -206739,7 +19137,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -206763,7 +19160,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -206788,7 +19184,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -206812,7 +19207,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -206836,7 +19230,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -206860,7 +19253,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -206886,7 +19278,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -206912,7 +19303,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -206936,7 +19326,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -206961,7 +19350,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -206992,7 +19380,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -207023,7 +19410,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -207052,7 +19438,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -207081,7 +19466,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -207112,7 +19496,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -207141,7 +19524,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -207172,7 +19554,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -207200,7 +19581,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -207226,7 +19606,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -207250,7 +19629,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -207276,7 +19654,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -207300,7 +19677,6 @@ "int32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -207324,7 +19700,6 @@ "uint32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -207349,7 +19724,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -207378,7 +19752,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -207407,7 +19780,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -207436,7 +19808,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -207464,7 +19835,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -207488,7 +19858,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -207512,7 +19881,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -207537,7 +19905,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -207564,7 +19931,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -207589,7 +19955,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -207617,7 +19982,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -207645,7 +20009,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -207673,7 +20036,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -207703,7 +20065,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -207741,7 +20102,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -207779,7 +20139,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -207816,7 +20175,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -207852,7 +20210,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -207885,7 +20242,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -207919,7 +20275,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -207957,7 +20312,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -207995,7 +20349,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -208032,7 +20385,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -208068,7 +20420,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -208101,7 +20452,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -208133,7 +20483,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -208164,7 +20513,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -208193,7 +20541,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -208224,7 +20571,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -208254,7 +20600,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -208285,7 +20630,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -208316,7 +20660,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -208347,7 +20690,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -208378,7 +20720,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -208409,7 +20750,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -208440,7 +20780,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -208471,7 +20810,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -208502,7 +20840,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -208533,7 +20870,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -208562,7 +20898,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -208591,7 +20926,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -208620,7 +20954,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -208649,7 +20982,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -208678,7 +21010,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -208707,7 +21038,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -208736,7 +21066,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -208765,7 +21094,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -208794,7 +21122,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -208823,7 +21150,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -208852,7 +21178,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -208881,7 +21206,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -208909,7 +21233,6 @@ "float32_t value" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -208935,7 +21258,6 @@ "float64_t value" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -208959,7 +21281,6 @@ "poly16_t value" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -208985,7 +21306,6 @@ "poly64_t value" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -209010,7 +21330,6 @@ "poly8_t value" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -209036,7 +21355,6 @@ "int16_t value" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -209062,7 +21380,6 @@ "int32_t value" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -209088,7 +21405,6 @@ "int64_t value" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -209114,7 +21430,6 @@ "int8_t value" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -209140,7 +21455,6 @@ "uint16_t value" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -209166,7 +21480,6 @@ "uint32_t value" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -209192,7 +21505,6 @@ "uint64_t value" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -209218,7 +21530,6 @@ "uint8_t value" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -209245,7 +21556,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -209274,7 +21584,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -209303,7 +21612,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -209332,7 +21640,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -209361,7 +21668,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -209390,7 +21696,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -209419,7 +21724,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -209448,7 +21752,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -209477,7 +21780,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -209506,7 +21808,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -209535,7 +21836,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -209564,7 +21864,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -209593,7 +21892,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -209622,7 +21920,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -209651,7 +21948,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -209680,7 +21976,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -209709,7 +22004,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -209738,7 +22032,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -209767,7 +22060,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -209798,7 +22090,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -209827,7 +22118,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -209858,7 +22148,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -209888,7 +22177,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -209919,7 +22207,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -209950,7 +22237,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -209981,7 +22267,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -210012,7 +22297,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -210043,7 +22327,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -210074,7 +22357,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -210105,7 +22387,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -210136,7 +22417,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -210167,7 +22447,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -210196,7 +22475,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -210225,7 +22503,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -210254,7 +22531,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -210283,7 +22559,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -210312,7 +22587,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -210341,7 +22615,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -210370,7 +22643,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -210399,7 +22671,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -210428,7 +22699,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -210457,7 +22727,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -210486,7 +22755,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -210515,7 +22783,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -210543,7 +22810,6 @@ "float32_t value" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -210569,7 +22835,6 @@ "float64_t value" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -210593,7 +22858,6 @@ "poly16_t value" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -210619,7 +22883,6 @@ "poly64_t value" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -210644,7 +22907,6 @@ "poly8_t value" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -210670,7 +22932,6 @@ "int16_t value" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -210696,7 +22957,6 @@ "int32_t value" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -210722,7 +22982,6 @@ "int64_t value" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -210748,7 +23007,6 @@ "int8_t value" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -210774,7 +23032,6 @@ "uint16_t value" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -210800,7 +23057,6 @@ "uint32_t value" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -210826,7 +23082,6 @@ "uint64_t value" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -210852,7 +23107,6 @@ "uint8_t value" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -210879,7 +23133,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -210908,7 +23161,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -210937,7 +23189,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -210966,7 +23217,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -210995,7 +23245,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -211024,7 +23273,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -211054,7 +23302,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -211082,7 +23329,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -211110,7 +23356,6 @@ "int64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -211138,7 +23383,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -211166,7 +23410,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -211194,7 +23437,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -211222,7 +23464,6 @@ "uint64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -211250,7 +23491,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -211277,7 +23517,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -211307,7 +23546,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -211337,7 +23575,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -211367,7 +23604,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -211397,7 +23633,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -211427,7 +23662,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -211457,7 +23691,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -211487,7 +23720,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -211517,7 +23749,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -211547,7 +23778,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -211577,7 +23807,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -211607,7 +23836,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -211637,7 +23865,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -211667,7 +23894,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -211697,7 +23923,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -211727,7 +23952,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -211758,7 +23982,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -211793,7 +24016,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -211826,7 +24048,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -211861,7 +24082,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -211895,7 +24115,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -211930,7 +24149,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -211965,7 +24183,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -212000,7 +24217,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -212035,7 +24251,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -212070,7 +24285,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -212105,7 +24319,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -212140,7 +24353,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -212175,7 +24387,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -212210,7 +24421,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -212245,7 +24455,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -212278,7 +24487,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -212313,7 +24521,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -212347,7 +24554,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -212382,7 +24588,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -212417,7 +24622,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -212452,7 +24656,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -212487,7 +24690,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -212522,7 +24724,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -212557,7 +24758,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -212592,7 +24792,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -212627,7 +24826,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -212662,7 +24860,6 @@ "float32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -212696,7 +24893,6 @@ "float64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -212729,7 +24925,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -212766,7 +24961,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -212803,7 +24997,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -212840,7 +25033,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -212876,7 +25068,6 @@ "float32_t n" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -212910,7 +25101,6 @@ "float64_t n" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -212943,7 +25133,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -212980,7 +25169,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -213016,7 +25204,6 @@ "float32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213050,7 +25237,6 @@ "float64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213083,7 +25269,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213120,7 +25305,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213157,7 +25341,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213194,7 +25377,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213230,7 +25412,6 @@ "float32_t n" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213264,7 +25445,6 @@ "float64_t n" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213297,7 +25477,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -213334,7 +25513,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -213370,7 +25548,6 @@ "float32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -213404,7 +25581,6 @@ "float64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -213437,7 +25613,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -213474,7 +25649,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -213511,7 +25685,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -213548,7 +25721,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -213584,7 +25756,6 @@ "float32_t n" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -213616,7 +25787,6 @@ "float64_t n" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -213649,7 +25819,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -213686,7 +25855,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -213722,7 +25890,6 @@ "float32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213756,7 +25923,6 @@ "float64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213789,7 +25955,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213826,7 +25991,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213863,7 +26027,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213900,7 +26063,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -213936,7 +26098,6 @@ "float32_t n" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -213968,7 +26129,6 @@ "float64_t n" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -214001,7 +26161,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -214038,7 +26197,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -214072,7 +26230,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -214098,7 +26255,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -214122,7 +26278,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -214148,7 +26303,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -214173,7 +26327,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -214199,7 +26352,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -214225,7 +26377,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -214251,7 +26402,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -214277,7 +26427,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -214303,7 +26452,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -214329,7 +26477,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -214355,7 +26502,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -214381,7 +26527,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -214408,7 +26553,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -214439,7 +26583,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -214468,7 +26611,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -214499,7 +26641,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64_t" }, "Arguments_Preparation": { @@ -214529,7 +26670,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -214560,7 +26700,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -214591,7 +26730,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -214622,7 +26760,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -214653,7 +26790,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -214684,7 +26820,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -214715,7 +26850,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -214746,7 +26880,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -214777,7 +26910,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -214807,7 +26939,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -214833,7 +26964,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -214857,7 +26987,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -214883,7 +27012,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -214908,7 +27036,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -214934,7 +27061,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -214960,7 +27086,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -214986,7 +27111,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -215012,7 +27136,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -215038,7 +27161,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -215064,7 +27186,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -215090,7 +27211,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -215116,7 +27236,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -215143,7 +27262,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -215174,7 +27292,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -215203,7 +27320,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16_t" }, "Arguments_Preparation": { @@ -215234,7 +27350,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64_t" }, "Arguments_Preparation": { @@ -215264,7 +27379,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8_t" }, "Arguments_Preparation": { @@ -215295,7 +27409,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -215326,7 +27439,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -215357,7 +27469,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -215388,7 +27499,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -215419,7 +27529,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -215450,7 +27559,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -215481,7 +27589,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -215512,7 +27619,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -215543,7 +27649,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -215573,7 +27678,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -215603,7 +27707,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -215633,7 +27736,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -215663,7 +27765,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -215693,7 +27794,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -215723,7 +27823,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -215753,7 +27852,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -215783,7 +27881,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -215813,7 +27910,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -215843,7 +27939,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -215873,7 +27968,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -215903,7 +27997,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -215933,7 +28026,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -215963,7 +28055,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -215993,7 +28084,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -216023,7 +28113,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -216053,7 +28142,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -216083,7 +28171,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -216113,7 +28200,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -216143,7 +28229,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -216173,7 +28258,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -216203,7 +28287,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -216233,7 +28316,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -216262,7 +28344,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -216288,7 +28369,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -216312,7 +28392,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -216338,7 +28417,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -216363,7 +28441,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -216389,7 +28466,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -216415,7 +28491,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -216441,7 +28516,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -216467,7 +28541,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -216493,7 +28566,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -216519,7 +28591,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -216545,7 +28616,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -216571,7 +28641,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -216597,7 +28666,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -216623,7 +28691,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -216649,7 +28716,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -216675,7 +28741,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -216701,7 +28766,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -216725,7 +28789,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -216749,7 +28812,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -216773,7 +28835,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -216799,7 +28860,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -216834,7 +28894,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -216867,7 +28926,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -216902,7 +28960,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -216936,7 +28993,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -216971,7 +29027,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -217006,7 +29061,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -217041,7 +29095,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -217076,7 +29129,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -217111,7 +29163,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -217146,7 +29197,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -217181,7 +29231,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -217216,7 +29265,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -217249,7 +29297,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -217275,7 +29322,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -217301,7 +29347,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -217327,7 +29372,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -217353,7 +29397,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -217378,7 +29421,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -217403,7 +29445,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -217428,7 +29469,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -217453,7 +29493,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -217479,7 +29518,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -217505,7 +29543,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -217531,7 +29568,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -217557,7 +29593,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -217583,7 +29618,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -217609,7 +29643,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -217635,7 +29668,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -217661,7 +29693,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -217687,7 +29718,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -217713,7 +29743,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -217739,7 +29768,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -217765,7 +29793,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -217791,7 +29818,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -217817,7 +29843,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -217843,7 +29868,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -217869,7 +29893,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -217895,7 +29918,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -217921,7 +29943,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -217947,7 +29968,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -217973,7 +29993,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -217999,7 +30018,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -218025,7 +30043,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -218051,7 +30068,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -218077,7 +30093,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -218103,7 +30118,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -218129,7 +30143,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -218155,7 +30168,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -218181,7 +30193,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -218207,7 +30218,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -218233,7 +30243,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -218259,7 +30268,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -218285,7 +30293,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -218311,7 +30318,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -218337,7 +30343,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -218363,7 +30368,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -218389,7 +30393,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -218415,7 +30418,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -218439,7 +30441,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -218465,7 +30466,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -218490,7 +30490,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -218516,7 +30515,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -218542,7 +30540,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -218568,7 +30565,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -218594,7 +30590,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -218620,7 +30615,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -218646,7 +30640,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -218672,7 +30665,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -218698,7 +30690,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -218724,7 +30715,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -218750,7 +30740,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -218776,7 +30765,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -218802,7 +30790,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -218828,7 +30815,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -218852,7 +30838,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -218876,7 +30861,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -218900,7 +30884,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -218926,7 +30909,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -218961,7 +30943,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -218994,7 +30975,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -219029,7 +31009,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -219063,7 +31042,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -219098,7 +31076,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -219133,7 +31110,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -219168,7 +31144,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -219203,7 +31178,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -219238,7 +31212,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -219273,7 +31246,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -219308,7 +31280,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -219343,7 +31314,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -219376,7 +31346,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -219402,7 +31371,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -219428,7 +31396,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -219454,7 +31421,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -219480,7 +31446,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -219505,7 +31470,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -219530,7 +31494,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -219555,7 +31518,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -219580,7 +31542,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -219606,7 +31567,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -219632,7 +31592,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -219658,7 +31617,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -219684,7 +31642,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -219710,7 +31667,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -219736,7 +31692,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -219762,7 +31717,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -219788,7 +31742,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -219814,7 +31767,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -219840,7 +31792,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -219866,7 +31817,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -219892,7 +31842,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -219918,7 +31867,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -219944,7 +31892,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -219970,7 +31917,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -219996,7 +31942,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -220022,7 +31967,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -220048,7 +31992,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -220074,7 +32017,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -220100,7 +32042,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -220126,7 +32067,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -220152,7 +32092,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -220178,7 +32117,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -220204,7 +32142,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -220230,7 +32167,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -220256,7 +32192,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -220282,7 +32217,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -220308,7 +32242,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -220334,7 +32267,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -220360,7 +32292,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -220386,7 +32317,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -220412,7 +32342,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -220438,7 +32367,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -220464,7 +32392,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -220490,7 +32417,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -220516,7 +32442,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -220542,7 +32467,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -220566,7 +32490,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -220592,7 +32515,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -220617,7 +32539,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -220643,7 +32564,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -220669,7 +32589,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -220695,7 +32614,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -220721,7 +32639,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -220747,7 +32664,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -220773,7 +32689,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -220799,7 +32714,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -220825,7 +32739,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -220851,7 +32764,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -220877,7 +32789,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -220903,7 +32814,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -220938,7 +32848,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x2_t" }, "Arguments_Preparation": { @@ -220971,7 +32880,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -221006,7 +32914,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -221039,7 +32946,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -221074,7 +32980,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -221109,7 +33014,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -221144,7 +33048,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -221177,7 +33080,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -221212,7 +33114,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -221247,7 +33148,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -221282,7 +33182,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -221315,7 +33214,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -221348,7 +33246,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -221374,7 +33271,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x2_t" }, "Arguments_Preparation": { @@ -221399,7 +33295,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -221425,7 +33320,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -221451,7 +33345,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -221477,7 +33370,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x2_t" }, "Arguments_Preparation": { @@ -221503,7 +33395,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -221529,7 +33420,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -221555,7 +33445,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -221581,7 +33470,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x2_t" }, "Arguments_Preparation": { @@ -221607,7 +33495,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -221633,7 +33520,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -221659,7 +33545,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -221683,7 +33568,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -221709,7 +33593,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -221733,7 +33616,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -221759,7 +33641,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -221785,7 +33666,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -221811,7 +33691,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -221835,7 +33714,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -221861,7 +33739,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -221887,7 +33764,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -221913,7 +33789,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -221937,7 +33812,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -221963,7 +33837,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -221989,7 +33862,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -222015,7 +33887,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -222050,7 +33921,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x2_t" }, "Arguments_Preparation": { @@ -222083,7 +33953,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -222118,7 +33987,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -222151,7 +34019,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -222184,7 +34051,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -222219,7 +34085,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -222254,7 +34119,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -222287,7 +34151,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -222320,7 +34183,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -222355,7 +34217,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -222390,7 +34251,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -222423,7 +34283,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -222454,7 +34313,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -222480,7 +34338,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x2_t" }, "Arguments_Preparation": { @@ -222504,7 +34361,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -222530,7 +34386,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -222556,7 +34411,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -222582,7 +34436,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x2_t" }, "Arguments_Preparation": { @@ -222606,7 +34459,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -222632,7 +34484,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -222658,7 +34509,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -222684,7 +34534,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x2_t" }, "Arguments_Preparation": { @@ -222708,7 +34557,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -222734,7 +34582,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -222760,7 +34607,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -222784,7 +34630,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -222810,7 +34655,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -222835,7 +34679,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -222861,7 +34704,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -222887,7 +34729,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -222913,7 +34754,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -222939,7 +34779,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -222965,7 +34804,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -222991,7 +34829,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -223017,7 +34854,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -223043,7 +34879,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -223069,7 +34904,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -223095,7 +34929,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -223121,7 +34954,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x3_t" }, "Arguments_Preparation": { @@ -223156,7 +34988,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x3_t" }, "Arguments_Preparation": { @@ -223189,7 +35020,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -223224,7 +35054,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -223257,7 +35086,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -223292,7 +35120,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -223327,7 +35154,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -223362,7 +35188,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -223395,7 +35220,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -223430,7 +35254,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -223465,7 +35288,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -223500,7 +35322,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -223533,7 +35354,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -223566,7 +35386,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x3_t" }, "Arguments_Preparation": { @@ -223592,7 +35411,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x3_t" }, "Arguments_Preparation": { @@ -223617,7 +35435,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x3_t" }, "Arguments_Preparation": { @@ -223643,7 +35460,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x3_t" }, "Arguments_Preparation": { @@ -223669,7 +35485,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x3_t" }, "Arguments_Preparation": { @@ -223695,7 +35510,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x3_t" }, "Arguments_Preparation": { @@ -223721,7 +35535,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x3_t" }, "Arguments_Preparation": { @@ -223747,7 +35560,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x3_t" }, "Arguments_Preparation": { @@ -223773,7 +35585,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x3_t" }, "Arguments_Preparation": { @@ -223799,7 +35610,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x3_t" }, "Arguments_Preparation": { @@ -223825,7 +35635,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x3_t" }, "Arguments_Preparation": { @@ -223851,7 +35660,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -223877,7 +35685,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -223901,7 +35708,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -223927,7 +35733,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -223951,7 +35756,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -223977,7 +35781,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -224003,7 +35806,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -224029,7 +35831,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -224053,7 +35854,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -224079,7 +35879,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -224105,7 +35904,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -224131,7 +35929,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -224155,7 +35952,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -224181,7 +35977,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -224207,7 +36002,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -224233,7 +36027,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x3_t" }, "Arguments_Preparation": { @@ -224268,7 +36061,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x3_t" }, "Arguments_Preparation": { @@ -224301,7 +36093,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -224336,7 +36127,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -224369,7 +36159,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -224402,7 +36191,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -224437,7 +36225,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -224472,7 +36259,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -224505,7 +36291,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -224538,7 +36323,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -224573,7 +36357,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -224608,7 +36391,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -224641,7 +36423,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -224672,7 +36453,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x3_t" }, "Arguments_Preparation": { @@ -224698,7 +36478,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x3_t" }, "Arguments_Preparation": { @@ -224722,7 +36501,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x3_t" }, "Arguments_Preparation": { @@ -224748,7 +36526,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x3_t" }, "Arguments_Preparation": { @@ -224774,7 +36551,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x3_t" }, "Arguments_Preparation": { @@ -224800,7 +36576,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x3_t" }, "Arguments_Preparation": { @@ -224824,7 +36599,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x3_t" }, "Arguments_Preparation": { @@ -224850,7 +36624,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x3_t" }, "Arguments_Preparation": { @@ -224876,7 +36649,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x3_t" }, "Arguments_Preparation": { @@ -224902,7 +36674,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x3_t" }, "Arguments_Preparation": { @@ -224926,7 +36697,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x3_t" }, "Arguments_Preparation": { @@ -224952,7 +36722,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -224978,7 +36747,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -225002,7 +36770,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -225028,7 +36795,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -225053,7 +36819,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -225079,7 +36844,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -225105,7 +36869,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -225131,7 +36894,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -225157,7 +36919,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -225183,7 +36944,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -225209,7 +36969,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -225235,7 +36994,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -225261,7 +37019,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -225287,7 +37044,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -225313,7 +37069,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -225339,7 +37094,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x4_t" }, "Arguments_Preparation": { @@ -225374,7 +37128,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1x4_t" }, "Arguments_Preparation": { @@ -225407,7 +37160,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -225442,7 +37194,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -225475,7 +37226,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -225510,7 +37260,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -225545,7 +37294,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -225580,7 +37328,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -225613,7 +37360,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -225648,7 +37394,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -225683,7 +37428,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -225718,7 +37462,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -225751,7 +37494,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -225784,7 +37526,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x4_t" }, "Arguments_Preparation": { @@ -225810,7 +37551,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1x4_t" }, "Arguments_Preparation": { @@ -225835,7 +37575,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x4_t" }, "Arguments_Preparation": { @@ -225861,7 +37600,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x4_t" }, "Arguments_Preparation": { @@ -225887,7 +37625,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x4_t" }, "Arguments_Preparation": { @@ -225913,7 +37650,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x1x4_t" }, "Arguments_Preparation": { @@ -225939,7 +37675,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x4_t" }, "Arguments_Preparation": { @@ -225965,7 +37700,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x4_t" }, "Arguments_Preparation": { @@ -225991,7 +37725,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x4_t" }, "Arguments_Preparation": { @@ -226017,7 +37750,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1x4_t" }, "Arguments_Preparation": { @@ -226043,7 +37775,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x4_t" }, "Arguments_Preparation": { @@ -226069,7 +37800,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -226095,7 +37825,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -226119,7 +37848,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -226145,7 +37873,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -226169,7 +37896,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -226195,7 +37921,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -226221,7 +37946,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -226247,7 +37971,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -226271,7 +37994,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -226297,7 +38019,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -226323,7 +38044,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -226349,7 +38069,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -226373,7 +38092,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -226399,7 +38117,6 @@ "float32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -226425,7 +38142,6 @@ "float64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -226451,7 +38167,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x4_t" }, "Arguments_Preparation": { @@ -226486,7 +38201,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2x4_t" }, "Arguments_Preparation": { @@ -226519,7 +38233,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -226554,7 +38267,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -226587,7 +38299,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -226620,7 +38331,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -226655,7 +38365,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -226690,7 +38399,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -226723,7 +38431,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -226756,7 +38463,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -226791,7 +38497,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -226826,7 +38531,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -226859,7 +38563,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -226890,7 +38593,6 @@ "poly16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x4_t" }, "Arguments_Preparation": { @@ -226916,7 +38618,6 @@ "poly64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2x4_t" }, "Arguments_Preparation": { @@ -226940,7 +38641,6 @@ "poly8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x4_t" }, "Arguments_Preparation": { @@ -226966,7 +38666,6 @@ "int16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x4_t" }, "Arguments_Preparation": { @@ -226992,7 +38691,6 @@ "int32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x4_t" }, "Arguments_Preparation": { @@ -227018,7 +38716,6 @@ "int64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "int64x2x4_t" }, "Arguments_Preparation": { @@ -227042,7 +38739,6 @@ "int8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x4_t" }, "Arguments_Preparation": { @@ -227068,7 +38764,6 @@ "uint16_t const * ptr" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x4_t" }, "Arguments_Preparation": { @@ -227094,7 +38789,6 @@ "uint32_t const * ptr" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x4_t" }, "Arguments_Preparation": { @@ -227120,7 +38814,6 @@ "uint64_t const * ptr" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2x4_t" }, "Arguments_Preparation": { @@ -227144,7 +38837,6 @@ "uint8_t const * ptr" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x4_t" }, "Arguments_Preparation": { @@ -227170,7 +38862,6 @@ "poly128_t const * ptr" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -227196,7 +38887,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -227226,7 +38916,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -227254,7 +38943,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -227284,7 +38972,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -227314,7 +39001,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -227344,7 +39030,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -227374,7 +39059,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -227404,7 +39088,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -227434,7 +39117,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -227463,7 +39145,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -227491,7 +39172,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -227520,7 +39200,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -227547,7 +39226,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -227571,7 +39249,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -227595,7 +39272,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -227620,7 +39296,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -227650,7 +39325,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -227678,7 +39352,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -227708,7 +39381,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -227738,7 +39410,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -227768,7 +39439,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -227798,7 +39468,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -227828,7 +39497,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -227857,7 +39525,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -227881,7 +39548,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -227905,7 +39571,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -227929,7 +39594,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -227953,7 +39617,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -227977,7 +39640,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -228001,7 +39663,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -228025,7 +39686,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -228049,7 +39709,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -228073,7 +39732,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -228097,7 +39755,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -228121,7 +39778,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -228145,7 +39801,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -228169,7 +39824,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -228193,7 +39847,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -228218,7 +39871,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -228248,7 +39900,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -228276,7 +39927,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -228306,7 +39956,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -228336,7 +39985,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -228366,7 +40014,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -228396,7 +40043,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -228426,7 +40072,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -228456,7 +40101,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -228485,7 +40129,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -228513,7 +40156,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -228542,7 +40184,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -228569,7 +40210,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -228593,7 +40233,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -228617,7 +40256,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -228642,7 +40280,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -228672,7 +40309,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -228700,7 +40336,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -228730,7 +40365,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -228760,7 +40394,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -228790,7 +40423,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -228820,7 +40452,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -228850,7 +40481,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -228879,7 +40509,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -228903,7 +40532,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -228927,7 +40555,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -228951,7 +40578,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -228975,7 +40601,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -228999,7 +40624,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -229023,7 +40647,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -229047,7 +40670,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -229071,7 +40693,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -229095,7 +40716,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -229119,7 +40739,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -229143,7 +40762,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -229167,7 +40785,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -229191,7 +40808,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -229215,7 +40831,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -229241,7 +40856,6 @@ "float32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -229275,7 +40889,6 @@ "float64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -229308,7 +40921,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -229341,7 +40953,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -229380,7 +40991,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -229419,7 +41029,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -229458,7 +41067,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -229497,7 +41105,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -229528,7 +41135,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -229565,7 +41171,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -229602,7 +41207,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -229639,7 +41243,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -229675,7 +41278,6 @@ "float32_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -229709,7 +41311,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -229743,7 +41344,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -229777,7 +41377,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -229811,7 +41410,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -229845,7 +41443,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -229879,7 +41476,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -229913,7 +41509,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -229947,7 +41542,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -229981,7 +41575,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -230015,7 +41608,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -230050,7 +41642,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230087,7 +41678,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230124,7 +41714,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230161,7 +41750,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230198,7 +41786,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230235,7 +41822,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230272,7 +41858,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230309,7 +41894,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230345,7 +41929,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230377,7 +41960,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230409,7 +41991,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230441,7 +42022,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230473,7 +42053,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230505,7 +42084,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230537,7 +42115,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -230569,7 +42146,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230601,7 +42177,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230633,7 +42208,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -230666,7 +42240,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230705,7 +42278,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230744,7 +42316,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230783,7 +42354,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230822,7 +42392,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -230859,7 +42428,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -230896,7 +42464,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -230933,7 +42500,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -230969,7 +42535,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231003,7 +42568,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -231037,7 +42601,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -231071,7 +42634,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -231105,7 +42667,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231139,7 +42700,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -231173,7 +42733,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -231207,7 +42766,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -231241,7 +42799,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -231275,7 +42832,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -231309,7 +42865,6 @@ "float32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -231343,7 +42898,6 @@ "float64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -231376,7 +42930,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -231409,7 +42962,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -231448,7 +43000,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231487,7 +43038,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -231526,7 +43076,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -231565,7 +43114,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -231596,7 +43144,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -231633,7 +43180,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231670,7 +43216,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -231707,7 +43252,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -231743,7 +43287,6 @@ "float32_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -231777,7 +43320,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -231811,7 +43353,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231845,7 +43386,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -231879,7 +43419,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -231913,7 +43452,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -231947,7 +43485,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -231981,7 +43518,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -232015,7 +43551,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -232049,7 +43584,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -232083,7 +43617,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -232117,7 +43650,6 @@ "float32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -232151,7 +43683,6 @@ "float64x1_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -232184,7 +43715,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -232217,7 +43747,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -232256,7 +43785,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -232295,7 +43823,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -232334,7 +43861,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -232373,7 +43899,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -232404,7 +43929,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -232441,7 +43965,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -232478,7 +44001,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -232515,7 +44037,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -232551,7 +44072,6 @@ "float32_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -232585,7 +44105,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -232619,7 +44138,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -232653,7 +44171,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -232687,7 +44204,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -232721,7 +44237,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -232755,7 +44270,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -232789,7 +44303,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -232823,7 +44336,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -232857,7 +44369,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -232891,7 +44402,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -232926,7 +44436,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -232963,7 +44472,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233000,7 +44508,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233037,7 +44544,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233074,7 +44580,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233111,7 +44616,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233148,7 +44652,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233185,7 +44688,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233221,7 +44723,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233253,7 +44754,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233285,7 +44785,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233317,7 +44816,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233349,7 +44847,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233381,7 +44878,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233413,7 +44909,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -233445,7 +44940,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233477,7 +44971,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233509,7 +45002,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -233542,7 +45034,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233581,7 +45072,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233620,7 +45110,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233659,7 +45148,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233698,7 +45186,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233735,7 +45222,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233772,7 +45258,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233809,7 +45294,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233845,7 +45329,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -233879,7 +45362,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -233913,7 +45395,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -233947,7 +45428,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -233981,7 +45461,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -234015,7 +45494,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -234049,7 +45527,6 @@ "int8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -234083,7 +45560,6 @@ "uint16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -234117,7 +45593,6 @@ "uint32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -234151,7 +45626,6 @@ "uint8x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -234185,7 +45659,6 @@ "float32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -234219,7 +45692,6 @@ "float64x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -234252,7 +45724,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -234285,7 +45756,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -234324,7 +45794,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -234363,7 +45832,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -234402,7 +45870,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -234441,7 +45908,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -234472,7 +45938,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -234509,7 +45974,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -234546,7 +46010,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -234583,7 +46046,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -234619,7 +46081,6 @@ "float32_t c" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -234653,7 +46114,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -234687,7 +46147,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -234721,7 +46180,6 @@ "uint16_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -234755,7 +46213,6 @@ "uint32_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -234789,7 +46246,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -234823,7 +46279,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -234857,7 +46312,6 @@ "int8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -234891,7 +46345,6 @@ "uint16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -234925,7 +46378,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -234959,7 +46411,6 @@ "uint8x16_t c" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -234993,7 +46444,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -235026,7 +46476,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -235057,7 +46506,6 @@ "float32_t value" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -235083,7 +46531,6 @@ "float64_t value" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -235107,7 +46554,6 @@ "poly16_t value" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -235133,7 +46579,6 @@ "poly8_t value" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -235159,7 +46604,6 @@ "int16_t value" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -235185,7 +46629,6 @@ "int32_t value" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -235211,7 +46654,6 @@ "int64_t value" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -235237,7 +46679,6 @@ "int8_t value" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -235263,7 +46704,6 @@ "uint16_t value" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -235289,7 +46729,6 @@ "uint32_t value" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -235315,7 +46754,6 @@ "uint64_t value" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -235341,7 +46779,6 @@ "uint8_t value" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -235367,7 +46804,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -235391,7 +46827,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -235415,7 +46850,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -235439,7 +46873,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -235463,7 +46896,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -235487,7 +46919,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -235511,7 +46942,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -235537,7 +46967,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -235563,7 +46992,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -235589,7 +47017,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -235615,7 +47042,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -235641,7 +47067,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -235668,7 +47093,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -235698,7 +47122,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -235728,7 +47151,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -235758,7 +47180,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -235788,7 +47209,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -235818,7 +47238,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -235847,7 +47266,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -235873,7 +47291,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -235899,7 +47316,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -235925,7 +47341,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -235951,7 +47366,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -235977,7 +47391,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -236003,7 +47416,6 @@ "float32_t value" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -236029,7 +47441,6 @@ "float64_t value" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -236053,7 +47464,6 @@ "poly16_t value" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -236079,7 +47489,6 @@ "poly8_t value" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -236105,7 +47514,6 @@ "int16_t value" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -236131,7 +47539,6 @@ "int32_t value" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -236157,7 +47564,6 @@ "int64_t value" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -236183,7 +47589,6 @@ "int8_t value" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -236209,7 +47614,6 @@ "uint16_t value" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -236235,7 +47639,6 @@ "uint32_t value" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -236261,7 +47664,6 @@ "uint64_t value" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -236287,7 +47689,6 @@ "uint8_t value" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -236314,7 +47715,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -236344,7 +47744,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -236373,7 +47772,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -236408,7 +47806,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -236441,7 +47838,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -236476,7 +47872,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -236511,7 +47906,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -236546,7 +47940,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -236581,7 +47974,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -236614,7 +48006,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -236647,7 +48038,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -236680,7 +48070,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -236713,7 +48102,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -236746,7 +48134,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -236778,7 +48165,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -236808,7 +48194,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -236836,7 +48221,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -236866,7 +48250,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -236896,7 +48279,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -236926,7 +48308,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -236956,7 +48337,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -236986,7 +48366,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -237016,7 +48395,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -237046,7 +48424,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -237076,7 +48453,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -237106,7 +48482,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -237136,7 +48511,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -237167,7 +48541,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -237200,7 +48573,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -237233,7 +48605,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -237266,7 +48637,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -237299,7 +48669,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -237332,7 +48701,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -237365,7 +48733,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -237398,7 +48765,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -237431,7 +48797,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -237464,7 +48829,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -237496,7 +48860,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -237524,7 +48887,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -237552,7 +48914,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -237580,7 +48941,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -237608,7 +48968,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -237637,7 +48996,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -237665,7 +49023,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -237693,7 +49050,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -237721,7 +49077,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -237749,7 +49104,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -237777,7 +49131,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -237805,7 +49158,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -237834,7 +49186,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -237869,7 +49220,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -237904,7 +49254,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -237939,7 +49288,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -237974,7 +49322,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -238007,7 +49354,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -238040,7 +49386,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -238073,7 +49418,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -238105,7 +49449,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -238135,7 +49478,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -238165,7 +49507,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -238195,7 +49536,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -238225,7 +49565,6 @@ "poly64_t b" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -238254,7 +49593,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -238284,7 +49622,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -238314,7 +49651,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -238344,7 +49680,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -238374,7 +49709,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -238404,7 +49738,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -238434,7 +49767,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -238464,7 +49796,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -238494,7 +49825,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -238523,7 +49853,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -238558,7 +49887,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -238591,7 +49919,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -238626,7 +49953,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -238661,7 +49987,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -238696,7 +50021,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -238731,7 +50055,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -238764,7 +50087,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -238797,7 +50119,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -238830,7 +50151,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -238863,7 +50183,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -238896,7 +50215,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -238928,7 +50246,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -238958,7 +50275,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -238986,7 +50302,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -239016,7 +50331,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -239046,7 +50360,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -239076,7 +50389,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -239106,7 +50418,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -239136,7 +50447,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -239166,7 +50476,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -239196,7 +50505,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -239226,7 +50534,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -239256,7 +50563,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -239286,7 +50592,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -239317,7 +50622,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -239350,7 +50654,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -239382,7 +50685,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -239410,7 +50712,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -239439,7 +50740,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -239472,7 +50772,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -239505,7 +50804,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -239538,7 +50836,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -239570,7 +50867,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -239599,7 +50895,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -239632,7 +50927,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -239664,7 +50958,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -239692,7 +50985,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -239721,7 +51013,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -239754,7 +51045,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -239787,7 +51077,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -239820,7 +51109,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -239852,7 +51140,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -239881,7 +51168,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -239914,7 +51200,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -239945,7 +51230,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -239971,7 +51255,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -239997,7 +51280,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -240023,7 +51305,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -240049,7 +51330,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -240075,7 +51355,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -240101,7 +51380,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -240127,7 +51405,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -240153,7 +51430,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -240179,7 +51455,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -240205,7 +51480,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -240231,7 +51505,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -240257,7 +51530,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -240283,7 +51555,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -240309,7 +51580,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -240335,7 +51605,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -240359,7 +51628,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -240385,7 +51653,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -240411,7 +51678,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -240435,7 +51701,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -240461,7 +51726,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -240485,7 +51749,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -240511,7 +51774,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -240535,7 +51797,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -240561,7 +51822,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -240587,7 +51847,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -240611,7 +51870,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -240638,7 +51896,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -240668,7 +51925,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -240698,7 +51954,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -240728,7 +51983,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -240758,7 +52012,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -240788,7 +52041,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -240818,7 +52070,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -240848,7 +52099,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -240878,7 +52128,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -240908,7 +52157,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -240938,7 +52186,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -240968,7 +52215,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -240998,7 +52244,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -241028,7 +52273,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -241058,7 +52302,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -241088,7 +52331,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -241118,7 +52360,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -241148,7 +52389,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -241178,7 +52418,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -241208,7 +52447,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -241238,7 +52476,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -241268,7 +52505,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -241298,7 +52534,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -241328,7 +52563,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -241358,7 +52592,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -241388,7 +52621,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -241418,7 +52650,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -241448,7 +52679,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -241478,7 +52708,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -241508,7 +52737,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -241538,7 +52766,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -241568,7 +52795,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -241598,7 +52824,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -241628,7 +52853,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -241658,7 +52882,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -241688,7 +52911,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -241718,7 +52940,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -241748,7 +52969,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -241778,7 +52998,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -241808,7 +53027,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -241838,7 +53056,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -241868,7 +53085,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -241898,7 +53114,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -241928,7 +53143,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -241958,7 +53172,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -241988,7 +53201,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -242018,7 +53230,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -242048,7 +53259,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -242078,7 +53288,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -242108,7 +53317,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -242138,7 +53346,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -242167,7 +53374,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -242191,7 +53397,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -242215,7 +53420,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -242239,7 +53443,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -242265,7 +53468,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -242291,7 +53493,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -242317,7 +53518,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -242343,7 +53543,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -242369,7 +53568,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -242395,7 +53593,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -242421,7 +53618,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -242447,7 +53643,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -242473,7 +53668,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -242499,7 +53693,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -242525,7 +53718,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -242552,7 +53744,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -242580,7 +53771,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -242608,7 +53798,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -242636,7 +53825,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -242664,7 +53852,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -242692,7 +53879,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -242720,7 +53906,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -242748,7 +53933,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -242776,7 +53960,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -242804,7 +53987,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -242831,7 +54013,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -242856,7 +54037,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -242886,7 +54066,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -242916,7 +54095,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -242946,7 +54124,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -242976,7 +54153,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -243006,7 +54182,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -243036,7 +54211,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -243066,7 +54240,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -243094,7 +54267,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -243122,7 +54294,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -243149,7 +54320,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -243173,7 +54343,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -243198,7 +54367,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -243226,7 +54394,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -243254,7 +54421,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -243282,7 +54448,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -243310,7 +54475,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -243338,7 +54502,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -243366,7 +54529,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -243394,7 +54556,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -243421,7 +54582,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -243445,7 +54605,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -243470,7 +54629,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -243500,7 +54658,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -243530,7 +54687,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -243560,7 +54716,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -243590,7 +54745,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -243620,7 +54774,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -243650,7 +54803,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -243680,7 +54832,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -243708,7 +54859,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -243736,7 +54886,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -243763,7 +54912,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -243787,7 +54935,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -243812,7 +54959,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -243840,7 +54986,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -243868,7 +55013,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -243896,7 +55040,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -243924,7 +55067,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -243952,7 +55094,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -243980,7 +55121,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -244008,7 +55148,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -244035,7 +55174,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -244059,7 +55197,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -244083,7 +55220,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -244109,7 +55245,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -244135,7 +55270,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -244159,7 +55293,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -244185,7 +55318,6 @@ "int8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -244209,7 +55341,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -244233,7 +55364,6 @@ "int16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -244257,7 +55387,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -244283,7 +55412,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -244309,7 +55437,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -244333,7 +55460,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -244359,7 +55485,6 @@ "int32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -244384,7 +55509,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -244414,7 +55538,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -244444,7 +55567,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -244474,7 +55596,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -244504,7 +55625,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -244534,7 +55654,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -244564,7 +55683,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -244594,7 +55712,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -244624,7 +55741,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -244652,7 +55768,6 @@ "uint8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -244680,7 +55795,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -244708,7 +55822,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -244736,7 +55849,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -244764,7 +55876,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -244792,7 +55903,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -244822,7 +55932,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -244852,7 +55961,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -244882,7 +55990,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -244912,7 +56019,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -244942,7 +56048,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -244972,7 +56077,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -245002,7 +56106,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -245032,7 +56135,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -245060,7 +56162,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -245090,7 +56191,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245127,7 +56227,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245164,7 +56263,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245201,7 +56299,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245237,7 +56334,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245269,7 +56365,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245301,7 +56396,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245333,7 +56427,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245366,7 +56459,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245405,7 +56497,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245444,7 +56535,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245481,7 +56571,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245517,7 +56606,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245551,7 +56639,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245585,7 +56672,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245619,7 +56705,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245654,7 +56739,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -245691,7 +56775,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -245727,7 +56810,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -245760,7 +56842,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -245797,7 +56878,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -245833,7 +56913,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -245866,7 +56945,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245903,7 +56981,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -245940,7 +57017,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -245977,7 +57053,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246013,7 +57088,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246045,7 +57119,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246077,7 +57150,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246109,7 +57181,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246142,7 +57213,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246181,7 +57251,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246220,7 +57289,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246257,7 +57325,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246293,7 +57360,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246327,7 +57393,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246361,7 +57426,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -246395,7 +57459,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -246430,7 +57493,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -246467,7 +57529,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -246503,7 +57564,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -246536,7 +57596,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -246573,7 +57632,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -246609,7 +57667,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -246641,7 +57698,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -246676,7 +57732,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -246711,7 +57766,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -246744,7 +57798,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -246776,7 +57829,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -246806,7 +57858,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -246836,7 +57887,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -246866,7 +57916,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -246897,7 +57946,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -246930,7 +57978,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -246962,7 +58009,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -246991,7 +58037,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -247026,7 +58071,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247061,7 +58105,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -247094,7 +58137,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247126,7 +58168,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -247156,7 +58197,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247186,7 +58226,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -247216,7 +58255,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247247,7 +58285,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247280,7 +58317,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247312,7 +58348,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247341,7 +58376,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247374,7 +58408,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247407,7 +58440,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247440,7 +58472,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247472,7 +58503,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247500,7 +58530,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247528,7 +58557,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247556,7 +58584,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247585,7 +58612,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247620,7 +58646,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247655,7 +58680,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247688,7 +58712,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247720,7 +58743,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247750,7 +58772,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247780,7 +58801,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -247810,7 +58830,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -247841,7 +58860,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247874,7 +58892,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247906,7 +58923,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -247935,7 +58951,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -247968,7 +58983,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -248000,7 +59014,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -248028,7 +59041,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -248056,7 +59068,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -248084,7 +59095,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -248112,7 +59122,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -248140,7 +59149,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -248168,7 +59176,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -248195,7 +59202,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -248221,7 +59227,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -248247,7 +59252,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -248273,7 +59277,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -248299,7 +59302,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -248325,7 +59327,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -248351,7 +59352,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -248375,7 +59375,6 @@ "uint64_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -248399,7 +59398,6 @@ "int16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -248423,7 +59421,6 @@ "uint16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -248447,7 +59444,6 @@ "int32_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -248471,7 +59467,6 @@ "uint32_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -248496,7 +59491,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -248524,7 +59518,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -248552,7 +59545,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -248579,7 +59571,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -248605,7 +59596,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -248631,7 +59621,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -248657,7 +59646,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -248681,7 +59669,6 @@ "int16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -248705,7 +59692,6 @@ "int32_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -248729,7 +59715,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -248755,7 +59740,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -248781,7 +59765,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -248805,7 +59788,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -248831,7 +59813,6 @@ "int8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -248855,7 +59836,6 @@ "int64_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -248879,7 +59859,6 @@ "int16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -248903,7 +59882,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -248929,7 +59907,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -248955,7 +59932,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -248979,7 +59955,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -249005,7 +59980,6 @@ "int32_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -249032,7 +60006,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249069,7 +60042,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249106,7 +60078,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249143,7 +60114,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249179,7 +60149,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249211,7 +60180,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249244,7 +60212,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249281,7 +60248,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249317,7 +60283,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249350,7 +60315,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -249387,7 +60351,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -249424,7 +60387,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -249461,7 +60423,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -249497,7 +60458,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -249529,7 +60489,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -249562,7 +60521,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -249599,7 +60557,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -249635,7 +60592,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -249668,7 +60624,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249705,7 +60660,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249742,7 +60696,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249779,7 +60732,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249815,7 +60767,6 @@ "int16x4_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -249847,7 +60798,6 @@ "int32x2_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -249880,7 +60830,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249917,7 +60866,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249953,7 +60901,6 @@ "int16_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -249986,7 +60933,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250023,7 +60969,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250060,7 +61005,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250097,7 +61041,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250133,7 +61076,6 @@ "int16x8_t c" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250165,7 +61107,6 @@ "int32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250198,7 +61139,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -250235,7 +61175,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -250271,7 +61210,6 @@ "int32_t c" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -250303,7 +61241,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -250338,7 +61275,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -250373,7 +61309,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -250406,7 +61341,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -250438,7 +61372,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -250468,7 +61401,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -250498,7 +61430,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -250528,7 +61459,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -250559,7 +61489,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -250592,7 +61521,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -250624,7 +61552,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -250653,7 +61580,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250688,7 +61614,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250723,7 +61648,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250756,7 +61680,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250788,7 +61711,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250818,7 +61740,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250848,7 +61769,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -250878,7 +61798,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -250909,7 +61828,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -250942,7 +61860,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -250974,7 +61891,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -251002,7 +61918,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -251032,7 +61947,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -251062,7 +61976,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -251092,7 +62005,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -251122,7 +62034,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -251152,7 +62063,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -251182,7 +62092,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -251212,7 +62121,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -251242,7 +62150,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -251270,7 +62177,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -251298,7 +62204,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -251326,7 +62231,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -251354,7 +62258,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -251382,7 +62285,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -251410,7 +62312,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -251440,7 +62341,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -251470,7 +62370,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -251500,7 +62399,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -251530,7 +62428,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -251560,7 +62457,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -251590,7 +62486,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -251620,7 +62515,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -251650,7 +62544,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -251678,7 +62571,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -251707,7 +62599,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -251740,7 +62631,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -251773,7 +62663,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -251806,7 +62695,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -251839,7 +62727,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -251872,7 +62759,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -251904,7 +62790,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -251935,7 +62820,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -251966,7 +62850,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -251997,7 +62880,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -252028,7 +62910,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -252059,7 +62940,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -252090,7 +62970,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -252119,7 +62998,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -252148,7 +63026,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -252177,7 +63054,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -252206,7 +63082,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -252235,7 +63110,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -252265,7 +63139,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -252298,7 +63171,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -252331,7 +63203,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -252363,7 +63234,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -252394,7 +63264,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -252425,7 +63294,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -252456,7 +63324,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -252485,7 +63352,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -252514,7 +63380,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -252543,7 +63408,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -252574,7 +63438,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -252605,7 +63468,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -252636,7 +63498,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -252667,7 +63528,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -252698,7 +63558,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -252729,7 +63588,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -252760,7 +63618,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -252791,7 +63648,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -252821,7 +63677,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -252851,7 +63706,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -252881,7 +63735,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -252911,7 +63764,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -252941,7 +63793,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -252971,7 +63822,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -253001,7 +63851,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -253031,7 +63880,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -253060,7 +63908,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -253089,7 +63936,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -253117,7 +63963,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -253145,7 +63990,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -253174,7 +64018,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -253203,7 +64046,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -253231,7 +64073,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -253259,7 +64100,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -253288,7 +64128,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -253317,7 +64156,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -253345,7 +64183,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -253373,7 +64210,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -253404,7 +64240,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -253435,7 +64270,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -253466,7 +64300,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -253497,7 +64330,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -253528,7 +64360,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -253559,7 +64390,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -253590,7 +64420,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -253621,7 +64450,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -253651,7 +64479,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -253681,7 +64508,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -253711,7 +64537,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -253741,7 +64566,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -253771,7 +64595,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -253801,7 +64624,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -253831,7 +64653,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -253861,7 +64682,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -253890,7 +64710,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -253919,7 +64738,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -253947,7 +64765,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -253975,7 +64792,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -254006,7 +64822,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -254037,7 +64852,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -254068,7 +64882,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -254099,7 +64912,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -254128,7 +64940,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -254157,7 +64968,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -254186,7 +64996,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -254217,7 +65026,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -254248,7 +65056,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -254279,7 +65086,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -254310,7 +65116,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -254340,7 +65145,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -254373,7 +65177,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -254406,7 +65209,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -254439,7 +65241,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -254472,7 +65273,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -254505,7 +65305,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -254537,7 +65336,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -254568,7 +65366,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -254599,7 +65396,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -254630,7 +65426,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -254661,7 +65456,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -254692,7 +65486,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -254723,7 +65516,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -254752,7 +65544,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -254781,7 +65572,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -254810,7 +65600,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -254839,7 +65628,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -254868,7 +65656,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -254898,7 +65685,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -254931,7 +65717,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -254964,7 +65749,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -254996,7 +65780,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -255027,7 +65810,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -255058,7 +65840,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -255089,7 +65870,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -255118,7 +65898,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -255147,7 +65926,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -255176,7 +65954,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -255206,7 +65983,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -255236,7 +66012,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -255266,7 +66041,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -255296,7 +66070,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -255326,7 +66099,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -255356,7 +66128,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -255386,7 +66157,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -255416,7 +66186,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -255444,7 +66213,6 @@ "uint8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -255472,7 +66240,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -255500,7 +66267,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -255528,7 +66294,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -255556,7 +66321,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -255584,7 +66348,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -255614,7 +66377,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -255644,7 +66406,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -255674,7 +66435,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -255704,7 +66464,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -255734,7 +66493,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -255764,7 +66522,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -255794,7 +66551,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -255824,7 +66580,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -255852,7 +66607,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -255880,7 +66634,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -255908,7 +66661,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -255936,7 +66688,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -255964,7 +66715,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -255992,7 +66742,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256020,7 +66769,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256048,7 +66796,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256076,7 +66823,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -256104,7 +66850,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -256132,7 +66877,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -256160,7 +66904,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256188,7 +66931,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256216,7 +66958,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256244,7 +66985,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -256272,7 +67012,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -256300,7 +67039,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -256328,7 +67066,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256356,7 +67093,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256384,7 +67120,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256412,7 +67147,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -256440,7 +67174,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -256468,7 +67201,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -256496,7 +67228,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256524,7 +67255,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256553,7 +67283,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256585,7 +67314,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -256617,7 +67345,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -256649,7 +67376,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -256681,7 +67407,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256713,7 +67438,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256745,7 +67469,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256777,7 +67500,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -256809,7 +67531,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -256841,7 +67562,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -256873,7 +67593,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -256905,7 +67624,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -256937,7 +67655,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -256969,7 +67686,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -257001,7 +67717,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -257033,7 +67748,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -257065,7 +67779,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -257097,7 +67810,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -257129,7 +67841,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -257161,7 +67872,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -257193,7 +67903,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -257225,7 +67934,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -257257,7 +67965,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -257289,7 +67996,6 @@ "uint8x16_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -257321,7 +68027,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -257353,7 +68058,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -257385,7 +68089,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -257417,7 +68120,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -257449,7 +68151,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -257481,7 +68182,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -257512,7 +68212,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -257542,7 +68241,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -257572,7 +68270,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -257602,7 +68299,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -257632,7 +68328,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -257662,7 +68357,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -257692,7 +68386,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -257717,7 +68410,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -257741,7 +68433,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -257765,7 +68456,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -257789,7 +68479,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -257813,7 +68502,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -257837,7 +68525,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -257861,7 +68548,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -257887,7 +68573,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -257911,7 +68596,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -257937,7 +68621,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -257961,7 +68644,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -257987,7 +68669,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -258011,7 +68692,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -258037,7 +68717,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -258062,7 +68741,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258092,7 +68770,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258120,7 +68797,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -258148,7 +68824,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -258178,7 +68853,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -258206,7 +68880,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -258233,7 +68906,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -258257,7 +68929,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -258281,7 +68952,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258305,7 +68975,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258331,7 +69000,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258357,7 +69025,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258383,7 +69050,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258409,7 +69075,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258435,7 +69100,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258461,7 +69125,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258487,7 +69150,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258513,7 +69175,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258539,7 +69200,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -258565,7 +69225,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258589,7 +69248,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258613,7 +69271,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258637,7 +69294,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258661,7 +69317,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258685,7 +69340,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258709,7 +69363,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258733,7 +69386,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258757,7 +69409,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258781,7 +69432,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258805,7 +69455,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258829,7 +69478,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -258853,7 +69501,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -258879,7 +69526,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -258903,7 +69549,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -258928,7 +69573,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -258954,7 +69598,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -258980,7 +69623,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259006,7 +69648,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259032,7 +69673,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259058,7 +69698,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259084,7 +69723,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259110,7 +69748,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259136,7 +69773,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -259162,7 +69798,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259187,7 +69822,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259211,7 +69845,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259236,7 +69869,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259261,7 +69893,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259286,7 +69917,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259311,7 +69941,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259336,7 +69965,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259361,7 +69989,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259386,7 +70013,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259411,7 +70037,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -259436,7 +70061,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259462,7 +70086,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259486,7 +70109,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259512,7 +70134,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259537,7 +70158,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259563,7 +70183,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259589,7 +70208,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259615,7 +70233,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259641,7 +70258,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259667,7 +70283,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259693,7 +70308,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259719,7 +70333,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -259745,7 +70358,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259771,7 +70383,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259795,7 +70406,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259821,7 +70431,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259846,7 +70455,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259872,7 +70480,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259898,7 +70505,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259924,7 +70530,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259950,7 +70555,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -259976,7 +70580,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -260002,7 +70605,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -260028,7 +70630,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -260054,7 +70655,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260080,7 +70680,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260104,7 +70703,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260130,7 +70728,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260155,7 +70752,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260181,7 +70777,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260207,7 +70802,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260233,7 +70827,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260259,7 +70852,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260285,7 +70877,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260311,7 +70902,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260337,7 +70927,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -260363,7 +70952,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260389,7 +70977,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260413,7 +71000,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260439,7 +71025,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260464,7 +71049,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260490,7 +71074,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260516,7 +71099,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260542,7 +71124,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260568,7 +71149,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260594,7 +71174,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260620,7 +71199,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260646,7 +71224,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -260672,7 +71249,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260698,7 +71274,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260722,7 +71297,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260748,7 +71322,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260773,7 +71346,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260799,7 +71371,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260825,7 +71396,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260851,7 +71421,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260877,7 +71446,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260903,7 +71471,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260929,7 +71496,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260955,7 +71521,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -260981,7 +71546,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261007,7 +71571,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261031,7 +71594,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261057,7 +71619,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261082,7 +71643,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261108,7 +71668,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261134,7 +71693,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261160,7 +71718,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261186,7 +71743,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261212,7 +71768,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261238,7 +71793,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261264,7 +71818,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -261290,7 +71843,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261316,7 +71868,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261340,7 +71891,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261366,7 +71916,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261391,7 +71940,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261417,7 +71965,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261443,7 +71990,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261469,7 +72015,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261495,7 +72040,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261521,7 +72065,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261547,7 +72090,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261573,7 +72115,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -261599,7 +72140,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261625,7 +72165,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261649,7 +72188,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261675,7 +72213,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261700,7 +72237,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261726,7 +72262,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261752,7 +72287,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261778,7 +72312,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261804,7 +72337,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261830,7 +72362,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261856,7 +72387,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261882,7 +72412,6 @@ "uint8x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -261908,7 +72437,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -261934,7 +72462,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -261958,7 +72485,6 @@ "poly16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -261984,7 +72510,6 @@ "poly64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262009,7 +72534,6 @@ "poly8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262035,7 +72559,6 @@ "int16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262061,7 +72584,6 @@ "int32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262087,7 +72609,6 @@ "int64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262113,7 +72634,6 @@ "int8x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262139,7 +72659,6 @@ "uint16x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262165,7 +72684,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262191,7 +72709,6 @@ "uint64x1_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -262217,7 +72734,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262241,7 +72757,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262267,7 +72782,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262293,7 +72807,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262319,7 +72832,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262345,7 +72857,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262371,7 +72882,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262397,7 +72907,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262423,7 +72932,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262449,7 +72957,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262475,7 +72982,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -262501,7 +73007,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262525,7 +73030,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262549,7 +73053,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262573,7 +73076,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262597,7 +73099,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262621,7 +73122,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262645,7 +73145,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262669,7 +73168,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262693,7 +73191,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262717,7 +73214,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262741,7 +73237,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262765,7 +73260,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262791,7 +73285,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -262815,7 +73308,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262840,7 +73332,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262864,7 +73355,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262889,7 +73379,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262914,7 +73403,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262939,7 +73427,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262964,7 +73451,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -262989,7 +73475,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -263014,7 +73499,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -263039,7 +73523,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -263064,7 +73547,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -263089,7 +73571,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "128", "value": "poly128_t" }, "Arguments_Preparation": { @@ -263114,7 +73595,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263140,7 +73620,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263164,7 +73643,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263189,7 +73667,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263214,7 +73691,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263240,7 +73716,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263266,7 +73741,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263292,7 +73766,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263318,7 +73791,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263344,7 +73816,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263370,7 +73841,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263396,7 +73866,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263422,7 +73891,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -263448,7 +73916,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263473,7 +73940,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263497,7 +73963,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263522,7 +73987,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263547,7 +74011,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263572,7 +74035,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263597,7 +74059,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263622,7 +74083,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263647,7 +74107,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263672,7 +74131,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263697,7 +74155,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263722,7 +74179,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -263747,7 +74203,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263773,7 +74228,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263797,7 +74251,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263822,7 +74275,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263848,7 +74300,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263873,7 +74324,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263899,7 +74349,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263925,7 +74374,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263951,7 +74399,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -263977,7 +74424,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -264003,7 +74449,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -264029,7 +74474,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -264055,7 +74499,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -264081,7 +74524,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264107,7 +74549,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264131,7 +74572,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264156,7 +74596,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264182,7 +74621,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264207,7 +74645,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264233,7 +74670,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264259,7 +74695,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264285,7 +74720,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264311,7 +74745,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264337,7 +74770,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264363,7 +74795,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264389,7 +74820,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -264415,7 +74845,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264441,7 +74870,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264465,7 +74893,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264490,7 +74917,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264516,7 +74942,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264541,7 +74966,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264567,7 +74991,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264593,7 +75016,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264619,7 +75041,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264645,7 +75066,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264671,7 +75091,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264697,7 +75116,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264723,7 +75141,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -264749,7 +75166,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264775,7 +75191,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264799,7 +75214,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264824,7 +75238,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264850,7 +75263,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264875,7 +75287,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264901,7 +75312,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264927,7 +75337,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264953,7 +75362,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -264979,7 +75387,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -265005,7 +75412,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -265031,7 +75437,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -265057,7 +75462,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -265083,7 +75487,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265109,7 +75512,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265133,7 +75535,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265158,7 +75559,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265184,7 +75584,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265209,7 +75608,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265235,7 +75633,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265261,7 +75658,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265287,7 +75683,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265313,7 +75708,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265339,7 +75733,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265365,7 +75758,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265391,7 +75783,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -265417,7 +75808,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265443,7 +75833,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265467,7 +75856,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265492,7 +75880,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265518,7 +75905,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265543,7 +75929,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265569,7 +75954,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265595,7 +75979,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265621,7 +76004,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265647,7 +76029,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265673,7 +76054,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265699,7 +76079,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265725,7 +76104,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -265751,7 +76129,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265777,7 +76154,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265801,7 +76177,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265826,7 +76201,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265852,7 +76226,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265877,7 +76250,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265903,7 +76275,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265929,7 +76300,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265955,7 +76325,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -265981,7 +76350,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -266007,7 +76375,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -266033,7 +76400,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -266059,7 +76425,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -266085,7 +76450,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266111,7 +76475,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266135,7 +76498,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266160,7 +76522,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266186,7 +76547,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266211,7 +76571,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266237,7 +76596,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266263,7 +76621,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266289,7 +76646,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266315,7 +76671,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266341,7 +76696,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266367,7 +76721,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266393,7 +76746,6 @@ "uint8x16_t a" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -266419,7 +76771,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266445,7 +76796,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266469,7 +76819,6 @@ "poly128_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266494,7 +76843,6 @@ "poly16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266520,7 +76868,6 @@ "poly64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266545,7 +76892,6 @@ "poly8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266571,7 +76917,6 @@ "int16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266597,7 +76942,6 @@ "int32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266623,7 +76967,6 @@ "int64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266649,7 +76992,6 @@ "int8x16_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266675,7 +77017,6 @@ "uint16x8_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266701,7 +77042,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266727,7 +77067,6 @@ "uint64x2_t a" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266753,7 +77092,6 @@ "poly8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -266779,7 +77117,6 @@ "int8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -266805,7 +77142,6 @@ "uint8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -266831,7 +77167,6 @@ "poly8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -266857,7 +77192,6 @@ "int8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -266883,7 +77217,6 @@ "uint8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -266909,7 +77242,6 @@ "poly16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -266935,7 +77267,6 @@ "poly8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -266961,7 +77292,6 @@ "int16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -266987,7 +77317,6 @@ "int8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -267013,7 +77342,6 @@ "uint16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -267039,7 +77367,6 @@ "uint8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -267065,7 +77392,6 @@ "poly16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -267091,7 +77417,6 @@ "poly8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -267117,7 +77442,6 @@ "int16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -267143,7 +77467,6 @@ "int8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -267169,7 +77492,6 @@ "uint16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -267195,7 +77517,6 @@ "uint8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -267221,7 +77542,6 @@ "float32x2_t vec" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -267247,7 +77567,6 @@ "poly16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -267273,7 +77592,6 @@ "poly8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -267299,7 +77617,6 @@ "int16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -267325,7 +77642,6 @@ "int32x2_t vec" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -267351,7 +77667,6 @@ "int8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -267377,7 +77692,6 @@ "uint16x4_t vec" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -267403,7 +77717,6 @@ "uint32x2_t vec" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -267429,7 +77742,6 @@ "uint8x8_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -267455,7 +77767,6 @@ "float32x4_t vec" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -267481,7 +77792,6 @@ "poly16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -267507,7 +77817,6 @@ "poly8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -267533,7 +77842,6 @@ "int16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -267559,7 +77867,6 @@ "int32x4_t vec" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -267585,7 +77892,6 @@ "int8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -267611,7 +77917,6 @@ "uint16x8_t vec" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -267637,7 +77942,6 @@ "uint32x4_t vec" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -267663,7 +77967,6 @@ "uint8x16_t vec" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -267690,7 +77993,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -267720,7 +78022,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -267750,7 +78051,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -267780,7 +78080,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -267810,7 +78109,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -267840,7 +78138,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -267870,7 +78167,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -267900,7 +78196,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -267930,7 +78225,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -267960,7 +78254,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -267990,7 +78283,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -268020,7 +78312,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -268049,7 +78340,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268073,7 +78363,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268097,7 +78386,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268121,7 +78409,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268145,7 +78432,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268169,7 +78455,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268193,7 +78478,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268217,7 +78501,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268241,7 +78524,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268265,7 +78547,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268289,7 +78570,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268313,7 +78593,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268337,7 +78616,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268361,7 +78639,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268385,7 +78662,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268409,7 +78685,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268433,7 +78708,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268458,7 +78732,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268482,7 +78755,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268507,7 +78779,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268531,7 +78802,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268556,7 +78826,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268580,7 +78849,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268605,7 +78873,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268629,7 +78896,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268654,7 +78920,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268678,7 +78943,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268703,7 +78967,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268727,7 +78990,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268752,7 +79014,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268776,7 +79037,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268801,7 +79061,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268826,7 +79085,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268851,7 +79109,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268876,7 +79133,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -268901,7 +79157,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -268926,7 +79181,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -268950,7 +79204,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -268975,7 +79228,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -268999,7 +79251,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -269024,7 +79275,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -269048,7 +79298,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -269073,7 +79322,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -269097,7 +79345,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -269122,7 +79369,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -269147,7 +79393,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -269177,7 +79422,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -269207,7 +79451,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -269237,7 +79480,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -269267,7 +79509,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -269297,7 +79538,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -269327,7 +79567,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -269357,7 +79596,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -269387,7 +79625,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -269415,7 +79652,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -269443,7 +79679,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -269473,7 +79708,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -269503,7 +79737,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -269533,7 +79766,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -269563,7 +79795,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -269593,7 +79824,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -269623,7 +79853,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -269653,7 +79882,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -269683,7 +79911,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -269714,7 +79941,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -269745,7 +79971,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -269776,7 +80001,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -269807,7 +80031,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -269838,7 +80061,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -269869,7 +80091,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -269900,7 +80121,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -269931,7 +80151,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -269960,7 +80179,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -269990,7 +80208,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -270023,7 +80240,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -270056,7 +80272,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -270089,7 +80304,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -270122,7 +80336,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -270155,7 +80368,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -270187,7 +80399,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -270218,7 +80429,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -270249,7 +80459,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -270280,7 +80489,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -270311,7 +80519,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -270342,7 +80549,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -270373,7 +80579,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -270404,7 +80609,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -270435,7 +80639,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -270466,7 +80669,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -270497,7 +80699,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -270528,7 +80729,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -270559,7 +80759,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -270590,7 +80789,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -270620,7 +80818,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -270646,7 +80843,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -270670,7 +80866,6 @@ "uint32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -270696,7 +80891,6 @@ "float64_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -270720,7 +80914,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -270746,7 +80939,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -270770,7 +80962,6 @@ "uint32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -270796,7 +80987,6 @@ "float32_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -270821,7 +81011,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -270851,7 +81040,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -270879,7 +81067,6 @@ "float64_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64_t" }, "Arguments_Preparation": { @@ -270907,7 +81094,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -270937,7 +81123,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -270965,7 +81150,6 @@ "float32_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32_t" }, "Arguments_Preparation": { @@ -270994,7 +81178,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -271029,7 +81212,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -271064,7 +81246,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -271099,7 +81280,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -271134,7 +81314,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -271169,7 +81348,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -271204,7 +81382,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -271239,7 +81416,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -271274,7 +81450,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -271307,7 +81482,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -271340,7 +81514,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -271375,7 +81548,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -271410,7 +81582,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -271445,7 +81616,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -271480,7 +81650,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -271515,7 +81684,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -271550,7 +81718,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -271585,7 +81752,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -271620,7 +81786,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -271652,7 +81817,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -271684,7 +81848,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -271716,7 +81879,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -271748,7 +81910,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -271780,7 +81941,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -271811,7 +81971,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -271841,7 +82000,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -271871,7 +82029,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -271901,7 +82058,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -271931,7 +82087,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -271961,7 +82116,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -271992,7 +82146,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -272027,7 +82180,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -272060,7 +82212,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -272095,7 +82246,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -272129,7 +82279,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -272164,7 +82313,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -272199,7 +82347,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -272234,7 +82381,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -272269,7 +82415,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -272304,7 +82449,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -272339,7 +82483,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -272374,7 +82517,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -272409,7 +82551,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -272444,7 +82585,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -272479,7 +82619,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -272512,7 +82651,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -272547,7 +82685,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -272581,7 +82718,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -272616,7 +82752,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -272651,7 +82786,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -272686,7 +82820,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -272721,7 +82854,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -272756,7 +82888,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -272791,7 +82922,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -272826,7 +82956,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -272861,7 +82990,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -272896,7 +83024,6 @@ "uint32x4_t wk" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -272927,7 +83054,6 @@ "uint32_t hash_e" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -272954,7 +83080,6 @@ "uint32x4_t wk" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -272987,7 +83112,6 @@ "uint32x4_t wk" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273020,7 +83144,6 @@ "uint32x4_t w8_11" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273052,7 +83175,6 @@ "uint32x4_t w12_15" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273082,7 +83204,6 @@ "uint32x4_t wk" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273115,7 +83236,6 @@ "uint32x4_t wk" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273147,7 +83267,6 @@ "uint32x4_t w4_7" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273177,7 +83296,6 @@ "uint32x4_t w12_15" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -273210,7 +83328,6 @@ "uint64x2_t hash_ab" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -273240,7 +83357,6 @@ "uint64x2_t kwh_kwh2" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -273269,7 +83385,6 @@ "uint64x2_t w2_" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -273298,7 +83413,6 @@ "uint64x2_t w9_10" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -273327,7 +83441,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -273358,7 +83471,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -273389,7 +83501,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -273420,7 +83531,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -273451,7 +83561,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -273482,7 +83591,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -273513,7 +83621,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -273544,7 +83651,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -273575,7 +83681,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -273605,7 +83710,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -273635,7 +83739,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -273665,7 +83768,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -273695,7 +83797,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -273725,7 +83826,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -273755,7 +83855,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -273785,7 +83884,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -273815,7 +83913,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -273844,7 +83941,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -273873,7 +83969,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -273901,7 +83996,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -273929,7 +84023,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -273938,7 +84031,7 @@ }, "n": { "minimum": 0, - "maximum": 16 + "maximum": 15 } }, "Architectures": [ @@ -273958,7 +84051,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -273967,7 +84059,7 @@ }, "n": { "minimum": 0, - "maximum": 32 + "maximum": 31 } }, "Architectures": [ @@ -273987,7 +84079,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -273996,7 +84087,7 @@ }, "n": { "minimum": 0, - "maximum": 8 + "maximum": 7 } }, "Architectures": [ @@ -274016,7 +84107,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -274025,7 +84115,7 @@ }, "n": { "minimum": 0, - "maximum": 16 + "maximum": 15 } }, "Architectures": [ @@ -274045,7 +84135,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -274054,7 +84143,7 @@ }, "n": { "minimum": 0, - "maximum": 32 + "maximum": 31 } }, "Architectures": [ @@ -274074,7 +84163,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -274083,7 +84171,7 @@ }, "n": { "minimum": 0, - "maximum": 8 + "maximum": 7 } }, "Architectures": [ @@ -274103,7 +84191,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -274112,7 +84199,7 @@ }, "n": { "minimum": 0, - "maximum": 16 + "maximum": 15 } }, "Architectures": [ @@ -274134,7 +84221,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -274143,7 +84229,7 @@ }, "n": { "minimum": 0, - "maximum": 32 + "maximum": 31 } }, "Architectures": [ @@ -274165,7 +84251,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -274174,7 +84259,7 @@ }, "n": { "minimum": 0, - "maximum": 8 + "maximum": 7 } }, "Architectures": [ @@ -274196,7 +84281,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -274205,7 +84289,7 @@ }, "n": { "minimum": 0, - "maximum": 16 + "maximum": 15 } }, "Architectures": [ @@ -274227,7 +84311,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -274236,7 +84319,7 @@ }, "n": { "minimum": 0, - "maximum": 32 + "maximum": 31 } }, "Architectures": [ @@ -274258,7 +84341,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -274267,7 +84349,7 @@ }, "n": { "minimum": 0, - "maximum": 8 + "maximum": 7 } }, "Architectures": [ @@ -274289,7 +84371,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -274320,7 +84401,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -274351,7 +84431,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -274382,7 +84461,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -274413,7 +84491,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -274444,7 +84521,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -274475,7 +84551,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -274506,7 +84581,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -274537,7 +84611,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -274567,7 +84640,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -274597,7 +84669,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -274627,7 +84698,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -274657,7 +84727,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -274687,7 +84756,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -274717,7 +84785,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -274747,7 +84814,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -274777,7 +84843,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -274808,7 +84873,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -274839,7 +84903,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -274870,7 +84933,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -274901,7 +84963,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -274932,7 +84993,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -274963,7 +85023,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -274994,7 +85053,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -275025,7 +85083,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -275054,7 +85111,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -275084,7 +85140,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -275117,7 +85172,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -275150,7 +85204,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -275183,7 +85236,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -275216,7 +85268,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -275249,7 +85300,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -275281,7 +85331,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -275312,7 +85361,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -275343,7 +85391,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -275374,7 +85421,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -275405,7 +85451,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -275436,7 +85481,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -275467,7 +85511,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -275498,7 +85541,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -275529,7 +85571,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -275560,7 +85601,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -275591,7 +85631,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -275622,7 +85661,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -275653,7 +85691,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -275684,7 +85721,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -275716,7 +85752,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -275751,7 +85786,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -275785,7 +85819,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -275820,7 +85853,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -275855,7 +85887,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -275890,7 +85921,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -275925,7 +85955,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -275960,7 +85989,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -275995,7 +86023,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -276030,7 +86057,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -276065,7 +86091,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -276100,7 +86125,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -276133,7 +86157,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -276166,7 +86189,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -276201,7 +86223,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -276235,7 +86256,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -276270,7 +86290,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -276305,7 +86324,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -276340,7 +86358,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -276375,7 +86392,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -276410,7 +86426,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -276445,7 +86460,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276480,7 +86494,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -276515,7 +86528,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -276550,7 +86562,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276578,7 +86589,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276606,7 +86616,6 @@ "uint32x4_t c" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276635,7 +86644,6 @@ "const int imm2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276668,7 +86676,6 @@ "const int imm2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276701,7 +86708,6 @@ "const int imm2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276734,7 +86740,6 @@ "const int imm2" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276765,7 +86770,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276791,7 +86795,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -276817,7 +86820,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -276845,7 +86847,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -276873,7 +86874,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -276901,7 +86901,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -276929,7 +86928,6 @@ "int8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8_t" }, "Arguments_Preparation": { @@ -276957,7 +86955,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -276985,7 +86982,6 @@ "int16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16_t" }, "Arguments_Preparation": { @@ -277013,7 +87009,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -277041,7 +87036,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -277069,7 +87063,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -277097,7 +87090,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -277125,7 +87117,6 @@ "int32_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32_t" }, "Arguments_Preparation": { @@ -277152,7 +87143,6 @@ "float32x2_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -277176,7 +87166,6 @@ "float64x1_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -277200,7 +87189,6 @@ "float32x4_t a" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -277224,7 +87212,6 @@ "float64x2_t a" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -277250,7 +87237,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -277285,7 +87271,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -277320,7 +87305,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -277355,7 +87339,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -277390,7 +87373,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -277425,7 +87407,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -277460,7 +87441,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -277495,7 +87475,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -277530,7 +87509,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -277563,7 +87541,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -277596,7 +87573,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -277631,7 +87607,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -277666,7 +87641,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -277701,7 +87675,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -277736,7 +87709,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -277771,7 +87743,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -277806,7 +87777,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -277841,7 +87811,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -277876,7 +87845,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -277911,7 +87879,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x1_t" }, "Arguments_Preparation": { @@ -277945,7 +87912,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -277980,7 +87946,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -278015,7 +87980,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -278050,7 +88014,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -278085,7 +88048,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -278120,7 +88082,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -278155,7 +88116,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -278190,7 +88150,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -278225,7 +88184,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -278260,7 +88218,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -278293,7 +88250,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -278326,7 +88282,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -278361,7 +88316,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -278395,7 +88349,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -278430,7 +88383,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -278465,7 +88417,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -278500,7 +88451,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -278535,7 +88485,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -278570,7 +88519,6 @@ "const int n" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -278605,7 +88553,6 @@ "const int n" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -278640,7 +88587,6 @@ "const int n" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -278675,7 +88621,6 @@ "const int n" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -278709,7 +88654,6 @@ "float32x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278739,7 +88683,6 @@ "float32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278769,7 +88712,6 @@ "float32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278799,7 +88741,6 @@ "float32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278829,7 +88770,6 @@ "float64x1_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278857,7 +88797,6 @@ "float64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278885,7 +88824,6 @@ "float64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278913,7 +88851,6 @@ "float64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278942,7 +88879,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -278977,7 +88913,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279010,7 +88945,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279045,7 +88979,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279079,7 +89012,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279114,7 +89046,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279149,7 +89080,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279184,7 +89114,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279219,7 +89148,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279254,7 +89182,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279289,7 +89216,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279324,7 +89250,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279359,7 +89284,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279393,7 +89317,6 @@ "poly16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279423,7 +89346,6 @@ "poly16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279453,7 +89375,6 @@ "poly16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279483,7 +89404,6 @@ "poly16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279513,7 +89433,6 @@ "poly64x1_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279542,7 +89461,6 @@ "poly64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279571,7 +89489,6 @@ "poly64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279600,7 +89517,6 @@ "poly64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279629,7 +89545,6 @@ "poly8x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279659,7 +89574,6 @@ "poly8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279689,7 +89603,6 @@ "poly8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279719,7 +89632,6 @@ "poly8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279749,7 +89661,6 @@ "int16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279779,7 +89690,6 @@ "int16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279809,7 +89719,6 @@ "int16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279839,7 +89748,6 @@ "int16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279869,7 +89777,6 @@ "int32x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279899,7 +89806,6 @@ "int32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279929,7 +89835,6 @@ "int32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279959,7 +89864,6 @@ "int32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -279989,7 +89893,6 @@ "int64x1_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280019,7 +89922,6 @@ "int64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280049,7 +89951,6 @@ "int64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280079,7 +89980,6 @@ "int64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280109,7 +90009,6 @@ "int8x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280139,7 +90038,6 @@ "int8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280169,7 +90067,6 @@ "int8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280199,7 +90096,6 @@ "int8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280229,7 +90125,6 @@ "uint16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280259,7 +90154,6 @@ "uint16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280289,7 +90183,6 @@ "uint16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280319,7 +90212,6 @@ "uint16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280349,7 +90241,6 @@ "uint32x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280379,7 +90270,6 @@ "uint32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280409,7 +90299,6 @@ "uint32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280439,7 +90328,6 @@ "uint32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280469,7 +90357,6 @@ "uint64x1_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280499,7 +90386,6 @@ "uint64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280529,7 +90415,6 @@ "uint64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280559,7 +90444,6 @@ "uint64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280589,7 +90473,6 @@ "uint8x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280619,7 +90502,6 @@ "uint8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280649,7 +90531,6 @@ "uint8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280679,7 +90560,6 @@ "uint8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280709,7 +90589,6 @@ "float32x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280739,7 +90618,6 @@ "float32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280769,7 +90647,6 @@ "float32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280799,7 +90676,6 @@ "float32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280829,7 +90705,6 @@ "float64x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280857,7 +90732,6 @@ "float64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280885,7 +90759,6 @@ "float64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280913,7 +90786,6 @@ "float64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280942,7 +90814,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -280977,7 +90848,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281010,7 +90880,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281045,7 +90914,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281079,7 +90947,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281114,7 +90981,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281149,7 +91015,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281184,7 +91049,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281219,7 +91083,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281254,7 +91117,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281289,7 +91151,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281324,7 +91185,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281359,7 +91219,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281393,7 +91252,6 @@ "poly16x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281423,7 +91281,6 @@ "poly16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281453,7 +91310,6 @@ "poly16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281483,7 +91339,6 @@ "poly16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281513,7 +91368,6 @@ "poly64x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281542,7 +91396,6 @@ "poly64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281571,7 +91424,6 @@ "poly64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281601,7 +91453,6 @@ "poly64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281630,7 +91481,6 @@ "poly8x16_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281660,7 +91510,6 @@ "poly8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281690,7 +91539,6 @@ "poly8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281720,7 +91568,6 @@ "poly8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281750,7 +91597,6 @@ "int16x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281780,7 +91626,6 @@ "int16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281810,7 +91655,6 @@ "int16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281840,7 +91684,6 @@ "int16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281870,7 +91713,6 @@ "int32x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281900,7 +91742,6 @@ "int32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281930,7 +91771,6 @@ "int32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281960,7 +91800,6 @@ "int32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -281990,7 +91829,6 @@ "int64x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282020,7 +91858,6 @@ "int64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282050,7 +91887,6 @@ "int64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282080,7 +91916,6 @@ "int64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282110,7 +91945,6 @@ "int8x16_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282140,7 +91974,6 @@ "int8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282170,7 +92003,6 @@ "int8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282200,7 +92032,6 @@ "int8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282230,7 +92061,6 @@ "uint16x8_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282260,7 +92090,6 @@ "uint16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282290,7 +92119,6 @@ "uint16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282320,7 +92148,6 @@ "uint16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282350,7 +92177,6 @@ "uint32x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282380,7 +92206,6 @@ "uint32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282410,7 +92235,6 @@ "uint32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282440,7 +92264,6 @@ "uint32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282470,7 +92293,6 @@ "uint64x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282500,7 +92322,6 @@ "uint64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282530,7 +92351,6 @@ "uint64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282560,7 +92380,6 @@ "uint64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282590,7 +92409,6 @@ "uint8x16_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282620,7 +92438,6 @@ "uint8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282650,7 +92467,6 @@ "uint8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282680,7 +92496,6 @@ "uint8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282710,7 +92525,6 @@ "float32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282740,7 +92554,6 @@ "float64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282769,7 +92582,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282804,7 +92616,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282837,7 +92648,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282872,7 +92682,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282905,7 +92714,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282940,7 +92748,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -282975,7 +92782,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283010,7 +92816,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283043,7 +92848,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283078,7 +92882,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283113,7 +92916,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283148,7 +92950,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283181,7 +92982,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283215,7 +93015,6 @@ "poly16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283245,7 +93044,6 @@ "poly64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283274,7 +93072,6 @@ "poly8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283304,7 +93101,6 @@ "int16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283334,7 +93130,6 @@ "int32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283364,7 +93159,6 @@ "int64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283394,7 +93188,6 @@ "int8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283424,7 +93217,6 @@ "uint16x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283454,7 +93246,6 @@ "uint32x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283484,7 +93275,6 @@ "uint64x1x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283514,7 +93304,6 @@ "uint8x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283544,7 +93333,6 @@ "float32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283574,7 +93362,6 @@ "float64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283603,7 +93390,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283638,7 +93424,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283671,7 +93456,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283706,7 +93490,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283739,7 +93522,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283772,7 +93554,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283807,7 +93588,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283842,7 +93622,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283875,7 +93654,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283908,7 +93686,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283943,7 +93720,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -283978,7 +93754,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284011,7 +93786,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284043,7 +93817,6 @@ "poly16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284073,7 +93846,6 @@ "poly64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284101,7 +93873,6 @@ "poly8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284131,7 +93902,6 @@ "int16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284161,7 +93931,6 @@ "int32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284191,7 +93960,6 @@ "int64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284219,7 +93987,6 @@ "int8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284249,7 +94016,6 @@ "uint16x8x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284279,7 +94045,6 @@ "uint32x4x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284309,7 +94074,6 @@ "uint64x2x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284337,7 +94101,6 @@ "uint8x16x2_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284367,7 +94130,6 @@ "float32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284397,7 +94159,6 @@ "float64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284426,7 +94187,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284461,7 +94221,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284494,7 +94253,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284529,7 +94287,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284562,7 +94319,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284597,7 +94353,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284632,7 +94387,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284667,7 +94421,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284700,7 +94453,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284735,7 +94487,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284770,7 +94521,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284805,7 +94555,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284838,7 +94587,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284872,7 +94620,6 @@ "poly16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284902,7 +94649,6 @@ "poly64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284931,7 +94677,6 @@ "poly8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284961,7 +94706,6 @@ "int16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -284991,7 +94735,6 @@ "int32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285021,7 +94764,6 @@ "int64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285051,7 +94793,6 @@ "int8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285081,7 +94822,6 @@ "uint16x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285111,7 +94851,6 @@ "uint32x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285141,7 +94880,6 @@ "uint64x1x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285171,7 +94909,6 @@ "uint8x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285201,7 +94938,6 @@ "float32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285231,7 +94967,6 @@ "float64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285260,7 +94995,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285295,7 +95029,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285328,7 +95061,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285363,7 +95095,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285396,7 +95127,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285431,7 +95161,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285466,7 +95195,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285501,7 +95229,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285534,7 +95261,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285569,7 +95295,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285604,7 +95329,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285639,7 +95363,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285672,7 +95395,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285706,7 +95428,6 @@ "poly16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285736,7 +95457,6 @@ "poly64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285764,7 +95484,6 @@ "poly8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285794,7 +95513,6 @@ "int16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285824,7 +95542,6 @@ "int32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285854,7 +95571,6 @@ "int64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285882,7 +95598,6 @@ "int8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285912,7 +95627,6 @@ "uint16x8x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285942,7 +95656,6 @@ "uint32x4x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -285972,7 +95685,6 @@ "uint64x2x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286000,7 +95712,6 @@ "uint8x16x3_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286030,7 +95741,6 @@ "float32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286060,7 +95770,6 @@ "float64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286089,7 +95798,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286124,7 +95832,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286157,7 +95864,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286192,7 +95898,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286225,7 +95930,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286260,7 +95964,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286295,7 +95998,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286330,7 +96032,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286363,7 +96064,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286398,7 +96098,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286433,7 +96132,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286468,7 +96166,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286501,7 +96198,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286535,7 +96231,6 @@ "poly16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286565,7 +96260,6 @@ "poly64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286594,7 +96288,6 @@ "poly8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286624,7 +96317,6 @@ "int16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286654,7 +96346,6 @@ "int32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286684,7 +96375,6 @@ "int64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286714,7 +96404,6 @@ "int8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286744,7 +96433,6 @@ "uint16x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286774,7 +96462,6 @@ "uint32x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286804,7 +96491,6 @@ "uint64x1x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286834,7 +96520,6 @@ "uint8x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286864,7 +96549,6 @@ "float32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286894,7 +96578,6 @@ "float64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286923,7 +96606,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286958,7 +96640,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -286991,7 +96672,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287026,7 +96706,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287059,7 +96738,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287092,7 +96770,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287127,7 +96804,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287162,7 +96838,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287195,7 +96870,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287228,7 +96902,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287263,7 +96936,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287298,7 +96970,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287331,7 +97002,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287363,7 +97033,6 @@ "poly16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287393,7 +97062,6 @@ "poly64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287421,7 +97089,6 @@ "poly8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287451,7 +97118,6 @@ "int16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287481,7 +97147,6 @@ "int32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287511,7 +97176,6 @@ "int64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287539,7 +97203,6 @@ "int8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287569,7 +97232,6 @@ "uint16x8x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287599,7 +97261,6 @@ "uint32x4x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287629,7 +97290,6 @@ "uint64x2x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287657,7 +97317,6 @@ "uint8x16x4_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287687,7 +97346,6 @@ "poly128_t val" ], "return_type": { - "element_bit_size": "0", "value": "void" }, "Arguments_Preparation": { @@ -287716,7 +97374,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -287746,7 +97403,6 @@ "float64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x1_t" }, "Arguments_Preparation": { @@ -287774,7 +97430,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -287804,7 +97459,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -287834,7 +97488,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -287864,7 +97517,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -287894,7 +97546,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -287924,7 +97575,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -287954,7 +97604,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -287984,7 +97633,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -288014,7 +97662,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -288042,7 +97689,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -288071,7 +97717,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -288103,7 +97748,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -288135,7 +97779,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -288167,7 +97810,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -288199,7 +97841,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -288231,7 +97872,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -288262,7 +97902,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -288292,7 +97931,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -288322,7 +97960,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -288352,7 +97989,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -288382,7 +98018,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -288412,7 +98047,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -288442,7 +98076,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -288470,7 +98103,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -288498,7 +98130,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -288526,7 +98157,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -288554,7 +98184,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -288582,7 +98211,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -288610,7 +98238,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -288640,7 +98267,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -288670,7 +98296,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -288700,7 +98325,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -288730,7 +98354,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -288760,7 +98383,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -288790,7 +98412,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -288820,7 +98441,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -288848,7 +98468,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -288878,7 +98497,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -288908,7 +98526,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -288938,7 +98555,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -288968,7 +98584,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -288998,7 +98613,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -289028,7 +98642,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -289058,7 +98671,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -289088,7 +98700,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -289116,7 +98727,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -289144,7 +98754,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -289172,7 +98781,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -289200,7 +98808,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -289228,7 +98835,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -289256,7 +98862,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -289286,7 +98891,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -289316,7 +98920,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -289346,7 +98949,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -289376,7 +98978,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -289406,7 +99007,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -289438,7 +99038,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -289476,7 +99075,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -289513,7 +99111,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -289551,7 +99148,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -289586,7 +99182,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -289614,7 +99209,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -289642,7 +99236,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -289670,7 +99263,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -289698,7 +99290,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -289726,7 +99317,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -289754,7 +99344,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -289782,7 +99371,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -289810,7 +99398,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -289838,7 +99425,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -289866,7 +99452,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -289894,7 +99479,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -289923,7 +99507,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -289956,7 +99539,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -289989,7 +99571,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -290022,7 +99603,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -290052,7 +99632,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -290082,7 +99661,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -290112,7 +99690,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -290145,7 +99722,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -290178,7 +99754,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -290211,7 +99786,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -290241,7 +99815,6 @@ "int8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -290271,7 +99844,6 @@ "uint8x8_t idx" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -290300,7 +99872,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -290328,7 +99899,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -290356,7 +99926,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -290384,7 +99953,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -290412,7 +99980,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -290440,7 +100007,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -290468,7 +100034,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -290496,7 +100061,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -290524,7 +100088,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -290552,7 +100115,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -290580,7 +100142,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -290608,7 +100169,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -290636,7 +100196,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -290664,7 +100223,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -290692,7 +100250,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -290720,7 +100277,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -290748,7 +100304,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -290776,7 +100331,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -290804,7 +100358,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -290832,7 +100385,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -290860,7 +100412,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -290888,7 +100439,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -290916,7 +100466,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -290944,7 +100493,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -290972,7 +100520,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -291000,7 +100547,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -291028,7 +100574,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -291056,7 +100601,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -291084,7 +100628,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -291112,7 +100655,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -291140,7 +100682,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -291168,7 +100709,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -291196,7 +100736,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -291224,7 +100763,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -291252,7 +100790,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -291280,7 +100817,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -291308,7 +100844,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -291336,7 +100871,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -291364,7 +100898,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -291392,7 +100925,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -291420,7 +100952,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -291448,7 +100979,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -291476,7 +101006,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -291504,7 +101033,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -291532,7 +101060,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -291563,7 +101090,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -291594,7 +101120,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -291625,7 +101150,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -291656,7 +101180,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -291687,7 +101210,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -291718,7 +101240,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -291749,7 +101270,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -291780,7 +101300,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -291811,7 +101330,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -291842,7 +101360,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -291873,7 +101390,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -291904,7 +101420,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -291935,7 +101450,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -291966,7 +101480,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -291997,7 +101510,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -292028,7 +101540,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -292059,7 +101570,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -292090,7 +101600,6 @@ "poly64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -292119,7 +101628,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -292149,7 +101657,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -292179,7 +101686,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -292209,7 +101715,6 @@ "int64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -292237,7 +101742,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -292267,7 +101771,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -292297,7 +101800,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -292327,7 +101829,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x1_t" }, "Arguments_Preparation": { @@ -292355,7 +101856,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -292385,7 +101885,6 @@ "int64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -292413,7 +101912,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64_t" }, "Arguments_Preparation": { @@ -292441,7 +101939,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -292470,7 +101967,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -292500,7 +101996,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -292530,7 +102025,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -292560,7 +102054,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -292588,7 +102081,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -292618,7 +102110,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -292648,7 +102139,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -292678,7 +102168,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -292706,7 +102195,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -292736,7 +102224,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -292764,7 +102251,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -292792,7 +102278,6 @@ "uint64x1_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x1_t" }, "Arguments_Preparation": { @@ -292820,7 +102305,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -292848,7 +102332,6 @@ "uint8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8_t" }, "Arguments_Preparation": { @@ -292876,7 +102359,6 @@ "uint64_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64_t" }, "Arguments_Preparation": { @@ -292904,7 +102386,6 @@ "uint16_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16_t" }, "Arguments_Preparation": { @@ -292932,7 +102413,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -292960,7 +102440,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -292988,7 +102467,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -293016,7 +102494,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -293044,7 +102521,6 @@ "uint32_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32_t" }, "Arguments_Preparation": { @@ -293074,7 +102550,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -293112,7 +102587,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -293148,7 +102622,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -293182,7 +102655,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -293220,7 +102692,6 @@ "const int lane" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -293256,7 +102727,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -293288,7 +102758,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -293320,7 +102789,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -293348,7 +102816,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -293376,7 +102843,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -293404,7 +102870,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -293432,7 +102897,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -293460,7 +102924,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -293488,7 +102951,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -293516,7 +102978,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -293544,7 +103005,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -293572,7 +103032,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -293600,7 +103059,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -293628,7 +103086,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -293656,7 +103113,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -293684,7 +103140,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -293712,7 +103167,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -293740,7 +103194,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -293768,7 +103221,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -293796,7 +103248,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -293824,7 +103275,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -293852,7 +103302,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -293880,7 +103329,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -293908,7 +103356,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -293936,7 +103383,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -293964,7 +103410,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -293992,7 +103437,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -294020,7 +103464,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -294048,7 +103491,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -294076,7 +103518,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -294104,7 +103545,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -294132,7 +103572,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -294160,7 +103599,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -294188,7 +103626,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -294216,7 +103653,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -294244,7 +103680,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -294272,7 +103707,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -294300,7 +103734,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -294328,7 +103761,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -294356,7 +103788,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -294384,7 +103815,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -294412,7 +103842,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -294440,7 +103869,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -294468,7 +103896,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -294496,7 +103923,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -294524,7 +103950,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -294552,7 +103977,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -294583,7 +104007,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -294614,7 +104037,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -294645,7 +104067,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -294676,7 +104097,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -294707,7 +104127,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -294738,7 +104157,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -294769,7 +104187,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -294800,7 +104217,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -294831,7 +104247,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -294862,7 +104277,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -294893,7 +104307,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -294924,7 +104337,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -294955,7 +104367,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -294986,7 +104397,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -295017,7 +104427,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -295048,7 +104457,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -295079,7 +104487,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { @@ -295111,7 +104518,6 @@ "const int imm6" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -295141,7 +104547,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -295169,7 +104574,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -295197,7 +104601,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -295225,7 +104628,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -295253,7 +104655,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -295281,7 +104682,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -295309,7 +104709,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -295337,7 +104736,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -295365,7 +104763,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -295393,7 +104790,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -295421,7 +104817,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -295449,7 +104844,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -295477,7 +104871,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -295505,7 +104898,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -295533,7 +104925,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -295561,7 +104952,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -295589,7 +104979,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -295617,7 +105006,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -295645,7 +105033,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -295673,7 +105060,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -295701,7 +105087,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -295729,7 +105114,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -295757,7 +105141,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2_t" }, "Arguments_Preparation": { @@ -295785,7 +105168,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4_t" }, "Arguments_Preparation": { @@ -295813,7 +105195,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8_t" }, "Arguments_Preparation": { @@ -295841,7 +105222,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4_t" }, "Arguments_Preparation": { @@ -295869,7 +105249,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2_t" }, "Arguments_Preparation": { @@ -295897,7 +105276,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8_t" }, "Arguments_Preparation": { @@ -295925,7 +105303,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4_t" }, "Arguments_Preparation": { @@ -295953,7 +105330,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2_t" }, "Arguments_Preparation": { @@ -295981,7 +105357,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8_t" }, "Arguments_Preparation": { @@ -296009,7 +105384,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4_t" }, "Arguments_Preparation": { @@ -296037,7 +105411,6 @@ "float64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "float64x2_t" }, "Arguments_Preparation": { @@ -296065,7 +105438,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8_t" }, "Arguments_Preparation": { @@ -296093,7 +105465,6 @@ "poly64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "poly64x2_t" }, "Arguments_Preparation": { @@ -296121,7 +105492,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16_t" }, "Arguments_Preparation": { @@ -296149,7 +105519,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8_t" }, "Arguments_Preparation": { @@ -296177,7 +105546,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4_t" }, "Arguments_Preparation": { @@ -296205,7 +105573,6 @@ "int64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "int64x2_t" }, "Arguments_Preparation": { @@ -296233,7 +105600,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16_t" }, "Arguments_Preparation": { @@ -296261,7 +105627,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8_t" }, "Arguments_Preparation": { @@ -296289,7 +105654,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4_t" }, "Arguments_Preparation": { @@ -296317,7 +105681,6 @@ "uint64x2_t b" ], "return_type": { - "element_bit_size": "64", "value": "uint64x2_t" }, "Arguments_Preparation": { @@ -296345,7 +105708,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16_t" }, "Arguments_Preparation": { @@ -296373,7 +105735,6 @@ "float32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x2x2_t" }, "Arguments_Preparation": { @@ -296404,7 +105765,6 @@ "poly16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x4x2_t" }, "Arguments_Preparation": { @@ -296435,7 +105795,6 @@ "poly8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x8x2_t" }, "Arguments_Preparation": { @@ -296466,7 +105825,6 @@ "int16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x4x2_t" }, "Arguments_Preparation": { @@ -296497,7 +105855,6 @@ "int32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x2x2_t" }, "Arguments_Preparation": { @@ -296528,7 +105885,6 @@ "int8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x8x2_t" }, "Arguments_Preparation": { @@ -296559,7 +105915,6 @@ "uint16x4_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x4x2_t" }, "Arguments_Preparation": { @@ -296590,7 +105945,6 @@ "uint32x2_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x2x2_t" }, "Arguments_Preparation": { @@ -296621,7 +105975,6 @@ "uint8x8_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x8x2_t" }, "Arguments_Preparation": { @@ -296652,7 +106005,6 @@ "float32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "float32x4x2_t" }, "Arguments_Preparation": { @@ -296683,7 +106035,6 @@ "poly16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "poly16x8x2_t" }, "Arguments_Preparation": { @@ -296714,7 +106065,6 @@ "poly8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "poly8x16x2_t" }, "Arguments_Preparation": { @@ -296745,7 +106095,6 @@ "int16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "int16x8x2_t" }, "Arguments_Preparation": { @@ -296776,7 +106125,6 @@ "int32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "int32x4x2_t" }, "Arguments_Preparation": { @@ -296807,7 +106155,6 @@ "int8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "int8x16x2_t" }, "Arguments_Preparation": { @@ -296838,7 +106185,6 @@ "uint16x8_t b" ], "return_type": { - "element_bit_size": "16", "value": "uint16x8x2_t" }, "Arguments_Preparation": { @@ -296869,7 +106215,6 @@ "uint32x4_t b" ], "return_type": { - "element_bit_size": "32", "value": "uint32x4x2_t" }, "Arguments_Preparation": { @@ -296900,7 +106245,6 @@ "uint8x16_t b" ], "return_type": { - "element_bit_size": "8", "value": "uint8x16x2_t" }, "Arguments_Preparation": { From 4d8d13ac8fb68961a37401818026eed977d8a0f2 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Tue, 7 Jan 2025 16:51:53 +0000 Subject: [PATCH 6/8] fix: always inline signed conversions --- crates/core_arch/src/arm_shared/neon/mod.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index fe5f8361e0..504e6eab0f 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -26,7 +26,7 @@ macro_rules! impl_sign_conversions_neon { impl AsUnsigned for $signed { type Unsigned = $unsigned; - #[inline] + #[inline(always)] fn as_unsigned(self) -> $unsigned { unsafe { transmute(self) } } @@ -35,7 +35,7 @@ macro_rules! impl_sign_conversions_neon { impl AsSigned for $unsigned { type Signed = $signed; - #[inline] + #[inline(always)] fn as_signed(self) -> $signed { unsafe { transmute(self) } } From 5eeea56425965cbcc3491af70e7a04a100ba0b95 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Tue, 7 Jan 2025 17:00:03 +0000 Subject: [PATCH 7/8] remove - relaxing if size --- crates/core_arch/src/arm_shared/neon/mod.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index 504e6eab0f..793862ec8e 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -12,12 +12,12 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::* use stdarch_test::assert_instr; pub(crate) trait AsUnsigned { - type Unsigned: ?Sized; + type Unsigned: Sized; fn as_unsigned(self) -> Self::Unsigned; } pub(crate) trait AsSigned { - type Signed: ?Sized; + type Signed: Sized; fn as_signed(self) -> Self::Signed; } From ee567436da4fb4b9b15902458495d2073fa42bd7 Mon Sep 17 00:00:00 2001 From: James Barford-Evans Date: Wed, 8 Jan 2025 11:19:26 +0000 Subject: [PATCH 8/8] refactor - remove Sized as it is implicit --- crates/core_arch/src/arm_shared/neon/mod.rs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/crates/core_arch/src/arm_shared/neon/mod.rs b/crates/core_arch/src/arm_shared/neon/mod.rs index 793862ec8e..7f95e9ed98 100644 --- a/crates/core_arch/src/arm_shared/neon/mod.rs +++ b/crates/core_arch/src/arm_shared/neon/mod.rs @@ -12,12 +12,12 @@ use crate::{core_arch::simd::*, hint::unreachable_unchecked, intrinsics::simd::* use stdarch_test::assert_instr; pub(crate) trait AsUnsigned { - type Unsigned: Sized; + type Unsigned; fn as_unsigned(self) -> Self::Unsigned; } pub(crate) trait AsSigned { - type Signed: Sized; + type Signed; fn as_signed(self) -> Self::Signed; }