From 861381c870afd791b644da9a41875be4ce4d2aa6 Mon Sep 17 00:00:00 2001
From: Steven Herbst <sherbst@stanford.edu>
Date: Mon, 20 Jan 2020 21:08:42 -0800
Subject: [PATCH] allow user to specify clock and reset for an LDS

---
 msdsl/model.py      | 13 +++++++++----
 tests/rc/test_rc.py |  6 ++++--
 tests/rc/test_rc.sv |  4 +++-
 3 files changed, 16 insertions(+), 7 deletions(-)

diff --git a/msdsl/model.py b/msdsl/model.py
index 1dfaa99..a1f6167 100644
--- a/msdsl/model.py
+++ b/msdsl/model.py
@@ -312,7 +312,7 @@ def get_equation_io(self, eqn_sys: EqnSys):
         # return result
         return inputs, states, outputs, sel_bits
 
-    def add_eqn_sys(self, eqns: List[ModelExpr], extra_outputs=None):
+    def add_eqn_sys(self, eqns: List[ModelExpr], extra_outputs=None, clk=None, rst=None):
         """
         Accepts a list of equations that can contain derivatives of analog state variables.  The approach used is
         to convert the system of differential equations into a standard-form linear dynamical system (reference:
@@ -322,6 +322,8 @@ def add_eqn_sys(self, eqns: List[ModelExpr], extra_outputs=None):
 
         :param eqns:            List of equations.
         :param extra_outputs:   List of internal variables in the system of equations that should be bound to analog signals.
+        :param clk:             Name of clock signal to use (None will default to `CLK_MSDSL)
+        :param rst:             Name of the reset signal to use (None will default to `RST_MSDSL)
         """
 
         # set defaults
@@ -368,9 +370,12 @@ def add_eqn_sys(self, eqns: List[ModelExpr], extra_outputs=None):
             sel = None
 
         # add the discrete-time equation
-        self.add_discrete_time_lds(collection=collection, inputs=inputs, states=states, outputs=outputs, sel=sel)
+        self.add_discrete_time_lds(collection=collection, inputs=inputs,
+                                   states=states, outputs=outputs, sel=sel,
+                                   clk=clk, rst=rst)
 
-    def add_discrete_time_lds(self, collection, inputs=None, states=None, outputs=None, sel=None):
+    def add_discrete_time_lds(self, collection, inputs=None, states=None, outputs=None, sel=None,
+                              clk=None, rst=None):
         # set defaults
         inputs = inputs if inputs is not None else []
         states = states if states is not None else []
@@ -381,7 +386,7 @@ def add_discrete_time_lds(self, collection, inputs=None, states=None, outputs=No
         for row in range(len(states)):
             expr = sum_op([array(collection.A[row, col], sel) * states[col] for col in range(len(states))])
             expr += sum_op([array(collection.B[row, col], sel) * inputs[col] for col in range(len(inputs))])
-            self.set_next_cycle(states[row], expr)
+            self.set_next_cycle(states[row], expr, clk=clk, rst=rst)
 
         # output updates
         for row in range(len(outputs)):
diff --git a/tests/rc/test_rc.py b/tests/rc/test_rc.py
index 13142c1..189a32b 100644
--- a/tests/rc/test_rc.py
+++ b/tests/rc/test_rc.py
@@ -22,8 +22,11 @@ def gen_model(tau, dt):
     model = MixedSignalModel('model', dt=dt)
     model.add_analog_input('v_in')
     model.add_analog_output('v_out')
+    model.add_digital_input('clk')
+    model.add_digital_input('rst')
 
-    model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out)/tau])
+    model.add_eqn_sys([Deriv(model.v_out) == (model.v_in - model.v_out)/tau],
+                      clk=model.clk, rst=model.rst)
 
     BUILD_DIR.mkdir(parents=True, exist_ok=True)
     model_file = BUILD_DIR / 'model.sv'
@@ -76,7 +79,6 @@ def cycle():
         simulator=simulator,
         ext_srcs=[model_file, get_file('rc/test_rc.sv')],
         inc_dirs=[get_svreal_header().parent],
-        defines={'CLK_MSDSL': 'dut.clk', 'RST_MSDSL': 'dut.rst'},
         ext_model_file=True,
         disp_type='realtime'
     )
diff --git a/tests/rc/test_rc.sv b/tests/rc/test_rc.sv
index 63dae03..da9f8af 100644
--- a/tests/rc/test_rc.sv
+++ b/tests/rc/test_rc.sv
@@ -17,6 +17,8 @@ module test_rc(
         `PASS_REAL(v_out, v_out_int)
     ) model_i (
         .v_in(v_in_int),
-        .v_out(v_out_int)
+        .v_out(v_out_int),
+        .clk(clk),
+        .rst(rst)
     );
 endmodule
\ No newline at end of file