fixed occasional spacing issues

tex/chapters/9_conclusion.tex

@@ -5,7 +5,7 @@ \chapter{Conclusion}
 Universities should be working to lower the barrier of entry into SystemVerilog design. Throughout this thesis, several critical challenges in Verilog/SystemVerilog education have been addressed and resolved, contributing to the enhancement of the learning experience for students. These issues encompassed a range of areas, and the solutions put forward have had a significant impact.
 
 \begin{itemize}
-    \item \textbf{Synthesizable vs. Verification Features:} A critical issue in Verilog education lies in distinguishing between synthesizable and verification features. This thesis has addressed this concern through multiple avenues. Using netlist graph viewers like DigitalJS Online, which enables students to visualize the synthesis process, helps visually demonstrate what constructs lead to valid netlists. Additionally, style guides like from the lowRISC Organization and linters such as Verilator document best practices for writing synthesizable code. Finally, autograders can provide immediate, personalized feedback to students on whether their code is both behaviorally correct and synthesizable.
+    \item \textbf{Synthesizable vs.\ Verification Features:} A critical issue in Verilog education lies in distinguishing between synthesizable and verification features. This thesis has addressed this concern through multiple avenues. Using netlist graph viewers like DigitalJS Online, which enables students to visualize the synthesis process, helps visually demonstrate what constructs lead to valid netlists. Additionally, style guides like from the lowRISC Organization and linters such as Verilator document best practices for writing synthesizable code. Finally, autograders can provide immediate, personalized feedback to students on whether their code is both behaviorally correct and synthesizable.
     \item \textbf{Prevalence of Bugs in Common HDL Tools:} Common Verilog and SystemVerilog tools often suffer from bugs when using lesser-used features. To mitigate this, style guides and linters should be used to teach students the best syntax and strategies for avoiding common pitfalls. Autograders can also play a pivotal role by seamlessly testing student code across a multitude of tools. If a submission passes tests for several tools, it is much more likely that it will work properly for all tools.
     \item \textbf{Inaccessibility of Proprietary Tools:} The reliance on proprietary tools in Verilog education has been a barrier to accessibility for many beginners. Open-source tools highlighted in this work present a solution by being cost-free, easier to install, and more user-friendly. This shift towards open-source tools enhances equity in education and industry and enables a broader spectrum of engineers to engage effectively with Verilog.
     \item \textbf{The Lack of Reliable Educational Resources:} There is a shortage of reliable educational resources in Verilog/SystemVerilog. In this thesis, a comprehensive list of resources has been provided in \autoref{chapter:resources}, serving as a valuable reference for both instructors and students. These resources cover a range of use-cases and are designed to support a deeper understanding of synthesizable Verilog.

tex/figures/c-like.tex

@@ -23,7 +23,7 @@
     }
 
     \caption[
-        Structural vs. C-like Verilog
+        Structural vs.\ C-like Verilog
     ]{
         Provided is an example of when C-like constructs can be used to write cleaner code compared to purely structural constructs. Sub-figures \ref{subfig:structural_only} and \ref{subfig:c-like_allowed} both implement the Find First Set operation, but \ref{subfig:c-like_allowed} is better.
     }

tex/figures/dc_vs_synplify.tex

@@ -5,7 +5,7 @@
     \caption[
         Inconsistencies in SystemVerilog Support in synthesis tools
     ]{
-        Differences in SystemVerilog Support in Synopsys Design Compiler vs. Synopsys Synplify-Pro from \enquote{Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification} \cite{sutherland}
+        Differences in SystemVerilog Support in Synopsys Design Compiler vs.\ Synopsys Synplify-Pro from \enquote{Synthesizing SystemVerilog: Busting the Myth that SystemVerilog is only for Verification} \cite{sutherland}
     }
     \label{fig:dc_vs_synplify}
 \end{figure}

tex/figures/virtual_memory.tex

@@ -17,7 +17,7 @@
     \caption[
         Virtual Memory Lab
     ]{
-        The Virtual Memory Lab aids students in understanding concepts such as physical vs. virtual memory, page tables, privilege levels, and trap handling in RISC-V architecture.
+        The Virtual Memory Lab aids students in understanding concepts such as physical vs.\ virtual memory, page tables, privilege levels, and trap handling in RISC-V architecture.
     }
     \label{fig:virtual_memory}
 

tex/final/appendix.tex

@@ -55,7 +55,7 @@ \section{lowRISC Verilog Coding Style Guide}
 \section{BSG System Verilog Coding Standards}
 
 \begin{itemize}
-    \item \href{https://docs.google.com/document/d/1xA5XUzBtz_D6aSyIBQUwFk_kSUdckrfxa2uzGjMgmCU}{\footnotesize docs.google.com/document/d/1xA5XUzBtz\_D6aSyIBQUwFk\_kSUdckrfxa2uzGjMgmCU} \cite{BSGstyleguide}
+    \item {\fontsize{9}{12} \url{https://docs.google.com/document/d/1xA5XUzBtz_D6aSyIBQUwFk_kSUdckrfxa2uzGjMgmCU}} \cite{BSGstyleguide}
     \item Projects that use BSG System Verilog Coding Standards:
     \begin{itemize}
         \item Bespoke Silicon Group: BlackParrot RISC-V Core \cite{blackparrot}