diff --git a/firmware/bios/Makefile b/firmware/bios/Makefile
index e49fe6f..dd79988 100644
--- a/firmware/bios/Makefile
+++ b/firmware/bios/Makefile
@@ -3,7 +3,8 @@ CROSS ?= riscv-none-embed-
 CC = $(CROSS)gcc
 OBJCOPY = $(CROSS)objcopy
 
-CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section --specs=nano.specs
+UART_DIV ?= 13
+CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section --specs=nano.specs -DUART_DIV=$(UART_DIV)
 
 all: bios.bin
 
diff --git a/firmware/bios/start.S b/firmware/bios/start.S
index b2da890..7231280 100644
--- a/firmware/bios/start.S
+++ b/firmware/bios/start.S
@@ -9,6 +9,10 @@
 
 #define BOOT_DEBUG
 
+#ifndef UART_DIV
+# define UART_DIV 13
+#endif
+
 	.section .text.start
 	.global _start
 _start:
@@ -16,7 +20,7 @@ _start:
 #ifdef BOOT_DEBUG
 	// Set UART divisor
 	li a0, 0x81000000
-	li a1, 13
+	li a1, UART_DIV
 	sw a1, 4(a0)
 
 	// Output '1'
diff --git a/firmware/boot/Makefile b/firmware/boot/Makefile
index 66d459d..86282af 100644
--- a/firmware/boot/Makefile
+++ b/firmware/boot/Makefile
@@ -5,16 +5,18 @@ OBJCOPY = $(CROSS)objcopy
 
 CFLAGS=-Wall -Os -march=rv32i -mabi=ilp32 -ffreestanding -flto -nostartfiles -fomit-frame-pointer -Wl,--gc-section --specs=nano.specs
 
+UART_DIV ?= 13
+
 all: boot-hram.hex boot-qpi.hex boot-sim.hex
 
 boot-hram.elf: lnk-boot.lds boot.S
-	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DMEM_HRAM -o $@ boot.S
+	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DMEM_HRAM -DUART_DIV=$(UART_DIV) -o $@ boot.S
 
 boot-qpi.elf: lnk-boot.lds boot.S
-	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DMEM_QPI -o $@ boot.S
+	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DMEM_QPI  -DUART_DIV=$(UART_DIV) -o $@ boot.S
 
 boot-sim.elf: lnk-boot.lds boot.S
-	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DBOOT_SIM -o $@ boot.S
+	$(CC) $(CFLAGS) -Wl,-Bstatic,-T,lnk-boot.lds,--strip-debug -DBOOT_SIM -DUART_DIV=$(UART_DIV) -o $@ boot.S
 
 %.bin: %.elf
 	$(OBJCOPY) -O binary $< $@
diff --git a/firmware/boot/boot.S b/firmware/boot/boot.S
index 61a70b9..d2b62cf 100644
--- a/firmware/boot/boot.S
+++ b/firmware/boot/boot.S
@@ -14,6 +14,10 @@
 //#define MEM_HRAM
 //#define MEM_QPI
 
+#ifndef UART_DIV
+# define UART_DIV 13
+#endif
+
 /* Config */
 	.equ	HRAM_BASE, 0x80000000
 	.equ	QPI_BASE,  0x80000000
@@ -33,7 +37,7 @@ _start:
 #ifdef BOOT_DEBUG
 		// Set UART divisor
 	li		a0, UART_BASE
-	li		a1, 13
+	li		a1, UART_DIV
 	sw		a1, 4(a0)
 
 		// Output banner
diff --git a/gateware/riscv_linux/Makefile b/gateware/riscv_linux/Makefile
index 99170c9..b3855a6 100644
--- a/gateware/riscv_linux/Makefile
+++ b/gateware/riscv_linux/Makefile
@@ -51,6 +51,15 @@ ifeq ($(MEM),qpi)
 	YOSYS_READ_ARGS += -DMEM_QPI=1
 endif
 
+OVERCLOCK ?= 0
+
+ifeq ($(OVERCLOCK),1)
+	UART_DIV := 18
+	YOSYS_READ_ARGS += -DOVERCLOCK=1
+else
+	UART_DIV := 13
+endif
+
 # Include default rules
 include ../build/project-rules.mk
 
@@ -69,10 +78,10 @@ $(BUILD_TMP)/boot.hex:
 
 # Build of BootLoader, BIOS code and DTB
 ../../firmware/boot/%.hex: _force_run_
-	make -C ../../firmware/boot/ $*.hex
+	make -C ../../firmware/boot/ UART_DIV=$(UART_DIV) $*.hex
 
 ../../firmware/bios/%.hex: _force_run_
-	make -C ../../firmware/bios/ $*.hex
+	make -C ../../firmware/bios/ UART_DIV=$(UART_DIV) $*.hex
 
 ../../firmware/dt/ice40linux.dtb: _force_run_
 	make -C ../../firmware/dt/ ice40linux.dtb
@@ -87,6 +96,13 @@ $(BUILD_TMP)/boot-hw.hex: $(FW_BOOT_HW) $(FW_BIOS)
 $(BUILD_TMP)/boot-sim.hex: $(FW_BOOT_SIM) $(FW_BIOS)
 	./sw/hexmerge.py 0:$(FW_BOOT_SIM) 256:$(FW_BIOS) > $@
 
+# Clean
+clean-fw:
+	make -C ../../firmware/boot/ clean
+	make -C ../../firmware/bios/ clean
+	make -C ../../firmware/dt/ clean
+.PHONY: clean-fw
+
 # Force call to update .hex from other Makefiles
 _force_run_:
 .PHONY: _force_run_
diff --git a/gateware/riscv_linux/data/clocks.py b/gateware/riscv_linux/data/clocks.py
index 779abad..09f6023 100644
--- a/gateware/riscv_linux/data/clocks.py
+++ b/gateware/riscv_linux/data/clocks.py
@@ -1,4 +1,10 @@
-BASE = 15
+# Find PLL
+pll = [v for k,v in ctx.cells if 'PLL' in v.type][0]
+
+BASE = {
+	('0000', '1001111', '100'): 15,
+	('0000', '0110100', '011'): 20,
+}[(pll.params['DIVR'], pll.params['DIVF'], pll.params['DIVQ'])]
 
 ctx.addClock("clk_1x", 1 * BASE)
 ctx.addClock("clk_4x", 4 * BASE)