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| 1 | +#!/usr/bin/env python3 |
| 2 | +"""Script for generating RISC-V register definition JSON files. |
| 3 | +""" |
| 4 | + |
| 5 | +from enum import Enum |
| 6 | +import os |
| 7 | + |
| 8 | +from GenRegisterJSON import GenRegisterJSON |
| 9 | +from GenRegisterJSON import RegisterGroup |
| 10 | + |
| 11 | +def main(): |
| 12 | + # Make rv64 directory if it doesn't exist |
| 13 | + if not os.path.exists("rv64"): |
| 14 | + os.makedirs("rv64") |
| 15 | + os.chdir("rv64") |
| 16 | + |
| 17 | + # Generate rv64g int, fp and CSR registers |
| 18 | + RV64_XLEN = 8 |
| 19 | + VLEN = 32 |
| 20 | + reg_int = GenRegisterJSON(RegisterGroup.INT, 32, RV64_XLEN) |
| 21 | + reg_fp = GenRegisterJSON(RegisterGroup.FP, 32, RV64_XLEN) |
| 22 | + reg_vec = GenRegisterJSON(RegisterGroup.VEC, 32, VLEN) |
| 23 | + reg_csr = GenRegisterJSON(RegisterGroup.CSR, 0, RV64_XLEN) |
| 24 | + |
| 25 | + # Add register for the PC |
| 26 | + num = 32 |
| 27 | + reg_int.add_custom_register("pc", num, "Program counter", 8, [], {}, 0, True) |
| 28 | + |
| 29 | + # Add registers for atomic load-reservation and store-conditional instructions |
| 30 | + num += 1 |
| 31 | + reg_int.add_custom_register("resv_addr", num, "Load reservation address", 8, [], {}, 0, True) |
| 32 | + num += 1 |
| 33 | + reg_int.add_custom_register("resv_valid", num, "Load reservation valid", 8, [], {}, 0, True) |
| 34 | + |
| 35 | + reg_int.write_json("reg_int.json") |
| 36 | + reg_fp.write_json("reg_fp.json") |
| 37 | + reg_vec.write_json("reg_vec.json") |
| 38 | + reg_csr.write_json("reg_csr.json") |
| 39 | + |
| 40 | + # Make rv32 directory if it doesn't exist |
| 41 | + os.chdir("..") |
| 42 | + if not os.path.exists("rv32"): |
| 43 | + os.makedirs("rv32") |
| 44 | + os.chdir("rv32") |
| 45 | + |
| 46 | + # Generate rv32g int, fp and CSR registers |
| 47 | + RV32_XLEN = 4 |
| 48 | + reg_int = GenRegisterJSON(RegisterGroup.INT, 32, RV32_XLEN) |
| 49 | + reg_fp = GenRegisterJSON(RegisterGroup.FP, 32, RV32_XLEN) |
| 50 | + reg_vec = GenRegisterJSON(RegisterGroup.VEC, 32, VLEN) |
| 51 | + reg_csr = GenRegisterJSON(RegisterGroup.CSR, 0, RV32_XLEN) |
| 52 | + |
| 53 | + reg_int.write_json("reg_int.json"); |
| 54 | + reg_fp.write_json("reg_fp.json"); |
| 55 | + reg_vec.write_json("reg_vec.json") |
| 56 | + reg_csr.write_json("reg_csr.json"); |
| 57 | + |
| 58 | + |
| 59 | +if __name__ == "__main__": |
| 60 | + main() |
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