Skip to content

Commit

Permalink
Run rustfmt on rcc.rs
Browse files Browse the repository at this point in the history 
"cargo fmt" does not work because it requires both test mode and
the #![no_std] attribute, which the crate lib.rs doesn't enable in
test mode.  But manually running rustfmt does.
  • Loading branch information
@BryanKadzban @eldruin
BryanKadzban authored and eldruin committed Mar 27, 2024
1 parent 2b31bdd commit f6a5d1f
Showing 1 changed file with 67 additions and 39 deletions.
106 changes: 67 additions & 39 deletions src/rcc.rs
View file
Original file line number Diff line number Diff line change
Expand Up @@ -616,45 +616,61 @@ impl CFGR {
// the software division. Fortunately our 26 bit choice for the
// decimal place, and the fact that these are 1/N, means we can
// fit them into 26 bits, so a u32 is fine.
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllp {
PLLP::Div2 => 2u32,
PLLP::Div4 => 4u32,
PLLP::Div6 => 6u32,
PLLP::Div8 => 8u32,
} + 1) >> 1;
sysclk =
(((base_clk as u64 * self.plln as u64 * one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
/ match self.pllp {
PLLP::Div2 => 2u32,
PLLP::Div4 => 4u32,
PLLP::Div6 => 6u32,
PLLP::Div8 => 8u32,
}
+ 1)
>> 1;
sysclk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)

Check warning on line 629 in src/rcc.rs

View workflow job for this annotation

GitHub Actions / clippy

casting to the same type is unnecessary (`u64` -> `u64`) 

warning: casting to the same type is unnecessary (`u64` -> `u64`)
   --> src/rcc.rs:629:25
    |
629 |             sysclk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
    |                         ^^^^^^^^^^^^^^^ help: try: `base_clk`
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#unnecessary_cast
    = note: `#[warn(clippy::unnecessary_cast)]` on by default
>> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64)
>> Self::FIXED_POINT_RSHIFT
<< Self::BASE_CLK_SHIFT;
}

// Check if pll48clk is valid
if let Some(pll48clk) = self.pll48clk {
match pll48clk {
PLL48CLK::Pllq => {
pll48clk_valid = {
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_q = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1;
let pll48clk = (((base_clk as u64 * self.plln as u64
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
* one_over_q as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
let one_over_m =
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_q =
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllq as u32) + 1) >> 1;
let pll48clk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)

Check warning on line 645 in src/rcc.rs

View workflow job for this annotation

GitHub Actions / clippy

casting to the same type is unnecessary (`u64` -> `u64`) 

warning: casting to the same type is unnecessary (`u64` -> `u64`)
   --> src/rcc.rs:645:43
    |
645 |                         let pll48clk = (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
    |                                           ^^^^^^^^^^^^^^^ help: try: `base_clk`
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#unnecessary_cast
>> Self::FIXED_POINT_RSHIFT)
* one_over_q as u64)
>> Self::FIXED_POINT_RSHIFT
<< Self::BASE_CLK_SHIFT;
(48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk)
}
}
PLL48CLK::Pllsai => {
pll48clk_valid = {
if self.use_pllsai {
// base_clk * pllsain has the same range as above
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllsaip {
PLLSAIP::Div2 => 2u32,
PLLSAIP::Div4 => 4u32,
PLLSAIP::Div6 => 6u32,
PLLSAIP::Div8 => 8u32,
} + 1) >> 1;
let pll48clk = (((base_clk as u64 * self.pllsain as u64
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
let one_over_m =
((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
/ match self.pllsaip {
PLLSAIP::Div2 => 2u32,
PLLSAIP::Div4 => 4u32,
PLLSAIP::Div6 => 6u32,
PLLSAIP::Div8 => 8u32,
}
+ 1)
>> 1;
let pll48clk =
(((base_clk as u64 * self.pllsain as u64 * one_over_m as u64)

Check warning on line 669 in src/rcc.rs

View workflow job for this annotation

GitHub Actions / clippy

casting to the same type is unnecessary (`u64` -> `u64`) 

warning: casting to the same type is unnecessary (`u64` -> `u64`)
   --> src/rcc.rs:669:36
    |
669 | ...                   (((base_clk as u64 * self.pllsain as u64 * one_over_m as u64)
    |                          ^^^^^^^^^^^^^^^ help: try: `base_clk`
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#unnecessary_cast
>> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64)
>> Self::FIXED_POINT_RSHIFT
<< Self::BASE_CLK_SHIFT;
(48_000_000 - 120_000..=48_000_000 + 120_000).contains(&pll48clk)
} else {
false
Expand Down Expand Up @@ -850,9 +866,12 @@ impl CFGR {
continue;
}
// See the comments around Self::FIXED_POINT_LSHIFT to see how this works.
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;
let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT) * n as u64
* one_over_m as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT) as u32;
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;

Check warning on line 869 in src/rcc.rs

View workflow job for this annotation

GitHub Actions / clippy

casting to the same type is unnecessary (`u32` -> `u32`) 

warning: casting to the same type is unnecessary (`u32` -> `u32`)
   --> src/rcc.rs:869:65
    |
869 |             let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (m as u32) + 1) >> 1;
    |                                                                 ^^^^^^^^^^ help: try: `m`
    |
    = help: for further information visit https://rust-lang.github.io/rust-clippy/master/index.html#unnecessary_cast
let f_vco_clock = (((f_pll_clock_input as u64 >> Self::BASE_CLK_SHIFT)
* n as u64
* one_over_m as u64)
>> Self::FIXED_POINT_RSHIFT
<< Self::BASE_CLK_SHIFT) as u32;
if f_vco_clock < 50_000_000 {
m += 1;
n = 432;
Expand Down Expand Up @@ -908,7 +927,8 @@ impl CFGR {
Some(hse) => hse.freq,
None => HSI_FREQUENCY,
}
.raw() >> Self::BASE_CLK_SHIFT;
.raw()
>> Self::BASE_CLK_SHIFT;

let sysclk = if let Some(clk) = self.sysclk {
clk
Expand Down Expand Up @@ -936,21 +956,29 @@ impl CFGR {

// We check if (pllm, plln, pllp) allow to obtain the requested Sysclk,
// so that we don't have to calculate them
let one_over_m = ((1<<Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1<<Self::FIXED_POINT_LSHIFT) / match self.pllp {
PLLP::Div2 => 2u32,
PLLP::Div4 => 4u32,
PLLP::Div6 => 6u32,
PLLP::Div8 => 8u32,
} + 1) >> 1;
let one_over_m = ((1 << Self::FIXED_POINT_LSHIFT) / (self.pllm as u32) + 1) >> 1;
let one_over_p = ((1 << Self::FIXED_POINT_LSHIFT)
/ match self.pllp {
PLLP::Div2 => 2u32,
PLLP::Div4 => 4u32,
PLLP::Div6 => 6u32,
PLLP::Div8 => 8u32,
}
+ 1)
>> 1;
let p_ok = (sysclk as u64)
== (((base_clk as u64 * self.plln as u64 * one_over_m as u64) >> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64) >> Self::FIXED_POINT_RSHIFT << Self::BASE_CLK_SHIFT;
== (((base_clk as u64 * self.plln as u64 * one_over_m as u64)
>> Self::FIXED_POINT_RSHIFT)
* one_over_p as u64)
>> Self::FIXED_POINT_RSHIFT
<< Self::BASE_CLK_SHIFT;
if p_ok && q.is_none() {
return;
}

if let Some((m, n, p, q)) = CFGR::calculate_mnpq(base_clk << Self::BASE_CLK_SHIFT, FreqRequest { p, q }) {
if let Some((m, n, p, q)) =
CFGR::calculate_mnpq(base_clk << Self::BASE_CLK_SHIFT, FreqRequest { p, q })
{
self.pllm = m as u8;
self.plln = n as u16;
if let Some(p) = p {
Expand Down

0 comments on commit f6a5d1f

Please sign in to comment.