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@syntacore

Syntacore

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  1. scr1 Public

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog 914 296

  2. scr1-sdk Public

    open-source SDKs for the SCR1 core

    C 74 33

Repositories

Showing 10 of 40 repositories
  • sc-bl Public

    Syntacore first stage bootloader

    C 10 8 0 2 Updated May 13, 2025
  • snippy Public
    LLVM 59 9 11 (2 issues need help) 2 Updated May 7, 2025
  • riscv-gcc Public Forked from riscvarchive/riscv-gcc
    C 0 GPL-2.0 278 0 0 Updated Apr 2, 2025
  • u-boot Public
    C 0 0 0 0 Updated Mar 17, 2025
  • openocd Public Forked from openocd-org/openocd

    OpenOCD Syntacore targets

    C 7 855 0 0 Updated Mar 3, 2025
  • opensbi Public
    C 1 0 0 0 Updated Dec 9, 2024
  • scr1-sdk Public

    open-source SDKs for the SCR1 core

    C 74 33 1 (1 issue needs help) 0 Updated Nov 15, 2024
  • scr1 Public

    SCR1 is a high-quality open-source RISC-V MCU core in Verilog

    SystemVerilog 914 296 4 2 Updated Nov 15, 2024
  • zephyr Public Forked from zephyrproject-rtos/zephyr

    Primary GIT Repository for the Zephyr Project

    C 1 Apache-2.0 7,397 0 0 Updated Nov 9, 2024
  • linux Public
    C 3 1 0 0 Updated Oct 21, 2024
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