The RISC-V vector (V) extension is orthogonal to CHERI because the vector registers only hold integer or floating-point data. The vector registers are not extended to hold capabilities.
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Note
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A future extension may allow tags to be stored in vector registers.
Until that time, vector load and store instructions must not be used to implement generic
memory copying in software, such as the memcpy() standard C library function,
because the vector registers do not hold capabilities, so the tags of any
copied capabilities will be set to 0 in the destination memory.
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Vector loads and stores all follow the behavior as described in [section_int_load_store_insns].
The assembly syntax of all vector loads and stores are updated in {cheri_cap_mode_name}, so that the address operand becomes a c operand instead of an x operand.
According to the vector extension cite:[riscv-v-spec] only active elements are accessed or updated in memory. Therefore only active elements are subject to CHERI exception checks. If a vector load or store has no active elements then no CHERI fault will be taken.
This is consistent with other exceptions such as page faults which are only taken on active elements.
In the case of fault-only-first loads, a CHERI bounds violation is only taken if any bytes of element 0 are out of bounds, or if the CHERI bounds are malformed and there are any active elements. If another active element causes a CHERI bounds violation then it is treated the same way as other exceptions, the trap is not taken and instead vl is reduced. All other CHERI fault types, such as tag violations, are taken if there are any active elements.
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Note
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Indexed loads in {cheri_cap_mode_name} check the bounds of every access against
the authority capability in cs1. Therefore the approach of having a zero base
register and treating every element as an absolute address may not work well
in this mode.
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