tables.adoc

Appendix A: Extension summary

{lr_sc_bh_ext_name}

{lr_sc_bh_ext_name} is a separate extension independent of CHERI, but is required for CHERI software.

These instructions are not controlled by the CRE bits in [mseccfg], [menvcfg] or [senvcfg].

Table 1. {lr_sc_bh_ext_name} instruction extension

{sh4add_ext_name}

{sh4add_ext_name} is a separate extension independent of CHERI, but improves performance for CHERI code as the natural data width of pointers has doubled.

These instructions are not controlled by the CRE bits in [mseccfg], [menvcfg] or [senvcfg].

Table 2. {sh4add_ext_name} instruction extension

{cheri_base_ext_name}

{cheri_base_ext_name} defines the set of instructions supported by a core when in {cheri_cap_mode_name}.

Some instructions depend on the presence of other extensions, as listed in Table 3.

Table 3. {cheri_base_ext_name} instruction extension - Pure {cheri_cap_mode_name} instructions

{cheri_default_ext_name}

{cheri_default_ext_name} defines the set of instructions added by the {cheri_int_mode_name}, in addition to {cheri_base_ext_name}.

Note	{cheri_default_ext_name} implies {cheri_base_ext_name}

Table 4. {cheri_default_ext_name} instruction extension - {cheri_int_mode_name} instructions

Appendix B: Capability Width CSR Summary

Table 5. CSRs renamed and extended to capability width Table 6. Action taken on writing to extended CSRs^**

^* The vector range check is to ensure that vectored entry to the handler is within bounds of the capability written to Xtvecc. The check on writing must include the lowest (0 offset) and highest possible offset (e.g. 64 * MXLEN bits where HICAUSE=16).

^** XLEN bits of extended capability CSRs are written when executing [CSRRWI], [CSRRC], [CSRRS], [CSRRCI] or [CSRRSI] regardless of the CHERI execution mode. When using [CSRRW], CLEN bits are written when the CHERI execution mode is {cheri_cap_mode_name} and XLEN bits are written when the mode is {cheri_int_mode_name}; therefore, writing XLEN bits with [CSRRW] is only possible when {cheri_default_ext_name} is implemented.

Table 7. Action taken on writing to new capability CSRs⁺

⁺ XLEN bits of new capability CSRs added in {cheri_default_ext_name} are written when executing [CSRRWI], [CSRRC], [CSRRS], [CSRRCI] or [CSRRSI] regardless of the CHERI execution mode. CLEN bits are always written when using [CSRRW] regardless of the CHERI execution mode.

Note	Implementations which allow misa.C to be writable need to legalise Xepcc on reading if the misa.C value has changed since the value was written as this can cause the read value of bit [1] to change state.

Table 8. CLEN-wide CSRs storing executable vectors or data pointers

Some CSRs store executable vectors or data pointers as shown in Table 8. These CSRs do not need to store the full width address on RV64. If they store fewer address bits then writes are subject to the invalid address check in [section_invalid_addr_conv].

Table 9. CLEN-wide CSRs which store all CLEN+1 bits

Table 9 shows which CLEN-wide CSRs store all CLEN+1 bits. No other CLEN-wide CSRs store any reserved bits. All CLEN-wide CSRs store all non-reserved metadata fields.

Table 10. All CLEN-wide CSRs. {cheri_base_ext_name} is a prerequisite for all CSRs in this table

Appendix C: Instructions and CHERI Execution Mode

Table 11, Table 12 and Table 13 summarise on which CHERI execution mode each instruction may be executed in.

Table 11. Instructions valid for execution in {cheri_cap_mode_name} only Table 12. Instructions valid for execution in {cheri_int_mode_name} only Table 13. Instructions valid for execution in both {cheri_int_mode_name} and {cheri_cap_mode_name} Table 14. Mnemonics with the same encoding but mapped to different instructions in {cheri_int_mode_name} and {cheri_cap_mode_name} Table 15. Instruction encodings which vary depending on the current XLEN

Note	[MODESW_CAP], [MODESW_INT] and [SCMODE] only exist in {cheri_cap_mode_name} if {cheri_int_mode_name} is also present. A hart does not support the [m_bit] if it does not implement the {cheri_default_ext_name} extension.

Table 16. Conditions for detecting illegal CHERI instructions

Table 17 summarizes the behavior of a hart supporting both {cheri_base_ext_name} and {cheri_default_ext_name} in connection with the CRE and the CHERI execution mode while in a privilege other than debug mode.

Table 17. Hart’s behavior depending on the effective CRE and CHERI execution mode

CRE	[pcc].m	Authorizing capability1	New CHERI CSRs2	Extended CHERI CSRs3	CHERI instructions4	Compressed instructions remapped5	Note
0	X6	[ddc] or [pcc]	✘	XLEN	✘	No	Fully RISC-V compatible7
1	0	[ddc] or [pcc]	CLEN	XLEN	✔	No	{cheri_int_mode_name}
1	1	Instruction’s capability operand	CLEN	CLEN	✔	Yes	{cheri_cap_mode_name}

¹ Authorizing capability for memory access instructions.

² Whether accesses to new CHERI CSRs are permitted or raise illegal instruction exceptions. If permitted, then the bit width of the CSR read/write with [CSRRW] is indicated.

³ The bit width of accesses to extended CHERI CSRs using [CSRRW].

⁴ Whether CHERI instructions are permitted or raise illegal instruction exceptions.

⁵ See Table 14 for a list of remapped instructions.

⁶ [pcc].m is irrelevant when CRE=0.

⁷ The hart is fully compatible with standard RISC-V when CRE=0 provided that [pcc], [mtvecc], [mepcc], [stvecc], [sepcc], [vstvecc], [vsepcc] and [ddc] hold the [infinite-cap] capability.