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CsRegs.cpp
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// Copyright 2020 Western Digital Corporation or its affiliates.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#include <iostream>
#include <algorithm>
#include <cassert>
#include <cfenv>
#include <array>
#include <bit>
#include <tuple>
#include "CsRegs.hpp"
#include "FpRegs.hpp"
#include "VecRegs.hpp"
#include "float-util.hpp"
using namespace WdRiscv;
template <typename URV>
CsRegs<URV>::CsRegs()
: regs_(size_t(CsrNumber::MAX_CSR_) + 1)
{
// Define CSR entries.
defineMachineRegs();
defineSupervisorRegs();
defineUserRegs();
defineHypervisorRegs();
defineDebugRegs();
defineVectorRegs();
defineFpRegs();
defineAiaRegs();
defineStateEnableRegs();
defineEntropyReg();
definePmaRegs();
defineSteeRegs();
}
template <typename URV>
CsRegs<URV>::~CsRegs()
{
regs_.clear();
nameToNumber_.clear();
}
template <typename URV>
Csr<URV>*
CsRegs<URV>::defineCsr(std::string name, CsrNumber csrn, bool mandatory,
bool implemented, URV resetValue, URV writeMask,
URV pokeMask, bool quiet)
{
size_t ix = size_t(csrn);
if (ix >= regs_.size())
return nullptr;
if (nameToNumber_.contains(name))
{
if (not quiet)
std::cerr << "Error: CSR " << name << " already defined\n";
return nullptr;
}
auto& csr = regs_.at(ix);
if (csr.isDefined())
{
if (not quiet)
std::cerr << "Error: CSR 0x" << std::hex << size_t(csrn) << std::dec
<< " is already defined as " << csr.getName() << '\n';
return nullptr;
}
PrivilegeMode priv = PrivilegeMode((ix & 0x300) >> 8);
if (priv == PrivilegeMode::Reserved) {
priv = PrivilegeMode::Supervisor;
}
csr.definePrivilegeMode(priv);
csr.setIsDebug(csrn >= CsrNumber::_MIN_DBG and csrn <= CsrNumber::_MAX_DBG);
csr.setDefined(true);
csr.config(name, csrn, mandatory, implemented, resetValue, writeMask, pokeMask);
nameToNumber_.insert_or_assign(std::move(name), csrn);
return &csr;
}
template <typename URV>
Csr<URV>*
CsRegs<URV>::findCsr(std::string_view name)
{
const auto iter = nameToNumber_.find(name);
if (iter == nameToNumber_.end())
return nullptr;
size_t num = size_t(iter->second);
if (num >= regs_.size())
return nullptr;
return ®s_.at(num);
}
template <typename URV>
Csr<URV>*
CsRegs<URV>::findCsr(CsrNumber number)
{
size_t ix = size_t(number);
if (ix >= regs_.size())
return nullptr;
return ®s_.at(ix);
}
template <typename URV>
const Csr<URV>*
CsRegs<URV>::findCsr(CsrNumber number) const
{
size_t ix = size_t(number);
if (ix >= regs_.size())
return nullptr;
return ®s_.at(ix);
}
template <typename URV>
Csr<URV>*
CsRegs<URV>::getImplementedCsr(CsrNumber num, bool virtualMode)
{
auto csr = getImplementedCsr(num);
if (not csr)
return csr;
if (not virtualMode)
return csr;
if (not csr->mapsToVirtual())
return csr;
num = advance(num, 0x100); // Get VCSR corresponding to CSR.
return getImplementedCsr(num);
}
template <typename URV>
const Csr<URV>*
CsRegs<URV>::getImplementedCsr(CsrNumber num, bool virtualMode) const
{
auto csr = getImplementedCsr(num);
if (not csr)
return csr;
if (not virtualMode)
return csr;
if (not csr->mapsToVirtual())
return csr;
num = advance(num, 0x100); // Get VCSR corresponding to CSR.
return getImplementedCsr(num);
}
template <typename URV>
bool
CsRegs<URV>::readSip(URV& value) const
{
value = 0;
auto sip = getImplementedCsr(CsrNumber::SIP);
if (not sip)
return false;
value = effectiveSip();
// Bits SGEIP, VSEIP, VSTIP, VSSIP are read-only zero in SIE/SIP.
value &= ~ URV(0x1444);
return true;
}
template <typename URV>
bool
CsRegs<URV>::readSie(URV& value) const
{
value = 0;
auto sie = getImplementedCsr(CsrNumber::SIE);
if (not sie)
return false;
auto sieVal = sie->read();
value = sieVal;
auto deleg = getImplementedCsr(CsrNumber::MIDELEG);
auto mvien = getImplementedCsr(CsrNumber::MVIEN);
auto mvip = getImplementedCsr(CsrNumber::MVIP);
if (deleg and mvien and mvip)
{
// Where MIDELEG is 0 and MVIEN is 1, SIE becomes writable.
URV mask = mvien->read() & ~deleg->read();
value = shadowSie_ & mask;
// Everywhere else it is masked by MIDELEG
mask = ~mask & deleg->read();
value |= (sieVal & mask);
}
else if (deleg)
value = sieVal & deleg->read();
// Bits SGEIP, VSEIP, VSTIP, VSSIP are read-only zero in SIE/SIP.
value &= ~ URV(0x1444);
return true;
}
template <typename URV>
bool
CsRegs<URV>::readMvip(URV& value) const
{
value = 0;
auto mvip = getImplementedCsr(CsrNumber::MVIP);
if (not mvip)
return false;
value = mvip->read();
auto mip = getImplementedCsr(CsrNumber::MIP);
auto mvien = getImplementedCsr(CsrNumber::MVIEN);
if (mip and mvien)
{
// Bit 1 is an alias of mip when MVIEN is not set.
URV b1 = URV(0x2);
URV mask = mvien->read() ^ b1;
mask &= b1;
value = (value & ~mask) | (mip->read() & mask);
// Bit STIE (5) of MVIP is an alias to bit 5 of MIP if bit 5 of MIP is writable.
// Othrwise, it is zero.
mask = URV(0x20); // Bit 5
value &= ~mask; // Clear bit 5.
if ((mip->getWriteMask() & mask) != 0) // Bit 5 writable in mip
value |= (mip->read() & mask); // Set bit 5 to that of mip
}
return true;
}
template <typename URV>
bool
CsRegs<URV>::writeMvip(URV value)
{
auto mvip = getImplementedCsr(CsrNumber::MVIP);
if (not mvip)
return false;
auto mvien = getImplementedCsr(CsrNumber::MVIEN);
auto mip = getImplementedCsr(CsrNumber::MIP);
if (mvien and mip)
{
// Bit 1/9 of MVIP is an alias to bit 1/9 in MIP if bit 1/9 is not set in MVIEN.
URV mvienVal = mvien->read();
URV mask = mvienVal;
URV b19 = URV(0x202);
mask ^= b19;
// Bit STIE (5) of MVIP is an alias to bit 5 of MIP if bit 5 of MIP is writable.
// Othrwise, it is zero.
URV b5 = URV(0x20); // Bit 5 mask
if ((mip->getWriteMask() & b5) != 0) // Bit 5 writable in mip
mask |= b5;
mask &= b19 | b5;
mip->write((mip->read() & ~mask) | (value & mask));
recordWrite(CsrNumber::MIP);
}
mvip->write(value);
recordWrite(CsrNumber::MVIP);
return true;
}
template <typename URV>
bool
CsRegs<URV>::writeMvien(URV value)
{
auto mvien = getImplementedCsr(CsrNumber::MVIEN);
mvien->write(value);
recordWrite(CsrNumber::MVIEN);
auto mip = getImplementedCsr(CsrNumber::MIP);
if (mip)
{
URV b9 = URV(0x200);
URV mask = (mvien->read() ^ b9) & b9;
// Bit 9 is read-only when MVIEN is set.
mip->setWriteMask((mip->getWriteMask() & ~b9) | mask);
}
// Bits 13-63 are read-only zero in hideleg if both
// mideleg/mvien are not set.
auto mideleg = getImplementedCsr(CsrNumber::MIDELEG);
auto hideleg = getImplementedCsr(CsrNumber::HIDELEG);
if (mideleg and hideleg)
{
URV mask = URV(0x1fff);
hideleg->setReadMask((hideleg->getReadMask() & mask) |
(mideleg->read() & value & ~mask));
hideleg->write(hideleg->read());
}
return true;
}
template <typename URV>
URV
CsRegs<URV>::adjustTimeValue(CsrNumber num, URV value, bool virtMode) const
{
if (not virtMode)
return value;
auto delta = getImplementedCsr(CsrNumber::HTIMEDELTA);
if (num == CsrNumber::TIME)
{
if (delta)
value += delta->read();
}
else if (num == CsrNumber::TIMEH)
{
auto time = getImplementedCsr(CsrNumber::TIME);
auto deltah = getImplementedCsr(CsrNumber::HTIMEDELTAH);
if (time and delta and deltah)
{
uint64_t t64 = (uint64_t(value) << 32) | uint32_t(time->read());
uint64_t d64 = (uint64_t(deltah->read()) << 32) | uint32_t(delta->read());
t64 += d64;
value = t64 >> 32;
}
}
return value;
}
template <typename URV>
URV
CsRegs<URV>::adjustSstateenValue(CsrNumber num, URV value, bool virtMode) const
{
using CN = CsrNumber;
if (num >= CN::SSTATEEN0 and num <= CN::SSTATEEN3)
{
CN base = CN::SSTATEEN0;
unsigned ix = unsigned(num) - unsigned(base);
// If a bit is zero in MSTATEEN, it becomes zero in SSTATEEN
CsrNumber mnum = advance(CN::MSTATEEN0, ix);
auto mcsr = getImplementedCsr(mnum);
if (mcsr)
value &= mcsr->read();
// If a bit is zero in HSTATEEN, it becomes zero in SSTATEEN
if (virtMode)
{
CsrNumber hnum = advance(CN::HSTATEEN0, ix);
auto hcsr = getImplementedCsr(hnum);
if (hcsr)
value &= hcsr->read();
}
}
return value;
}
template <typename URV>
URV
CsRegs<URV>::adjustHstateenValue(CsrNumber num, URV value) const
{
using CN = CsrNumber;
if ((num >= CN::HSTATEEN0 and num <= CN::HSTATEEN3) or
(num >= CN::HSTATEEN0H and num <= CN::HSTATEEN3H))
{
CN base = CN::HSTATEEN0;
if (num >= CN::HSTATEEN0H and num <= CN::HSTATEEN3H)
base = CN::HSTATEEN0H;
unsigned ix = unsigned(num) - unsigned(base);
// If a bit is zero in MSTATEEN, it becomes zero in HSTATEEN
CN mnum = CN::MSTATEEN0;
if (num >= CN::HSTATEEN0H and num <= CN::HSTATEEN3H)
mnum = CN::MSTATEEN0H;
mnum = advance(mnum, ix);
auto mcsr = getImplementedCsr(mnum);
if (mcsr)
value &= mcsr->read();
}
return value;
}
template <typename URV>
URV
CsRegs<URV>::adjustScountovfValue(URV value, bool virtMode) const
{
auto csr = getImplementedCsr(CsrNumber::MCOUNTEREN);
assert(csr and "MCOUNTEREN not implemented");
URV mask = csr->read();
if (virtMode)
{
csr = getImplementedCsr(CsrNumber::HCOUNTEREN);
assert(csr and "HCOUNTERN not implemented");
mask &= csr->read();
}
return value & mask;
}
template <typename URV>
bool
CsRegs<URV>::readMireg(CsrNumber num, URV& value, bool virtMode) const
{
URV sel = 0;
peek(CsrNumber::MISELECT, sel);
if (imsic_)
{
auto csr = getImplementedCsr(num, virtMode);
if (not csr)
return false;
return imsic_->readMireg(sel, value);
}
return false;
}
template <typename URV>
bool
CsRegs<URV>::readSireg(CsrNumber num, URV& value, bool virtMode) const
{
URV sel = 0;
peek(CsrNumber::SISELECT, sel);
if (imsic_)
{
auto csr = getImplementedCsr(num, virtMode);
if (not csr)
return false;
unsigned guest = 0;
if (virtMode)
{
URV hs = 0;
peek(CsrNumber::HSTATUS, hs);
HstatusFields<URV> hsf(hs);
guest = hsf.bits_.VGEIN;
}
return imsic_->readSireg(virtMode, guest, sel, value);
}
return false;
}
template <typename URV>
bool
CsRegs<URV>::readVsireg(CsrNumber num, URV& value, bool virtMode) const
{
URV sel = 0;
peek(CsrNumber::VSISELECT, sel);
if (imsic_)
{
auto csr = getImplementedCsr(num, virtMode);
if (not csr)
return false;
URV hs = 0;
peek(CsrNumber::HSTATUS, hs);
HstatusFields<URV> hsf(hs);
unsigned guest = hsf.bits_.VGEIN;
return imsic_->readSireg(true, guest, sel, value);
}
return false;
}
template <typename URV>
bool
CsRegs<URV>::read(CsrNumber num, PrivilegeMode mode, URV& value) const
{
using CN = CsrNumber;
if (not isReadable(num, mode, virtMode_))
return false;
auto csr = getImplementedCsr(num, virtMode_);
num = csr->getNumber(); // CSR may have been remapped from S to VS
if (num >= CN::TDATA1 and num <= CN::TINFO)
return readTrigger(num, mode, value);
if (num == CN::FFLAGS or num == CN::FRM)
{
auto fcsr = getImplementedCsr(CN::FCSR);
if (not fcsr)
return false;
value = fcsr->read();
if (num == CN::FFLAGS)
value = FcsrFields{value}.bits_.FFLAGS;
else
value = FcsrFields{value}.bits_.FRM;
return true;
}
else if (num == CN::MIREG)
return readMireg(num, value, virtMode_);
else if (num == CN::SIREG)
return readSireg(num, value, virtMode_);
else if (num == CN::VSIREG)
return readVsireg(num, value, virtMode_);
else if (num == CN::SIP)
return readSip(value);
else if (num == CN::SIE)
return readSie(value);
if (num == CN::MTOPEI)
{
if (not imsic_)
return false;
value = imsic_->machineTopId();
value |= value << 16; // Bits 26:16 same as bits 10;0 as required by spec.
return true;
}
else if (num == CN::STOPEI)
{
if (not imsic_)
return false;
value = imsic_->supervisorTopId();
value |= value << 16; // Bits 26:16 same as bits 10;0 as required by spec.
return true;
}
else if (num == CN::VSTOPEI)
{
if (not imsic_)
return false;
const auto& hs = regs_.at(size_t(CsrNumber::HSTATUS));
URV hsVal = hs.read();
HstatusFields<URV> hsf(hsVal);
unsigned vgein = hsf.bits_.VGEIN;
if (not vgein or vgein >= imsic_->guestCount())
return false;
value = imsic_->guestTopId(vgein);
value |= value << 16; // Bits 26:16 same as bits 10;0 as required by spec.
return true;
}
if (num == CN::MTOPI or num == CN::STOPI or num == CN::VSTOPI)
return readTopi(num, value, virtMode_);
else if (num == CN::SIE)
return readSie(value);
else if (num == CN::SIP)
return readSip(value);
else if (num == CN::MVIP)
return readMvip(value);
value = csr->read();
if (virtMode_ and (num == CN::TIME or num == CN::TIMEH))
value = adjustTimeValue(num, value, virtMode_); // In virt mode, time is time + htimedelta.
else if (num >= CN::PMPADDR0 and num <= CN::PMPADDR63)
value = adjustPmpValue(num, value);
else if (num >= CN::SSTATEEN0 and num <= CN::SSTATEEN3)
value = adjustSstateenValue(num, value, virtMode_);
else if ((num >= CN::HSTATEEN0 and num <= CN::HSTATEEN3) or
(num >= CN::HSTATEEN0H and num <= CN::HSTATEEN3H))
value = adjustHstateenValue(num, value);
else if (num == CN::SCOUNTOVF and mode != PrivilegeMode::Machine)
value = adjustScountovfValue(value, virtMode_);
return true;
}
template <typename URV>
bool
CsRegs<URV>::readSignExtend(CsrNumber number, PrivilegeMode mode, URV& value) const
{
if (not read(number, mode, value))
return false;
if (value == 0)
return true;
auto csr = getImplementedCsr(number, virtMode_);
URV mask = csr->getWriteMask();
unsigned lz = std::countl_zero(mask);
using SRV = typename std::make_signed_t<URV>;
SRV svalue = value;
svalue = (svalue << lz) >> lz;
value = svalue;
return true;
}
template <typename URV>
void
CsRegs<URV>::enableSupervisorMode(bool flag)
{
superEnabled_ = flag;
using CN = CsrNumber;
auto enableCsr = [this] (CN csrn, bool flag) {
auto csr = findCsr(csrn);
if (csr)
csr->setImplemented(flag);
};
for (auto csrn : { CN::SSTATUS, CN::SIE, CN::STVEC, CN::SCOUNTEREN,
CN::SSCRATCH, CN::SEPC, CN::SCAUSE, CN::STVAL, CN::SIP,
CN::SENVCFG, CN::SATP, CN::MEDELEG, CN::MIDELEG,
CN::SCONTEXT } )
enableCsr(csrn, flag);
if (hyperEnabled_)
for (auto csrn : { CN::VSSTATUS, CN::VSIE, CN::VSTVEC, CN::VSSCRATCH,
CN::VSEPC, CN::VSCAUSE, CN::VSTVAL, CN::VSIP, CN::VSATP } )
enableCsr(csrn, flag);
using IC = InterruptCause;
// In MIP/MIE, make writable/pokable bits corresponding to
// SEIP/STIP/SSIP (supervisor external/timer/software interrupt
// pending) when sstc is enabled and read-only-zero when supervisor
// is disabled.
URV sbits = ( URV(1) << unsigned(IC::S_EXTERNAL) |
URV(1) << unsigned(IC::S_TIMER) |
URV(1) << unsigned(IC::S_SOFTWARE) );
for (auto csrn : { CN::MIP, CN::MIE } )
{
auto csr = findCsr(csrn);
if (csr)
{
URV mask = csr->getWriteMask();
mask = flag? mask | sbits : mask & ~sbits;
csr->setWriteMask(mask);
mask = csr->getPokeMask();
mask = flag? mask | sbits : mask & ~sbits;
csr->setPokeMask(mask);
}
}
// Make IR/TM/CY bits read only zero in MCOUNTERNE/SCOUNTEREN/HCOUNTEREN if the
// RETIRED/TIME/CYCLE CSRs is not implemented. This is not explicitly stated in the spec
// but it is in the lore.
URV mask = 0; // Least sig 3 bits of MCOUNTEREN.
if (regs_.at(unsigned(CN::CYCLE)).isImplemented())
mask |= 1;
if (regs_.at(unsigned(CN::TIME)).isImplemented())
mask |= 2;
if (regs_.at(unsigned(CN::INSTRET)).isImplemented())
mask |= 4;
auto& mce = regs_.at(unsigned(CN::MCOUNTEREN));
auto& sce = regs_.at(unsigned(CN::SCOUNTEREN));
auto& hce = regs_.at(unsigned(CN::SCOUNTEREN));
mce.setReadMask((mce.getReadMask() & ~URV(7)) | mask);
sce.setReadMask((sce.getReadMask() & ~URV(7)) | mask);
hce.setReadMask((hce.getReadMask() & ~URV(7)) | mask);
updateSstc(); // To activate/deactivate STIMECMP.
enableSscofpmf(cofEnabled_); // To activate/deactivate SCOUNTOVF.
enableSmstateen(stateenOn_); // To activate/deactivate STATEEN CSRs.
enableSdtrig(sdtrigOn_); // To activate/deactivate SCONTEXT.
enableSsqosid(ssqosidOn_); // To activate/deactivate SRMCFG.
}
template <typename URV>
void
CsRegs<URV>::updateSstc()
{
bool stce = menvcfgStce();
URV mMask = 0;
if (not peek(CsrNumber::MCOUNTEREN, mMask))
return;
bool mTm = (mMask & 2) >> 1;
PrivilegeMode mode = (stce & mTm)? PrivilegeMode::Supervisor : PrivilegeMode::Machine;
auto stimecmp = findCsr(CsrNumber::STIMECMP);
if (sstcEnabled_ and not stimecmp->isImplemented())
stimecmp->setImplemented(true);
stimecmp->setPrivilegeMode(mode);
stimecmp->setHypervisor(stce);
if (rv32_)
{
auto stimecmph = findCsr(CsrNumber::STIMECMPH);
if (sstcEnabled_ and not stimecmph->isImplemented())
stimecmph->setImplemented(true);
stimecmph->setPrivilegeMode(mode);
stimecmp->setHypervisor(stce);
}
if (superEnabled_)
{
// S_TIMER bit in MIP is read-only if stimecmp is implemented and
// writeable if it is not.
auto mip = findCsr(CsrNumber::MIP);
if (mip)
{
URV mask = mip->getWriteMask();
URV stBit = URV(1) << unsigned(InterruptCause::S_TIMER);
bool readOnly = stce;
mask = readOnly? mask & ~stBit : mask | stBit;
mip->setWriteMask(mask);
}
}
URV hMask = 0;
peek(CsrNumber::HCOUNTEREN, hMask);
bool hstce = henvcfgStce();
bool hTm = (hMask & 2) >> 1;
auto vstimecmp = findCsr(CsrNumber::VSTIMECMP);
vstimecmp->setImplemented(sstcEnabled_ and hyperEnabled_);
vstimecmp->setPrivilegeMode(mode);
if (rv32_)
{
auto vstimecmph = findCsr(CsrNumber::VSTIMECMPH);
vstimecmph->setImplemented(sstcEnabled_ and hyperEnabled_);
vstimecmph->setPrivilegeMode(mode);
}
if (stce)
{
bool noVs = not (hstce and hTm);
stimecmp->setHypervisor(noVs);
if (rv32_)
findCsr(CsrNumber::STIMECMPH)->setHypervisor(noVs);
}
// If henvcfg.VSTCE is cleared, we also clear the VSTIP bit. This is
// unspecified behavior and we do this to match RTL.
auto mip = findCsr(CsrNumber::MIP);
if (mip and not hstce)
{
URV mask = URV(1) << URV(InterruptCause::VS_TIMER);
auto hvip = findCsr(CsrNumber::HVIP);
URV vstip = hvip? hvip->read() : 0;
mip->poke((mip->read() & ~mask) | vstip);
hyperWrite(mip);
}
auto hip = findCsr(CsrNumber::HIP);
if (hip)
{
// Update VSTIP bit in HIP. See chapter 3 of SSTC spc.
URV mask = hip->getReadMask();
URV vstBit = URV(1) << unsigned(InterruptCause::VS_TIMER);
if (stce and not hstce)
mask = mask & ~vstBit; // Make read-only zero
else
mask = mask | vstBit; // Make readable
hip->setReadMask(mask);
}
}
template <typename URV>
void
CsRegs<URV>::enableHypervisorMode(bool flag)
{
hyperEnabled_ = flag;
using CN = CsrNumber;
auto enableCsr = [this] (CN csrn, bool flag) {
auto csr = findCsr(csrn);
if (csr)
csr->setImplemented(flag);
};
for (auto csrn : { CN::HSTATUS, CN::HEDELEG, CN::HIDELEG, CN::HIE, CN::HCOUNTEREN,
CN::HGEIE, CN::HTVAL, CN::HIP, CN::HVIP, CN::HTINST, CN::HGEIP, CN::HENVCFG,
CN::HGATP, CN::HCONTEXT, CN::HTIMEDELTA, CN::MTVAL2, CN::MTINST, CN::HCONTEXT } )
enableCsr(csrn, flag);
if (rv32_)
for (auto csrn : { CN::HENVCFGH, CN::HTIMEDELTAH } )
enableCsr(csrn, flag);
if (superEnabled_)
for (auto csrn : { CN::VSSTATUS, CN::VSIE, CN::VSTVEC, CN::VSSCRATCH,
CN::VSEPC, CN::VSCAUSE, CN::VSTVAL, CN::VSIP, CN::VSATP })
enableCsr(csrn, flag);
// Enable/disable MPV and GVA bits
{
uint64_t hyperBits;
Csr<URV>* mstatus;
if (not rv32_)
{
hyperBits = uint64_t(0x3) << 38;
mstatus = findCsr(CN::MSTATUS);
}
else
{
hyperBits = 0x3 << 6;
mstatus = findCsr(CN::MSTATUSH);
}
if (not flag)
mstatus->write(mstatus->read() & ~hyperBits); // Clear MPV and GVA.
URV mask = mstatus->getWriteMask();
mask = flag? (mask | hyperBits) : (mask & ~hyperBits);
mstatus->setWriteMask(mask);
mask = mstatus->getPokeMask();
mask = flag? (mask | hyperBits) : (mask & ~hyperBits);
mstatus->setPokeMask(mask);
mask = mstatus->getReadMask();
mask = flag? (mask | hyperBits) : (mask & ~hyperBits);
mstatus->setReadMask(mask);
}
// Bits correspondig to VSEIP, VSTIP, VSSIP, and SGEIP.
URV vsBits = 0x444;
URV sgBit = geilen_ ? 0x1000 : 0; // Bit SGEIP
auto csr = findCsr(CN::MIDELEG);
if (flag)
{
// Make VSEIP, VSTIP, and VSSIP and posibly SGEIP read-only one.
URV rooMask = vsBits | sgBit; // Bits to be made read-only-one.
csr->setWriteMask(csr->getWriteMask() | rooMask); // Make bits writeable.
csr->setReadMask(csr->getReadMask() | rooMask); // Open for reading.
csr->write(csr->read() | rooMask); // Set bits to one.
csr->setWriteMask(csr->getWriteMask() & ~rooMask); // Make bits read-only.
}
else
{
// Make VSEIP, VSTIP, VSSIP, and SGEIP read only zero.
auto mask = csr->getReadMask();
mask &= ~URV(0x1444);
csr->setReadMask(mask);
}
if (flag)
{
auto hideleg = getImplementedCsr(CsrNumber::HIDELEG);
assert(hideleg);
auto vsip = getImplementedCsr(CsrNumber::VSIP);
auto vsie = getImplementedCsr(CsrNumber::VSIE);
URV mask = 0x222; // Bits VSEIP, VSTIP, and VSSIP of VSIP
mask &= (hideleg->read() >> 1);
if (vsip)
vsip->setReadMask(mask);
if (vsie)
vsie->setReadMask(mask);
}
// If hypervisor is off, related bits in MEDELEG are read-only-zero (bits 23:20 and 10).
csr = findCsr(CN::MEDELEG);
if (csr)
{
URV bits = URV(0xf) << 20; // Bits 23:20
bits |= URV(1) << 10; // Bit 10
auto mask = csr->getReadMask();
csr->setReadMask(flag ? (mask | bits) : (mask & ~bits));
}
// Bit MIP.VSSIP is writeable if hypervisor is enabled, otherwise it is not
csr = findCsr(CN::MIP);
if (csr)
{
URV bit = 4;
auto mask = csr->getWriteMask();
csr->setWriteMask(flag ? (mask | bit) : (mask & ~bit));
}
// In MIE, bits VSEIE, VSTIE, VSSIE, and SGEIE become read-only-zero if no hypervisor.
csr = findCsr(CN::MIE);
if (csr)
{
URV bits = 0x1444;
auto mask = csr->getReadMask();
csr->setReadMask(flag ? (mask | bits) : (mask & ~bits));
if (not flag)
csr->write(csr->read()); // Clear bits in CSR that are now read-only-zero.
mask = csr->getWriteMask();
csr->setWriteMask(flag ? (mask | bits) : (mask & ~bits));
}
updateSstc(); // To activate/deactivate VSTIMECMP.
enableSmstateen(stateenOn_); // To activate/deactivate STATEEN CSRs.
enableAia(aiaEnabled_); // To activate/deactivate AIA hypervisor CSRs.
enableSdtrig(sdtrigOn_); // To activate/deactivate HCONTEXT.
enableSsqosid(ssqosidOn_); // To activate/deactivate SRMCFG.
triggers_.enableHypervisor(flag);
}
template <typename URV>
void
CsRegs<URV>::enableRvf(bool flag)
{
for (auto csrn : { CsrNumber::FCSR, CsrNumber::FFLAGS, CsrNumber::FRM } )
{
auto csr = findCsr(csrn);
if (not csr)
{
std::cerr << "Error: enableRvf: CSR number 0x"
<< std::hex << URV(csrn) << std::dec << " undefined\n";
assert(0);
}
else if (not csr->isImplemented())
csr->setImplemented(flag);
}
// If neither F or S extension is enabled then FS bits in MSTATUS are
// read only zero; otherwise, they are readable.
auto mstatus = findCsr(CsrNumber::MSTATUS);
if (mstatus)
{
MstatusFields<URV> fields(mstatus->getReadMask());
fields.bits_.FS = 0;
if (flag or superEnabled_)
fields.bits_.FS = ~ fields.bits_.FS;
mstatus->setReadMask(fields.value_);
}
}
template <typename URV>
void
CsRegs<URV>::enableSscofpmf(bool flag)
{
cofEnabled_ = flag;
auto csrn = CsrNumber::SCOUNTOVF;
auto csr = findCsr(csrn);
if (not csr)
{
std::cerr << "Error: enableSscofpmf: CSR number 0x"
<< std::hex << URV(csrn) << std::dec << " is not defined\n";
assert(0);
}
else
csr->setImplemented(flag & superEnabled_);
// Add CSR fields.
std::vector<typename Csr<URV>::Field> hpm = {{"zero", 3}};
for (unsigned i = 3; i <= 31; ++i)
hpm.push_back({"HPM" + std::to_string(i), 1});
setCsrFields(csrn, hpm);
// Mask/unmask LCOF bits
for (auto csrn : {CsrNumber::MIE, CsrNumber::MIP, CsrNumber::SIE, CsrNumber::SIP})
{
auto csr = findCsr(csrn);
if (csr)
{
auto lcof = URV(1) << URV(InterruptCause::LCOF);
if (flag)
{
csr->setWriteMask(csr->getWriteMask() | lcof);
csr->setReadMask(csr->getReadMask() | lcof);
}
else
{
csr->setWriteMask(csr->getWriteMask() & ~lcof);
csr->setReadMask(csr->getReadMask() & ~lcof);
}
}
}
mPerfRegs_.enableOverflow(flag);
if (flag and not mPerfRegs_.ovfCallback_)
{
// Define callback to be invoked when a counter overflows. The
// callback sets the LCOF bit of the MIP CSR.
mPerfRegs_.ovfCallback_ = [this](unsigned ix) {
assert(ix < 29);