{reg: [ {bits: 2, name: 'op', type: 8, attr: ['2','C2=10']}, {bits: 5, name: 'cs2', type: 4, attr: ['5','src']}, {bits: 6, name: 'imm', type: 3, attr: ['6','offset[5:3|8:6]','offset[5:4|9:6]']}, {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap rv32: C.SCSP=111', 'cap rv64: C.SCSP=101']}, ], config: {bits: 16}}
{reg: [ {bits: 2, name: 'op', type: 8, attr: ['2', 'C0=00']}, {bits: 3, name: 'cs2\'', type: 3, attr: ['3', 'src']}, {bits: 2, name: 'imm', type: 2, attr: ['2', 'offset[7:6]','offset[7:6]']}, {bits: 3, name: 'cs1\'', type: 3, attr: ['3', 'base']}, {bits: 3, name: 'imm', types:3, attr: ['3', 'offset[5:3]','offset[5:4|8]']}, {bits: 3, name: 'funct3', type: 8, attr: ['3', 'cap rv32: C.SC=111','cap rv64: C.SC=101']}, ], config: {bits: 16}}