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Mention B-ext support in README
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README.md

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Shuttle: A Rocket-based Superscalar In-order RISC-V Core
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Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDC instruction set with supervisor and user-mode.
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Shuttle is a Rocket-based superscalar in-order RISC-V core, supporting the base RV64IMAFDCB instruction set with supervisor and user-mode.
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Shuttle is a 6-stage core that can be configured to be dual, three, or quad-issue, although dual-issue is the most sensible design point.
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Shuttle is *not* designed to meet any power, performance, or area targets.
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It exists purely as a demonstrative example of another RISC-V CPU design point.

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