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vikramjain236vikramjain236
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Merge pull request #80 from ucb-ucie/protocol
Fixing the tlfront with clock source node
2 parents e9d2790 + 816bc50 commit 2388f0d

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4 files changed

+131
-103
lines changed

4 files changed

+131
-103
lines changed

‎src/main/scala/tilelink/Configs.scala

+5-4
Original file line numberDiff line numberDiff line change
@@ -29,14 +29,15 @@ trait CanHaveTLUCIAdapter { this: BaseSubsystem =>
2929
protoParams = params.proto,
3030
fdiParams = params.fdi
3131
))
32+
uciTL.clockNode := bus.fixedClockNode
3233
bus.coupleTo(s"ucie_tl_man_port") {
33-
uciTL.managerNode :*= TLWidthWidget(bus.beatBytes) :*= TLFragmenter(bus.beatBytes, p(CacheBlockBytes)) :*= _
34+
uciTL.managerNode := TLWidthWidget(bus.beatBytes) := TLSourceShrinker(params.tl.sourceIDWidth) := TLFragmenter(bus.beatBytes, p(CacheBlockBytes)) := _
3435
} //manager node because SBUS is making request?
35-
bus.coupleFrom(s"ucie_tl_cl_port") { _ :*= TLFragmenter(bus.beatBytes, p(CacheBlockBytes)) :*= TLWidthWidget(bus.beatBytes) :*= uciTL.clientNode }
36+
bus.coupleFrom(s"ucie_tl_cl_port") { _ := TLWidthWidget(bus.beatBytes) := uciTL.clientNode }
37+
bus.coupleTo(s"ucie_tl_ctrl_port") { uciTL.regNode.node := TLWidthWidget(bus.beatBytes) := TLFragmenter(bus.beatBytes, bus.blockBytes) := _ }
3638
}
3739
}
3840

3941
class WithUCITLAdapter(params: UCITLParams) extends Config((site, here, up) => {
4042
case UCITLKey => Some(params)
41-
})
42-
43+
})

‎src/main/scala/tilelink/UCITLFront.scala

+54-54
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ import sideband._
2323
*/
2424
class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerParams,
2525
val fdiParams: FdiParams)
26-
(implicit p: Parameters) extends LazyModule {
26+
(implicit p: Parameters) extends ClockSinkDomain(ClockSinkParameters())(p) {
2727

2828
val device = new SimpleDevice("ucie-front", Seq("ucie,ucie0"))
2929

@@ -49,40 +49,40 @@ class UCITLFront(val tlParams: TileLinkParams, val protoParams: ProtocolLayerPar
4949
val clientNode: TLClientNode = TLClientNode(Seq(TLMasterPortParameters.v1(
5050
Seq(TLMasterParameters.v1(
5151
name = "ucie-client",
52-
sourceId = IdRange(0, 32),
52+
sourceId = IdRange(0, 1 << tlParams.sourceIDWidth),
5353
requestFifo = true,
5454
visibility = Seq(AddressSet(tlParams.ADDRESS, tlParams.ADDR_RANGE))
5555
)))))
5656

57-
lazy val module = new UCITLFrontImp(this)
58-
}
57+
override lazy val module = new UCITLFrontImp
5958

60-
class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
59+
class UCITLFrontImp extends Impl {
6160
val io = IO(new Bundle {
6261
// val sbus_clk = Input(Clock()) // System bus clock
6362
// val sbus_reset = Input(Bool()) // System bus reset
6463
// val lclk = Input(Clock()) // lclk is the FDI signalling clock
6564
// val lreset = Input(Bool()) // should the UCIe modules have its own reset?
66-
val fdi = new Fdi(outer.fdiParams)
65+
val fdi = new Fdi(fdiParams)
6766
})
67+
withClockAndReset(clock, reset) {
6868

6969
val fault = RegInit(false.B) // if fault in ecc code
7070

7171
// Instantiate the agnostic protocol layer
72-
val protocol = Module(new ProtocolLayer(outer.fdiParams))
72+
val protocol = Module(new ProtocolLayer(fdiParams))
7373
io.fdi <> protocol.io.fdi
7474
protocol.io.fault := fault
7575

7676
// Hamming encode and decode
77-
val hammingEncoder = Module(new HammingEncode(outer.protoParams))
78-
val hammingDecoder = Module(new HammingDecode(outer.protoParams))
77+
val hammingEncoder = Module(new HammingEncode(protoParams))
78+
val hammingDecoder = Module(new HammingDecode(protoParams))
7979
// Defaults
8080
hammingEncoder.io.data := 0.U
8181
hammingDecoder.io.data := 0.U
8282
hammingDecoder.io.checksum := 0.U
8383

8484
//Sideband node for protocol layer
85-
val protocol_sb_node = Module(new SidebandNode((new SidebandParams), outer.fdiParams))
85+
val protocol_sb_node = Module(new SidebandNode((new SidebandParams), fdiParams))
8686

8787
protocol_sb_node.io.outer.rx.bits := protocol.io.fdi.lpConfig.bits
8888
protocol_sb_node.io.outer.rx.valid := protocol.io.fdi.lpConfig.valid
@@ -92,33 +92,33 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
9292
protocol.io.fdi.plConfig.valid := protocol_sb_node.io.outer.tx.valid
9393
protocol_sb_node.io.outer.tx.credit := protocol.io.fdi.plConfigCredit
9494

95-
protocol_sb_node.io.inner.layer_to_node.bits := Cat(outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high,
96-
outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low,
97-
outer.regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high,
98-
outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low)
99-
protocol_sb_node.io.inner.layer_to_node.valid := outer.regNode.module.io.sb_csrs.sideband_mailbox_sw_valid
95+
protocol_sb_node.io.inner.layer_to_node.bits := Cat(regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_high,
96+
regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_data_low,
97+
regNode.module.io.sb_csrs.sidebank_mailbox_sw_to_node_index_high,
98+
regNode.module.io.sb_csrs.sideband_mailbox_sw_to_node_index_low)
99+
protocol_sb_node.io.inner.layer_to_node.valid := regNode.module.io.sb_csrs.sideband_mailbox_sw_valid
100100

101-
outer.regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0)
102-
outer.regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32)
103-
outer.regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64)
104-
outer.regNode.module.io.sb_csrs.sideband_mailbox_data_high := protocol_sb_node.io.inner.node_to_layer.bits(127, 96)
105-
protocol_sb_node.io.inner.node_to_layer.ready := outer.regNode.module.io.sb_csrs.sideband_mailbox_ready
106-
outer.regNode.module.io.sb_csrs.sideband_mailbox_valid := protocol_sb_node.io.inner.node_to_layer.valid
107-
108-
val tlBundleParams = new TLBundleParameters(addressBits = outer.tlParams.addressWidth,
109-
dataBits = outer.tlParams.dataWidth,
110-
sourceBits = outer.tlParams.sourceIDWidth,
111-
sinkBits = outer.tlParams.sinkIDWidth,
112-
sizeBits = outer.tlParams.sizeWidth,
101+
regNode.module.io.sb_csrs.sideband_mailbox_index_low := protocol_sb_node.io.inner.node_to_layer.bits(31, 0)
102+
regNode.module.io.sb_csrs.sideband_mailbox_index_high := protocol_sb_node.io.inner.node_to_layer.bits(63, 32)
103+
regNode.module.io.sb_csrs.sideband_mailbox_data_low := protocol_sb_node.io.inner.node_to_layer.bits(95, 64)
104+
regNode.module.io.sb_csrs.sideband_mailbox_data_high := protocol_sb_node.io.inner.node_to_layer.bits(127, 96)
105+
protocol_sb_node.io.inner.node_to_layer.ready := regNode.module.io.sb_csrs.sideband_mailbox_ready
106+
regNode.module.io.sb_csrs.sideband_mailbox_valid := protocol_sb_node.io.inner.node_to_layer.valid
107+
108+
val tlBundleParams = new TLBundleParameters(addressBits = tlParams.addressWidth,
109+
dataBits = tlParams.dataWidth,
110+
sourceBits = tlParams.sourceIDWidth,
111+
sinkBits = tlParams.sinkIDWidth,
112+
sizeBits = tlParams.sizeWidth,
113113
echoFields = Nil,
114114
requestFields = Nil,
115115
responseFields = Nil,
116116
hasBCE = false)
117117

118-
val client_tl = outer.clientNode.out(0)._1
119-
val client_edge = outer.clientNode.out(0)._2
120-
val manager_tl = outer.managerNode.in(0)._1
121-
val manager_edge = outer.managerNode.in(0)._2
118+
val client_tl = clientNode.out(0)._1
119+
val client_edge = clientNode.out(0)._2
120+
val manager_tl = managerNode.in(0)._1
121+
val manager_edge = managerNode.in(0)._2
122122

123123
val clientParams = client_edge.bundle
124124
val managerParams = manager_edge.bundle
@@ -139,21 +139,21 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
139139
// The TX packets can be A request from manager node or D response from
140140
// the client node. This needs to be arbitrated to be sent to partner die.
141141
// =======================
142-
val txArbiter = Module(new Arbiter(new TLBundleAUnionD(outer.tlParams), 2))
143-
val txATLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
144-
val txDTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
145-
//val txTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
142+
val txArbiter = Module(new Arbiter(new TLBundleAUnionD(tlParams), 2))
143+
val txATLPayload = Wire(new TLBundleAUnionD(tlParams))
144+
val txDTLPayload = Wire(new TLBundleAUnionD(tlParams))
145+
//val txTLPayload = Wire(new TLBundleAUnionD(tlParams))
146146

147147
val aHasData = manager_edge.hasData(manager_tl.a.bits)
148148
val rx_fire = protocol.io.TLplData_valid
149-
val uciRxPayload = Wire(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams)) // User-defined UCIe flit for streaming
150-
val uciTxPayload = Wire(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams)) // User-defined UCIe flit for streaming
149+
val uciRxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming
150+
val uciTxPayload = Wire(new UCIRawPayloadFormat(tlParams, protoParams)) // User-defined UCIe flit for streaming
151151

152152
// defaults
153-
uciRxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams))
154-
uciTxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams))
155-
txATLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
156-
txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
153+
uciRxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(tlParams, protoParams))
154+
uciTxPayload := 0.U.asTypeOf(new UCIRawPayloadFormat(tlParams, protoParams))
155+
txATLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
156+
txDTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
157157

158158
/*
159159
manager_tl.a.ready = (inward.io.enq.ready & ~protocol.io.fdi.lpStallAck &
@@ -191,7 +191,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
191191
// Arbitrate the A and D channels from the credited msgs
192192
creditedMsgA.io.out.ready := txArbiter.io.in(0).ready
193193
txArbiter.io.in(0).valid := creditedMsgA.io.out.fire
194-
//txArbiter.io.in(0).bits <> creditedMsgA.io.out.bits.asTypeOf(new TLBundleAUnionD(outer.tlParams))
194+
//txArbiter.io.in(0).bits <> creditedMsgA.io.out.bits.asTypeOf(new TLBundleAUnionD(tlParams))
195195
txArbiter.io.in(0).bits.opcode := creditedMsgA.io.out.bits.opcode
196196
txArbiter.io.in(0).bits.param := creditedMsgA.io.out.bits.param
197197
txArbiter.io.in(0).bits.size := creditedMsgA.io.out.bits.size
@@ -204,7 +204,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
204204

205205
creditedMsgD.io.out.ready := txArbiter.io.in(1).ready
206206
txArbiter.io.in(1).valid := creditedMsgD.io.out.fire
207-
//txArbiter.io.in(1).bits <> creditedMsgD.io.out.bits.asTypeOf(new TLBundleAUnionD(outer.tlParams))
207+
//txArbiter.io.in(1).bits <> creditedMsgD.io.out.bits.asTypeOf(new TLBundleAUnionD(tlParams))
208208
txArbiter.io.in(1).bits.opcode := creditedMsgD.io.out.bits.opcode
209209
txArbiter.io.in(1).bits.param := creditedMsgD.io.out.bits.param
210210
txArbiter.io.in(1).bits.size := creditedMsgD.io.out.bits.size
@@ -233,7 +233,7 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
233233
val checksum_reg = RegInit(0.U(64.W))
234234
checksum_reg := hammingEncoder.io.checksum
235235

236-
val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(outer.tlParams, outer.protoParams), 1))
236+
val tx_pipe = Module(new Pipe(new UCIRawPayloadFormat(tlParams, protoParams), 1))
237237
tx_pipe.io.enq.bits := uciTxPayload
238238
tx_pipe.io.enq.valid := txArbiter.io.out.fire
239239
// Dequeue the TX TL packets and translate to UCIe flit
@@ -252,8 +252,8 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
252252
outwardA.io.credit.ready := tx_pipe.io.deq.valid && creditA
253253
outwardD.io.credit.ready := tx_pipe.io.deq.valid && creditD
254254

255-
val txACredit = WireDefault(0.U(outer.protoParams.creditWidth.W))
256-
val txDCredit = WireDefault(0.U(outer.protoParams.creditWidth.W))
255+
val txACredit = WireDefault(0.U(protoParams.creditWidth.W))
256+
val txDCredit = WireDefault(0.U(protoParams.creditWidth.W))
257257

258258
when(outwardA.io.credit.valid){
259259
txACredit := outwardA.io.credit.bits
@@ -300,19 +300,19 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
300300
// =======================
301301
// TL RX packets coming from the UCIe stack to the System, push on the outward queue
302302
// =======================
303-
val rxTLPayload = Wire(new TLBundleAUnionD(outer.tlParams))
304-
rxTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(outer.tlParams))
303+
val rxTLPayload = Wire(new TLBundleAUnionD(tlParams))
304+
rxTLPayload := 0.U.asTypeOf(new TLBundleAUnionD(tlParams))
305305
// protocol.io.fdi.lpData.irdy := outward.io.enq.ready
306306

307307
// map the uciRxPayload and the plData based on the uciPayload formatting
308308
// map the uciRxPayload to the rxTLPayload TLBundle
309309
when(rx_fire) {
310310
// ucie cmd
311-
uciRxPayload.cmd := protocol.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(outer.protoParams))
311+
uciRxPayload.cmd := protocol.io.TLplData_bits(511, 448).asTypeOf(new UCICmdFormat(protoParams))
312312
// ucie header 1
313-
uciRxPayload.header1 := protocol.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(outer.tlParams))
313+
uciRxPayload.header1 := protocol.io.TLplData_bits(447,384).asTypeOf(new UCIHeader1Format(tlParams))
314314
// ucie header 2
315-
uciRxPayload.header2 := protocol.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(outer.tlParams))
315+
uciRxPayload.header2 := protocol.io.TLplData_bits(383, 320).asTypeOf(new UCIHeader2Format(tlParams))
316316
// ucie data payload
317317
uciRxPayload.data(3) := protocol.io.TLplData_bits(319,256)
318318
uciRxPayload.data(2) := protocol.io.TLplData_bits(255,192)
@@ -372,6 +372,6 @@ class UCITLFrontImp(outer: UCITLFront) extends LazyModuleImp(outer) {
372372

373373
// soft resets: can be reset or flush and reset, in flush and reset, the packets are
374374
// sent out before triggering reset
375-
protocol.io.soft_reset := (outer.regNode.module.io.d2d_csrs.d2d_state_can_reset |
376-
outer.regNode.module.io.d2d_csrs.d2d_flush_and_reset)
377-
}
375+
protocol.io.soft_reset := (regNode.module.io.d2d_csrs.d2d_state_can_reset |
376+
regNode.module.io.d2d_csrs.d2d_flush_and_reset)
377+
}}}

‎src/test/scala/protocol/FdiLoopbackTest.scala

+25-5
Original file line numberDiff line numberDiff line change
@@ -7,6 +7,7 @@ import chiseltest._
77
import org.chipsalliance.cde.config.{Field, Parameters, Config}
88
import freechips.rocketchip.tilelink._
99
import freechips.rocketchip.util._
10+
import freechips.rocketchip.prci._
1011
import freechips.rocketchip.diplomacy._
1112
// import freechips.rocketchip.unittest._
1213
import edu.berkeley.cs.ucie.digital.interfaces.FdiParams
@@ -19,7 +20,10 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
1920
val protoParams = ProtocolLayerParams()
2021
val tlParams = TileLinkParams(address=0x0, addressRange=0xffff, configAddress=0x40000, inwardQueueDepth=8, outwardQueueDepth=8)
2122
val delay = 0.0
22-
val txns = 10
23+
val txns = 5
24+
25+
// Create clock source
26+
val clockSourceNode = ClockSourceNode(Seq(ClockSourceParameters()))
2327

2428
val csrfuzz = LazyModule(new TLFuzzer(txns))
2529
val fuzz = LazyModule(new TLFuzzer(txns))
@@ -29,20 +33,23 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
2933
// val fdiLoopback = LazyModule(new FdiLoopback(fdiParams))
3034
// val tlUcieDie2 = LazyModule()
3135

36+
tlUcieDie1.clockNode := clockSourceNode
3237
// CSR node
3338
tlUcieDie1.regNode.node := csrfuzz.node
3439
// connect data nodes
35-
tlUcieDie1.managerNode := fuzz.node
40+
tlUcieDie1.managerNode := TLSourceShrinker(tlParams.sourceIDWidth) := fuzz.node
3641
ram.node := tlUcieDie1.clientNode
3742
// fdiLoopback.ram.node := tlUcieDie1.clientNode
3843
lazy val module = new Impl
3944
class Impl extends LazyModuleImp(this) {
4045
val io = IO(new Bundle {
46+
val uci_clock = Input(new ClockBundle(ClockBundleParameters()))
4147
val finished = Output(Bool())
4248
})
4349
// connect IOs
4450
io.finished := fuzz.module.io.finished
4551
val fdiLoopback = Module(new FdiLoopback(fdiParams))
52+
io.uci_clock <> clockSourceNode.out(0)._1
4653
// inputs to tlUcieDie1
4754
tlUcieDie1.module.io.fdi.lpData.ready := fdiLoopback.io.fdi1.lpData.ready
4855
tlUcieDie1.module.io.fdi.plData := fdiLoopback.io.fdi1.plData
@@ -93,18 +100,31 @@ class FdiLoopbackTester (implicit p: Parameters) extends LazyModule {
93100
tlUcieDie1.module.io.fdi.lpConfigCredit := fdiLoopback.io.fdi1.lpConfigCredit
94101
}
95102
}
103+
104+
class FDITLTestHarness(implicit val p: Parameters) extends Module with HasSuccessIO {
105+
val tester = Module(LazyModule(new FdiLoopbackTester).module)
106+
tester.io.uci_clock.clock := clock
107+
tester.io.uci_clock.reset := reset
108+
io.success := tester.io.finished
109+
110+
// Dummy plusarg to avoid breaking verilator builds with emulator.cc
111+
val useless_plusarg = PlusArg("useless_plusarg", width=1)
112+
dontTouch(useless_plusarg)
113+
ElaborationArtefacts.add("plusArgs", PlusArgArtefacts.serialize_cHeader)
114+
}
115+
96116
class FdiLoopbackTest extends AnyFlatSpec with ChiselScalatestTester {
97117
behavior of "FdiLoopback"
98118
val txns = 2
99119
val timeout = 1000
100120
implicit val p: Parameters = Parameters.empty
101121
it should "finish request and response before timeout" in {
102-
test(LazyModule(new FdiLoopbackTester()).module) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation))
122+
test(new FDITLTestHarness()) {c => //.withAnnotations(Seq(VcsBackendAnnotation, WriteVcdAnnotation))
103123
println("start Fdi Loopback Test")
104124
c.clock.setTimeout(timeout+10)
105125
c.clock.step(timeout)
106-
c.io.finished.expect(true.B)
107-
println("Fdi Loopback Test finished? " + c.io.finished.peek())
126+
c.io.success.expect(true.B)
127+
println("Fdi Loopback Test finished? " + c.io.success.peek())
108128
}
109129
}
110130
}

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