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vikramjain236vikramjain236
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Merge pull request #77 from ucb-ucie/d2dadapter_main
D2Dadapter main
2 parents 29327dc + 5b5e3a7 commit 3362bea

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‎src/main/scala/d2dadapter/D2DAdapter.scala

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package edu.berkeley.cs.ucie.digital
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package d2dadapter
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import chisel3._
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//import chisel3.util._
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//import chisel3.experimental._
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import interfaces._
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import sideband._
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class D2DAdapterIO (val fdiParams: FdiParams, val rdiParams: RdiParams) extends Bundle {
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val fdi = Flipped(new Fdi(fdiParams))
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val rdi = new Rdi(rdiParams)
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}
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/**
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* Top module for the D2D adapter which instantiates:
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* 1) LinkManagement Controller
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* 2) SB node
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* 3) MB node
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* 4) FDI and RDI stall handlers
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* @param fdiParams
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* @param rdiParams
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* @param sbParams
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*/
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class D2DAdapter(val fdiParams: FdiParams, val rdiParams: RdiParams,
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val sbParams: SidebandParams) extends Module {
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val io = IO(new D2DAdapterIO(fdiParams, rdiParams))
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assert(fdiParams.width == rdiParams.width)
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assert(fdiParams.sbWidth == rdiParams.sbWidth)
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val link_manager = Module(new LinkManagementController(fdiParams, rdiParams, sbParams))
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val fdi_stall_handler = Module(new FDIStallHandler())
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val rdi_stall_handler = Module(new RDIStallHandler())
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val d2d_sideband = Module(new D2DSidebandModule(fdiParams, sbParams))
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val d2d_mainband = Module(new D2DMainbandModule(fdiParams, rdiParams, sbParams))
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val parity_generator = Module(new ParityGenerator(fdiParams))
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// default assignments for the FDI and RDI interfaces
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io.fdi.plProtocolValid := true.B
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io.fdi.plProtocolFlitFormat := FlitFormat.raw
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io.fdi.plProtocol := Protocol.streaming
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io.fdi.plSpeedMode := io.rdi.plSpeedMode
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io.fdi.plLinkWidth := io.rdi.plLinkWidth
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io.fdi.plFlitCancel := false.B
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io.fdi.plNfError := false.B
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io.fdi.plTrainError := false.B
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io.fdi.plError := false.B
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io.fdi.plCerror := false.B
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io.fdi.plPhyInRecenter := false.B
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io.fdi.plPhyInL1 := false.B
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io.fdi.plPhyInL2 := false.B
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io.fdi.plDllp.bits := 0.U
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io.fdi.plDllp.valid := false.B
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io.fdi.plDllpOfc := false.B
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io.fdi.plClkReq := true.B
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io.rdi.lpClkAck := true.B
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io.fdi.plWakeAck := true.B
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io.fdi.plRetimerCrd := false.B
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io.rdi.lpRetimerCrd := false.B
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io.rdi.lpWakeReq := true.B
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// link management controller
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// FDI interface
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link_manager.io.fdi_lp_state_req := io.fdi.lpStateReq
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link_manager.io.fdi_lp_linkerror := io.fdi.lpLinkError
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link_manager.io.fdi_lp_rx_active_sts := io.fdi.lpRxActiveStatus
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io.fdi.plStateStatus := link_manager.io.fdi_pl_state_sts
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io.fdi.plRxActiveReq := link_manager.io.fdi_pl_rx_active_req
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io.fdi.plInbandPres := link_manager.io.fdi_pl_inband_pres
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// RDI interface
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io.rdi.lpLinkError := link_manager.io.rdi_lp_linkerror
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io.rdi.lpStateReq:= link_manager.io.rdi_lp_state_req
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link_manager.io.rdi_pl_state_sts := io.rdi.plStateStatus
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link_manager.io.rdi_pl_inband_pres := io.rdi.plInbandPres
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// link manager <-> D2D sideband
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d2d_sideband.io.sideband_snt := link_manager.io.sb_snd
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link_manager.io.sb_rcv := d2d_sideband.io.sideband_rcv
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link_manager.io.sb_rdy := d2d_sideband.io.sideband_rdy
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// stall handler <-> LinkManagementController
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link_manager.io.linkmgmt_stalldone := fdi_stall_handler.io.linkmgmt_stalldone
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fdi_stall_handler.io.linkmgmt_stallreq := link_manager.io.linkmgmt_stallreq
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//TODO: should move this to a MMIO register
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link_manager.io.cycles_1us := 1000.U
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// parity generator <-> link manager
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link_manager.io.parity_tx_sw_en := false.B // TODO: this should be software triggered, MMIO regs?
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link_manager.io.parity_rx_sw_en := false.B // TODO: this should be software triggered, MMIO regs?
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parity_generator.io.parity_rx_enable := link_manager.io.parity_rx_enable
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parity_generator.io.parity_tx_enable := link_manager.io.parity_tx_enable
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// Sideband
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io.fdi.plConfig.bits := d2d_sideband.io.fdi_pl_cfg
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io.fdi.plConfig.valid := d2d_sideband.io.fdi_pl_cfg_vld
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d2d_sideband.io.fdi_pl_cfg_crd := io.fdi.plConfigCredit
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d2d_sideband.io.fdi_lp_cfg := io.fdi.lpConfig.bits
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d2d_sideband.io.fdi_lp_cfg_vld := io.fdi.lpConfig.valid
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io.fdi.lpConfigCredit := d2d_sideband.io.fdi_lp_cfg_crd
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d2d_sideband.io.rdi_pl_cfg := io.rdi.plConfig.bits
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d2d_sideband.io.rdi_pl_cfg_vld := io.rdi.plConfig.valid
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io.rdi.plConfigCredit := d2d_sideband.io.rdi_pl_cfg_crd
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io.rdi.lpConfig.bits := d2d_sideband.io.rdi_lp_cfg
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io.rdi.lpConfig.valid := d2d_sideband.io.rdi_lp_cfg_vld
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d2d_sideband.io.rdi_lp_cfg_crd := io.rdi.lpConfigCredit
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// stall handler
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io.fdi.plStallReq := fdi_stall_handler.io.fdi_pl_stallreq
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fdi_stall_handler.io.fdi_lp_stallack := io.fdi.lpStallAck
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rdi_stall_handler.io.rdi_pl_stallreq := io.rdi.plStallReq
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io.rdi.lpStallAck := rdi_stall_handler.io.rdi_lp_stallack
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// mainband module
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// FDI
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d2d_mainband.io.fdi_lp_irdy := io.fdi.lpData.irdy
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d2d_mainband.io.fdi_lp_valid := io.fdi.lpData.valid
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d2d_mainband.io.fdi_lp_data := io.fdi.lpData.bits
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d2d_mainband.io.fdi_lp_stream := io.fdi.lpStream
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io.fdi.lpData.ready := d2d_mainband.io.fdi_pl_trdy
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io.fdi.plData.valid := d2d_mainband.io.fdi_pl_valid
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io.fdi.plData.bits := d2d_mainband.io.fdi_pl_data
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io.fdi.plStream := d2d_mainband.io.fdi_pl_stream
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// RDI
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io.rdi.lpData.irdy := d2d_mainband.io.rdi_lp_irdy
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io.rdi.lpData.valid := d2d_mainband.io.rdi_lp_valid
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io.rdi.lpData.bits := d2d_mainband.io.rdi_lp_data
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d2d_mainband.io.rdi_pl_trdy := io.rdi.lpData.ready
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d2d_mainband.io.rdi_pl_valid := io.rdi.plData.valid
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d2d_mainband.io.rdi_pl_data := io.rdi.plData.bits
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d2d_mainband.io.d2d_state := link_manager.io.fdi_pl_state_sts
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// stall handler <-> mainband
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d2d_mainband.io.mainband_stallreq := rdi_stall_handler.io.mainband_stallreq
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rdi_stall_handler.io.mainband_stalldone := d2d_mainband.io.mainband_stalldone
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// parity generator <-> mainband
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//(Bits((8 * fdiParams.width).W))
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parity_generator.io.snd_data := d2d_mainband.io.snd_data.asTypeOf(Vec(fdiParams.width, UInt(8.W)))
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parity_generator.io.snd_data_vld := d2d_mainband.io.snd_data_vld
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parity_generator.io.rcv_data := d2d_mainband.io.rcv_data.asTypeOf(Vec(fdiParams.width, UInt(8.W)))
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parity_generator.io.rcv_data_vld := d2d_mainband.io.rcv_data_vld
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d2d_mainband.io.parity_insert := parity_generator.io.parity_insert
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d2d_mainband.io.parity_data := parity_generator.io.parity_data.asTypeOf(Bits((8 * fdiParams.width).W))
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parity_generator.io.parity_rdy := d2d_mainband.io.parity_rdy
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d2d_mainband.io.parity_check := parity_generator.io.parity_check
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// Parity generator submodule other IOs
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parity_generator.io.parity_n := ParityN.ONE
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parity_generator.io.rdi_state := io.rdi.plStateStatus
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// Store these into some MMIO based registers
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val parity_check_result = parity_generator.io.parity_check_result
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val parity_check_result_valid = parity_generator.io.parity_check_result_valid
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}

‎src/main/scala/d2dadapter/D2DAdapterConstants.scala

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package edu.berkeley.cs.ucie.digital
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package d2dadapter
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import chisel3._
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//import chisel3.util._
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//import interfaces._
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//import sideband._
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// LinkInitModule constants
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object LinkInitState extends ChiselEnum {
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val INIT_START = Value(0x0.U(3.W))
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val RDI_BRINGUP = Value(0x1.U(3.W))
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val PARAM_EXCH = Value(0x2.U(3.W))
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val FDI_BRINGUP = Value(0x3.U(3.W))
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val INIT_DONE = Value(0x4.U(3.W))
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}
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// Sideband constants
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object D2DAdapterSignalSize{
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val SIDEBAND_MESSAGE_OP_WIDTH = 6.W
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}
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object SideBandMessage{
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// start with 01: RES
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// start with 00: REQ
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// start with 1: others
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val NOP: UInt = "b000000".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REQ_ACTIVE: UInt = "b000001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REQ_L1: UInt = "b000100".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REQ_L2: UInt = "b001000".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REQ_LINKRESET: UInt = "b001001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REQ_DISABLED: UInt = "b001100".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_ACTIVE: UInt = "b010001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_PMNAK: UInt = "b010011".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_L1: UInt = "b010100".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_L2: UInt = "b011000".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_LINKRESET: UInt = "b011001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val RSP_DISABLED: UInt = "b011100".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val PARITY_FEATURE_REQ: UInt = "b100001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val PARITY_FEATURE_ACK: UInt = "b110001".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val PARITY_FEATURE_NAK: UInt = "b110010".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val ADV_CAP: UInt = "b100100".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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val REGISTER_ACCESS: UInt = "b101000".U(D2DAdapterSignalSize.SIDEBAND_MESSAGE_OP_WIDTH)
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}
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// Stall Handler constants
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object StallHandlerWidth{
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val STATE_WIDTH = 2.W
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}
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object StallHandshakeState extends ChiselEnum{
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val IDLE = Value(0x0.U(StallHandlerWidth.STATE_WIDTH))
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val REQSNT = Value(0x1.U(StallHandlerWidth.STATE_WIDTH))
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val REQFALL = Value(0x2.U(StallHandlerWidth.STATE_WIDTH))
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val COMPLETE = Value(0x3.U(StallHandlerWidth.STATE_WIDTH))
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}
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// Parity module constants
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object ParityGeneratorWidth{
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val PARITY_N_WIDTH = 3.W
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}
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object ParityAmount{
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val BASESIZE: Int = 64
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val PARITY_DATA_NBYTE_1: Int = 64
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val DATA_NBYTE_1: Int = 256 * 256 * 1
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val PARITY_DATA_NBYTE_2: Int = 64 * 2
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val DATA_NBYTE_2: Int = 256 * 256 * 2
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val PARITY_DATA_NBYTE_4: Int = 64 * 4
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val DATA_NBYTE_4: Int = 256 * 256 * 4
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val CORRECT_REG_WIDTH = 256.W // 4 * 64 for maximum four 64Bytes parity
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}
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object ParityN{
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val ONE: UInt = "b000".U
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val TWO: UInt = "b001".U
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val FOUR: UInt = "b010".U
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}

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