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Merge pull request #93 from ucb-ucie/lanes-no-fifo
Lanes no fifo
2 parents 4161912 + 7f7e31d commit 994a4d4

9 files changed

+146
-204
lines changed

‎src/main/scala/e2e/UCITop.scala

+1-1
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ class UCITop(
4545
// IOs for connecting to the AFE in the standalone mode
4646
val mbAfe_tx = if (afeParams.STANDALONE) Some(Output(new MainbandIo(afeParams.mbLanes))) else None
4747
val mbAfe_rx = if (afeParams.STANDALONE) Some(Input(new MainbandIo(afeParams.mbLanes))) else None
48-
val phyAfe = if (afeParams.STANDALONE) None else Some(Flipped(new MainbandLaneIO(afeParams)))
48+
val phyAfe = if (afeParams.STANDALONE) None else Some(Flipped(new MainbandLaneIOWithFifoIO(afeParams)))
4949
val sbTxIO = Output(new SidebandIo)
5050
val sbRxIO = Input(new SidebandIo)
5151
})

‎src/main/scala/logphy/Lanes.scala

+84-138
Original file line numberDiff line numberDiff line change
@@ -51,30 +51,15 @@ object OneToLanes {
5151
}
5252
}
5353

54-
class Lanes(
55-
afeParams: AfeParams,
56-
queueParams: AsyncQueueParams,
57-
) extends Module {
58-
val io = IO(new Bundle() {
59-
val scramble = Input(Bool())
60-
val mainbandLaneIO = new MainbandLaneIO(afeParams)
61-
val mainbandIO = new MainbandIO(afeParams)
62-
})
54+
class LaneIO(afeParams: AfeParams) extends Bundle {
55+
val scramble = Input(Bool())
56+
val mainbandLaneIO = new MainbandLaneIO(afeParams)
57+
val mainbandIO = new MainbandIO(afeParams)
58+
}
59+
60+
abstract class LanesModule(afeParams: AfeParams) extends Module {
61+
val io = IO(new LaneIO(afeParams))
6362

64-
val txMBFifo =
65-
Module(
66-
new AsyncQueue(
67-
Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)),
68-
queueParams,
69-
),
70-
)
71-
val rxMBFifo =
72-
Module(
73-
new AsyncQueue(
74-
Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)),
75-
queueParams,
76-
),
77-
)
7863
val rxScrambler =
7964
Module(
8065
new UCIeScrambler(afeParams = afeParams, numLanes = afeParams.mbLanes),
@@ -85,91 +70,109 @@ class Lanes(
8570
new UCIeScrambler(afeParams = afeParams, numLanes = afeParams.mbLanes),
8671
)
8772

88-
rxMBFifo.io.enq <> io.mainbandLaneIO.rxData
89-
rxMBFifo.io.deq_clock := clock
90-
rxMBFifo.io.deq_reset := reset
91-
rxMBFifo.io.enq_clock := io.mainbandLaneIO.fifoParams.clk
92-
rxMBFifo.io.enq_reset := io.mainbandLaneIO.fifoParams.reset
93-
txMBFifo.io.deq <> io.mainbandLaneIO.txData
94-
txMBFifo.io.enq_clock := clock
95-
txMBFifo.io.enq_reset := reset
96-
txMBFifo.io.deq_clock := io.mainbandLaneIO.fifoParams.clk
97-
txMBFifo.io.deq_reset := io.mainbandLaneIO.fifoParams.reset
98-
99-
assert(
100-
afeParams.mbSerializerRatio > 8 && afeParams.mbSerializerRatio % 8 == 0,
101-
)
73+
val rxScramblerInput = Wire(chiselTypeOf(io.mainbandLaneIO.rxData))
74+
val txScramblerOutput = Wire(chiselTypeOf(io.mainbandLaneIO.txData))
10275

103-
val ratioBytes = afeParams.mbSerializerRatio / 8
76+
val scrambledTx = Wire(chiselTypeOf(io.mainbandLaneIO.txData.bits))
77+
val descrambledRx = Wire(chiselTypeOf(io.mainbandLaneIO.rxData.bits))
78+
val rxDataInput = Wire(chiselTypeOf(io.mainbandLaneIO.rxData.bits))
10479

105-
val scrambledTx = Wire(chiselTypeOf(txMBFifo.io.enq.bits))
106-
val descrambledRx = Wire(chiselTypeOf(rxMBFifo.io.deq.bits))
80+
rxScrambler.io.data_in := rxScramblerInput.bits
81+
rxScrambler.io.valid := rxScramblerInput.fire
82+
descrambledRx := rxScrambler.io.data_out
10783

108-
val rxDataInput = Wire(chiselTypeOf(rxMBFifo.io.deq.bits))
109-
rxDataInput := Mux(io.scramble, descrambledRx, rxMBFifo.io.deq.bits)
84+
rxDataInput := Mux(
85+
io.scramble,
86+
rxScrambler.io.data_out,
87+
rxScramblerInput.bits,
88+
)
11089

111-
/** Data Scrambling / De-scrambling */
90+
io.mainbandIO.rxData.bits := LanesToOne(
91+
rxDataInput,
92+
afeParams.mbLanes,
93+
afeParams.mbSerializerRatio,
94+
)
95+
io.mainbandIO.rxData.valid := rxScramblerInput.valid
96+
rxScramblerInput.ready := true.B
11297

113-
rxScrambler.io.data_in := rxMBFifo.io.deq.bits
114-
rxScrambler.io.valid := rxMBFifo.io.deq.fire
115-
descrambledRx := rxScrambler.io.data_out
98+
scrambledTx := txScrambler.io.data_out
11699
txScrambler.io.data_in := OneToLanes(
117100
io.mainbandIO.txData.bits,
118101
afeParams.mbLanes,
119102
afeParams.mbSerializerRatio,
120103
)
121104
txScrambler.io.valid := io.mainbandIO.txData.fire
122-
scrambledTx := txScrambler.io.data_out
123105

124-
/** Queue data into FIFOs */
125-
126-
txMBFifo.io.enq.valid := io.mainbandIO.txData.valid
127-
io.mainbandIO.txData.ready := txMBFifo.io.enq.ready
128-
txMBFifo.io.enq.bits := Mux(
106+
txScramblerOutput.valid := io.mainbandIO.txData.valid
107+
io.mainbandIO.txData.ready := txScramblerOutput.ready
108+
txScramblerOutput.bits := Mux(
129109
io.scramble,
130110
scrambledTx,
131111
txScrambler.io.data_in,
132112
)
133113

134-
io.mainbandIO.rxData.valid := rxMBFifo.io.deq.valid
135-
io.mainbandIO.rxData.bits := LanesToOne(
136-
rxDataInput,
137-
afeParams.mbLanes,
138-
afeParams.mbSerializerRatio,
139-
)
140-
rxMBFifo.io.deq.ready := true.B
141114
}
142115

143-
class MainbandSimIO(afeParams: AfeParams) extends Bundle {
144-
val txData = Decoupled(
145-
Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)),
146-
)
147-
val rxData = Flipped(
148-
Decoupled(Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W))),
116+
class LanesNoFifo(
117+
afeParams: AfeParams,
118+
) extends LanesModule(afeParams) {
119+
120+
assert(
121+
afeParams.mbSerializerRatio > 8 && afeParams.mbSerializerRatio % 8 == 0,
149122
)
123+
124+
rxScramblerInput <> io.mainbandLaneIO.rxData
125+
io.mainbandLaneIO.txData <> txScramblerOutput
126+
150127
}
151128

152-
class SimLanes(
129+
class Lanes(
153130
afeParams: AfeParams,
154131
queueParams: AsyncQueueParams,
155-
) extends Module {
132+
) extends LanesModule(afeParams) {
156133

157-
val io = IO(new Bundle() {
158-
val scramble = Input(Bool())
159-
val mainbandIo = new MainbandSimIO(afeParams)
160-
val mainbandLaneIO = new MainbandIO(afeParams)
161-
})
134+
val asyncQueueIO = IO(Input(new FifoParams))
162135

163-
val rxScrambler =
136+
val txMBFifo =
164137
Module(
165-
new UCIeScrambler(afeParams = afeParams, numLanes = afeParams.mbLanes),
138+
new AsyncQueue(
139+
Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)),
140+
queueParams,
141+
),
166142
)
167-
168-
val txScrambler =
143+
val rxMBFifo =
169144
Module(
170-
new UCIeScrambler(afeParams = afeParams, numLanes = afeParams.mbLanes),
145+
new AsyncQueue(
146+
Vec(afeParams.mbLanes, Bits(afeParams.mbSerializerRatio.W)),
147+
queueParams,
148+
),
171149
)
172150

151+
rxMBFifo.io.enq <> io.mainbandLaneIO.rxData
152+
rxMBFifo.io.deq_clock := clock
153+
rxMBFifo.io.deq_reset := reset
154+
rxMBFifo.io.enq_clock := asyncQueueIO.clk
155+
rxMBFifo.io.enq_reset := asyncQueueIO.reset
156+
txMBFifo.io.deq <> io.mainbandLaneIO.txData
157+
txMBFifo.io.enq_clock := clock
158+
txMBFifo.io.enq_reset := reset
159+
txMBFifo.io.deq_clock := asyncQueueIO.clk
160+
txMBFifo.io.deq_reset := asyncQueueIO.reset
161+
162+
assert(
163+
afeParams.mbSerializerRatio > 8 && afeParams.mbSerializerRatio % 8 == 0,
164+
)
165+
166+
rxScramblerInput <> rxMBFifo.io.deq
167+
txMBFifo.io.enq <> txScramblerOutput
168+
169+
}
170+
171+
class SimLanes(
172+
afeParams: AfeParams,
173+
queueParams: AsyncQueueParams,
174+
) extends LanesModule(afeParams) {
175+
173176
val txMBFifo =
174177
Module(
175178
new Queue(
@@ -185,70 +188,13 @@ class SimLanes(
185188
),
186189
)
187190

188-
rxMBFifo.io.enq <> io.mainbandIo.rxData
189-
txMBFifo.io.deq <> io.mainbandIo.txData
191+
rxMBFifo.io.enq <> io.mainbandLaneIO.rxData
192+
txMBFifo.io.deq <> io.mainbandLaneIO.txData
190193

191-
txMBFifo.io.enq.valid := io.mainbandLaneIO.txData.valid
192-
io.mainbandLaneIO.rxData.valid := rxMBFifo.io.deq.valid
193194
assert(
194195
afeParams.mbSerializerRatio > 8 && afeParams.mbSerializerRatio % 8 == 0,
195196
)
196197

197-
val ratioBytes = afeParams.mbSerializerRatio / 8
198-
val txDataVec = Wire(
199-
Vec(afeParams.mbLanes, Vec(ratioBytes, UInt(8.W))),
200-
)
201-
val rxDataVec = Wire(
202-
Vec(ratioBytes, Vec(afeParams.mbLanes, UInt(8.W))),
203-
)
204-
val txDataBytes = Wire(
205-
Vec(afeParams.mbLanes * ratioBytes, UInt(8.W)),
206-
)
207-
txDataBytes := io.mainbandLaneIO.txData.asTypeOf(txDataBytes)
208-
209-
for (i <- 0 until afeParams.mbLanes) {
210-
for (j <- 0 until ratioBytes) {
211-
txDataVec(i)(j) := txDataBytes(afeParams.mbLanes * j + i)
212-
}
213-
}
214-
215-
val scrambledTx = Wire(chiselTypeOf(txMBFifo.io.enq.bits))
216-
val descrambledRx = Wire(chiselTypeOf(rxMBFifo.io.deq.bits))
217-
218-
val rxDataInput = Wire(chiselTypeOf(rxMBFifo.io.deq.bits))
219-
rxDataInput := Mux(io.scramble, descrambledRx, rxMBFifo.io.deq.bits)
220-
221-
for (i <- 0 until afeParams.mbLanes) {
222-
for (j <- 0 until ratioBytes) {
223-
rxDataVec(j)(i) := rxDataInput(i).asTypeOf(
224-
VecInit(Seq.fill(ratioBytes)(0.U(8.W))),
225-
)(j)
226-
}
227-
}
228-
229-
/** Data Scrambling / De-scrambling */
230-
231-
rxScrambler.io.data_in := rxMBFifo.io.deq.bits
232-
rxScrambler.io.valid := rxMBFifo.io.deq.fire
233-
descrambledRx := rxScrambler.io.data_out
234-
235-
for (i <- 0 until afeParams.mbLanes) {
236-
txScrambler.io.data_in(i) := txDataVec(i).asUInt
237-
}
238-
txScrambler.io.valid := io.mainbandLaneIO.txData.fire
239-
scrambledTx := txScrambler.io.data_out
240-
241-
/** Queue data into FIFOs */
242-
243-
txMBFifo.io.enq.valid := io.mainbandLaneIO.txData.valid
244-
io.mainbandLaneIO.txData.ready := txMBFifo.io.enq.ready
245-
txMBFifo.io.enq.bits := Mux(
246-
io.scramble,
247-
scrambledTx,
248-
txScrambler.io.data_in,
249-
)
250-
251-
io.mainbandLaneIO.rxData.valid := rxMBFifo.io.deq.valid
252-
io.mainbandLaneIO.rxData.bits := rxDataVec.asUInt
253-
rxMBFifo.io.deq.ready := true.B
198+
rxScramblerInput <> rxMBFifo.io.deq
199+
txMBFifo.io.enq <> txScramblerOutput
254200
}

‎src/main/scala/logphy/LogPhyTypes.scala

+8-2
Original file line numberDiff line numberDiff line change
@@ -81,8 +81,6 @@ class MainbandLaneIO(
8181
afeParams: AfeParams,
8282
) extends Bundle {
8383

84-
val fifoParams = Input(new FifoParams())
85-
8684
/** Data to transmit on the mainband.
8785
*
8886
* Output from the async FIFO.
@@ -104,6 +102,14 @@ class MainbandLaneIO(
104102
)
105103
}
106104

105+
class MainbandLaneIOWithFifoIO(
106+
afeParams: AfeParams,
107+
) extends MainbandLaneIO(afeParams) {
108+
109+
val fifoParams = Input(new FifoParams())
110+
111+
}
112+
107113
class MainbandIO(
108114
afeParams: AfeParams,
109115
) extends Bundle {

‎src/main/scala/logphy/LogicalPhy.scala

+18-26
Original file line numberDiff line numberDiff line change
@@ -79,40 +79,32 @@ class LogicalPhy(
7979

8080
val rdiDataMapper = Module(new RdiDataMapper(rdiParams, afeParams))
8181

82-
val lanes = Module(new Lanes(afeParams, laneAsyncQueueParams))
82+
val lanes =
83+
if (afeParams.STANDALONE) {
84+
Module(new Lanes(afeParams, laneAsyncQueueParams))
85+
} else {
86+
Module(new LanesNoFifo(afeParams))
87+
}
8388

8489
/** TODO: need to drive this from state machine */
85-
lanes.io.scramble := true.B
90+
lanes.io.scramble := trainingModule.io.currentState === LinkTrainingState.active
91+
when(trainingModule.io.currentState === LinkTrainingState.active) {
92+
rdiDataMapper.io.mainbandIO <> lanes.io.mainbandIO
93+
trainingModule.io.mainbandFSMIO.mainbandIO.rxData.noenq()
94+
trainingModule.io.mainbandFSMIO.mainbandIO.txData.nodeq()
95+
}.otherwise {
96+
rdiDataMapper.io.mainbandIO.rxData.noenq()
97+
rdiDataMapper.io.mainbandIO.txData.nodeq()
98+
trainingModule.io.mainbandFSMIO.mainbandIO <> lanes.io.mainbandIO
99+
}
86100

87101
/** Connect internal FIFO to AFE */
88102
if (afeParams.STANDALONE) {
89103
lanes.io.mainbandLaneIO.txData <> io.mbAfe.get.txData
90104
lanes.io.mainbandLaneIO.rxData <> io.mbAfe.get.rxData
91-
lanes.io.mainbandLaneIO.fifoParams <> io.mbAfe.get.fifoParams
92-
when(trainingModule.io.currentState === LinkTrainingState.active) {
93-
rdiDataMapper.io.mainbandLaneIO <> lanes.io.mainbandIO
94-
trainingModule.io.mainbandFSMIO.mainbandIO.rxData.noenq()
95-
trainingModule.io.mainbandFSMIO.mainbandIO.txData.nodeq()
96-
}.otherwise {
97-
rdiDataMapper.io.mainbandLaneIO.rxData.noenq()
98-
rdiDataMapper.io.mainbandLaneIO.txData.nodeq()
99-
trainingModule.io.mainbandFSMIO.mainbandIO <> lanes.io.mainbandIO
100-
}
105+
lanes.asInstanceOf[Lanes].asyncQueueIO <> io.mbAfe.get.fifoParams
101106
} else {
102-
rdiDataMapper.io.mainbandLaneIO <> io.phyAfe.get
103-
// defaults to zero
104-
/** TODO: not sure what is going on here */
105-
lanes.io.mainbandLaneIO.fifoParams.clk := 0.U.asTypeOf(Clock())
106-
lanes.io.mainbandLaneIO.fifoParams.reset := 0.U
107-
lanes.io.mainbandLaneIO.txData.ready := 0.U
108-
lanes.io.mainbandLaneIO.rxData.valid := 0.U
109-
lanes.io.mainbandLaneIO.rxData.bits := 0.U.asTypeOf(
110-
lanes.io.mainbandIO.rxData.bits,
111-
)
112-
lanes.io.mainbandLaneIO.txData.valid := 0.U
113-
lanes.io.mainbandLaneIO.txData.bits := 0.U.asTypeOf(
114-
lanes.io.mainbandIO.txData.bits,
115-
)
107+
lanes.io.mainbandLaneIO <> io.phyAfe.get
116108
}
117109

118110
/** Connect RDI to Mainband IO */

‎src/main/scala/logphy/MBInitFSM.scala

-2
Original file line numberDiff line numberDiff line change
@@ -154,7 +154,6 @@ class MBInitFSM(
154154
}
155155
}
156156
is(ParamSubState.SEND_RESP) {
157-
printf("in MB init send resp\n")
158157
io.sbTrainIO.msgReq.valid := true.B
159158
val exchangedMaxDataRate = Wire(UInt(4.W))
160159
exchangedMaxDataRate := Mux(
@@ -178,7 +177,6 @@ class MBInitFSM(
178177
}
179178
}
180179
is(ParamSubState.WAIT_RESP) {
181-
printf("in MB init wait resp\n")
182180
io.sbTrainIO.msgReqStatus.ready := true.B
183181
when(io.sbTrainIO.msgReqStatus.fire) {
184182
when(

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