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vikramjain236vikramjain236
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Merge pull request #67 from ucb-ucie/sideband_main
Sideband main
2 parents b6eb23f + 10e38f5 commit bdb7388

13 files changed

+2217
-15
lines changed

‎build.sbt

+61-14
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,40 @@
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// ThisBuild / organization := "edu.berkeley.cs"
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// ThisBuild / version := "0.0.1-SNAPSHOT"
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// ThisBuild / scalaVersion := "2.13.10"
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// ThisBuild / scalacOptions := Seq(
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// "-deprecation",
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// "-feature",
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// "-language:reflectiveCalls",
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// "-Xcheckinit",
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// "-Xlint",
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// )
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// Compile / doc / scalacOptions += "-groups"
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// val chiselVersion = "3.6.0"
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// lazy val root = (project in file("."))
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// .settings(
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// name := "uciedigital",
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// libraryDependencies ++= Seq(
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// "edu.berkeley.cs" %% "chisel3" % chiselVersion,
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// "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % Test,
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// "org.scalatest" %% "scalatest" % "3.2.17" % Test,
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// "edu.berkeley.cs" %% "rocketchip" % "1.6.0",
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// "edu.berkeley.cs" %% "rocket-macros" % "1.6.0",
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// "edu.berkeley.cs" %% "cde" % "1.6.0",
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// ),
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// addCompilerPlugin(
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// "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full,
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// ),
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// )
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// // Plugins
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// Global / excludeLintKeys += idePackagePrefix
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// root / idePackagePrefix := Some("edu.berkeley.cs.ucie.digital")
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name := "ucie_digital"
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ThisBuild / organization := "edu.berkeley.cs"
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ThisBuild / version := "0.0.1-SNAPSHOT"
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@@ -14,19 +51,29 @@ Compile / doc / scalacOptions += "-groups"
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val chiselVersion = "3.6.0"
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lazy val root = (project in file("."))
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.settings(
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name := "uciedigital",
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libraryDependencies ++= Seq(
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"edu.berkeley.cs" %% "chisel3" % chiselVersion,
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"edu.berkeley.cs" %% "chiseltest" % "0.6.2" % Test,
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"org.scalatest" %% "scalatest" % "3.2.17" % Test,
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),
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addCompilerPlugin(
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"edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full,
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),
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// SNAPSHOT repositories
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libraryDependencies ++=
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Seq(
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"edu.berkeley.cs" %% "rocketchip-3.6.0" % "1.6-3.6.0-e3773366a-SNAPSHOT",
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"edu.berkeley.cs" %% "chisel3" % chiselVersion,
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"edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test",
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"org.scalatest" %% "scalatest" % "3.2.17" % "test",
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)
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30-
// Plugins
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Global / excludeLintKeys += idePackagePrefix
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root / idePackagePrefix := Some("edu.berkeley.cs.ucie.digital")
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resolvers ++= Resolver.sonatypeOssRepos("snapshots")
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resolvers ++= Resolver.sonatypeOssRepos("releases")
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resolvers += Resolver.mavenLocal
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addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)
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import Tests._
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Test / fork := true
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Test / testGrouping := (Test / testGrouping).value.flatMap { group =>
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group.tests.map { test =>
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Group(test.name, Seq(test), SubProcess(ForkOptions()))
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}
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}
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concurrentRestrictions := Seq(Tags.limit(Tags.ForkedTestGroup, 72))
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‎project/build.properties

+1-1
Original file line numberDiff line numberDiff line change
@@ -1 +1 @@
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sbt.version=1.9.8
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sbt.version=1.9.7

‎src/main/scala/sideband/sb-msg-encoding.scala

+401
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‎src/main/scala/sideband/sidebandChannel.scala

+58
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package edu.berkeley.cs.ucie.digital
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package sideband
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import chisel3._
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import interfaces._
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class D2DSidebandChannel(
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val myID: BigInt = BigInt(1),
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val sbParams: SidebandParams,
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val fdiParams: FdiParams,
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) extends Module {
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val io = IO(new D2DSidebandChannelIO(sbParams, fdiParams))
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// Instantiate submodule
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val upper_node = Module(new SidebandNode(sbParams, fdiParams))
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val switcher = Module(new sidebandSwitcher(myID, sbParams))
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val lower_node = Module(new SidebandNode(sbParams, fdiParams))
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// Connect outer signals
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io.to_upper_layer <> upper_node.io.outer
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io.to_lower_layer <> lower_node.io.outer
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// Connect two sidebandNodes and switcher
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upper_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_above
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upper_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_above
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lower_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_below
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lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below
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// Connect inner signals
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io.inner <> switcher.io.inner
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}
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34+
class PHYSidebandChannel(
35+
val myID: BigInt = BigInt(2),
36+
val sbParams: SidebandParams,
37+
val fdiParams: FdiParams,
38+
) extends Module {
39+
val io = IO(new PHYSidebandChannelIO(sbParams, fdiParams))
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// Instantiate submodule
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val upper_node = Module(new SidebandNode(sbParams, fdiParams))
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val switcher = Module(new sidebandSwitcher(myID, sbParams))
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val lower_node = Module(new SidebandLinkNode(sbParams, fdiParams))
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// Connect outer signals
47+
io.to_upper_layer <> upper_node.io.outer
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io.to_lower_layer <> lower_node.io.outer
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// Connect two sidebandNodes and switcher
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upper_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_above
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upper_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_above
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lower_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_below
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lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below
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// Connect inner signals
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io.inner <> switcher.io.inner
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}

‎src/main/scala/sideband/sidebandIO.scala

+167
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@@ -0,0 +1,167 @@
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package edu.berkeley.cs.ucie.digital
2+
package sideband
3+
4+
import chisel3._
5+
import chisel3.util._
6+
7+
import interfaces._
8+
9+
class D2DSidebandChannelIO(
10+
val sbParams: SidebandParams,
11+
val fdiParams: FdiParams,
12+
) extends Bundle {
13+
// connect to another sideband node in the layer above (protocol layer)
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val to_upper_layer = new Bundle {
15+
val tx = new Bundle {
16+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val valid = Output(Bool())
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val credit = Input(Bool())
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}
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val rx = new Bundle {
21+
val bits = Input(UInt(fdiParams.sbWidth.W))
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val valid = Input(Bool())
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val credit = Output(Bool())
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}
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}
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// connect to another sideband node in the layer below (physical layer)
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val to_lower_layer = new Bundle {
28+
val tx = new Bundle {
29+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val valid = Output(Bool())
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val credit = Input(Bool())
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}
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val rx = new Bundle {
34+
val bits = Input(UInt(fdiParams.sbWidth.W))
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val valid = Input(Bool())
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val credit = Output(Bool())
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}
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}
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// d2d layer drive these
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val inner = Flipped(new SidebandSwitcherbundle(sbParams))
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}
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43+
class PHYSidebandChannelIO(
44+
val sbParams: SidebandParams,
45+
val fdiParams: FdiParams,
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) extends Bundle {
47+
// connect to another sideband node in the layer above (d2d layer)
48+
val to_upper_layer = new Bundle {
49+
val tx = new Bundle {
50+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val valid = Output(Bool())
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val credit = Input(Bool())
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}
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val rx = new Bundle {
55+
val bits = Input(UInt(fdiParams.sbWidth.W))
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val valid = Input(Bool())
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val credit = Output(Bool())
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}
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}
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// connect to another sideband node in the layer below (link layer)
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val to_lower_layer = new Bundle {
62+
val tx = new Bundle {
63+
val bits = Output(UInt(fdiParams.sbWidth.W))
64+
val clock = Output(Bool())
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}
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val rx = new Bundle {
67+
val bits = Input(UInt(fdiParams.sbWidth.W))
68+
val clock = Input(Bool())
69+
}
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}
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// phy layer drive these
72+
val inner = Flipped(new SidebandSwitcherbundle(sbParams))
73+
}
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75+
// IO for the RDI and FDI sideband
76+
class SidebandNodeIO(val sbParams: SidebandParams, val fdiParams: FdiParams)
77+
extends Bundle {
78+
// layers drive these
79+
val inner = new Bundle {
80+
val layer_to_node = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
81+
/* This signal overrides the tx.ready and takes up the priority reserved
82+
* queue slot */
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// Should only be asserted high for access completion packets
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val node_to_layer = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
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}
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// connect these to another sideband node
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val outer = new Bundle {
88+
val tx = new Bundle {
89+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val valid = Output(Bool())
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val credit = Input(Bool())
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}
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val rx = new Bundle {
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val bits = Input(UInt(fdiParams.sbWidth.W))
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val valid = Input(Bool())
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val credit = Output(Bool())
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}
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}
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}
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101+
class SidebandNodeOuterIO(
102+
val sbParams: SidebandParams,
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val fdiParams: FdiParams,
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) extends Bundle {
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val tx = new Bundle {
106+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val valid = Output(Bool())
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val credit = Input(Bool())
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}
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val rx = new Bundle {
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val bits = Input(UInt(fdiParams.sbWidth.W))
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val valid = Input(Bool())
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val credit = Output(Bool())
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}
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}
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class SidebandLinkNodeOuterIO(
118+
val sbParams: SidebandParams,
119+
val fdiParams: FdiParams,
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) extends Bundle {
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val tx = new Bundle {
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val bits = Output(UInt(fdiParams.sbWidth.W))
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val clock = Output(Bool())
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}
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val rx = new Bundle {
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val bits = Input(UInt(fdiParams.sbWidth.W))
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val clock = Input(Bool())
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}
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}
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// IO for the remote sideband
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class SidebandLinkIO(val sbParams: SidebandParams, val fdiParams: FdiParams)
133+
extends Bundle {
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// layers drive these
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val inner = new Bundle {
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val layer_to_node = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
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/* This signal overrides the tx.ready and takes up the priority reserved
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* queue slot */
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// Should only be asserted high for access completion packets
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val node_to_layer = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
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}
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// connect these to another sideband node
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val outer = new Bundle {
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val tx = new Bundle {
145+
val bits = Output(UInt(fdiParams.sbWidth.W))
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val clock = Output(Bool())
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}
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val rx = new Bundle {
149+
val bits = Input(UInt(fdiParams.sbWidth.W))
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val clock = Input(Bool())
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}
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}
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}
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class SidebandSwitcherIO(val sbParams: SidebandParams) extends Bundle {
156+
// layer drive these
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val inner = Flipped(new SidebandSwitcherbundle(sbParams))
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// Sideband node drive these
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val outer = new SidebandSwitcherbundle(sbParams)
160+
}
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class SidebandSwitcherbundle(val sbParams: SidebandParams) extends Bundle {
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val node_to_layer_above = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
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val layer_to_node_above = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
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val node_to_layer_below = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
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val layer_to_node_below = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
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}

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