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Scrambler Module #57
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Scrambler Module #57
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2f0554f
single lane scrambler
pawat-unj 0012187
Merge branch 'main' of github.com:ucb-ucie/uciedigital into scrambler
pawat-unj 71ba809
Scrambler done, pending testing
pawat-unj c2e5dd7
Scrambler
pawat-unj 74f84a8
scrambler without test
pawat-unj 60a7c86
scrambler with test
pawat-unj bd5863b
removed .apply() in scrambler
pawat-unj aad805b
scrambler reformatted
pawat-unj f51c262
scrambler reformatted
pawat-unj 7e38993
missing python test script
pawat-unj 4a6bfc5
Merge branch 'main' into scrambler
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Original file line number | Diff line number | Diff line change |
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@@ -0,0 +1,67 @@ | ||
package edu.berkeley.cs.ucie.digital | ||
package interfaces | ||
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import chisel3._ | ||
import chisel3.util.random._ | ||
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class Scrambler( | ||
afeParams: AfeParams, | ||
width: Int, | ||
seed: BigInt, | ||
) extends Module { | ||
val io = IO(new Bundle { | ||
val data_in = Input(UInt(afeParams.mbSerializerRatio.W)) | ||
val valid = Input(Bool()) | ||
val seed = Input(UInt(23.W)) | ||
val data_out = Output(UInt(afeParams.mbSerializerRatio.W)) | ||
}) | ||
val LFSR = Module( | ||
new FibonacciLFSR( | ||
23, | ||
Set(23, 21, 18, 15, 7, 2, 1), | ||
Some(seed), | ||
XOR, | ||
width, | ||
false, | ||
), | ||
) | ||
LFSR.io.increment := io.valid | ||
LFSR.io.seed.bits := VecInit(io.seed.asBools) | ||
LFSR.io.seed.valid := (reset.asBool) | ||
val LFSR_result = LFSR.io.out | ||
// printf(cf"$LFSR_result.asUInt") | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. can remove this line |
||
io.data_out := LFSR_result.asUInt ^ io.data_in | ||
} | ||
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class UCIeScrambler( | ||
afeParams: AfeParams, | ||
width: Int, | ||
numLanes: Int, | ||
) extends Module { | ||
val io = IO(new Bundle { | ||
val data_in = Input(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) | ||
val valid = Input(Bool()) | ||
val data_out = Output(Vec(numLanes, UInt(afeParams.mbSerializerRatio.W))) | ||
}) | ||
val UCIe_seeds = List( | ||
"1dbfbc", | ||
"0607bb", | ||
"1ec760", | ||
"18c0db", | ||
"010f12", | ||
"19cfc9", | ||
"0277ce", | ||
"1bb807", | ||
) | ||
val seeds = (for (i <- 0 until numLanes) yield UCIe_seeds(i % 8)).toList | ||
val scramblers = | ||
seeds.map(seed => Module(new Scrambler(afeParams, width, BigInt(seed, 16)))) | ||
for (i <- 0 until scramblers.length) { | ||
scramblers(i).io.data_in := io.data_in(i) | ||
scramblers(i).io.valid := io.valid | ||
scramblers(i).reset := reset | ||
scramblers(i).clock := clock | ||
scramblers(i).io.seed := ("h" + seeds(i)).U(23.W) | ||
io.data_out(i) := scramblers(i).io.data_out | ||
} | ||
} |
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Original file line number | Diff line number | Diff line change |
---|---|---|
@@ -0,0 +1,32 @@ | ||
package edu.berkeley.cs.ucie.digital | ||
package interfaces | ||
|
||
import chisel3._ | ||
import chiseltest._ | ||
import org.scalatest.funspec.AnyFunSpec | ||
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class ScramblerTest extends AnyFunSpec with ChiselScalatestTester { | ||
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describe("Scrambler") { | ||
it("4 lane scrambler test") { | ||
test(new UCIeScrambler(new AfeParams(), 16, 4)) { c => | ||
c.reset.poke(true.B) | ||
c.clock.step() | ||
c.clock.step() | ||
c.reset.poke(false.B) | ||
c.clock.step() | ||
c.io.valid.poke(true.B) | ||
|
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c.io.data_in(0).poke(1.U(16.W)) | ||
There was a problem hiding this comment. Choose a reason for hiding this commentThe reason will be displayed to describe this comment to others. Learn more. would be good to add a few more clock steps to the test |
||
c.io.data_in(1).poke(1012.U(16.W)) | ||
c.io.data_in(2).poke(823.U(16.W)) | ||
c.io.data_in(3).poke(134.U(16.W)) | ||
c.io.data_out(0).expect(49085.U(16.W)) | ||
c.io.data_out(1).expect(1103.U(16.W)) | ||
c.io.data_out(2).expect(50263.U(16.W)) | ||
c.io.data_out(3).expect(49245.U(16.W)) | ||
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} | ||
} | ||
} | ||
} |
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do you need this? does
LFSR.io.out.asUInt
not work?