Sideband main

build.sbt

@@ -1,3 +1,40 @@
+// ThisBuild / organization := "edu.berkeley.cs"
+// ThisBuild / version := "0.0.1-SNAPSHOT"
+
+// ThisBuild / scalaVersion := "2.13.10"
+// ThisBuild / scalacOptions := Seq(
+//   "-deprecation",
+//   "-feature",
+//   "-language:reflectiveCalls",
+//   "-Xcheckinit",
+//   "-Xlint",
+// )
+
+// Compile / doc / scalacOptions += "-groups"
+
+// val chiselVersion = "3.6.0"
+
+// lazy val root = (project in file("."))
+//   .settings(
+//     name := "uciedigital",
+//     libraryDependencies ++= Seq(
+//       "edu.berkeley.cs" %% "chisel3" % chiselVersion,
+//       "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % Test,
+//       "org.scalatest" %% "scalatest" % "3.2.17" % Test,
+//       "edu.berkeley.cs" %% "rocketchip" % "1.6.0",
+//       "edu.berkeley.cs" %% "rocket-macros" % "1.6.0",
+//       "edu.berkeley.cs" %% "cde" % "1.6.0",
+//     ),
+//     addCompilerPlugin(
+//       "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full,
+//     ),
+//   )
+
+// // Plugins
+// Global / excludeLintKeys += idePackagePrefix
+// root / idePackagePrefix := Some("edu.berkeley.cs.ucie.digital")
+
+name := "ucie_digital"
 ThisBuild / organization := "edu.berkeley.cs"
 ThisBuild / version := "0.0.1-SNAPSHOT"
 
@@ -14,19 +51,29 @@ Compile / doc / scalacOptions += "-groups"
 
 val chiselVersion = "3.6.0"
 
-lazy val root = (project in file("."))
-  .settings(
-    name := "uciedigital",
-    libraryDependencies ++= Seq(
-      "edu.berkeley.cs" %% "chisel3" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % Test,
-      "org.scalatest" %% "scalatest" % "3.2.17" % Test,
-    ),
-    addCompilerPlugin(
-      "edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full,
-    ),
+// SNAPSHOT repositories
+libraryDependencies ++=
+  Seq(
+    "edu.berkeley.cs" %% "rocketchip-3.6.0" % "1.6-3.6.0-e3773366a-SNAPSHOT",
+    "edu.berkeley.cs" %% "chisel3" % chiselVersion,
+    "edu.berkeley.cs" %% "chiseltest" % "0.6.2" % "test",
+    "org.scalatest" %% "scalatest" % "3.2.17" % "test",
   )
 
-// Plugins
-Global / excludeLintKeys += idePackagePrefix
-root / idePackagePrefix := Some("edu.berkeley.cs.ucie.digital")
+resolvers ++= Resolver.sonatypeOssRepos("snapshots")
+resolvers ++= Resolver.sonatypeOssRepos("releases")
+resolvers += Resolver.mavenLocal
+
+addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full)
+
+import Tests._
+
+Test / fork := true
+Test / testGrouping := (Test / testGrouping).value.flatMap { group =>
+   group.tests.map { test =>
+      Group(test.name, Seq(test), SubProcess(ForkOptions()))
+   }
+}
+
+concurrentRestrictions := Seq(Tags.limit(Tags.ForkedTestGroup, 72))
+

project/build.properties

@@ -1 +1 @@
-sbt.version=1.9.8
+sbt.version=1.9.7

src/main/scala/sideband/sidebandChannel.scala

@@ -0,0 +1,63 @@
+package edu.berkeley.cs.ucie.digital
+package sideband
+
+import chisel3._
+import chisel3.util._
+import chisel3.experimental._
+
+import interfaces._
+
+// import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util._
+
+class D2DSidebandChannel(
+    val myID: BigInt = BigInt(1),
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Module {
+  val io = IO(new D2DSidebandChannelIO(sbParams, fdiParams))
+
+  // Instantiate submodule
+  val upper_node = Module(new SidebandNode(sbParams, fdiParams))
+  val switcher = Module(new sidebandSwitcher(myID, sbParams))
+  val lower_node = Module(new SidebandNode(sbParams, fdiParams))
+
+  // Connect outer signals
+  io.to_upper_layer <> upper_node.io.outer
+  io.to_lower_layer <> lower_node.io.outer
+
+  // Connect two sidebandNodes and switcher
+  upper_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_above
+  upper_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_above
+  lower_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_below
+  lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below
+
+  // Connect inner signals
+  io.inner <> switcher.io.inner
+}
+
+class PHYSidebandChannel(
+    val myID: BigInt = BigInt(2),
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Module {
+  val io = IO(new PHYSidebandChannelIO(sbParams, fdiParams))
+
+  // Instantiate submodule
+  val upper_node = Module(new SidebandNode(sbParams, fdiParams))
+  val switcher = Module(new sidebandSwitcher(myID, sbParams))
+  val lower_node = Module(new SidebandLinkNode(sbParams, fdiParams))
+
+  // Connect outer signals
+  io.to_upper_layer <> upper_node.io.outer
+  io.to_lower_layer <> lower_node.io.outer
+
+  // Connect two sidebandNodes and switcher
+  upper_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_above
+  upper_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_above
+  lower_node.io.inner.layer_to_node <> switcher.io.outer.layer_to_node_below
+  lower_node.io.inner.node_to_layer <> switcher.io.outer.node_to_layer_below
+
+  // Connect inner signals
+  io.inner <> switcher.io.inner
+}

src/main/scala/sideband/sidebandIO.scala

@@ -0,0 +1,171 @@
+package edu.berkeley.cs.ucie.digital
+package sideband
+
+import chisel3._
+import chisel3.util._
+import chisel3.experimental._
+
+import interfaces._
+
+// import freechips.rocketchip.config.Parameters
+import freechips.rocketchip.util._
+
+class D2DSidebandChannelIO(
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Bundle {
+  // connect to another sideband node in the layer above (protocol layer)
+  val to_upper_layer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val valid = Output(Bool())
+      val credit = Input(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val valid = Input(Bool())
+      val credit = Output(Bool())
+    }
+  }
+  // connect to another sideband node in the layer below (physical layer)
+  val to_lower_layer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val valid = Output(Bool())
+      val credit = Input(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val valid = Input(Bool())
+      val credit = Output(Bool())
+    }
+  }
+  // d2d layer drive these
+  val inner = Flipped(new SidebandSwitcherbundle(sbParams))
+}
+
+class PHYSidebandChannelIO(
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Bundle {
+  // connect to another sideband node in the layer above (d2d layer)
+  val to_upper_layer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val valid = Output(Bool())
+      val credit = Input(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val valid = Input(Bool())
+      val credit = Output(Bool())
+    }
+  }
+  // connect to another sideband node in the layer below (link layer)
+  val to_lower_layer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val clock = Output(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val clock = Input(Bool())
+    }
+  }
+  // phy layer drive these
+  val inner = Flipped(new SidebandSwitcherbundle(sbParams))
+}
+
+// IO for the RDI and FDI sideband
+class SidebandNodeIO(val sbParams: SidebandParams, val fdiParams: FdiParams)
+    extends Bundle {
+  // layers drive these
+  val inner = new Bundle {
+    val layer_to_node = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
+    /* This signal overrides the tx.ready and takes up the priority reserved
+     * queue slot */
+    // Should only be asserted high for access completion packets
+    val node_to_layer = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
+  }
+  // connect these to another sideband node
+  val outer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val valid = Output(Bool())
+      val credit = Input(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val valid = Input(Bool())
+      val credit = Output(Bool())
+    }
+  }
+}
+
+class SidebandNodeOuterIO(
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Bundle {
+  val tx = new Bundle {
+    val bits = Output(UInt(fdiParams.sbWidth.W))
+    val valid = Output(Bool())
+    val credit = Input(Bool())
+  }
+  val rx = new Bundle {
+    val bits = Input(UInt(fdiParams.sbWidth.W))
+    val valid = Input(Bool())
+    val credit = Output(Bool())
+  }
+}
+
+class SidebandLinkNodeOuterIO(
+    val sbParams: SidebandParams,
+    val fdiParams: FdiParams,
+) extends Bundle {
+  val tx = new Bundle {
+    val bits = Output(UInt(fdiParams.sbWidth.W))
+    val clock = Output(Bool())
+  }
+  val rx = new Bundle {
+    val bits = Input(UInt(fdiParams.sbWidth.W))
+    val clock = Input(Bool())
+  }
+}
+
+// IO for the remote sideband
+class SidebandLinkIO(val sbParams: SidebandParams, val fdiParams: FdiParams)
+    extends Bundle {
+  // layers drive these
+  val inner = new Bundle {
+    val layer_to_node = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
+    /* This signal overrides the tx.ready and takes up the priority reserved
+     * queue slot */
+    // Should only be asserted high for access completion packets
+    val node_to_layer = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
+  }
+  // connect these to another sideband node
+  val outer = new Bundle {
+    val tx = new Bundle {
+      val bits = Output(UInt(fdiParams.sbWidth.W))
+      val clock = Output(Bool())
+    }
+    val rx = new Bundle {
+      val bits = Input(UInt(fdiParams.sbWidth.W))
+      val clock = Input(Bool())
+    }
+  }
+}
+
+class SidebandSwitcherIO(val sbParams: SidebandParams) extends Bundle {
+  // layer drive these
+  val inner = Flipped(new SidebandSwitcherbundle(sbParams))
+  // Sideband node drive these
+  val outer = new SidebandSwitcherbundle(sbParams)
+}
+
+class SidebandSwitcherbundle(val sbParams: SidebandParams) extends Bundle {
+  val node_to_layer_above = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
+  val layer_to_node_above = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
+  val node_to_layer_below = Flipped(Decoupled(UInt(sbParams.sbNodeMsgWidth.W)))
+  val layer_to_node_below = Decoupled(UInt(sbParams.sbNodeMsgWidth.W))
+}