Added state change logic for disabled and internal disabled logic

src/main/scala/d2dadapter/LinkDisabledSubmodule.scala

@@ -0,0 +1,58 @@
+package edu.berkeley.cs.ucie.digital
+package d2dadapter
+
+import chisel3._
+import chisel3.util._
+import interfaces._
+
+class LinkDisabledSubmoduleIO (params: D2DAdapterParams) extends Bundle {
+    val fdi_lp_state_req = Input()
+    val fdi_lp_state_req_prev = Input()
+    val rdi_pl_state_sts = Input()
+    val link_state = Input()
+    val disabled_entry = Output(Bool())
+    val disabled_sb_snd = Decoupled(UInt(16.W))
+    val disabled_sb_rcv = Flipped(Valid(UInt(16.W)))
+}
+
+/**
+  * LinkDisabledSubmodule handles the transition of FDI/RDI state machine
+  * from Reset, Active, Retrain, and LinkReset to Disabled state. The 
+  * transition is triggered by fdi_lp_state_req or though sideband messages
+  * coming from partner link.
+  * @param params
+  */
+class LinkDisabledSubmodule (params: D2DAdapterParams) extends Module {
+    val io = IO(new LinkDisabledSubmoduleIO(params))
+
+    val disabled_fdi_req_reg = RegInit(false.B)
+    val disabled_sbmsg_int_req_reg = RegInit(false.B)
+    val disabled_sbmsg_ext_req_reg = RegInit(false.B)
+
+    when(io.link_state === PhyState.reset ||
+         io.link_state === PhyState.active ||
+         io.link_state === PhyState.retrain ||
+         io.link_state === PhyState.linkReset) {
+
+        io.disabled_entry := disabled_int_req_reg || disabled_sbmsg_int_req_reg ||
+                             disabled_sbmsg_ext_req_reg
+
+        // State change request by fdi
+        when(io.link_state === PhyState.reset &&
+             io.fdi_lp_state_req === PhyStateReq.disabled &&
+             io.fdi_lp_state_req_prev === PhyState.nop) {
+            disabled_fdi_req_reg := true.B
+        }.elsewhen(io.fdi_lp_state_req === PhyStateReq.disabled &&
+                   io.link_state =/= PhyState.reset) {
+            disabled_fdi_req_reg := true.B
+        }.otherwise{
+            disabled_fdi_req_reg := disabled_fdi_req_reg
+        }
+
+        // TODO: State change requested with positive acknowledge from partner Die
+
+        // TODO: State change requested by partner Die with positive response
+    }.otherwise {
+
+    }
+}

src/main/scala/d2dadapter/LinkInitSubmodule.scala

@@ -0,0 +1,20 @@
+package edu.berkeley.cs.ucie.digital
+package d2dadapter
+
+import chisel3._
+import chisel3.util._
+import interfaces._
+import sideband._
+
+class LinkInitSubmoduleIO (params: D2DAdapterParams) extends Bundle {
+
+}
+
+/**
+  * 
+  *
+  * @param params
+  */
+class LinkInitSubmodule (params: D2DAdapterParams) extends Module {
+
+}

src/main/scala/d2dadapter/LinkManagementController.scala

@@ -4,57 +4,122 @@ package d2dadapter
 import chisel3._
 import chisel3.util._
 import interfaces._
+import sideband._
 
-class LinkManagementControllerIO (val params: D2DAdapterParams) extends Bundle {
+class LinkManagementControllerIO (params: D2DAdapterParams) extends Bundle {
     val fdi = Flipped(new Fdi(params))
     val rdi = new Rdi(params)
-    val sb = new Sb(params)
-} 
+    // TODO: We need to define a common packet format for SB internal messages
+    val sb_snd = Decoupled(UInt(16.W))
+    val sb_rcv = Flipped(Valid(UInt(16.W)))
+}
 
 /**
   * LinkManagementController for top level FDI/RDI state machine implementation, 
   * decoding the sideband messages and arbitration of triggers for the D2D adapter
   * state machine
-  * @param params
+  * @param params D2DAdapterParams
   */
-class LinkManagementController (val params: D2DAdapterParams) extends Module {
+class LinkManagementController (params: D2DAdapterParams) extends Module {
     val io = IO(new LinkManagementControllerIO(params))
 
-    // Output registers
+    // Submodule instantiations
+    val disabled_submodule = Module(new LinkDisabledSubmodule(params))
 
+    // Output registers
     // LinkError signal propagated to the PHY
     val rdi_lp_linkerror_reg = RegInit(PhyStateReq.nop)
+    val rdi_lp_state_req_reg = RegInit(PhyStateReq.nop)
+
+    val fdi_pl_rxactive_req_reg = RegInit(false.B)
+
+    // Internal registers
+    val fdi_lp_state_req_prev_reg = RegNext(io.fdi.lpStateReq)
 
     // FDI/RDI state register
     val link_state_reg = RegInit(PhyState.reset)
 
     // Top level IO signal assignments
+    // RDI
     io.rdi.lpLinkError := rdi_lp_linkerror_reg
+    io.rdi.lpStateReq := rdi_lp_state_req_reg
+    // FDI
     io.fdi.plStateStatus := link_state_reg
+    io.fdi.plRxActiveReq := fdi_pl_rxactive_req_reg
 
     // LinkError propagation from Protocol layer to PHY
     rdi_lp_linkerror_reg := io.fdi.lpLinkError
 
-    // FDI/RDI common state change triggers
+    // Submodule IO signal assignments
+    // Disabled submodule
+    disabled_submodule.io.fdi_lp_state_req := io.fdi.lpStateReq
+    disabled_submodule.io.fdi_lp_state_req_prev := fdi_lp_state_req_prev_reg
+    disabled_submodule.io.rdi_pl_state_sts := io.rdi.plStateStatus
+    disabled_submodule.io.link_state := link_state_reg
+    val disabled_entry := disabled_submodule.io.disabled_entry
+    // Intermediate sideband messgaes which gets assigned to top IO when required
+    val disabled_sb_snd := disabled_submodule.io.disabled_sb_snd
+    disabled_submodule.io.sb_rcv := io.sb_rcv
 
+    // FDI/RDI common state change triggers
     // LinkError logic
     // PHY informs the adapter over RDI that it is in linkError state
-    val linkerror_phy_sts = io.rdi.plStateStatus == PhyState.linkError
+    val linkerror_phy_sts = io.rdi.plStateStatus === PhyState.linkError
     // Protocol initiates linkError through lp_linkerror assertion
     val linkerror_fdi_req = io.fdi.lpLinkError
     // Placeholder for any other internal request logic which can trigger linkError
 
-    // TODO:RDI lp state request generation logic
+    // rx_deactive and rx_active signals for checking if rx on mainband is disabled
+    val rx_deactive := ~io.fdi.lpRxActiveStatus & ~io.fdi.plRxActiveReq
+    val rx_active := io.fdi.lpRxActiveStatus & io.fdi.plRxActiveReq
+
+    // Moved this condition to the disabled module
+    // Reset to disabled requires atleast one clock cycle of lp_state_req = Reset(NOP)
+    //val disabled_from_reset_fdi_req = ((fdi_lp_state_req_prev_reg === PhyStateReq.reset &&
+    //                                    io.fdi.lpStateReq === PhyStateReq.reset) &&
+    //                                    io.rdi.plStateStatus === PhyState.reset)
+
+    // TODO: Sideband message generation logic
+
+    // TODO: RDI lp state request generation logic
+    when(link_state_reg === PhyState.reset) {
+
+    }.elsewhen(link_state_reg === PhyState.active) {
+
+    }.elsewhen(link_state_reg === PhyState.retrain) {
+
+    }.elsewhen(link_state_reg === PhyState.linkError) {
+        // Section 8.3.4.2 for link error exit
+        when(io.fdi.lpStateReq === PhyStateReq.active && !linkerror_fdi_req &&
+                (io.rdi.plStateStatus === PhyState.linkError)) {
+            rdi_lp_state_req_reg := PhyStateReq.active
+        }.otherwise {
+            rdi_lp_state_req_reg := PhyStateReq.nop
+        }
+    }.elsewhen(link_state_reg === PhyState.disabled) {
+        when(io.fdi.lpStateReq === PhyStateReq.active) {
+            rdi_lp_state_req_reg := PhyStateReq.active
+        }.otherwise{
+            rdi_lp_state_req_reg := PhyStateReq.disabled
+        }
+    }.elsewhen(link_state_reg === PhyState.linkReset) {
+
+    }
 
     // FDI/RDI state machine. We use the same SM for optimized code as the spec
     // seems to trigger the state machines in tandem with no intermediate signalling 
     switch(link_state_reg) {
         // RESET
         is(PhyState.reset){
             when(linkerror_phy_sts || linkerror_fdi_req) {
+                // TODO: any internal condition to trigger linkError? + SB msgs
                 link_state_reg := PhyState.linkError
+            }.elsewhen(disabled_entry && rx_deactive) {
+                link_state_reg := PhyState.disabled
             }.elsewhen() {
-
+                link_state_reg := PhyState.linkReset
+            }.elsewhen() {
+                link_state_reg := PhyState.active
             }.otherwise {
                 link_state_reg := link_state_reg
             }
@@ -63,8 +128,8 @@ class LinkManagementController (val params: D2DAdapterParams) extends Module {
         is(PhyState.active) {
             when(linkerror_phy_sts || linkerror_fdi_req) {
                 link_state_reg := PhyState.linkError
-            }.elsewhen() {
-
+            }.elsewhen(disabled_entry && rx_deactive) {
+                link_state_reg := PhyState.disabled
             }.otherwise {
                 link_state_reg := link_state_reg
             }
@@ -73,8 +138,8 @@ class LinkManagementController (val params: D2DAdapterParams) extends Module {
         is(PhyState.retrain) {
             when(linkerror_phy_sts || linkerror_fdi_req) {
                 link_state_reg := PhyState.linkError
-            }.elsewhen() {
-
+            }.elsewhen(disabled_entry) {
+                link_state_reg := PhyState.disabled
             }.otherwise {
                 link_state_reg := link_state_reg
             }
@@ -84,7 +149,7 @@ class LinkManagementController (val params: D2DAdapterParams) extends Module {
             // TODO: Check this logic, also needs state change on internal reset request
             // 
             when(io.fdi.lpStateReq === PhyStateReq.active && !linkerror_fdi_req &&
-                (io.rdi.plStateStatus === PhyState.linkError)) {
+                (io.rdi.plStateStatus === PhyState.linkError) && rx_deactive) {
                     link_state_reg := PhyState.reset
                 }.otherwise {
                     link_state_reg := link_state_reg
@@ -94,8 +159,9 @@ class LinkManagementController (val params: D2DAdapterParams) extends Module {
         is(PhyState.disabled) {
             when(linkerror_phy_sts || linkerror_fdi_req) {
                 link_state_reg := PhyState.linkError
-            }.elsewhen() {
-
+            }.elsewhen(io.fdi.lpStateReq === PhyStateReq.active || 
+                        io.rdi.plStateStatus === PhyState.reset) {
+                link_state_reg := PhyState.reset
             }.otherwise {
                 link_state_reg := link_state_reg
             }
@@ -104,8 +170,8 @@ class LinkManagementController (val params: D2DAdapterParams) extends Module {
         is(PhyState.linkReset) {
             when(linkerror_phy_sts || linkerror_fdi_req) {
                 link_state_reg := PhyState.linkError
-            }.elsewhen() {
-
+            }.elsewhen(disabled_entry && rx_deactive) {
+                link_state_reg := PhyState.disabled
             }.otherwise {
                 link_state_reg := link_state_reg
             }