VPR 3.99 Release

Released: 1997-05-12

Downloaded from: http://www.eecg.utoronto.ca/~vaughn/vpr/downloadfiles/vpr399.tar.Z

Author: kmurray

README

@@ -1,5 +1,142 @@
-This tarfile contains:
+This archive contains VPR, an FPGA placement and routing tool, and VPACK,
+a program to pack LUTs and flip flops into coarser grained logic blocks and
+convert a netlist from blif format to VPR's .net format.
 
-manual.ps:  Postscript version of the VPR user's manual.
-vpr:        Directory containing source and sample input files for VPR.
-blifmap:    Directory containing source and a sample input file for blifmap.
+To see VPR in action on the sample files included here, type:
+
+vpr e64.net sample.arch out.p out.r
+
+
+If you want only global routing to be performed, use:
+
+vpr e64.net sample.arch out.p out.r -route_type global
+
+=============================================================================
+
+Major changes since the last version (Version 3.22) of VPR include:
+
+- The blifmap netlist translation program has been replaced by the more
+  powerful VPACK program.
+
+- VPR can now perform either combined global and detailed routing, or global
+  routing alone.
+
+To convert a technology-mapped file in .blif format to a logic block containing
+one 4-input LUT and a FF use:
+
+vpack input.blif output.net -lut_size 4 -no_clustering
+
+
+To convert the same blif file into a netlist in which every logic block 
+contains 4 LUTs and 4 FFs, and there are only 10 inputs to the LUTs, use:
+
+vpack input.blif output.net -lut_size 4 -cluster_size 4 -inputs_per_cluster 10
+
+
+
+To place and route this netlist in VPR, type:
+
+vpr input.net input.arch output.placed output.routed
+
+Note that the logic block used in the netlist and the logic block described
+in the architecture file must be the same.
+
+The speed quality/tradeoff of the VPR placer is best controlled with the
+-inner_num option.  Specifying -inner_num 1 on the command line will speed
+up the placer by a factor of 10, at the cost of about a 10% reduction in
+placement quality.
+
+The speed quality/tradeoff in the VPR router is best controlled with the
+-max_router_iterations and -initial_pres_fac options.  Setting 
+-max_router_iterations to 15 will roughly double the speed of the router, at
+the cost of some additional track usage, by making the router give up 
+and decide a circuit is unroutable at a given channel width sooner.  That is,
+the router will not take as long on unsuccessful routing attempts.  Setting 
+-initial_pres_fac to a large number (say 1000) will greatly speed up successful
+routings; it won't speed up unsuccessful routing attempts.
+
+
+==============================================================================
+Contents of the archive:
+
+manual.ps:  Postscript manual of VPR.
+README:     This file.
+
+./vpr
+
+  *.c, *.h:  Source code for VPR.
+
+  makefile:  Makefile for VPR.  Currently set for Solaris and gcc; you may
+             have to modify the library paths and compiler options on your
+             machine.
+
+  descript.txt:  A revision history of VPR.
+  
+  e64.net:  A sample netlist file from the MCNC bencmark set.  The logic 
+            block contains one LUT + one FF.
+
+  sample.arch:  A sample FPGA architecture file.  The logic block consists
+                of one LUT + one FF in the configuration shown in manual.ps.
+
+  e64.p:  A placement of e64 generated by VPR. 
+
+
+./vpack
+
+  *.c, *.h:  Source code for VPACK.
+
+  makefile:  Makefile for VPACK.  May have to be modified for non Solaris
+             machines or for compilers other than gcc.
+
+  descript.txt:  Revision history of VPACK.
+
+  e64.blif:  MCNC benchmark circuit e64 technology-mapped by Flowmap to 
+             4-input LUTs.  This is a combinational circuit.
+
+  s1423.blif:  A sequential MCNC benchmark circuit.  It has been technology-
+               mapped to 4-input LUTs and flip flops by Flowmap.
+
+
+==============================================================================
+
+Changes from VPR Version 3.22 to this Version (3.99):
+
+1) The blifmap program has been replaced by the VPACK program.  The command:
+
+   vpack input.blif output.net -lut_size 4 -no_clustering
+
+   is equivalent to
+
+   blifmap input.blif output.net -lut_size 4 -global
+
+
+2) The .net netlist format used as input to VPR has had a new line, the
+   subblock line, added to it.  VPACK will automatically add this new line
+   to every clb, so if you used blifmap to convert .blif files to .net
+   format, just use VPACK to reconvert the .blif files to this new format.
+   Old .net files will not work with this version of VPR.
+   See the manual for details of the new format.
+
+
+3) Several new lines have been added to the architecture file.  See the
+   manual for details.
+
+
+4) VPR now defaults to combined global and detailed routing, and tries 
+   30 routing iterations before deciding a circuit is unroutable at a
+   certain track width.  To do global routing with a maximum of 15 routing
+   iterations (the default in VPR version 3.22), use the command:
+
+   vpr input.net input.arch output.p output.r -route_type global
+        -max_router_iterations 15
+
+
+5) The placement file format has been slightly changed.  Block numbers are
+   no longer required in the placement file, and blocks can now be listed
+   in any order in a placement file used as input to VPR.  This should make
+   it much easier to read placements generated by other tools into VPR.
+   See the manual for details.
+
+
+6) One can now read in a fixed I/O configuration and force VPR to use these
+   I/O locations.  Use the -fix_pins <file.pads> option.