VPR 4.22 Release

Released: 1999-02-17

Downloaded from: http://www.eecg.utoronto.ca/~vaughn/vpr/downloadfiles/vpr422.tar.Z

Author: kmurray

README

@@ -0,0 +1,105 @@
+This archive contains VPR, an FPGA placement and routing tool, and VPack,
+a program to pack LUTs and flip flops into coarser grained logic blocks and
+convert a netlist from blif format to VPR's .net format.  There is a detailed
+postscript manual covering everything from how to compile the programs
+to how to use them in manual422.ps
+
+To see VPR in action on the (small) sample circuit (e64 from the MCNC 
+benchmark suite) and the sample FPGA architecture files type:
+
+cd vpr (if not already there)
+vpr e64-4x4lut.net 4x4lut_sanitized.arch e64.p e64.r -route_chan_width 40 -inner_num 3
+
+The logic block for this architecture contains 4, 4-input look-up tables and
+4 flip flops along with local routing (a cluster-based logic block of size
+4).  The routing wire segments all span 4 logic blocks in this architecture.
+
+
+I've also included a simpler architecture in which a logic block is only a
+4 LUT plus a flip flop, and in which all routing wires span only one logic
+block.  To run this case, try:
+
+cd vpr (if not already there)
+vpr e64-4lut.net 4lut_sanitized.arch e64.p e64.r -route_chan_width 10 -inner_num 3
+
+
+The two netlists (e64-4x4lut.net and e64-4lut.net) were created using VPack
+on a technology-mapped netlist in .blif format, with the appropriate options
+in each case:
+
+cd vpack  (if not already there)
+vpack e64.blif e64-4x4lut.net -cluster_size 4 -inputs_per_cluster 10
+
+and
+
+cd vpack  (if not already there)
+vpack e64.blif e64-4lut.net -no_clustering
+
+
+
+There are a lot of different ways to use VPR and VPack -- see manual422.ps
+for details.
+
+-- Vaughn Betz, Jan. 26, 1999
+
+
+==============================================================================
+Contents of the archive:
+
+manual422.ps:  Postscript manual of VPR.
+README.422:     This file.
+
+./vpr
+
+  *.c, *.h:  Source code for VPR.
+
+  makefile:  Makefile for VPR.  Currently set for Solaris and gcc; you may
+             have to modify the library paths and compiler options on your
+             machine.
+
+  descript.txt:  A revision history of VPR.
+  
+  e64-4x4lut.net:  A sample netlist file from the MCNC bencmark set.  The logic
+            block contains 4 4-input LUTs and 4 FFs.
+
+  e64-4lut.net:  A sample netlist file from the MCNC benchmark set.  The logic
+            block contains 1 4-LUT and 1 FF.
+
+  4x4lut_sanitized.arch:  A sample FPGA architecture file, with a logic block
+            containing 4 4-input LUTs and 4 FFs.
+
+  4lut_sanitized.arch:  A sample FPGA architecture file, with a logic block
+            containing 1 4-LUT and 1 FF.
+
+
+./vpack
+
+  *.c, *.h:  Source code for VPACK.
+
+  makefile:  Makefile for VPACK.  May have to be modified for non Solaris
+             machines or for compilers other than gcc.
+
+  descript.txt:  Revision history of VPACK.
+
+  e64.blif:  MCNC benchmark circuit e64 technology-mapped by Flowmap to 
+             4-input LUTs.  This is a combinational circuit.
+
+  s1423.blif:  A sequential MCNC benchmark circuit.  It has been technology-
+               mapped to 4-input LUTs and flip flops by Flowmap.
+
+
+==============================================================================
+
+Major changes from VPR Version 3.99 to this Version (4.22)
+
+1) A timing-driven router has been added to VPR, and is used by default.
+
+2) VPR now supports routing architectures with wires that span more than
+   1 logic block, and architectures that include both pass transistor and
+   buffered routing switches.
+
+3) Delay extraction and timing analysis have been added to VPR, so it now
+   outputs the speed of a placed and routed circuit.
+
+4) An area model has been incorporated, so it now estimates the area required
+   to lay out an FPGA's routing.

README.422

@@ -1,7 +1,7 @@
 #include <stdio.h>
-#include "vpack.h"
-#include "ext.h"
 #include "util.h"
+#include "vpack.h"
+#include "globals.h"
 #include "cluster.h"
 #include "output_clustering.h"
 
@@ -139,14 +139,17 @@ static void check_clocks (boolean *is_clock, int lut_size) {
              block[iblk].type == LUT_AND_LATCH) {
        for (ipin=1;ipin<lut_size+1;ipin++) {
           inet = block[iblk].nets[ipin]; 
-          if (is_clock[inet]) {
-            printf("Error in check_clocks.  Net %d (%s) is a clock, but also\n"
-                   "connects to a LUT input on block %d (%s).\n", inet, 
-                      net[inet].name, iblk, block[iblk].name);
-            printf("This would break the current clustering implementation \n"
-                   "and is electrically questionable, so clustering has been\n"
-                   "aborted.\n");
-            exit (1);
+          if (inet != OPEN) {
+             if (is_clock[inet]) {
+                printf("Error in check_clocks.  Net %d (%s) is a clock, but "
+                       "also\n"
+                       "\tconnects to a LUT input on block %d (%s).\n", inet, 
+                       net[inet].name, iblk, block[iblk].name);
+                printf("This would break the current clustering "
+                       "implementation and is electrically\n"
+                       "\tquestionable, so clustering has been aborted.\n");
+                exit (1);
+             }
           }
        }
     }
@@ -353,13 +356,18 @@ static int get_block_by_num_ext_inputs (int ext_inps, int lut_size, int
 
  while (ptr != NULL) {
     iblk = ptr->iblk;
+
     if (cluster_of_block[iblk] == NO_CLUSTER) {
        if (clocks_feasible (iblk, 0, clocks_avail, lut_size, NULL)) 
           return (iblk);
+
+       prev_ptr = ptr;
     }
+
     else if (remove_flag == REMOVE_CLUSTERED) {
        prev_ptr->next = ptr->next;
     }
+
     ptr = ptr->next;
  }
 
@@ -1232,7 +1240,8 @@ static void check_clustering (int num_clusters, int cluster_size,
 void do_clustering (int cluster_size, int inputs_per_cluster,
        int clocks_per_cluster, int lut_size, boolean global_clocks,
        boolean *is_clock, boolean hill_climbing_flag, 
-       enum e_cluster_seed cluster_seed_type, char *out_fname) {
+       enum e_cluster_seed cluster_seed_type, boolean 
+       muxes_to_cluster_output_pins, char *out_fname) {
 
 /* Does the actual work of clustering multiple LUT+FF logic blocks *
  * into clusters.                                                  */
@@ -1288,10 +1297,11 @@ void do_clustering (int cluster_size, int inputs_per_cluster,
                cluster_occupancy);
  output_clustering (cluster_contents, cluster_occupancy, cluster_size,
                inputs_per_cluster, clocks_per_cluster, num_clusters, 
-               lut_size, global_clocks, is_clock, out_fname);
+               lut_size, global_clocks, muxes_to_cluster_output_pins,
+               is_clock, out_fname);
 
  free (cluster_occupancy);
- free_matrix ((void **) cluster_contents, 0, num_clusters-1, 0, 
+ free_matrix (cluster_contents, 0, num_clusters-1, 0, 
            sizeof (int));
  free_clustering ();
 }

manual422.ps

@@ -1,5 +1,6 @@
 void do_clustering (int cluster_size, int inputs_per_cluster,
         int clocks_per_cluster, int lut_size, boolean global_clocks,
         boolean *is_clock, boolean hill_climbing_flag,
-        enum e_cluster_seed cluster_seed_type, char *out_fname);
+        enum e_cluster_seed cluster_seed_type, boolean
+        muxes_to_cluster_output_pins, char *out_fname);
 int num_input_pins (int iblk);