fix

vlib/v/gen/c/array.v

@@ -350,9 +350,15 @@ fn (mut g Gen) array_init_with_fields(node ast.ArrayInit, elem_type Type, is_amp
 		g.set_current_pos_as_last_stmt_pos()
 		g.indent++
 		g.writeln('int it = index;') // FIXME: Remove this line when it is fully forbidden
-		g.write('*pelem = ')
-		g.expr_with_init(node)
-		g.writeln(';')
+		if elem_type.unaliased_sym.kind != .array_fixed {
+			g.write('*pelem = ')
+			g.expr_with_init(node)
+			g.writeln(';')
+		} else {
+			g.write('memcpy(pelem, ')
+			g.expr_with_init(node)
+			g.writeln(', sizeof(${elem_styp}));')
+		}
 		g.indent--
 		g.writeln('}')
 		g.indent--

vlib/v/parser/parse_type.v

@@ -95,7 +95,7 @@ fn (mut p Parser) parse_array_type(expecting token.Kind, is_option bool) ast.Typ
 			p.error_with_pos('fixed size cannot be zero or negative', size_expr.pos())
 		}
 		idx := p.table.find_or_register_array_fixed(elem_type, fixed_size, size_expr,
-			p.fixed_array_dim == 1 && !is_option && p.inside_fn_return)
+			p.array_dim == 1 && p.fixed_array_dim == 1 && !is_option && p.inside_fn_return)
 		if elem_type.has_flag(.generic) {
 			return ast.new_type(idx).set_flag(.generic)
 		}
@@ -646,6 +646,10 @@ fn (mut p Parser) parse_any_type(language ast.Language, is_ptr bool, check_dot b
 		}
 		.lsbr, .nilsbr {
 			// array
+			p.array_dim++
+			defer {
+				p.array_dim--
+			}
 			return p.parse_array_type(p.tok.kind, is_option)
 		}
 		else {

vlib/v/parser/parser.v

@@ -72,6 +72,7 @@ mut:
 	inside_orm               bool
 	inside_chan_decl         bool
 	inside_attr_decl         bool
+	array_dim                int               // array dim parsing level
 	fixed_array_dim          int               // fixed array dim parsing level
 	or_is_handled            bool              // ignore `or` in this expression
 	builtin_mod              bool              // are we in the `builtin` module?

vlib/v/tests/fixed_array_on_array_test.v

@@ -0,0 +1,8 @@
+fn separate_wires(coo_adj_wires [][2]u32, id u64) [][2]u32 {
+	return [][2]u32{len: coo_adj_wires.len, init: coo_adj_wires[index]}
+}
+
+fn test_main() {
+	t := separate_wires([[u32(1), 2]!], 0)
+	assert t.str() == '[[1, 2]]'
+}