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Version 10.4b with improvements to the Z80 core, better CPU flag handling and added the ZEXALL documented opcode tester to ensure we're basically right.
1 parent 5e65a1e commit ead75a7

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11 files changed

+408
-17
lines changed

11 files changed

+408
-17
lines changed

‎ColecoDS.nds

-3.5 KB
Binary file not shown.

‎Makefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -15,7 +15,7 @@ include $(DEVKITARM)/ds_rules
1515

1616
export TARGET := ColecoDS
1717
export TOPDIR := $(CURDIR)
18-
export VERSION := 10.4a
18+
export VERSION := 10.4b
1919

2020
ICON := -b $(CURDIR)/logo.bmp "ColecoDS $(VERSION);wavemotion-dave;https://github.com/wavemotion-dave/ColecoDS"
2121

‎arm9/source/CRC32.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,7 @@
1616

1717
#define CRC32_POLY 0x04C11DB7
1818

19-
const u32 crc32_table[256] __attribute__((section(".dtcm"))) = {
19+
const u32 crc32_table[256] = {
2020
0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA, 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3, // 0 [0x00 .. 0x07]
2121
0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988, 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91, // 8 [0x08 .. 0x0F]
2222
0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE, 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7, // 16 [0x10 .. 0x17]
@@ -79,7 +79,7 @@ u32 crcBasedOnFilename(const char *filename)
7979
// ------------------------------------------------------------------------------------
8080
// Read the file in and compute CRC... it's a bit slow but good enough and accurate!
8181
// ------------------------------------------------------------------------------------
82-
u8 file_crc_buffer[4096];
82+
u8 file_crc_buffer[2048];
8383
ITCM_CODE u32 getFileCrc(const char* filename)
8484
{
8585
extern u32 file_size;

‎arm9/source/colecoDS.c

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -591,6 +591,7 @@ void setupStream(void)
591591
mmLoadEffect(SFX_FLOPPY);
592592
mmLoadEffect(SFX_ADAM_DDP);
593593

594+
#ifndef ZEXALL_TEST
594595
//----------------------------------------------------------------
595596
// open stream
596597
//----------------------------------------------------------------
@@ -601,6 +602,7 @@ void setupStream(void)
601602
myStream.timer = MM_TIMER0; // use hardware timer 0
602603
myStream.manual = false; // use automatic filling
603604
mmStreamOpen(&myStream);
605+
#endif
604606

605607
//----------------------------------------------------------------
606608
// when using 'automatic' filling, your callback will be triggered
@@ -3116,6 +3118,11 @@ void colecoDS_main(void)
31163118

31173119
// Force the sound engine to turn on when we start emulation
31183120
bStartSoundEngine = true;
3121+
3122+
#ifdef ZEXALL_TEST
3123+
extern void zextest(void);
3124+
zextest();
3125+
#endif
31193126

31203127
// -------------------------------------------------------------------
31213128
// Stay in this loop running the Coleco game until the user exits...
@@ -4721,6 +4728,7 @@ void debug_printf(const char * str, ...)
47214728

47224729
strcat(debug_buffer, szName);
47234730
debug_len += strlen(szName);
4731+
debug[0]++;
47244732
}
47254733

47264734
void debug_save()

‎arm9/source/cpu/tms9918a/tms9918a.c

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -801,6 +801,7 @@ ITCM_CODE byte Loop9918(void)
801801
/* If refreshing display area, call scanline handler */
802802
if ((CurLine >= tms_start_line) && (CurLine < tms_end_line))
803803
{
804+
#ifndef ZEXALL_TEST
804805
unsigned int tmp;
805806
if ((frameSkipIdx & frameSkip[myConfig.frameSkip]) == 0)
806807
ScanSprites(CurLine - tms_start_line, &tmp); // Skip rendering - but still scan sprites for the 5th sprite flag
@@ -809,7 +810,7 @@ ITCM_CODE byte Loop9918(void)
809810

810811
// ---------------------------------------------------------------------
811812
// Some programs require that we handle collisions more frequently
812-
// than just end of line. So we check every 64 scanlines (or 255 if
813+
// than just end of frame. So we check every 64 scanlines (or 255 if
813814
// we are the older DS-Lite/Phat). This is somewhat CPU intensive so
814815
// we are careful how often we run it - especially on older hardware.
815816
// ---------------------------------------------------------------------
@@ -820,6 +821,7 @@ ITCM_CODE byte Loop9918(void)
820821
if(CheckSprites()) VDPStatus|=TMS9918_STAT_OVRLAP; // Set the collision bit
821822
}
822823
}
824+
#endif
823825
}
824826
/* If time for emulated VBlank... */
825827
else if (CurLine == tms_end_line)

‎arm9/source/cpu/z80/Z80_interface.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -61,7 +61,7 @@ ITCM_CODE void MegaCartBankSwap(u8 bank)
6161
{
6262
MemoryMap[6] = ROM_Memory + ((u32)bank * (u32)0x4000);
6363
MemoryMap[7] = MemoryMap[6] + 0x2000;
64-
if (bank < 32)
64+
if (bank < 16) // First 256K of the ROM is in shadow VRAM for speed
6565
{
6666
//memcpy(RAM_Memory + 0xC000, ((u8*)0x06860000) + ((u32)bank * (u32)0x4000), 0x4000);
6767
u32 *src = (u32 *) (((u8*)0x06860000) + ((u32)bank * (u32)0x4000));

‎arm9/source/cpu/z80/cz80/CodesED.h

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -173,7 +173,7 @@ case OUTI:
173173
--CPU.BC.B.h;
174174
I=RdZ80(CPU.HL.W++);
175175
OutZ80(CPU.BC.W,I);
176-
CPU.AF.B.l=(I&0x80 ? N_FLAG:0)|(CPU.BC.B.h? 0:Z_FLAG)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
176+
CPU.AF.B.l = (CPU.AF.B.l & S_FLAG) | (I&0x80 ? N_FLAG:0) | (CPU.BC.B.h ? 0 : Z_FLAG) | (CPU.HL.B.l + I > 255 ? (C_FLAG | H_FLAG) : 0);
177177
break;
178178

179179
case OTIR:
@@ -187,7 +187,7 @@ case OTIR:
187187
}
188188
else
189189
{
190-
CPU.AF.B.l=Z_FLAG|(I&0x80 ? N_FLAG:0)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
190+
CPU.AF.B.l=(CPU.AF.B.l & S_FLAG) | Z_FLAG | (I&0x80 ? N_FLAG:0) | (CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
191191
CPU.ICount+=5;
192192
}
193193
break;
@@ -196,7 +196,7 @@ case OUTD:
196196
--CPU.BC.B.h;
197197
I=RdZ80(CPU.HL.W--);
198198
OutZ80(CPU.BC.W,I);
199-
CPU.AF.B.l=(I&0x80 ? N_FLAG:0)|(CPU.BC.B.h? 0:Z_FLAG)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
199+
CPU.AF.B.l=(CPU.AF.B.l & S_FLAG) | (I&0x80 ? N_FLAG:0) | (CPU.BC.B.h? 0:Z_FLAG) | (CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
200200
break;
201201

202202
case OTDR:
@@ -210,7 +210,7 @@ case OTDR:
210210
}
211211
else
212212
{
213-
CPU.AF.B.l=Z_FLAG|(I&0x80 ? N_FLAG:0)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
213+
CPU.AF.B.l=(CPU.AF.B.l & S_FLAG) | Z_FLAG | (I&0x80 ? N_FLAG:0) | (CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
214214
CPU.ICount+=5;
215215
}
216216
break;

‎arm9/source/cpu/z80/cz80/Tables.h

Lines changed: 64 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -37,6 +37,7 @@
3737
// -----------------------------------------------------------------
3838
static const byte Cycles[256] __attribute__((section(".dtcm"))) =
3939
{
40+
//0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F
4041
4+1, 10+1, 7+1, 6+1, 4+1, 4+1, 7+1, 4+1, 4+1, 11+1, 7+1, 6+1, 4+1, 4+1, 7+1, 4+1, // 0x00
4142
13+1, 10+1, 7+1, 6+1, 4+1, 4+1, 7+1, 4+1, 12+1, 11+1, 7+1, 6+1, 4+1, 4+1, 7+1, 4+1, // 0x10
4243
12+1, 10+1, 16+1, 6+1, 4+1, 4+1, 7+1, 4+1, 12+1, 11+1, 16+1, 6+1, 4+1, 4+1, 7+1, 4+1, // 0x20
@@ -169,6 +170,56 @@ static const byte ZSTable[256] __attribute__((section(".dtcm"))) =
169170
S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
170171
};
171172

173+
static const byte ZSTable_INC[256] __attribute__((section(".dtcm"))) =
174+
{
175+
Z_FLAG|H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
176+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
177+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
178+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
179+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
180+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
181+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
182+
H_FLAG,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
183+
H_FLAG|V_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
184+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
185+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
186+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
187+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
188+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
189+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,
190+
H_FLAG|S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG, S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG,S_FLAG
191+
};
192+
193+
194+
static const byte ZSTable_DEC[256] __attribute__((section(".dtcm"))) =
195+
{
196+
Z_FLAG|N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
197+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
198+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
199+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
200+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
201+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
202+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,H_FLAG|N_FLAG,
203+
N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,N_FLAG,V_FLAG|H_FLAG|N_FLAG,
204+
205+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
206+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
207+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
208+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
209+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
210+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
211+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
212+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
213+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
214+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
215+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
216+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
217+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
218+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG,
219+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,
220+
S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|N_FLAG,S_FLAG|H_FLAG|N_FLAG
221+
};
222+
172223
static const byte PZSTable[256] __attribute__((section(".dtcm"))) =
173224
{
174225
Z_FLAG|P_FLAG,0,0,P_FLAG,0,P_FLAG,P_FLAG,0,
@@ -214,6 +265,19 @@ static const byte PZSTable[256] __attribute__((section(".dtcm"))) =
214265
S_FLAG|P_FLAG,S_FLAG,S_FLAG,S_FLAG|P_FLAG
215266
};
216267

268+
static const byte PZSHTable_BIT[129] __attribute__((section(".dtcm"))) =
269+
{
270+
Z_FLAG|P_FLAG|H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
271+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
272+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
273+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
274+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
275+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
276+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
277+
H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,H_FLAG,
278+
S_FLAG|H_FLAG
279+
};
280+
217281
static const word DAATable[2048] __attribute__((section(".dtcm"))) =
218282
{
219283
0x0044,0x0100,0x0200,0x0304,0x0400,0x0504,0x0604,0x0700,

‎arm9/source/cpu/z80/cz80/Z80.c

Lines changed: 33 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -57,9 +57,21 @@ extern void cpu_writeport_msx(unsigned short Port, unsigned char Value);
5757
extern byte cpu_readport16(unsigned short Port);
5858
extern u8 bIsComplicatedRAM, my_config_clear_int, einstein_mode, memotech_mode;
5959
extern u16 vdp_int_source, keyboard_interrupt, joystick_interrupt;
60+
61+
#ifndef ZEXALL_TEST // If we're running normally, map in the standard Op/Rd/Wr handlers
62+
6063
inline byte OpZ80(word A) {return*(MemoryMap[(A)>>13] + ((A)&0x1FFF));}
6164
inline byte RdZ80(word A) {return (bIsComplicatedRAM ? cpu_readmem16_banked(A) : *(MemoryMap[(A)>>13] + ((A)&0x1FFF)));}
6265
#define WrZ80(A,V) cpu_writemem16(V,A)
66+
67+
#else // For ZEXALL_TEST we simplify things...
68+
69+
#define WrZ80(A,V) RAM_Memory[A]=V
70+
inline byte OpZ80(word A) {return RAM_Memory[A];}
71+
inline byte RdZ80(word A) {return RAM_Memory[A];}
72+
73+
#endif // ZEXALL_TEST
74+
6375
#define OutZ80(P,V) cpu_writeport16(P,V)
6476
#define InZ80(P) cpu_readport16(P)
6577

@@ -107,7 +119,7 @@ inline byte RdZ80(word A) {return (bIsComplicatedRAM ? cpu_readmem16_banked(A)
107119
CPU.AF.B.l=Rg&0x01;Rg>>=1;CPU.AF.B.l|=PZSTable[Rg]
108120

109121
#define M_BIT(Bit,Rg) \
110-
CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|H_FLAG|PZSTable[Rg&(1<<Bit)]
122+
CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|PZSHTable_BIT[Rg&(1<<Bit)]
111123

112124
#define M_SET(Bit,Rg) Rg|=1<<Bit
113125
#define M_RES(Bit,Rg) Rg&=~(1<<Bit)
@@ -182,15 +194,13 @@ inline byte RdZ80(word A) {return (bIsComplicatedRAM ? cpu_readmem16_banked(A)
182194

183195
#define M_INC(Rg) \
184196
Rg++; \
185-
CPU.AF.B.l= \
186-
(CPU.AF.B.l&C_FLAG)|ZSTable[Rg]| \
187-
(Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
197+
CPU.AF.B.l=(CPU.AF.B.l&C_FLAG)|ZSTable_INC[Rg];
198+
//(Rg==0x80? V_FLAG:0)|(Rg&0x0F? 0:H_FLAG)
188199

189200
#define M_DEC(Rg) \
190201
Rg--; \
191-
CPU.AF.B.l= \
192-
N_FLAG|(CPU.AF.B.l&C_FLAG)|ZSTable[Rg]| \
193-
(Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
202+
CPU.AF.B.l= (CPU.AF.B.l&C_FLAG)|ZSTable_DEC[Rg];
203+
//(Rg==0x7F? V_FLAG:0)|((Rg&0x0F)==0x0F? H_FLAG:0)
194204

195205
#define M_ADDW(Rg1,Rg2) \
196206
J.W=(CPU.Rg1.W+CPU.Rg2.W)&0xFFFF; \
@@ -519,6 +529,10 @@ ITCM_CODE int ExecZ80(register int RunCycles)
519529
{
520530
while(CPU.ICount>0)
521531
{
532+
#ifdef ZEXALL_TEST
533+
extern void zextrap(void);
534+
zextrap();
535+
#endif
522536
/* Read opcode and count cycles */
523537
I=OpZ80(CPU.PC.W++);
524538
CPU.ICount-=Cycles[I];
@@ -802,7 +816,18 @@ int ExecZ80_Simplified(register int RunCycles)
802816
{
803817
#include "Codes.h"
804818
case PFX_CB: CodesCB_Simplified();break;
805-
case PFX_ED: CodesED_Simplified();break;
819+
case PFX_ED:
820+
if (OpZ80(CPU.PC.W) == 0xA3) // This is so common so we trap it here to avoid the slow function call overhead
821+
{ //A3 is OUTI
822+
CPU.PC.W++;
823+
CPU.ICount-=16;
824+
--CPU.BC.B.h;
825+
I=RdZ80(CPU.HL.W++);
826+
OutZ80(CPU.BC.W,I);
827+
CPU.AF.B.l=(CPU.BC.B.h? 0:Z_FLAG)|(CPU.HL.B.l+I>255? (C_FLAG|H_FLAG):0);
828+
}
829+
else CodesED_Simplified();
830+
break;
806831
case PFX_FD: CodesFD_Simplified();break;
807832
case PFX_DD: CodesDD_Simplified();break;
808833
}

‎arm9/source/cpu/z80/cz80/Z80.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,8 @@
2727
extern "C" {
2828
#endif
2929

30+
//#define ZEXALL_TEST /* Uncomment this to run the ZEXALL Z80 instruction test */
31+
3032
/* Compilation options: */
3133
#define LSB_FIRST /* Compile for low-endian CPU */
3234
#define EXECZ80 /* Call Z80 each scanline */

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